Fix possible low power mode leakage

This commit is contained in:
Kwabena W. Agyeman 2023-06-04 20:28:54 -07:00
parent 22320201db
commit b6035f0487
3 changed files with 19 additions and 19 deletions

View File

@ -9769,17 +9769,11 @@ This DRC check is for 8-Layer Extended Capability boards with 4 mil drills to be
<wire x1="7.9" y1="1.9" x2="9.165" y2="1.95" width="0" layer="19" extent="16-16"/>
</signal>
<signal name="VDD_SNVS">
<contactref element="Q2" pad="1"/>
<contactref element="Q3" pad="1"/>
<contactref element="Q4" pad="1"/>
<contactref element="C9" pad="2"/>
<contactref element="IC2" pad="5"/>
<contactref element="D15" pad="1"/>
<wire x1="15.7" y1="5.25" x2="24.65" y2="11.8" width="0" layer="19" extent="16-16"/>
<wire x1="15.7" y1="5.25" x2="31.045" y2="24.4" width="0" layer="19" extent="1-16"/>
<wire x1="16.4" y1="4.1" x2="15.7" y2="5.25" width="0" layer="19" extent="16-16"/>
<wire x1="10.9" y1="7.65" x2="15.7" y2="5.25" width="0" layer="19" extent="16-16"/>
<wire x1="9.5" y1="8.95" x2="10.9" y2="7.65" width="0" layer="19" extent="16-16"/>
<wire x1="31.045" y1="24.4" x2="9.5" y2="8.95" width="0" layer="19" extent="1-16"/>
</signal>
<signal name="VDD_HIGH_CAP">
<contactref element="IC9" pad="P8"/>
@ -9883,8 +9877,14 @@ This DRC check is for 8-Layer Extended Capability boards with 4 mil drills to be
<contactref element="IC9" pad="M9"/>
<contactref element="C86" pad="1"/>
<contactref element="D15" pad="3"/>
<contactref element="Q2" pad="1"/>
<contactref element="Q3" pad="1"/>
<contactref element="Q4" pad="1"/>
<wire x1="19.525" y1="28.575" x2="32" y2="26.8" width="0" layer="19" extent="1-1"/>
<wire x1="19.45" y1="28.6" x2="19.525" y2="28.575" width="0" layer="19" extent="1-16"/>
<wire x1="32" y1="26.8" x2="19.45" y2="28.6" width="0" layer="19" extent="1-16"/>
<wire x1="24.65" y1="11.8" x2="32" y2="26.8" width="0" layer="19" extent="1-16"/>
<wire x1="10.9" y1="7.65" x2="24.65" y2="11.8" width="0" layer="19" extent="16-16"/>
<wire x1="9.5" y1="8.95" x2="10.9" y2="7.65" width="0" layer="19" extent="16-16"/>
</signal>
<signal name="JTAG_TRSTB_INT_UNUSED">
<contactref element="R49" pad="2"/>

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@ -14113,16 +14113,6 @@ Source: &lt;a href="http://www.onsemi.com/pub/Collateral/BAT54CLT1-D.PDF"&gt; Da
</net>
<net name="VDD_SNVS" class="0">
<segment>
<wire x1="154.94" y1="137.16" x2="154.94" y2="149.86" width="0.1524" layer="91"/>
<pinref part="Q2" gate="G$1" pin="G"/>
<label x="154.94" y="149.86" size="1.778" layer="95" rot="R90"/>
</segment>
<segment>
<wire x1="215.9" y1="137.16" x2="215.9" y2="149.86" width="0.1524" layer="91"/>
<pinref part="Q3" gate="G$1" pin="G"/>
<label x="215.9" y="149.86" size="1.778" layer="95" rot="R90"/>
</segment>
<segment>
<wire x1="78.74" y1="114.3" x2="96.52" y2="114.3" width="0.1524" layer="91"/>
<wire x1="96.52" y1="114.3" x2="96.52" y2="93.98" width="0.1524" layer="91"/>
<pinref part="C9" gate="G$1" pin="2"/>
@ -14187,6 +14177,16 @@ Source: &lt;a href="http://www.onsemi.com/pub/Collateral/BAT54CLT1-D.PDF"&gt; Da
<label x="144.78" y="116.84" size="1.778" layer="95" rot="R180"/>
<pinref part="D15" gate="G$1" pin="K"/>
</segment>
<segment>
<wire x1="154.94" y1="137.16" x2="154.94" y2="149.86" width="0.1524" layer="91"/>
<pinref part="Q2" gate="G$1" pin="G"/>
<label x="154.94" y="149.86" size="1.778" layer="95" rot="R90"/>
</segment>
<segment>
<wire x1="215.9" y1="137.16" x2="215.9" y2="149.86" width="0.1524" layer="91"/>
<pinref part="Q3" gate="G$1" pin="G"/>
<label x="215.9" y="149.86" size="1.778" layer="95" rot="R90"/>
</segment>
</net>
<net name="RST_BUTTON" class="0">
<segment>
@ -14383,7 +14383,7 @@ Source: &lt;a href="http://www.onsemi.com/pub/Collateral/BAT54CLT1-D.PDF"&gt; Da
<label x="165.1" y="111.76" size="1.778" layer="95"/>
</segment>
</net>
<net name="VDD_SNVS" class="0">
<net name="VDD_SNVS_CPU" class="0">
<segment>
<pinref part="Q4" gate="G$1" pin="G"/>
<wire x1="157.48" y1="119.38" x2="157.48" y2="129.54" width="0.1524" layer="91"/>