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ports/stm32: Refactor I2C bus definitions.
This commit is contained in:
parent
ec67194d68
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0195473235
@ -219,26 +219,12 @@
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#define OMV_AXI_QOS_MDMA_W_PRI 15 // Max pri to move data.
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// Main image sensor I2C bus
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#define ISC_I2C (I2C3)
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#define ISC_I2C_ID (3)
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#define ISC_I2C_SPEED (OMV_I2C_SPEED_STANDARD)
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#define ISC_I2C_SCL_PIN (&omv_pin_A8_I2C3)
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#define ISC_I2C_SDA_PIN (&omv_pin_C9_I2C3)
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#define ISC_I2C_CLK_ENABLE() __I2C3_CLK_ENABLE()
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#define ISC_I2C_CLK_DISABLE() __I2C3_CLK_DISABLE()
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#define ISC_I2C_FORCE_RESET() __HAL_RCC_I2C3_FORCE_RESET()
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#define ISC_I2C_RELEASE_RESET() __HAL_RCC_I2C3_RELEASE_RESET()
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// Thermal image sensor I2C bus
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#define FIR_I2C (I2C1)
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#define FIR_I2C_ID (1)
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#define FIR_I2C_SPEED (OMV_I2C_SPEED_FULL)
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#define FIR_I2C_SCL_PIN (&omv_pin_B8_I2C1)
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#define FIR_I2C_SDA_PIN (&omv_pin_B9_I2C1)
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#define FIR_I2C_CLK_ENABLE() __I2C1_CLK_ENABLE()
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#define FIR_I2C_CLK_DISABLE() __I2C1_CLK_DISABLE()
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#define FIR_I2C_FORCE_RESET() __HAL_RCC_I2C1_FORCE_RESET()
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#define FIR_I2C_RELEASE_RESET() __HAL_RCC_I2C1_RELEASE_RESET()
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// Soft I2C bus
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#define SOFT_I2C_SIOC_PIN (&omv_pin_C10_GPIO)
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@ -301,7 +287,19 @@
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#define AUDIO_DFSDM_CLK_DISABLE() __HAL_RCC_DFSDM1_CLK_DISABLE()
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#define AUDIO_DFSDM_DMA_CLK_ENABLE() __HAL_RCC_DMA1_CLK_ENABLE()
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// Physical I2C buses
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// I2C bus 1
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#define I2C1_ID (1)
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#define I2C1_SCL_PIN (&omv_pin_B8_I2C1)
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#define I2C1_SDA_PIN (&omv_pin_B9_I2C1)
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// I2C bus 3
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#define I2C3_ID (3)
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#define I2C3_SCL_PIN (&omv_pin_A8_I2C3)
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#define I2C3_SDA_PIN (&omv_pin_C9_I2C3)
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// Physical SPI buses.
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// SPI bus 5
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#define SPI5_ID (5)
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#define SPI5_SCLK_PIN (&omv_pin_F7_SPI5)
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#define SPI5_MISO_PIN (&omv_pin_F8_SPI5)
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@ -233,37 +233,16 @@
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#define OMV_AXI_QOS_LTDC_R_PRI 15 // Max pri to read out the frame buffer.
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// Image sensor I2C
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#define ISC_I2C (I2C3)
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#define ISC_I2C_ID (3)
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#define ISC_I2C_SPEED (OMV_I2C_SPEED_STANDARD)
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#define ISC_I2C_SCL_PIN (&omv_pin_H7_I2C3)
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#define ISC_I2C_SDA_PIN (&omv_pin_H8_I2C3)
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#define ISC_I2C_CLK_ENABLE() __I2C3_CLK_ENABLE()
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#define ISC_I2C_CLK_DISABLE() __I2C3_CLK_DISABLE()
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#define ISC_I2C_FORCE_RESET() __HAL_RCC_I2C3_FORCE_RESET()
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#define ISC_I2C_RELEASE_RESET() __HAL_RCC_I2C3_RELEASE_RESET()
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// Alternate I2C bus for the Portenta breakout
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#define ISC_I2C_ALT (I2C4)
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#define ISC_I2C_ALT_ID (4)
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#define ISC_I2C_ALT_SPEED (OMV_I2C_SPEED_STANDARD)
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#define ISC_I2C_ALT_SCL_PIN (&omv_pin_H11_I2C4)
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#define ISC_I2C_ALT_SDA_PIN (&omv_pin_H12_I2C4)
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#define ISC_I2C_ALT_CLK_ENABLE() __HAL_RCC_I2C4_CLK_ENABLE()
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#define ISC_I2C_ALT_CLK_DISABLE() __HAL_RCC_I2C4_CLK_DISABLE()
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#define ISC_I2C_ALT_FORCE_RESET() __HAL_RCC_I2C4_FORCE_RESET()
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#define ISC_I2C_ALT_RELEASE_RESET() __HAL_RCC_I2C4_RELEASE_RESET()
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// FIR I2C
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#define FIR_I2C (I2C3)
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#define FIR_I2C_ID (3)
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#define FIR_I2C_SPEED (OMV_I2C_SPEED_STANDARD)
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#define FIR_I2C_SCL_PIN (&omv_pin_H7_I2C3)
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#define FIR_I2C_SDA_PIN (&omv_pin_H8_I2C3)
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#define FIR_I2C_CLK_ENABLE() __I2C3_CLK_ENABLE()
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#define FIR_I2C_CLK_DISABLE() __I2C3_CLK_DISABLE()
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#define FIR_I2C_FORCE_RESET() __HAL_RCC_I2C3_FORCE_RESET()
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#define FIR_I2C_RELEASE_RESET() __HAL_RCC_I2C3_RELEASE_RESET()
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//#define SOFT_I2C_SIOC_PIN (&omv_pin_B10_GPIO)
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//#define SOFT_I2C_SIOD_PIN (&omv_pin_B11_GPIO)
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@ -308,6 +287,17 @@
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#define DCMI_VSYNC_PIN (&omv_pin_I5_DCMI)
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#define DCMI_PXCLK_PIN (&omv_pin_A6_DCMI)
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// Physical I2C buses.
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// I2C bus 3
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#define I2C3_ID (3)
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#define I2C3_SCL_PIN (&omv_pin_H7_I2C3)
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#define I2C3_SDA_PIN (&omv_pin_H8_I2C3)
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// I2C bus 4
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#define I2C4_ID (4)
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#define I2C4_SCL_PIN (&omv_pin_H11_I2C4)
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#define I2C4_SDA_PIN (&omv_pin_H12_I2C4)
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// SAI4
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#define AUDIO_SAI (SAI4_Block_A)
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// SCKx frequency = SAI_KER_CK / MCKDIV / 2
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@ -130,26 +130,12 @@
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#define OMV_FLASH_TXT_LENGTH 960K
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// Main image sensor I2C bus
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#define ISC_I2C (I2C1)
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#define ISC_I2C_ID (1)
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#define ISC_I2C_SPEED (OMV_I2C_SPEED_STANDARD)
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#define ISC_I2C_SCL_PIN (&omv_pin_B8_I2C1)
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#define ISC_I2C_SDA_PIN (&omv_pin_B9_I2C1)
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#define ISC_I2C_CLK_ENABLE() __I2C1_CLK_ENABLE()
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#define ISC_I2C_CLK_DISABLE() __I2C1_CLK_DISABLE()
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#define ISC_I2C_FORCE_RESET() __HAL_RCC_I2C1_FORCE_RESET()
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#define ISC_I2C_RELEASE_RESET() __HAL_RCC_I2C1_RELEASE_RESET()
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// Thermal image sensor I2C bus
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#define FIR_I2C (I2C2)
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#define FIR_I2C_ID (2)
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#define FIR_I2C_SPEED (OMV_I2C_SPEED_FULL)
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#define FIR_I2C_SCL_PIN (&omv_pin_B10_I2C2)
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#define FIR_I2C_SDA_PIN (&omv_pin_B11_I2C2)
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#define FIR_I2C_CLK_ENABLE() __I2C2_CLK_ENABLE()
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#define FIR_I2C_CLK_DISABLE() __I2C2_CLK_DISABLE()
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#define FIR_I2C_FORCE_RESET() __HAL_RCC_I2C2_FORCE_RESET()
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#define FIR_I2C_RELEASE_RESET() __HAL_RCC_I2C2_RELEASE_RESET()
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// Soft I2C bus
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#define SOFT_I2C_SIOC_PIN (&omv_pin_B10_GPIO)
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@ -188,7 +174,19 @@
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#define DCMI_VSYNC_PIN (&omv_pin_B7_DCMI)
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#define DCMI_PXCLK_PIN (&omv_pin_A6_DCMI)
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// Physical I2C buses
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// I2C bus 1
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#define I2C1_ID (1)
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#define I2C1_SCL_PIN (&omv_pin_B8_I2C1)
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#define I2C1_SDA_PIN (&omv_pin_B9_I2C1)
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// I2C bus 2
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#define I2C2_ID (2)
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#define I2C2_SCL_PIN (&omv_pin_B10_I2C2)
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#define I2C2_SDA_PIN (&omv_pin_B11_I2C2)
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// Physical SPI buses
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// SPI bus 2
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#define SPI2_ID (2)
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#define SPI2_SCLK_PIN (&omv_pin_B13_SPI2)
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#define SPI2_MISO_PIN (&omv_pin_B14_SPI2)
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@ -130,26 +130,12 @@
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#define OMV_FLASH_TXT_LENGTH 1920K
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// Main image sensor I2C bus
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#define ISC_I2C (I2C1)
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#define ISC_I2C_ID (1)
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#define ISC_I2C_SPEED (OMV_I2C_SPEED_STANDARD)
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#define ISC_I2C_SCL_PIN (&omv_pin_B8_I2C1)
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#define ISC_I2C_SDA_PIN (&omv_pin_B9_I2C1)
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#define ISC_I2C_CLK_ENABLE() __I2C1_CLK_ENABLE()
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#define ISC_I2C_CLK_DISABLE() __I2C1_CLK_DISABLE()
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#define ISC_I2C_FORCE_RESET() __HAL_RCC_I2C1_FORCE_RESET()
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#define ISC_I2C_RELEASE_RESET() __HAL_RCC_I2C1_RELEASE_RESET()
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// FIR I2C bus
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#define FIR_I2C (I2C2)
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#define FIR_I2C_ID (2)
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#define FIR_I2C_SPEED (OMV_I2C_SPEED_FULL)
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#define FIR_I2C_SCL_PIN (&omv_pin_B10_I2C2)
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#define FIR_I2C_SDA_PIN (&omv_pin_B11_I2C2)
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#define FIR_I2C_CLK_ENABLE() __I2C2_CLK_ENABLE()
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#define FIR_I2C_CLK_DISABLE() __I2C2_CLK_DISABLE()
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#define FIR_I2C_FORCE_RESET() __HAL_RCC_I2C2_FORCE_RESET()
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#define FIR_I2C_RELEASE_RESET() __HAL_RCC_I2C2_RELEASE_RESET()
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// Soft I2C bus
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#define SOFT_I2C_SIOC_PIN (&omv_pin_B10_GPIO)
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@ -188,7 +174,19 @@
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#define DCMI_VSYNC_PIN (&omv_pin_B7_DCMI)
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#define DCMI_PXCLK_PIN (&omv_pin_A6_DCMI)
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// Physical I2C buses.
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// I2C bus 1
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#define I2C1_ID (1)
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#define I2C1_SCL_PIN (&omv_pin_B8_I2C1)
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#define I2C1_SDA_PIN (&omv_pin_B9_I2C1)
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// I2C bus 2
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#define I2C2_ID (2)
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#define I2C2_SCL_PIN (&omv_pin_B10_I2C2)
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#define I2C2_SDA_PIN (&omv_pin_B11_I2C2)
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// Physical SPI buses
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// SPI bus 2
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#define SPI2_ID (2)
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#define SPI2_SCLK_PIN (&omv_pin_B13_SPI2)
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#define SPI2_MISO_PIN (&omv_pin_B14_SPI2)
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@ -217,26 +217,12 @@
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#define OMV_AXI_QOS_MDMA_W_PRI 15 // Max pri to move data.
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// Main image sensor I2C bus
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#define ISC_I2C (I2C1)
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#define ISC_I2C_ID (1)
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#define ISC_I2C_SPEED (OMV_I2C_SPEED_STANDARD)
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#define ISC_I2C_SCL_PIN (&omv_pin_B8_I2C1)
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#define ISC_I2C_SDA_PIN (&omv_pin_B9_I2C1)
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#define ISC_I2C_CLK_ENABLE() __I2C1_CLK_ENABLE()
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#define ISC_I2C_CLK_DISABLE() __I2C1_CLK_DISABLE()
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#define ISC_I2C_FORCE_RESET() __HAL_RCC_I2C1_FORCE_RESET()
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#define ISC_I2C_RELEASE_RESET() __HAL_RCC_I2C1_RELEASE_RESET()
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// Thermal image sensor I2C bus
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#define FIR_I2C (I2C2)
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#define FIR_I2C_ID (2)
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#define FIR_I2C_SPEED (OMV_I2C_SPEED_FULL)
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#define FIR_I2C_SCL_PIN (&omv_pin_B10_I2C2)
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#define FIR_I2C_SDA_PIN (&omv_pin_B11_I2C2)
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#define FIR_I2C_CLK_ENABLE() __I2C2_CLK_ENABLE()
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#define FIR_I2C_CLK_DISABLE() __I2C2_CLK_DISABLE()
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#define FIR_I2C_FORCE_RESET() __HAL_RCC_I2C2_FORCE_RESET()
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#define FIR_I2C_RELEASE_RESET() __HAL_RCC_I2C2_RELEASE_RESET()
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// Soft I2C bus
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#define SOFT_I2C_SIOC_PIN (&omv_pin_B10_GPIO)
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@ -280,7 +266,18 @@
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#define DCMI_VSYNC_PIN (&omv_pin_B7_DCMI)
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#define DCMI_PXCLK_PIN (&omv_pin_A6_DCMI)
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// Physical I2C buses.
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// I2C bus 1
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#define I2C1_ID (1)
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#define I2C1_SCL_PIN (&omv_pin_B8_I2C1)
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#define I2C1_SDA_PIN (&omv_pin_B9_I2C1)
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// I2C bus 2
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#define I2C2_ID (2)
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#define I2C2_SCL_PIN (&omv_pin_B10_I2C2)
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#define I2C2_SDA_PIN (&omv_pin_B11_I2C2)
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// Physical SPI buses.
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// SPI bus 2
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#define SPI2_ID (2)
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#define SPI2_SCLK_PIN (&omv_pin_B13_SPI2)
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#define SPI2_MISO_PIN (&omv_pin_B14_SPI2)
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@ -220,26 +220,12 @@
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#define OMV_AXI_QOS_MDMA_W_PRI 15 // Max pri to move data.
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// Main image sensor I2C bus
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#define ISC_I2C (I2C1)
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#define ISC_I2C_ID (1)
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#define ISC_I2C_SPEED (OMV_I2C_SPEED_STANDARD)
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#define ISC_I2C_SCL_PIN (&omv_pin_B8_I2C1)
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#define ISC_I2C_SDA_PIN (&omv_pin_B9_I2C1)
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#define ISC_I2C_CLK_ENABLE() __I2C1_CLK_ENABLE()
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#define ISC_I2C_CLK_DISABLE() __I2C1_CLK_DISABLE()
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#define ISC_I2C_FORCE_RESET() __HAL_RCC_I2C1_FORCE_RESET()
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#define ISC_I2C_RELEASE_RESET() __HAL_RCC_I2C1_RELEASE_RESET()
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// Thermal image sensor I2C bus
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#define FIR_I2C (I2C2)
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#define FIR_I2C_ID (2)
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#define FIR_I2C_SPEED (OMV_I2C_SPEED_FULL)
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#define FIR_I2C_SCL_PIN (&omv_pin_B10_I2C2)
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#define FIR_I2C_SDA_PIN (&omv_pin_B11_I2C2)
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#define FIR_I2C_CLK_ENABLE() __I2C2_CLK_ENABLE()
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#define FIR_I2C_CLK_DISABLE() __I2C2_CLK_DISABLE()
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#define FIR_I2C_FORCE_RESET() __HAL_RCC_I2C2_FORCE_RESET()
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#define FIR_I2C_RELEASE_RESET() __HAL_RCC_I2C2_RELEASE_RESET()
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// Soft I2C bus.
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#define SOFT_I2C_SIOC_PIN (&omv_pin_B10_GPIO)
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@ -283,7 +269,18 @@
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#define DCMI_VSYNC_PIN (&omv_pin_B7_DCMI)
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#define DCMI_PXCLK_PIN (&omv_pin_A6_DCMI)
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// Physical I2C buses.
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// I2C bus 1
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#define I2C1_ID (1)
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#define I2C1_SCL_PIN (&omv_pin_B8_I2C1)
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#define I2C1_SDA_PIN (&omv_pin_B9_I2C1)
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// I2C bus 2
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#define I2C2_ID (2)
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#define I2C2_SCL_PIN (&omv_pin_B10_I2C2)
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#define I2C2_SDA_PIN (&omv_pin_B11_I2C2)
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// Physical SPI buses.
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// SPI bus 2
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#define SPI2_ID (2)
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#define SPI2_SCLK_PIN (&omv_pin_B13_SPI2)
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#define SPI2_MISO_PIN (&omv_pin_B14_SPI2)
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@ -234,51 +234,23 @@
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#define OMV_AXI_QOS_MDMA_W_PRI 15 // Max pri to move data.
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// Image sensor I2C configuration
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#define ISC_I2C (I2C2)
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#define ISC_I2C_ID (2)
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#define ISC_I2C_SPEED (OMV_I2C_SPEED_STANDARD)
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#define ISC_I2C_SCL_PIN (&omv_pin_H4_I2C2)
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#define ISC_I2C_SDA_PIN (&omv_pin_H5_I2C2)
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#define ISC_I2C_CLK_ENABLE() __HAL_RCC_I2C2_CLK_ENABLE()
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#define ISC_I2C_CLK_DISABLE() __HAL_RCC_I2C2_CLK_DISABLE()
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#define ISC_I2C_FORCE_RESET() __HAL_RCC_I2C2_FORCE_RESET()
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#define ISC_I2C_RELEASE_RESET() __HAL_RCC_I2C2_RELEASE_RESET()
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// FIR sensor I2C configuration
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#define FIR_I2C (I2C1)
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#define FIR_I2C_ID (1)
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#define FIR_I2C_SPEED (OMV_I2C_SPEED_STANDARD)
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#define FIR_I2C_SCL_PIN (&omv_pin_B8_I2C1)
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#define FIR_I2C_SDA_PIN (&omv_pin_B9_I2C1)
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#define FIR_I2C_CLK_ENABLE() __HAL_RCC_I2C1_CLK_ENABLE()
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#define FIR_I2C_CLK_DISABLE() __HAL_RCC_I2C1_CLK_DISABLE()
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#define FIR_I2C_FORCE_RESET() __HAL_RCC_I2C1_FORCE_RESET()
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#define FIR_I2C_RELEASE_RESET() __HAL_RCC_I2C1_RELEASE_RESET()
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// TOF sensor I2C configuration
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#define TOF_I2C (I2C4)
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#define TOF_I2C_ID (4)
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#define TOF_I2C_SPEED (OMV_I2C_SPEED_STANDARD)
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#define TOF_I2C_SCL_PIN (&omv_pin_B6_I2C4)
|
||||
#define TOF_I2C_SDA_PIN (&omv_pin_B7_I2C4)
|
||||
#define TOF_I2C_CLK_ENABLE() __HAL_RCC_I2C4_CLK_ENABLE()
|
||||
#define TOF_I2C_CLK_DISABLE() __HAL_RCC_I2C4_CLK_DISABLE()
|
||||
#define TOF_I2C_FORCE_RESET() __HAL_RCC_I2C4_FORCE_RESET()
|
||||
#define TOF_I2C_RELEASE_RESET() __HAL_RCC_I2C4_RELEASE_RESET()
|
||||
|
||||
// IMU I2C configuration
|
||||
#define IMU_I2C (I2C4)
|
||||
#define IMU_I2C_ID (4)
|
||||
#define IMU_I2C_SPEED (0x4030040B)
|
||||
#define IMU_I2C_SCL_PIN (&omv_pin_B6_I2C4)
|
||||
#define IMU_I2C_SDA_PIN (&omv_pin_B7_I2C4)
|
||||
#define IMU_I2C_CLK_ENABLE() __HAL_RCC_I2C4_CLK_ENABLE()
|
||||
#define IMU_I2C_CLK_DISABLE() __HAL_RCC_I2C4_CLK_DISABLE()
|
||||
#define IMU_I2C_FORCE_RESET() __HAL_RCC_I2C4_FORCE_RESET()
|
||||
#define IMU_I2C_RELEASE_RESET() __HAL_RCC_I2C4_RELEASE_RESET()
|
||||
#define IMU_CHIP_LSM6DS3 (1)
|
||||
#define OMV_IMU_X_Y_ROTATION_DEGREES 0
|
||||
#define OMV_IMU_MOUNTING_Z_DIRECTION -1
|
||||
#define OMV_IMU_X_Y_ROTATION_DEGREES (0)
|
||||
#define OMV_IMU_MOUNTING_Z_DIRECTION (-1)
|
||||
|
||||
// DCMI timer configuration
|
||||
#define DCMI_TIM (TIM1)
|
||||
@ -306,6 +278,20 @@
|
||||
#define DCMI_HSYNC_PIN (&omv_pin_A4_DCMI)
|
||||
#define DCMI_PXCLK_PIN (&omv_pin_A6_DCMI)
|
||||
|
||||
// Physical I2C buses.
|
||||
// I2C bus 1
|
||||
#define I2C1_ID (1)
|
||||
#define I2C1_SCL_PIN (&omv_pin_B8_I2C1)
|
||||
#define I2C1_SDA_PIN (&omv_pin_B9_I2C1)
|
||||
// I2C bus 2
|
||||
#define I2C2_ID (2)
|
||||
#define I2C2_SCL_PIN (&omv_pin_H4_I2C2)
|
||||
#define I2C2_SDA_PIN (&omv_pin_H5_I2C2)
|
||||
// I2C bus 4
|
||||
#define I2C4_ID (4)
|
||||
#define I2C4_SCL_PIN (&omv_pin_B6_I2C4)
|
||||
#define I2C4_SDA_PIN (&omv_pin_B7_I2C4)
|
||||
|
||||
#define ISC_SPI (SPI6)
|
||||
// SPI6 clock source is PLL3Q (80MHz/4 == 20MHz) - Minimum (164*240*8*27 = 8,501,760Hz)
|
||||
#define ISC_SPI_PRESCALER (SPI_BAUDRATEPRESCALER_4)
|
||||
|
||||
@ -226,26 +226,12 @@
|
||||
#define OMV_AXI_QOS_LTDC_R_PRI 15 // Max pri to read out the frame buffer.
|
||||
|
||||
// Main image sensor I2C bus
|
||||
#define ISC_I2C (I2C1)
|
||||
#define ISC_I2C_ID (1)
|
||||
#define ISC_I2C_SPEED (OMV_I2C_SPEED_STANDARD)
|
||||
#define ISC_I2C_SCL_PIN (&omv_pin_B8_I2C1)
|
||||
#define ISC_I2C_SDA_PIN (&omv_pin_B9_I2C1)
|
||||
#define ISC_I2C_CLK_ENABLE() __I2C1_CLK_ENABLE()
|
||||
#define ISC_I2C_CLK_DISABLE() __I2C1_CLK_DISABLE()
|
||||
#define ISC_I2C_FORCE_RESET() __HAL_RCC_I2C1_FORCE_RESET()
|
||||
#define ISC_I2C_RELEASE_RESET() __HAL_RCC_I2C1_RELEASE_RESET()
|
||||
|
||||
// Thermal image sensor I2C bus
|
||||
#define FIR_I2C (I2C2)
|
||||
#define FIR_I2C_ID (2)
|
||||
#define FIR_I2C_SPEED (OMV_I2C_SPEED_FULL)
|
||||
#define FIR_I2C_SCL_PIN (&omv_pin_B10_I2C2)
|
||||
#define FIR_I2C_SDA_PIN (&omv_pin_B11_I2C2)
|
||||
#define FIR_I2C_CLK_ENABLE() __I2C2_CLK_ENABLE()
|
||||
#define FIR_I2C_CLK_DISABLE() __I2C2_CLK_DISABLE()
|
||||
#define FIR_I2C_FORCE_RESET() __HAL_RCC_I2C2_FORCE_RESET()
|
||||
#define FIR_I2C_RELEASE_RESET() __HAL_RCC_I2C2_RELEASE_RESET()
|
||||
|
||||
// Soft I2C bus.
|
||||
#define SOFT_I2C_SIOC_PIN (&omv_pin_B10_GPIO)
|
||||
@ -285,13 +271,25 @@
|
||||
#define DCMI_VSYNC_PIN (&omv_pin_B7_DCMI)
|
||||
#define DCMI_PXCLK_PIN (&omv_pin_A6_DCMI)
|
||||
|
||||
// Physical SPI buses.
|
||||
// Physical I2C buses.
|
||||
// I2C bus 1
|
||||
#define I2C1_ID (1)
|
||||
#define I2C1_SCL_PIN (&omv_pin_B8_I2C1)
|
||||
#define I2C1_SDA_PIN (&omv_pin_B9_I2C1)
|
||||
// I2C bus 2
|
||||
#define I2C2_ID (2)
|
||||
#define I2C2_SCL_PIN (&omv_pin_B10_I2C2)
|
||||
#define I2C2_SDA_PIN (&omv_pin_B11_I2C2)
|
||||
|
||||
#define SPI_ID (5)
|
||||
// Physical SPI buses.
|
||||
// SPI bus 5
|
||||
#define SPI5_ID (5)
|
||||
#define SPI5_SCLK_PIN (&omv_pin_H6_SPI5)
|
||||
#define SPI5_MISO_PIN (&omv_pin_H7_SPI5)
|
||||
#define SPI5_MOSI_PIN (&omv_pin_J10_SPI5)
|
||||
#define SPI5_SSEL_PIN (&omv_pin_K1_GPIO)
|
||||
#define SPI5_DMA_TX_CHANNEL (DMA2_Stream4)
|
||||
#define SPI5_DMA_RX_CHANNEL (DMA2_Stream3)
|
||||
|
||||
// LCD Interface
|
||||
#define OMV_LCD_CONTROLLER (LTDC)
|
||||
|
||||
@ -100,31 +100,39 @@ int omv_i2c_init(omv_i2c_t *i2c, uint32_t bus_id, uint32_t speed) {
|
||||
i2c->sda_pin = NULL;
|
||||
|
||||
switch (bus_id) {
|
||||
#if defined(I2C1)
|
||||
#if defined(I2C1_ID)
|
||||
case 1: {
|
||||
i2c->inst = &I2CHandle1;
|
||||
i2c->inst->Instance = I2C1;
|
||||
i2c->scl_pin = I2C1_SCL_PIN;
|
||||
i2c->sda_pin = I2C1_SDA_PIN;
|
||||
break;
|
||||
}
|
||||
#endif
|
||||
#if defined(I2C2)
|
||||
#if defined(I2C2_ID)
|
||||
case 2: {
|
||||
i2c->inst = &I2CHandle2;
|
||||
i2c->inst->Instance = I2C2;
|
||||
i2c->scl_pin = I2C2_SCL_PIN;
|
||||
i2c->sda_pin = I2C2_SDA_PIN;
|
||||
break;
|
||||
}
|
||||
#endif
|
||||
#if defined(I2C3)
|
||||
#if defined(I2C3_ID)
|
||||
case 3: {
|
||||
i2c->inst = &I2CHandle3;
|
||||
i2c->inst->Instance = I2C3;
|
||||
i2c->scl_pin = I2C3_SCL_PIN;
|
||||
i2c->sda_pin = I2C3_SDA_PIN;
|
||||
break;
|
||||
}
|
||||
#endif
|
||||
#if defined(I2C4)
|
||||
#if defined(I2C4_ID)
|
||||
case 4: {
|
||||
i2c->inst = &I2CHandle4;
|
||||
i2c->inst->Instance = I2C4;
|
||||
i2c->scl_pin = I2C4_SCL_PIN;
|
||||
i2c->sda_pin = I2C4_SDA_PIN;
|
||||
break;
|
||||
}
|
||||
#endif
|
||||
@ -136,26 +144,6 @@ int omv_i2c_init(omv_i2c_t *i2c, uint32_t bus_id, uint32_t speed) {
|
||||
return -1;
|
||||
}
|
||||
|
||||
if (i2c->inst->Instance == ISC_I2C) {
|
||||
i2c->scl_pin = ISC_I2C_SCL_PIN;
|
||||
i2c->sda_pin = ISC_I2C_SDA_PIN;
|
||||
#if defined(TOF_I2C)
|
||||
} else if (i2c->inst->Instance == TOF_I2C) {
|
||||
i2c->scl_pin = TOF_I2C_SCL_PIN;
|
||||
i2c->sda_pin = TOF_I2C_SDA_PIN;
|
||||
#endif
|
||||
#if defined(FIR_I2C)
|
||||
} else if (i2c->inst->Instance == FIR_I2C) {
|
||||
i2c->scl_pin = FIR_I2C_SCL_PIN;
|
||||
i2c->sda_pin = FIR_I2C_SDA_PIN;
|
||||
#endif
|
||||
#if defined(ISC_I2C_ALT)
|
||||
} else if (i2c->inst->Instance == ISC_I2C_ALT) {
|
||||
i2c->scl_pin = ISC_I2C_ALT_SCL_PIN;
|
||||
i2c->sda_pin = ISC_I2C_ALT_SDA_PIN;
|
||||
#endif
|
||||
}
|
||||
|
||||
// Configure the I2C handle
|
||||
i2c->inst->Init.AddressingMode = I2C_ADDRESSINGMODE_7BIT;
|
||||
#if !defined(STM32F4)
|
||||
@ -215,28 +203,28 @@ static int omv_i2c_set_irq_state(omv_i2c_t *i2c, bool enabled) {
|
||||
IRQn_Type ev_irqn;
|
||||
IRQn_Type er_irqn;
|
||||
switch (i2c->id) {
|
||||
#if defined(I2C1)
|
||||
#if defined(I2C1_ID)
|
||||
case 1: {
|
||||
ev_irqn = I2C1_EV_IRQn;
|
||||
er_irqn = I2C1_ER_IRQn;
|
||||
break;
|
||||
}
|
||||
#endif
|
||||
#if defined(I2C2)
|
||||
#if defined(I2C2_ID)
|
||||
case 2: {
|
||||
ev_irqn = I2C2_EV_IRQn;
|
||||
er_irqn = I2C2_ER_IRQn;
|
||||
break;
|
||||
}
|
||||
#endif
|
||||
#if defined(I2C3)
|
||||
#if defined(I2C3_ID)
|
||||
case 3: {
|
||||
ev_irqn = I2C3_EV_IRQn;
|
||||
er_irqn = I2C3_ER_IRQn;
|
||||
break;
|
||||
}
|
||||
#endif
|
||||
#if defined(I2C4)
|
||||
#if defined(I2C4_ID)
|
||||
case 4: {
|
||||
ev_irqn = I2C4_EV_IRQn;
|
||||
er_irqn = I2C4_ER_IRQn;
|
||||
|
||||
@ -214,40 +214,33 @@ void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c) {
|
||||
omv_gpio_t scl_pin = NULL;
|
||||
omv_gpio_t sda_pin = NULL;
|
||||
|
||||
if (hi2c->Instance == ISC_I2C) {
|
||||
// Enable I2C clock.
|
||||
ISC_I2C_CLK_ENABLE();
|
||||
scl_pin = ISC_I2C_SCL_PIN;
|
||||
sda_pin = ISC_I2C_SDA_PIN;
|
||||
#if defined(FIR_I2C)
|
||||
} else if (hi2c->Instance == FIR_I2C) {
|
||||
// Enable I2C clock.
|
||||
FIR_I2C_CLK_ENABLE();
|
||||
scl_pin = FIR_I2C_SCL_PIN;
|
||||
sda_pin = FIR_I2C_SDA_PIN;
|
||||
if (0) {
|
||||
#if defined(I2C1_ID)
|
||||
} else if (hi2c->Instance == I2C1) {
|
||||
__HAL_RCC_I2C1_CLK_ENABLE();
|
||||
scl_pin = I2C1_SCL_PIN;
|
||||
sda_pin = I2C1_SDA_PIN;
|
||||
#endif
|
||||
#if defined(TOF_I2C)
|
||||
} else if (hi2c->Instance == TOF_I2C) {
|
||||
// Enable I2C clock.
|
||||
TOF_I2C_CLK_ENABLE();
|
||||
scl_pin = TOF_I2C_SCL_PIN;
|
||||
sda_pin = TOF_I2C_SDA_PIN;
|
||||
#if defined(I2C2_ID)
|
||||
} else if (hi2c->Instance == I2C2) {
|
||||
__HAL_RCC_I2C2_CLK_ENABLE();
|
||||
scl_pin = I2C2_SCL_PIN;
|
||||
sda_pin = I2C2_SDA_PIN;
|
||||
#endif
|
||||
#if defined(IMU_I2C)
|
||||
} else if (hi2c->Instance == IMU_I2C) {
|
||||
// Enable I2C clock.
|
||||
IMU_I2C_CLK_ENABLE();
|
||||
scl_pin = IMU_I2C_SCL_PIN;
|
||||
sda_pin = IMU_I2C_SDA_PIN;
|
||||
#if defined(I2C3_ID)
|
||||
} else if (hi2c->Instance == I2C3) {
|
||||
__HAL_RCC_I2C3_CLK_ENABLE();
|
||||
scl_pin = I2C3_SCL_PIN;
|
||||
sda_pin = I2C3_SDA_PIN;
|
||||
#endif
|
||||
#if defined(ISC_I2C_ALT)
|
||||
} else if (hi2c->Instance == ISC_I2C_ALT) {
|
||||
// Enable I2C clock.
|
||||
ISC_I2C_ALT_CLK_ENABLE();
|
||||
scl_pin = ISC_I2C_ALT_SCL_PIN;
|
||||
sda_pin = ISC_I2C_ALT_SDA_PIN;
|
||||
#if defined(I2C4_ID)
|
||||
} else if (hi2c->Instance == I2C4) {
|
||||
__HAL_RCC_I2C4_CLK_ENABLE();
|
||||
scl_pin = I2C4_SCL_PIN;
|
||||
sda_pin = I2C4_SDA_PIN;
|
||||
#endif
|
||||
}
|
||||
|
||||
if (scl_pin && sda_pin) {
|
||||
omv_gpio_config(scl_pin, OMV_GPIO_MODE_ALT_OD, OMV_GPIO_PULL_NONE, OMV_GPIO_SPEED_LOW, -1);
|
||||
omv_gpio_config(sda_pin, OMV_GPIO_MODE_ALT_OD, OMV_GPIO_PULL_NONE, OMV_GPIO_SPEED_LOW, -1);
|
||||
@ -255,33 +248,30 @@ void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c) {
|
||||
}
|
||||
|
||||
void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c) {
|
||||
if (hi2c->Instance == ISC_I2C) {
|
||||
ISC_I2C_FORCE_RESET();
|
||||
ISC_I2C_RELEASE_RESET();
|
||||
ISC_I2C_CLK_DISABLE();
|
||||
#if defined(FIR_I2C)
|
||||
} else if (hi2c->Instance == FIR_I2C) {
|
||||
FIR_I2C_FORCE_RESET();
|
||||
FIR_I2C_RELEASE_RESET();
|
||||
FIR_I2C_CLK_DISABLE();
|
||||
if (0) {
|
||||
#if defined(I2C1_ID)
|
||||
} else if (hi2c->Instance == I2C1) {
|
||||
__HAL_RCC_I2C1_FORCE_RESET();
|
||||
__HAL_RCC_I2C1_RELEASE_RESET();
|
||||
__HAL_RCC_I2C1_CLK_DISABLE();
|
||||
#endif
|
||||
#if defined(TOF_I2C)
|
||||
} else if (hi2c->Instance == TOF_I2C) {
|
||||
TOF_I2C_FORCE_RESET();
|
||||
TOF_I2C_RELEASE_RESET();
|
||||
TOF_I2C_CLK_DISABLE();
|
||||
#if defined(I2C2_ID)
|
||||
} else if (hi2c->Instance == I2C2) {
|
||||
__HAL_RCC_I2C2_FORCE_RESET();
|
||||
__HAL_RCC_I2C2_RELEASE_RESET();
|
||||
__HAL_RCC_I2C2_CLK_DISABLE();
|
||||
#endif
|
||||
#if defined(IMU_I2C)
|
||||
} else if (hi2c->Instance == IMU_I2C) {
|
||||
IMU_I2C_FORCE_RESET();
|
||||
IMU_I2C_RELEASE_RESET();
|
||||
IMU_I2C_CLK_DISABLE();
|
||||
#if defined(I2C3_ID)
|
||||
} else if (hi2c->Instance == I2C3) {
|
||||
__HAL_RCC_I2C3_FORCE_RESET();
|
||||
__HAL_RCC_I2C3_RELEASE_RESET();
|
||||
__HAL_RCC_I2C3_CLK_DISABLE();
|
||||
#endif
|
||||
#if defined(ISC_I2C_ALT)
|
||||
} else if (hi2c->Instance == ISC_I2C_ALT) {
|
||||
ISC_I2C_ALT_FORCE_RESET();
|
||||
ISC_I2C_ALT_RELEASE_RESET();
|
||||
ISC_I2C_ALT_CLK_DISABLE();
|
||||
#if defined(I2C4_ID)
|
||||
} else if (hi2c->Instance == I2C4) {
|
||||
__HAL_RCC_I2C4_FORCE_RESET();
|
||||
__HAL_RCC_I2C4_RELEASE_RESET();
|
||||
__HAL_RCC_I2C4_CLK_DISABLE();
|
||||
#endif
|
||||
}
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue
Block a user