mirror of
https://github.com/openmv/openmv.git
synced 2025-11-04 14:49:50 +08:00
ports/stm32: Refactor I2C bus definitions.
This commit is contained in:
parent
ec67194d68
commit
0195473235
@ -219,26 +219,12 @@
|
||||
#define OMV_AXI_QOS_MDMA_W_PRI 15 // Max pri to move data.
|
||||
|
||||
// Main image sensor I2C bus
|
||||
#define ISC_I2C (I2C3)
|
||||
#define ISC_I2C_ID (3)
|
||||
#define ISC_I2C_SPEED (OMV_I2C_SPEED_STANDARD)
|
||||
#define ISC_I2C_SCL_PIN (&omv_pin_A8_I2C3)
|
||||
#define ISC_I2C_SDA_PIN (&omv_pin_C9_I2C3)
|
||||
#define ISC_I2C_CLK_ENABLE() __I2C3_CLK_ENABLE()
|
||||
#define ISC_I2C_CLK_DISABLE() __I2C3_CLK_DISABLE()
|
||||
#define ISC_I2C_FORCE_RESET() __HAL_RCC_I2C3_FORCE_RESET()
|
||||
#define ISC_I2C_RELEASE_RESET() __HAL_RCC_I2C3_RELEASE_RESET()
|
||||
|
||||
// Thermal image sensor I2C bus
|
||||
#define FIR_I2C (I2C1)
|
||||
#define FIR_I2C_ID (1)
|
||||
#define FIR_I2C_SPEED (OMV_I2C_SPEED_FULL)
|
||||
#define FIR_I2C_SCL_PIN (&omv_pin_B8_I2C1)
|
||||
#define FIR_I2C_SDA_PIN (&omv_pin_B9_I2C1)
|
||||
#define FIR_I2C_CLK_ENABLE() __I2C1_CLK_ENABLE()
|
||||
#define FIR_I2C_CLK_DISABLE() __I2C1_CLK_DISABLE()
|
||||
#define FIR_I2C_FORCE_RESET() __HAL_RCC_I2C1_FORCE_RESET()
|
||||
#define FIR_I2C_RELEASE_RESET() __HAL_RCC_I2C1_RELEASE_RESET()
|
||||
|
||||
// Soft I2C bus
|
||||
#define SOFT_I2C_SIOC_PIN (&omv_pin_C10_GPIO)
|
||||
@ -301,7 +287,19 @@
|
||||
#define AUDIO_DFSDM_CLK_DISABLE() __HAL_RCC_DFSDM1_CLK_DISABLE()
|
||||
#define AUDIO_DFSDM_DMA_CLK_ENABLE() __HAL_RCC_DMA1_CLK_ENABLE()
|
||||
|
||||
// Physical I2C buses
|
||||
// I2C bus 1
|
||||
#define I2C1_ID (1)
|
||||
#define I2C1_SCL_PIN (&omv_pin_B8_I2C1)
|
||||
#define I2C1_SDA_PIN (&omv_pin_B9_I2C1)
|
||||
|
||||
// I2C bus 3
|
||||
#define I2C3_ID (3)
|
||||
#define I2C3_SCL_PIN (&omv_pin_A8_I2C3)
|
||||
#define I2C3_SDA_PIN (&omv_pin_C9_I2C3)
|
||||
|
||||
// Physical SPI buses.
|
||||
// SPI bus 5
|
||||
#define SPI5_ID (5)
|
||||
#define SPI5_SCLK_PIN (&omv_pin_F7_SPI5)
|
||||
#define SPI5_MISO_PIN (&omv_pin_F8_SPI5)
|
||||
|
||||
@ -12,258 +12,237 @@
|
||||
#define __OMV_BOARDCONFIG_H__
|
||||
|
||||
// Architecture info
|
||||
#define OMV_ARCH_STR "PORTENTA H7 8192 SDRAM" // 33 chars max
|
||||
#define OMV_BOARD_TYPE "H7"
|
||||
#define OMV_UNIQUE_ID_ADDR 0x1FF1E800 // Unique ID address.
|
||||
#define OMV_UNIQUE_ID_SIZE 3 // Unique ID size in words.
|
||||
#define OMV_UNIQUE_ID_OFFSET 4 // Bytes offset for multi-word UIDs.
|
||||
#define OMV_ARCH_STR "PORTENTA H7 8192 SDRAM" // 33 chars max
|
||||
#define OMV_BOARD_TYPE "H7"
|
||||
#define OMV_UNIQUE_ID_ADDR 0x1FF1E800 // Unique ID address.
|
||||
#define OMV_UNIQUE_ID_SIZE 3 // Unique ID size in words.
|
||||
#define OMV_UNIQUE_ID_OFFSET 4 // Bytes offset for multi-word UIDs.
|
||||
|
||||
#define OMV_XCLK_MCO (0U)
|
||||
#define OMV_XCLK_TIM (1U)
|
||||
#define OMV_XCLK_OSC (2U)
|
||||
#define OMV_XCLK_MCO (0U)
|
||||
#define OMV_XCLK_TIM (1U)
|
||||
#define OMV_XCLK_OSC (2U)
|
||||
|
||||
// Sensor external clock source.
|
||||
#define OMV_XCLK_SOURCE (OMV_XCLK_TIM)
|
||||
#define OMV_XCLK_SOURCE (OMV_XCLK_TIM)
|
||||
|
||||
// Sensor external clock timer frequency.
|
||||
#define OMV_XCLK_FREQUENCY (12000000)
|
||||
#define OMV_XCLK_FREQUENCY (12000000)
|
||||
|
||||
// Enable hardware JPEG
|
||||
#define OMV_HARDWARE_JPEG (1)
|
||||
#define OMV_HARDWARE_JPEG (1)
|
||||
|
||||
// Enable MDMA sensor offload.
|
||||
#define OMV_ENABLE_SENSOR_MDMA (1)
|
||||
#define OMV_ENABLE_SENSOR_MDMA (1)
|
||||
|
||||
// Enable additional GPIO banks.
|
||||
#define OMV_ENABLE_GPIO_BANK_F (1)
|
||||
#define OMV_ENABLE_GPIO_BANK_G (1)
|
||||
#define OMV_ENABLE_GPIO_BANK_H (1)
|
||||
#define OMV_ENABLE_GPIO_BANK_I (1)
|
||||
#define OMV_ENABLE_GPIO_BANK_J (1)
|
||||
#define OMV_ENABLE_GPIO_BANK_K (1)
|
||||
#define OMV_ENABLE_GPIO_BANK_F (1)
|
||||
#define OMV_ENABLE_GPIO_BANK_G (1)
|
||||
#define OMV_ENABLE_GPIO_BANK_H (1)
|
||||
#define OMV_ENABLE_GPIO_BANK_I (1)
|
||||
#define OMV_ENABLE_GPIO_BANK_J (1)
|
||||
#define OMV_ENABLE_GPIO_BANK_K (1)
|
||||
|
||||
// Enable sensor drivers
|
||||
#define OMV_ENABLE_OV2640 (0)
|
||||
#define OMV_ENABLE_OV5640 (1)
|
||||
#define OMV_ENABLE_OV7690 (0)
|
||||
#define OMV_ENABLE_OV7725 (1)
|
||||
#define OMV_ENABLE_OV9650 (0)
|
||||
#define OMV_ENABLE_MT9M114 (0)
|
||||
#define OMV_ENABLE_MT9V0XX (1)
|
||||
#define OMV_ENABLE_LEPTON (0)
|
||||
#define OMV_ENABLE_HM01B0 (1)
|
||||
#define OMV_ENABLE_HM0360 (1)
|
||||
#define OMV_ENABLE_GC2145 (0)
|
||||
#define OMV_ENABLE_OV2640 (0)
|
||||
#define OMV_ENABLE_OV5640 (1)
|
||||
#define OMV_ENABLE_OV7690 (0)
|
||||
#define OMV_ENABLE_OV7725 (1)
|
||||
#define OMV_ENABLE_OV9650 (0)
|
||||
#define OMV_ENABLE_MT9M114 (0)
|
||||
#define OMV_ENABLE_MT9V0XX (1)
|
||||
#define OMV_ENABLE_LEPTON (0)
|
||||
#define OMV_ENABLE_HM01B0 (1)
|
||||
#define OMV_ENABLE_HM0360 (1)
|
||||
#define OMV_ENABLE_GC2145 (0)
|
||||
|
||||
// OV7725 sensor settings
|
||||
#define OMV_OV7725_PLL_CONFIG (0x41) // x4
|
||||
#define OMV_OV7725_BANDING (0x7F)
|
||||
#define OMV_OV7725_PLL_CONFIG (0x41) // x4
|
||||
#define OMV_OV7725_BANDING (0x7F)
|
||||
|
||||
// MT9V0XX sensor settings
|
||||
#define MT9V0XX_XCLK_FREQ (25000000)
|
||||
#define MT9V0XX_XCLK_FREQ (25000000)
|
||||
|
||||
// OV5640 sensor settings
|
||||
#define OMV_ENABLE_OV5640_AF (1)
|
||||
#define OMV_OV5640_XCLK_FREQ (12500000)
|
||||
#define OMV_OV5640_PLL_CTRL2 (0x7E)
|
||||
#define OMV_OV5640_PLL_CTRL3 (0x13)
|
||||
#define OMV_OV5640_REV_Y_CHECK (0)
|
||||
#define OMV_OV5640_REV_Y_FREQ (12500000)
|
||||
#define OMV_OV5640_REV_Y_CTRL2 (0x7E)
|
||||
#define OMV_OV5640_REV_Y_CTRL3 (0x13)
|
||||
#define OMV_ENABLE_OV5640_AF (1)
|
||||
#define OMV_OV5640_XCLK_FREQ (12500000)
|
||||
#define OMV_OV5640_PLL_CTRL2 (0x7E)
|
||||
#define OMV_OV5640_PLL_CTRL3 (0x13)
|
||||
#define OMV_OV5640_REV_Y_CHECK (0)
|
||||
#define OMV_OV5640_REV_Y_FREQ (12500000)
|
||||
#define OMV_OV5640_REV_Y_CTRL2 (0x7E)
|
||||
#define OMV_OV5640_REV_Y_CTRL3 (0x13)
|
||||
|
||||
// FIR Module
|
||||
#define OMV_ENABLE_FIR_MLX90621 (1)
|
||||
#define OMV_ENABLE_FIR_MLX90640 (1)
|
||||
#define OMV_ENABLE_FIR_MLX90641 (1)
|
||||
#define OMV_ENABLE_FIR_AMG8833 (1)
|
||||
#define OMV_ENABLE_FIR_LEPTON (1)
|
||||
#define OMV_ENABLE_FIR_MLX90621 (1)
|
||||
#define OMV_ENABLE_FIR_MLX90640 (1)
|
||||
#define OMV_ENABLE_FIR_MLX90641 (1)
|
||||
#define OMV_ENABLE_FIR_AMG8833 (1)
|
||||
#define OMV_ENABLE_FIR_LEPTON (1)
|
||||
|
||||
// Enable WiFi debug
|
||||
#define OMV_ENABLE_WIFIDBG (0)
|
||||
#define OMV_ENABLE_WIFIDBG (0)
|
||||
|
||||
// Enable self-tests on first boot
|
||||
#define OMV_ENABLE_SELFTEST (0)
|
||||
#define OMV_ENABLE_SELFTEST (0)
|
||||
|
||||
// If buffer size is bigger than this threshold, the quality is reduced.
|
||||
// This is only used for JPEG images sent to the IDE not normal compression.
|
||||
#define JPEG_QUALITY_THRESH (320 * 240 * 2)
|
||||
#define JPEG_QUALITY_THRESH (320 * 240 * 2)
|
||||
|
||||
// Low and high JPEG QS.
|
||||
#define JPEG_QUALITY_LOW 50
|
||||
#define JPEG_QUALITY_HIGH 90
|
||||
#define JPEG_QUALITY_LOW 50
|
||||
#define JPEG_QUALITY_HIGH 90
|
||||
|
||||
// FB Heap Block Size
|
||||
#define OMV_UMM_BLOCK_SIZE 256
|
||||
#define OMV_UMM_BLOCK_SIZE 256
|
||||
|
||||
// Core VBAT for selftests
|
||||
#define OMV_CORE_VBAT "3.0"
|
||||
#define OMV_CORE_VBAT "3.0"
|
||||
|
||||
// USB IRQn.
|
||||
#define OMV_USB_IRQN (OTG_HS_IRQn)
|
||||
#define OMV_USB_ULPI (1)
|
||||
#define OMV_USB_ULPI_STP_PIN (&omv_pin_C0_OTG_HS)
|
||||
#define OMV_USB_ULPI_DIR_PIN (&omv_pin_I11_OTG_HS)
|
||||
#define OMV_USB_IRQN (OTG_HS_IRQn)
|
||||
#define OMV_USB_ULPI (1)
|
||||
#define OMV_USB_ULPI_STP_PIN (&omv_pin_C0_OTG_HS)
|
||||
#define OMV_USB_ULPI_DIR_PIN (&omv_pin_I11_OTG_HS)
|
||||
|
||||
// Defined for cpu frequency scaling to override the revid.
|
||||
#define OMV_MAX_CPU_FREQ (400)
|
||||
#define OMV_MAX_CPU_FREQ (400)
|
||||
|
||||
// PLL1 400MHz/40MHz for SDMMC and FDCAN
|
||||
// USB and RNG are clocked from the HSI48
|
||||
#define OMV_OSC_PLL1M (5)
|
||||
#define OMV_OSC_PLL1N (160)
|
||||
#define OMV_OSC_PLL1P (2)
|
||||
#define OMV_OSC_PLL1Q (16)
|
||||
#define OMV_OSC_PLL1R (2)
|
||||
#define OMV_OSC_PLL1VCI (RCC_PLL1VCIRANGE_2)
|
||||
#define OMV_OSC_PLL1VCO (RCC_PLL1VCOWIDE)
|
||||
#define OMV_OSC_PLL1FRAC (0)
|
||||
#define OMV_OSC_PLL1M (5)
|
||||
#define OMV_OSC_PLL1N (160)
|
||||
#define OMV_OSC_PLL1P (2)
|
||||
#define OMV_OSC_PLL1Q (16)
|
||||
#define OMV_OSC_PLL1R (2)
|
||||
#define OMV_OSC_PLL1VCI (RCC_PLL1VCIRANGE_2)
|
||||
#define OMV_OSC_PLL1VCO (RCC_PLL1VCOWIDE)
|
||||
#define OMV_OSC_PLL1FRAC (0)
|
||||
|
||||
// PLL2 200MHz for FMC and QSPI.
|
||||
#define OMV_OSC_PLL2M (5)
|
||||
#define OMV_OSC_PLL2N (80)
|
||||
#define OMV_OSC_PLL2P (2)
|
||||
#define OMV_OSC_PLL2Q (2)
|
||||
#define OMV_OSC_PLL2R (2)
|
||||
#define OMV_OSC_PLL2VCI (RCC_PLL2VCIRANGE_2)
|
||||
#define OMV_OSC_PLL2VCO (RCC_PLL2VCOWIDE)
|
||||
#define OMV_OSC_PLL2FRAC (0)
|
||||
#define OMV_OSC_PLL2M (5)
|
||||
#define OMV_OSC_PLL2N (80)
|
||||
#define OMV_OSC_PLL2P (2)
|
||||
#define OMV_OSC_PLL2Q (2)
|
||||
#define OMV_OSC_PLL2R (2)
|
||||
#define OMV_OSC_PLL2VCI (RCC_PLL2VCIRANGE_2)
|
||||
#define OMV_OSC_PLL2VCO (RCC_PLL2VCOWIDE)
|
||||
#define OMV_OSC_PLL2FRAC (0)
|
||||
|
||||
// PLL3 160MHz for ADC and SPI123
|
||||
#define OMV_OSC_PLL3M (5)
|
||||
#define OMV_OSC_PLL3N (160)
|
||||
#define OMV_OSC_PLL3P (2)
|
||||
#define OMV_OSC_PLL3Q (5)
|
||||
#define OMV_OSC_PLL3R (2)
|
||||
#define OMV_OSC_PLL3VCI (RCC_PLL3VCIRANGE_2)
|
||||
#define OMV_OSC_PLL3VCO (RCC_PLL3VCOWIDE)
|
||||
#define OMV_OSC_PLL3FRAC (0)
|
||||
#define OMV_OSC_PLL3M (5)
|
||||
#define OMV_OSC_PLL3N (160)
|
||||
#define OMV_OSC_PLL3P (2)
|
||||
#define OMV_OSC_PLL3Q (5)
|
||||
#define OMV_OSC_PLL3R (2)
|
||||
#define OMV_OSC_PLL3VCI (RCC_PLL3VCIRANGE_2)
|
||||
#define OMV_OSC_PLL3VCO (RCC_PLL3VCOWIDE)
|
||||
#define OMV_OSC_PLL3FRAC (0)
|
||||
|
||||
// Clock Sources
|
||||
#define OMV_OSC_PLL_CLKSOURCE RCC_PLLSOURCE_HSE
|
||||
#define OMV_OSC_USB_CLKSOURCE RCC_USBCLKSOURCE_HSI48
|
||||
#define OMV_OSC_RNG_CLKSOURCE RCC_RNGCLKSOURCE_HSI48
|
||||
#define OMV_OSC_ADC_CLKSOURCE RCC_ADCCLKSOURCE_PLL3
|
||||
#define OMV_OSC_SPI123_CLKSOURCE RCC_SPI123CLKSOURCE_PLL3
|
||||
#define OMV_OSC_PLL_CLKSOURCE RCC_PLLSOURCE_HSE
|
||||
#define OMV_OSC_USB_CLKSOURCE RCC_USBCLKSOURCE_HSI48
|
||||
#define OMV_OSC_RNG_CLKSOURCE RCC_RNGCLKSOURCE_HSI48
|
||||
#define OMV_OSC_ADC_CLKSOURCE RCC_ADCCLKSOURCE_PLL3
|
||||
#define OMV_OSC_SPI123_CLKSOURCE RCC_SPI123CLKSOURCE_PLL3
|
||||
|
||||
// HSE/HSI/CSI State
|
||||
#define OMV_OSC_HSE_STATE (RCC_HSE_BYPASS)
|
||||
#define OMV_OSC_HSI48_STATE (RCC_HSI48_ON)
|
||||
#define OMV_OSC_HSE_STATE (RCC_HSE_BYPASS)
|
||||
#define OMV_OSC_HSI48_STATE (RCC_HSI48_ON)
|
||||
|
||||
// Flash Latency
|
||||
#define OMV_FLASH_LATENCY (FLASH_LATENCY_2)
|
||||
#define OMV_FLASH_LATENCY (FLASH_LATENCY_2)
|
||||
|
||||
// Power supply configuration
|
||||
#define OMV_PWR_SUPPLY (PWR_SMPS_1V8_SUPPLIES_LDO)
|
||||
#define OMV_PWR_SUPPLY (PWR_SMPS_1V8_SUPPLIES_LDO)
|
||||
|
||||
// Linker script constants (see the linker script template stm32fxxx.ld.S).
|
||||
// Note: fb_alloc is a stack-based, dynamically allocated memory on FB.
|
||||
// The maximum available fb_alloc memory = FB_ALLOC_SIZE + FB_SIZE - (w*h*bpp).
|
||||
#define OMV_MAIN_MEMORY SRAM1 // data, bss and heap
|
||||
#define OMV_STACK_MEMORY DTCM // stack memory
|
||||
#define OMV_DMA_MEMORY SRAM3 // DMA buffers memory.
|
||||
#define OMV_FB_MEMORY DRAM // Framebuffer, fb_alloc
|
||||
#define OMV_JPEG_MEMORY DRAM // JPEG buffer memory buffer.
|
||||
#define OMV_JPEG_MEMORY_OFFSET (7M) // JPEG buffer is placed after FB/fballoc memory.
|
||||
#define OMV_VOSPI_MEMORY SRAM4 // VoSPI buffer memory.
|
||||
#define OMV_FB_OVERLAY_MEMORY AXI_SRAM // Fast fb_alloc memory.
|
||||
#define OMV_MAIN_MEMORY SRAM1 // data, bss and heap
|
||||
#define OMV_STACK_MEMORY DTCM // stack memory
|
||||
#define OMV_DMA_MEMORY SRAM3 // DMA buffers memory.
|
||||
#define OMV_FB_MEMORY DRAM // Framebuffer, fb_alloc
|
||||
#define OMV_JPEG_MEMORY DRAM // JPEG buffer memory buffer.
|
||||
#define OMV_JPEG_MEMORY_OFFSET (7M) // JPEG buffer is placed after FB/fballoc memory.
|
||||
#define OMV_VOSPI_MEMORY SRAM4 // VoSPI buffer memory.
|
||||
#define OMV_FB_OVERLAY_MEMORY AXI_SRAM // Fast fb_alloc memory.
|
||||
|
||||
#define OMV_FB_SIZE (4M) // FB memory: header + VGA/GS image
|
||||
#define OMV_FB_ALLOC_SIZE (3M) // minimum fb alloc size
|
||||
#define OMV_FB_OVERLAY_SIZE (480 * 1024) // Fast fb_alloc memory size.
|
||||
#define OMV_STACK_SIZE (64K)
|
||||
#define OMV_HEAP_SIZE (160K)
|
||||
#define OMV_SDRAM_SIZE (8 * 1024 * 1024) // This needs to be here for UVC firmware.
|
||||
#define OMV_FB_SIZE (4M) // FB memory: header + VGA/GS image
|
||||
#define OMV_FB_ALLOC_SIZE (3M) // minimum fb alloc size
|
||||
#define OMV_FB_OVERLAY_SIZE (480 * 1024) // Fast fb_alloc memory size.
|
||||
#define OMV_STACK_SIZE (64K)
|
||||
#define OMV_HEAP_SIZE (160K)
|
||||
#define OMV_SDRAM_SIZE (8 * 1024 * 1024) // This needs to be here for UVC firmware.
|
||||
|
||||
#define OMV_LINE_BUF_SIZE (11 * 1024) // Image line buffer round(2592 * 2BPP * 2 buffers).
|
||||
#define OMV_MSC_BUF_SIZE (2K) // USB MSC bot data
|
||||
#define OMV_VFS_BUF_SIZE (1K) // VFS sturct + FATFS file buffer (624 bytes)
|
||||
#define OMV_FIR_LEPTON_BUF_SIZE (1K) // FIR Lepton Packet Double Buffer (328 bytes)
|
||||
#define OMV_JPEG_BUF_SIZE (1024 * 1024) // IDE JPEG buffer (header + data).
|
||||
#define OMV_LINE_BUF_SIZE (11 * 1024) // Image line buffer round(2592 * 2BPP * 2 buffers).
|
||||
#define OMV_MSC_BUF_SIZE (2K) // USB MSC bot data
|
||||
#define OMV_VFS_BUF_SIZE (1K) // VFS sturct + FATFS file buffer (624 bytes)
|
||||
#define OMV_FIR_LEPTON_BUF_SIZE (1K) // FIR Lepton Packet Double Buffer (328 bytes)
|
||||
#define OMV_JPEG_BUF_SIZE (1024 * 1024) // IDE JPEG buffer (header + data).
|
||||
|
||||
// Memory map.
|
||||
#define OMV_FLASH_ORIGIN 0x08000000
|
||||
#define OMV_FLASH_LENGTH 2048K
|
||||
#define OMV_DTCM_ORIGIN 0x20000000 // Note accessible by CPU and MDMA only.
|
||||
#define OMV_DTCM_LENGTH 128K
|
||||
#define OMV_SRAM1_ORIGIN 0x30000000
|
||||
#define OMV_SRAM1_LENGTH 256K // SRAM1 + SRAM2
|
||||
#define OMV_SRAM3_ORIGIN 0x30040000 // Second half of SRAM3 reserved for M4.
|
||||
#define OMV_SRAM3_LENGTH 16K
|
||||
#define OMV_SRAM4_ORIGIN 0x38000000
|
||||
#define OMV_SRAM4_LENGTH 64K
|
||||
#define OMV_AXI_SRAM_ORIGIN 0x24000000
|
||||
#define OMV_AXI_SRAM_LENGTH 512K
|
||||
#define OMV_DRAM_ORIGIN 0xC0000000
|
||||
#define OMV_DRAM_LENGTH 8M
|
||||
#define OMV_CM4_RAM_ORIGIN 0x30044000 // Cortex-M4 memory.
|
||||
#define OMV_CM4_RAM_LENGTH 16K
|
||||
#define OMV_CM4_FLASH_ORIGIN 0x08020000
|
||||
#define OMV_CM4_FLASH_LENGTH 128K
|
||||
#define OMV_FLASH_ORIGIN 0x08000000
|
||||
#define OMV_FLASH_LENGTH 2048K
|
||||
#define OMV_DTCM_ORIGIN 0x20000000 // Note accessible by CPU and MDMA only.
|
||||
#define OMV_DTCM_LENGTH 128K
|
||||
#define OMV_SRAM1_ORIGIN 0x30000000
|
||||
#define OMV_SRAM1_LENGTH 256K // SRAM1 + SRAM2
|
||||
#define OMV_SRAM3_ORIGIN 0x30040000 // Second half of SRAM3 reserved for M4.
|
||||
#define OMV_SRAM3_LENGTH 16K
|
||||
#define OMV_SRAM4_ORIGIN 0x38000000
|
||||
#define OMV_SRAM4_LENGTH 64K
|
||||
#define OMV_AXI_SRAM_ORIGIN 0x24000000
|
||||
#define OMV_AXI_SRAM_LENGTH 512K
|
||||
#define OMV_DRAM_ORIGIN 0xC0000000
|
||||
#define OMV_DRAM_LENGTH 8M
|
||||
#define OMV_CM4_RAM_ORIGIN 0x30044000 // Cortex-M4 memory.
|
||||
#define OMV_CM4_RAM_LENGTH 16K
|
||||
#define OMV_CM4_FLASH_ORIGIN 0x08020000
|
||||
#define OMV_CM4_FLASH_LENGTH 128K
|
||||
|
||||
// Flash configuration.
|
||||
#define OMV_FLASH_FFS_ORIGIN 0x08020000
|
||||
#define OMV_FLASH_FFS_LENGTH 128K
|
||||
#define OMV_FLASH_TXT_ORIGIN 0x08040000
|
||||
#define OMV_FLASH_TXT_LENGTH 1792K
|
||||
#define OMV_FLASH_EXT_ORIGIN 0x90000000
|
||||
#define OMV_FLASH_EXT_LENGTH 16M
|
||||
#define OMV_FLASH_FFS_ORIGIN 0x08020000
|
||||
#define OMV_FLASH_FFS_LENGTH 128K
|
||||
#define OMV_FLASH_TXT_ORIGIN 0x08040000
|
||||
#define OMV_FLASH_TXT_LENGTH 1792K
|
||||
#define OMV_FLASH_EXT_ORIGIN 0x90000000
|
||||
#define OMV_FLASH_EXT_LENGTH 16M
|
||||
|
||||
// Domain 1 DMA buffers region.
|
||||
#define OMV_DMA_MEMORY_D1 AXI_SRAM
|
||||
#define OMV_DMA_MEMORY_D1_SIZE (16 * 1024) // Reserved memory for DMA buffers
|
||||
#define OMV_DMA_REGION_D1_BASE (OMV_AXI_SRAM_ORIGIN + OMV_FB_OVERLAY_SIZE)
|
||||
#define OMV_DMA_REGION_D1_SIZE MPU_REGION_SIZE_32KB
|
||||
#define OMV_DMA_MEMORY_D1 AXI_SRAM
|
||||
#define OMV_DMA_MEMORY_D1_SIZE (16 * 1024) // Reserved memory for DMA buffers
|
||||
#define OMV_DMA_REGION_D1_BASE (OMV_AXI_SRAM_ORIGIN + OMV_FB_OVERLAY_SIZE)
|
||||
#define OMV_DMA_REGION_D1_SIZE MPU_REGION_SIZE_32KB
|
||||
|
||||
// Domain 2 DMA buffers region.
|
||||
#define OMV_DMA_MEMORY_D2 SRAM3
|
||||
#define OMV_DMA_MEMORY_D2_SIZE (1 * 1024) // Reserved memory for DMA buffers
|
||||
#define OMV_DMA_REGION_D2_BASE (OMV_SRAM3_ORIGIN + (0 * 1024))
|
||||
#define OMV_DMA_REGION_D2_SIZE MPU_REGION_SIZE_16KB
|
||||
#define OMV_DMA_MEMORY_D2 SRAM3
|
||||
#define OMV_DMA_MEMORY_D2_SIZE (1 * 1024) // Reserved memory for DMA buffers
|
||||
#define OMV_DMA_REGION_D2_BASE (OMV_SRAM3_ORIGIN + (0 * 1024))
|
||||
#define OMV_DMA_REGION_D2_SIZE MPU_REGION_SIZE_16KB
|
||||
|
||||
// Domain 3 DMA buffers region.
|
||||
#define OMV_DMA_MEMORY_D3 SRAM4
|
||||
#define OMV_DMA_MEMORY_D3_SIZE (32 * 1024) // Reserved memory for DMA buffers
|
||||
#define OMV_DMA_REGION_D3_BASE (OMV_SRAM4_ORIGIN + (0 * 1024))
|
||||
#define OMV_DMA_REGION_D3_SIZE MPU_REGION_SIZE_64KB
|
||||
#define OMV_DMA_MEMORY_D3 SRAM4
|
||||
#define OMV_DMA_MEMORY_D3_SIZE (32 * 1024) // Reserved memory for DMA buffers
|
||||
#define OMV_DMA_REGION_D3_BASE (OMV_SRAM4_ORIGIN + (0 * 1024))
|
||||
#define OMV_DMA_REGION_D3_SIZE MPU_REGION_SIZE_64KB
|
||||
|
||||
// AXI QoS - Low-High (0:15) - default 0
|
||||
#define OMV_AXI_QOS_MDMA_R_PRI 14 // Max pri to move data.
|
||||
#define OMV_AXI_QOS_MDMA_W_PRI 15 // Max pri to move data.
|
||||
#define OMV_AXI_QOS_LTDC_R_PRI 15 // Max pri to read out the frame buffer.
|
||||
#define OMV_AXI_QOS_MDMA_R_PRI 14 // Max pri to move data.
|
||||
#define OMV_AXI_QOS_MDMA_W_PRI 15 // Max pri to move data.
|
||||
#define OMV_AXI_QOS_LTDC_R_PRI 15 // Max pri to read out the frame buffer.
|
||||
|
||||
// Image sensor I2C
|
||||
#define ISC_I2C (I2C3)
|
||||
#define ISC_I2C_ID (3)
|
||||
#define ISC_I2C_SPEED (OMV_I2C_SPEED_STANDARD)
|
||||
#define ISC_I2C_SCL_PIN (&omv_pin_H7_I2C3)
|
||||
#define ISC_I2C_SDA_PIN (&omv_pin_H8_I2C3)
|
||||
#define ISC_I2C_CLK_ENABLE() __I2C3_CLK_ENABLE()
|
||||
#define ISC_I2C_CLK_DISABLE() __I2C3_CLK_DISABLE()
|
||||
#define ISC_I2C_FORCE_RESET() __HAL_RCC_I2C3_FORCE_RESET()
|
||||
#define ISC_I2C_RELEASE_RESET() __HAL_RCC_I2C3_RELEASE_RESET()
|
||||
#define ISC_I2C_ID (3)
|
||||
#define ISC_I2C_SPEED (OMV_I2C_SPEED_STANDARD)
|
||||
|
||||
// Alternate I2C bus for the Portenta breakout
|
||||
#define ISC_I2C_ALT (I2C4)
|
||||
#define ISC_I2C_ALT_ID (4)
|
||||
#define ISC_I2C_ALT_SPEED (OMV_I2C_SPEED_STANDARD)
|
||||
#define ISC_I2C_ALT_SCL_PIN (&omv_pin_H11_I2C4)
|
||||
#define ISC_I2C_ALT_SDA_PIN (&omv_pin_H12_I2C4)
|
||||
#define ISC_I2C_ALT_CLK_ENABLE() __HAL_RCC_I2C4_CLK_ENABLE()
|
||||
#define ISC_I2C_ALT_CLK_DISABLE() __HAL_RCC_I2C4_CLK_DISABLE()
|
||||
#define ISC_I2C_ALT_FORCE_RESET() __HAL_RCC_I2C4_FORCE_RESET()
|
||||
#define ISC_I2C_ALT_RELEASE_RESET() __HAL_RCC_I2C4_RELEASE_RESET()
|
||||
#define ISC_I2C_ALT_ID (4)
|
||||
#define ISC_I2C_ALT_SPEED (OMV_I2C_SPEED_STANDARD)
|
||||
|
||||
// FIR I2C
|
||||
#define FIR_I2C (I2C3)
|
||||
#define FIR_I2C_ID (3)
|
||||
#define FIR_I2C_SPEED (OMV_I2C_SPEED_STANDARD)
|
||||
#define FIR_I2C_SCL_PIN (&omv_pin_H7_I2C3)
|
||||
#define FIR_I2C_SDA_PIN (&omv_pin_H8_I2C3)
|
||||
#define FIR_I2C_CLK_ENABLE() __I2C3_CLK_ENABLE()
|
||||
#define FIR_I2C_CLK_DISABLE() __I2C3_CLK_DISABLE()
|
||||
#define FIR_I2C_FORCE_RESET() __HAL_RCC_I2C3_FORCE_RESET()
|
||||
#define FIR_I2C_RELEASE_RESET() __HAL_RCC_I2C3_RELEASE_RESET()
|
||||
#define FIR_I2C_ID (3)
|
||||
#define FIR_I2C_SPEED (OMV_I2C_SPEED_STANDARD)
|
||||
|
||||
//#define SOFT_I2C_SIOC_PIN (&omv_pin_B10_GPIO)
|
||||
//#define SOFT_I2C_SIOD_PIN (&omv_pin_B11_GPIO)
|
||||
@ -308,6 +287,17 @@
|
||||
#define DCMI_VSYNC_PIN (&omv_pin_I5_DCMI)
|
||||
#define DCMI_PXCLK_PIN (&omv_pin_A6_DCMI)
|
||||
|
||||
// Physical I2C buses.
|
||||
// I2C bus 3
|
||||
#define I2C3_ID (3)
|
||||
#define I2C3_SCL_PIN (&omv_pin_H7_I2C3)
|
||||
#define I2C3_SDA_PIN (&omv_pin_H8_I2C3)
|
||||
|
||||
// I2C bus 4
|
||||
#define I2C4_ID (4)
|
||||
#define I2C4_SCL_PIN (&omv_pin_H11_I2C4)
|
||||
#define I2C4_SDA_PIN (&omv_pin_H12_I2C4)
|
||||
|
||||
// SAI4
|
||||
#define AUDIO_SAI (SAI4_Block_A)
|
||||
// SCKx frequency = SAI_KER_CK / MCKDIV / 2
|
||||
|
||||
@ -130,26 +130,12 @@
|
||||
#define OMV_FLASH_TXT_LENGTH 960K
|
||||
|
||||
// Main image sensor I2C bus
|
||||
#define ISC_I2C (I2C1)
|
||||
#define ISC_I2C_ID (1)
|
||||
#define ISC_I2C_SPEED (OMV_I2C_SPEED_STANDARD)
|
||||
#define ISC_I2C_SCL_PIN (&omv_pin_B8_I2C1)
|
||||
#define ISC_I2C_SDA_PIN (&omv_pin_B9_I2C1)
|
||||
#define ISC_I2C_CLK_ENABLE() __I2C1_CLK_ENABLE()
|
||||
#define ISC_I2C_CLK_DISABLE() __I2C1_CLK_DISABLE()
|
||||
#define ISC_I2C_FORCE_RESET() __HAL_RCC_I2C1_FORCE_RESET()
|
||||
#define ISC_I2C_RELEASE_RESET() __HAL_RCC_I2C1_RELEASE_RESET()
|
||||
|
||||
// Thermal image sensor I2C bus
|
||||
#define FIR_I2C (I2C2)
|
||||
#define FIR_I2C_ID (2)
|
||||
#define FIR_I2C_SPEED (OMV_I2C_SPEED_FULL)
|
||||
#define FIR_I2C_SCL_PIN (&omv_pin_B10_I2C2)
|
||||
#define FIR_I2C_SDA_PIN (&omv_pin_B11_I2C2)
|
||||
#define FIR_I2C_CLK_ENABLE() __I2C2_CLK_ENABLE()
|
||||
#define FIR_I2C_CLK_DISABLE() __I2C2_CLK_DISABLE()
|
||||
#define FIR_I2C_FORCE_RESET() __HAL_RCC_I2C2_FORCE_RESET()
|
||||
#define FIR_I2C_RELEASE_RESET() __HAL_RCC_I2C2_RELEASE_RESET()
|
||||
|
||||
// Soft I2C bus
|
||||
#define SOFT_I2C_SIOC_PIN (&omv_pin_B10_GPIO)
|
||||
@ -188,7 +174,19 @@
|
||||
#define DCMI_VSYNC_PIN (&omv_pin_B7_DCMI)
|
||||
#define DCMI_PXCLK_PIN (&omv_pin_A6_DCMI)
|
||||
|
||||
// Physical I2C buses
|
||||
// I2C bus 1
|
||||
#define I2C1_ID (1)
|
||||
#define I2C1_SCL_PIN (&omv_pin_B8_I2C1)
|
||||
#define I2C1_SDA_PIN (&omv_pin_B9_I2C1)
|
||||
|
||||
// I2C bus 2
|
||||
#define I2C2_ID (2)
|
||||
#define I2C2_SCL_PIN (&omv_pin_B10_I2C2)
|
||||
#define I2C2_SDA_PIN (&omv_pin_B11_I2C2)
|
||||
|
||||
// Physical SPI buses
|
||||
// SPI bus 2
|
||||
#define SPI2_ID (2)
|
||||
#define SPI2_SCLK_PIN (&omv_pin_B13_SPI2)
|
||||
#define SPI2_MISO_PIN (&omv_pin_B14_SPI2)
|
||||
|
||||
@ -130,26 +130,12 @@
|
||||
#define OMV_FLASH_TXT_LENGTH 1920K
|
||||
|
||||
// Main image sensor I2C bus
|
||||
#define ISC_I2C (I2C1)
|
||||
#define ISC_I2C_ID (1)
|
||||
#define ISC_I2C_SPEED (OMV_I2C_SPEED_STANDARD)
|
||||
#define ISC_I2C_SCL_PIN (&omv_pin_B8_I2C1)
|
||||
#define ISC_I2C_SDA_PIN (&omv_pin_B9_I2C1)
|
||||
#define ISC_I2C_CLK_ENABLE() __I2C1_CLK_ENABLE()
|
||||
#define ISC_I2C_CLK_DISABLE() __I2C1_CLK_DISABLE()
|
||||
#define ISC_I2C_FORCE_RESET() __HAL_RCC_I2C1_FORCE_RESET()
|
||||
#define ISC_I2C_RELEASE_RESET() __HAL_RCC_I2C1_RELEASE_RESET()
|
||||
|
||||
// FIR I2C bus
|
||||
#define FIR_I2C (I2C2)
|
||||
#define FIR_I2C_ID (2)
|
||||
#define FIR_I2C_SPEED (OMV_I2C_SPEED_FULL)
|
||||
#define FIR_I2C_SCL_PIN (&omv_pin_B10_I2C2)
|
||||
#define FIR_I2C_SDA_PIN (&omv_pin_B11_I2C2)
|
||||
#define FIR_I2C_CLK_ENABLE() __I2C2_CLK_ENABLE()
|
||||
#define FIR_I2C_CLK_DISABLE() __I2C2_CLK_DISABLE()
|
||||
#define FIR_I2C_FORCE_RESET() __HAL_RCC_I2C2_FORCE_RESET()
|
||||
#define FIR_I2C_RELEASE_RESET() __HAL_RCC_I2C2_RELEASE_RESET()
|
||||
|
||||
// Soft I2C bus
|
||||
#define SOFT_I2C_SIOC_PIN (&omv_pin_B10_GPIO)
|
||||
@ -188,7 +174,19 @@
|
||||
#define DCMI_VSYNC_PIN (&omv_pin_B7_DCMI)
|
||||
#define DCMI_PXCLK_PIN (&omv_pin_A6_DCMI)
|
||||
|
||||
// Physical I2C buses.
|
||||
// I2C bus 1
|
||||
#define I2C1_ID (1)
|
||||
#define I2C1_SCL_PIN (&omv_pin_B8_I2C1)
|
||||
#define I2C1_SDA_PIN (&omv_pin_B9_I2C1)
|
||||
|
||||
// I2C bus 2
|
||||
#define I2C2_ID (2)
|
||||
#define I2C2_SCL_PIN (&omv_pin_B10_I2C2)
|
||||
#define I2C2_SDA_PIN (&omv_pin_B11_I2C2)
|
||||
|
||||
// Physical SPI buses
|
||||
// SPI bus 2
|
||||
#define SPI2_ID (2)
|
||||
#define SPI2_SCLK_PIN (&omv_pin_B13_SPI2)
|
||||
#define SPI2_MISO_PIN (&omv_pin_B14_SPI2)
|
||||
|
||||
@ -217,26 +217,12 @@
|
||||
#define OMV_AXI_QOS_MDMA_W_PRI 15 // Max pri to move data.
|
||||
|
||||
// Main image sensor I2C bus
|
||||
#define ISC_I2C (I2C1)
|
||||
#define ISC_I2C_ID (1)
|
||||
#define ISC_I2C_SPEED (OMV_I2C_SPEED_STANDARD)
|
||||
#define ISC_I2C_SCL_PIN (&omv_pin_B8_I2C1)
|
||||
#define ISC_I2C_SDA_PIN (&omv_pin_B9_I2C1)
|
||||
#define ISC_I2C_CLK_ENABLE() __I2C1_CLK_ENABLE()
|
||||
#define ISC_I2C_CLK_DISABLE() __I2C1_CLK_DISABLE()
|
||||
#define ISC_I2C_FORCE_RESET() __HAL_RCC_I2C1_FORCE_RESET()
|
||||
#define ISC_I2C_RELEASE_RESET() __HAL_RCC_I2C1_RELEASE_RESET()
|
||||
|
||||
// Thermal image sensor I2C bus
|
||||
#define FIR_I2C (I2C2)
|
||||
#define FIR_I2C_ID (2)
|
||||
#define FIR_I2C_SPEED (OMV_I2C_SPEED_FULL)
|
||||
#define FIR_I2C_SCL_PIN (&omv_pin_B10_I2C2)
|
||||
#define FIR_I2C_SDA_PIN (&omv_pin_B11_I2C2)
|
||||
#define FIR_I2C_CLK_ENABLE() __I2C2_CLK_ENABLE()
|
||||
#define FIR_I2C_CLK_DISABLE() __I2C2_CLK_DISABLE()
|
||||
#define FIR_I2C_FORCE_RESET() __HAL_RCC_I2C2_FORCE_RESET()
|
||||
#define FIR_I2C_RELEASE_RESET() __HAL_RCC_I2C2_RELEASE_RESET()
|
||||
|
||||
// Soft I2C bus
|
||||
#define SOFT_I2C_SIOC_PIN (&omv_pin_B10_GPIO)
|
||||
@ -280,7 +266,18 @@
|
||||
#define DCMI_VSYNC_PIN (&omv_pin_B7_DCMI)
|
||||
#define DCMI_PXCLK_PIN (&omv_pin_A6_DCMI)
|
||||
|
||||
// Physical I2C buses.
|
||||
// I2C bus 1
|
||||
#define I2C1_ID (1)
|
||||
#define I2C1_SCL_PIN (&omv_pin_B8_I2C1)
|
||||
#define I2C1_SDA_PIN (&omv_pin_B9_I2C1)
|
||||
// I2C bus 2
|
||||
#define I2C2_ID (2)
|
||||
#define I2C2_SCL_PIN (&omv_pin_B10_I2C2)
|
||||
#define I2C2_SDA_PIN (&omv_pin_B11_I2C2)
|
||||
|
||||
// Physical SPI buses.
|
||||
// SPI bus 2
|
||||
#define SPI2_ID (2)
|
||||
#define SPI2_SCLK_PIN (&omv_pin_B13_SPI2)
|
||||
#define SPI2_MISO_PIN (&omv_pin_B14_SPI2)
|
||||
|
||||
@ -220,26 +220,12 @@
|
||||
#define OMV_AXI_QOS_MDMA_W_PRI 15 // Max pri to move data.
|
||||
|
||||
// Main image sensor I2C bus
|
||||
#define ISC_I2C (I2C1)
|
||||
#define ISC_I2C_ID (1)
|
||||
#define ISC_I2C_SPEED (OMV_I2C_SPEED_STANDARD)
|
||||
#define ISC_I2C_SCL_PIN (&omv_pin_B8_I2C1)
|
||||
#define ISC_I2C_SDA_PIN (&omv_pin_B9_I2C1)
|
||||
#define ISC_I2C_CLK_ENABLE() __I2C1_CLK_ENABLE()
|
||||
#define ISC_I2C_CLK_DISABLE() __I2C1_CLK_DISABLE()
|
||||
#define ISC_I2C_FORCE_RESET() __HAL_RCC_I2C1_FORCE_RESET()
|
||||
#define ISC_I2C_RELEASE_RESET() __HAL_RCC_I2C1_RELEASE_RESET()
|
||||
|
||||
// Thermal image sensor I2C bus
|
||||
#define FIR_I2C (I2C2)
|
||||
#define FIR_I2C_ID (2)
|
||||
#define FIR_I2C_SPEED (OMV_I2C_SPEED_FULL)
|
||||
#define FIR_I2C_SCL_PIN (&omv_pin_B10_I2C2)
|
||||
#define FIR_I2C_SDA_PIN (&omv_pin_B11_I2C2)
|
||||
#define FIR_I2C_CLK_ENABLE() __I2C2_CLK_ENABLE()
|
||||
#define FIR_I2C_CLK_DISABLE() __I2C2_CLK_DISABLE()
|
||||
#define FIR_I2C_FORCE_RESET() __HAL_RCC_I2C2_FORCE_RESET()
|
||||
#define FIR_I2C_RELEASE_RESET() __HAL_RCC_I2C2_RELEASE_RESET()
|
||||
|
||||
// Soft I2C bus.
|
||||
#define SOFT_I2C_SIOC_PIN (&omv_pin_B10_GPIO)
|
||||
@ -283,7 +269,18 @@
|
||||
#define DCMI_VSYNC_PIN (&omv_pin_B7_DCMI)
|
||||
#define DCMI_PXCLK_PIN (&omv_pin_A6_DCMI)
|
||||
|
||||
// Physical I2C buses.
|
||||
// I2C bus 1
|
||||
#define I2C1_ID (1)
|
||||
#define I2C1_SCL_PIN (&omv_pin_B8_I2C1)
|
||||
#define I2C1_SDA_PIN (&omv_pin_B9_I2C1)
|
||||
// I2C bus 2
|
||||
#define I2C2_ID (2)
|
||||
#define I2C2_SCL_PIN (&omv_pin_B10_I2C2)
|
||||
#define I2C2_SDA_PIN (&omv_pin_B11_I2C2)
|
||||
|
||||
// Physical SPI buses.
|
||||
// SPI bus 2
|
||||
#define SPI2_ID (2)
|
||||
#define SPI2_SCLK_PIN (&omv_pin_B13_SPI2)
|
||||
#define SPI2_MISO_PIN (&omv_pin_B14_SPI2)
|
||||
|
||||
@ -234,51 +234,23 @@
|
||||
#define OMV_AXI_QOS_MDMA_W_PRI 15 // Max pri to move data.
|
||||
|
||||
// Image sensor I2C configuration
|
||||
#define ISC_I2C (I2C2)
|
||||
#define ISC_I2C_ID (2)
|
||||
#define ISC_I2C_SPEED (OMV_I2C_SPEED_STANDARD)
|
||||
#define ISC_I2C_SCL_PIN (&omv_pin_H4_I2C2)
|
||||
#define ISC_I2C_SDA_PIN (&omv_pin_H5_I2C2)
|
||||
#define ISC_I2C_CLK_ENABLE() __HAL_RCC_I2C2_CLK_ENABLE()
|
||||
#define ISC_I2C_CLK_DISABLE() __HAL_RCC_I2C2_CLK_DISABLE()
|
||||
#define ISC_I2C_FORCE_RESET() __HAL_RCC_I2C2_FORCE_RESET()
|
||||
#define ISC_I2C_RELEASE_RESET() __HAL_RCC_I2C2_RELEASE_RESET()
|
||||
|
||||
// FIR sensor I2C configuration
|
||||
#define FIR_I2C (I2C1)
|
||||
#define FIR_I2C_ID (1)
|
||||
#define FIR_I2C_SPEED (OMV_I2C_SPEED_STANDARD)
|
||||
#define FIR_I2C_SCL_PIN (&omv_pin_B8_I2C1)
|
||||
#define FIR_I2C_SDA_PIN (&omv_pin_B9_I2C1)
|
||||
#define FIR_I2C_CLK_ENABLE() __HAL_RCC_I2C1_CLK_ENABLE()
|
||||
#define FIR_I2C_CLK_DISABLE() __HAL_RCC_I2C1_CLK_DISABLE()
|
||||
#define FIR_I2C_FORCE_RESET() __HAL_RCC_I2C1_FORCE_RESET()
|
||||
#define FIR_I2C_RELEASE_RESET() __HAL_RCC_I2C1_RELEASE_RESET()
|
||||
|
||||
// TOF sensor I2C configuration
|
||||
#define TOF_I2C (I2C4)
|
||||
#define TOF_I2C_ID (4)
|
||||
#define TOF_I2C_SPEED (OMV_I2C_SPEED_STANDARD)
|
||||
#define TOF_I2C_SCL_PIN (&omv_pin_B6_I2C4)
|
||||
#define TOF_I2C_SDA_PIN (&omv_pin_B7_I2C4)
|
||||
#define TOF_I2C_CLK_ENABLE() __HAL_RCC_I2C4_CLK_ENABLE()
|
||||
#define TOF_I2C_CLK_DISABLE() __HAL_RCC_I2C4_CLK_DISABLE()
|
||||
#define TOF_I2C_FORCE_RESET() __HAL_RCC_I2C4_FORCE_RESET()
|
||||
#define TOF_I2C_RELEASE_RESET() __HAL_RCC_I2C4_RELEASE_RESET()
|
||||
|
||||
// IMU I2C configuration
|
||||
#define IMU_I2C (I2C4)
|
||||
#define IMU_I2C_ID (4)
|
||||
#define IMU_I2C_SPEED (0x4030040B)
|
||||
#define IMU_I2C_SCL_PIN (&omv_pin_B6_I2C4)
|
||||
#define IMU_I2C_SDA_PIN (&omv_pin_B7_I2C4)
|
||||
#define IMU_I2C_CLK_ENABLE() __HAL_RCC_I2C4_CLK_ENABLE()
|
||||
#define IMU_I2C_CLK_DISABLE() __HAL_RCC_I2C4_CLK_DISABLE()
|
||||
#define IMU_I2C_FORCE_RESET() __HAL_RCC_I2C4_FORCE_RESET()
|
||||
#define IMU_I2C_RELEASE_RESET() __HAL_RCC_I2C4_RELEASE_RESET()
|
||||
#define IMU_CHIP_LSM6DS3 (1)
|
||||
#define OMV_IMU_X_Y_ROTATION_DEGREES 0
|
||||
#define OMV_IMU_MOUNTING_Z_DIRECTION -1
|
||||
#define OMV_IMU_X_Y_ROTATION_DEGREES (0)
|
||||
#define OMV_IMU_MOUNTING_Z_DIRECTION (-1)
|
||||
|
||||
// DCMI timer configuration
|
||||
#define DCMI_TIM (TIM1)
|
||||
@ -306,6 +278,20 @@
|
||||
#define DCMI_HSYNC_PIN (&omv_pin_A4_DCMI)
|
||||
#define DCMI_PXCLK_PIN (&omv_pin_A6_DCMI)
|
||||
|
||||
// Physical I2C buses.
|
||||
// I2C bus 1
|
||||
#define I2C1_ID (1)
|
||||
#define I2C1_SCL_PIN (&omv_pin_B8_I2C1)
|
||||
#define I2C1_SDA_PIN (&omv_pin_B9_I2C1)
|
||||
// I2C bus 2
|
||||
#define I2C2_ID (2)
|
||||
#define I2C2_SCL_PIN (&omv_pin_H4_I2C2)
|
||||
#define I2C2_SDA_PIN (&omv_pin_H5_I2C2)
|
||||
// I2C bus 4
|
||||
#define I2C4_ID (4)
|
||||
#define I2C4_SCL_PIN (&omv_pin_B6_I2C4)
|
||||
#define I2C4_SDA_PIN (&omv_pin_B7_I2C4)
|
||||
|
||||
#define ISC_SPI (SPI6)
|
||||
// SPI6 clock source is PLL3Q (80MHz/4 == 20MHz) - Minimum (164*240*8*27 = 8,501,760Hz)
|
||||
#define ISC_SPI_PRESCALER (SPI_BAUDRATEPRESCALER_4)
|
||||
|
||||
@ -226,26 +226,12 @@
|
||||
#define OMV_AXI_QOS_LTDC_R_PRI 15 // Max pri to read out the frame buffer.
|
||||
|
||||
// Main image sensor I2C bus
|
||||
#define ISC_I2C (I2C1)
|
||||
#define ISC_I2C_ID (1)
|
||||
#define ISC_I2C_SPEED (OMV_I2C_SPEED_STANDARD)
|
||||
#define ISC_I2C_SCL_PIN (&omv_pin_B8_I2C1)
|
||||
#define ISC_I2C_SDA_PIN (&omv_pin_B9_I2C1)
|
||||
#define ISC_I2C_CLK_ENABLE() __I2C1_CLK_ENABLE()
|
||||
#define ISC_I2C_CLK_DISABLE() __I2C1_CLK_DISABLE()
|
||||
#define ISC_I2C_FORCE_RESET() __HAL_RCC_I2C1_FORCE_RESET()
|
||||
#define ISC_I2C_RELEASE_RESET() __HAL_RCC_I2C1_RELEASE_RESET()
|
||||
|
||||
// Thermal image sensor I2C bus
|
||||
#define FIR_I2C (I2C2)
|
||||
#define FIR_I2C_ID (2)
|
||||
#define FIR_I2C_SPEED (OMV_I2C_SPEED_FULL)
|
||||
#define FIR_I2C_SCL_PIN (&omv_pin_B10_I2C2)
|
||||
#define FIR_I2C_SDA_PIN (&omv_pin_B11_I2C2)
|
||||
#define FIR_I2C_CLK_ENABLE() __I2C2_CLK_ENABLE()
|
||||
#define FIR_I2C_CLK_DISABLE() __I2C2_CLK_DISABLE()
|
||||
#define FIR_I2C_FORCE_RESET() __HAL_RCC_I2C2_FORCE_RESET()
|
||||
#define FIR_I2C_RELEASE_RESET() __HAL_RCC_I2C2_RELEASE_RESET()
|
||||
|
||||
// Soft I2C bus.
|
||||
#define SOFT_I2C_SIOC_PIN (&omv_pin_B10_GPIO)
|
||||
@ -285,13 +271,25 @@
|
||||
#define DCMI_VSYNC_PIN (&omv_pin_B7_DCMI)
|
||||
#define DCMI_PXCLK_PIN (&omv_pin_A6_DCMI)
|
||||
|
||||
// Physical SPI buses.
|
||||
// Physical I2C buses.
|
||||
// I2C bus 1
|
||||
#define I2C1_ID (1)
|
||||
#define I2C1_SCL_PIN (&omv_pin_B8_I2C1)
|
||||
#define I2C1_SDA_PIN (&omv_pin_B9_I2C1)
|
||||
// I2C bus 2
|
||||
#define I2C2_ID (2)
|
||||
#define I2C2_SCL_PIN (&omv_pin_B10_I2C2)
|
||||
#define I2C2_SDA_PIN (&omv_pin_B11_I2C2)
|
||||
|
||||
#define SPI_ID (5)
|
||||
// Physical SPI buses.
|
||||
// SPI bus 5
|
||||
#define SPI5_ID (5)
|
||||
#define SPI5_SCLK_PIN (&omv_pin_H6_SPI5)
|
||||
#define SPI5_MISO_PIN (&omv_pin_H7_SPI5)
|
||||
#define SPI5_MOSI_PIN (&omv_pin_J10_SPI5)
|
||||
#define SPI5_SSEL_PIN (&omv_pin_K1_GPIO)
|
||||
#define SPI5_DMA_TX_CHANNEL (DMA2_Stream4)
|
||||
#define SPI5_DMA_RX_CHANNEL (DMA2_Stream3)
|
||||
|
||||
// LCD Interface
|
||||
#define OMV_LCD_CONTROLLER (LTDC)
|
||||
|
||||
@ -100,31 +100,39 @@ int omv_i2c_init(omv_i2c_t *i2c, uint32_t bus_id, uint32_t speed) {
|
||||
i2c->sda_pin = NULL;
|
||||
|
||||
switch (bus_id) {
|
||||
#if defined(I2C1)
|
||||
#if defined(I2C1_ID)
|
||||
case 1: {
|
||||
i2c->inst = &I2CHandle1;
|
||||
i2c->inst->Instance = I2C1;
|
||||
i2c->scl_pin = I2C1_SCL_PIN;
|
||||
i2c->sda_pin = I2C1_SDA_PIN;
|
||||
break;
|
||||
}
|
||||
#endif
|
||||
#if defined(I2C2)
|
||||
#if defined(I2C2_ID)
|
||||
case 2: {
|
||||
i2c->inst = &I2CHandle2;
|
||||
i2c->inst->Instance = I2C2;
|
||||
i2c->scl_pin = I2C2_SCL_PIN;
|
||||
i2c->sda_pin = I2C2_SDA_PIN;
|
||||
break;
|
||||
}
|
||||
#endif
|
||||
#if defined(I2C3)
|
||||
#if defined(I2C3_ID)
|
||||
case 3: {
|
||||
i2c->inst = &I2CHandle3;
|
||||
i2c->inst->Instance = I2C3;
|
||||
i2c->scl_pin = I2C3_SCL_PIN;
|
||||
i2c->sda_pin = I2C3_SDA_PIN;
|
||||
break;
|
||||
}
|
||||
#endif
|
||||
#if defined(I2C4)
|
||||
#if defined(I2C4_ID)
|
||||
case 4: {
|
||||
i2c->inst = &I2CHandle4;
|
||||
i2c->inst->Instance = I2C4;
|
||||
i2c->scl_pin = I2C4_SCL_PIN;
|
||||
i2c->sda_pin = I2C4_SDA_PIN;
|
||||
break;
|
||||
}
|
||||
#endif
|
||||
@ -136,26 +144,6 @@ int omv_i2c_init(omv_i2c_t *i2c, uint32_t bus_id, uint32_t speed) {
|
||||
return -1;
|
||||
}
|
||||
|
||||
if (i2c->inst->Instance == ISC_I2C) {
|
||||
i2c->scl_pin = ISC_I2C_SCL_PIN;
|
||||
i2c->sda_pin = ISC_I2C_SDA_PIN;
|
||||
#if defined(TOF_I2C)
|
||||
} else if (i2c->inst->Instance == TOF_I2C) {
|
||||
i2c->scl_pin = TOF_I2C_SCL_PIN;
|
||||
i2c->sda_pin = TOF_I2C_SDA_PIN;
|
||||
#endif
|
||||
#if defined(FIR_I2C)
|
||||
} else if (i2c->inst->Instance == FIR_I2C) {
|
||||
i2c->scl_pin = FIR_I2C_SCL_PIN;
|
||||
i2c->sda_pin = FIR_I2C_SDA_PIN;
|
||||
#endif
|
||||
#if defined(ISC_I2C_ALT)
|
||||
} else if (i2c->inst->Instance == ISC_I2C_ALT) {
|
||||
i2c->scl_pin = ISC_I2C_ALT_SCL_PIN;
|
||||
i2c->sda_pin = ISC_I2C_ALT_SDA_PIN;
|
||||
#endif
|
||||
}
|
||||
|
||||
// Configure the I2C handle
|
||||
i2c->inst->Init.AddressingMode = I2C_ADDRESSINGMODE_7BIT;
|
||||
#if !defined(STM32F4)
|
||||
@ -215,28 +203,28 @@ static int omv_i2c_set_irq_state(omv_i2c_t *i2c, bool enabled) {
|
||||
IRQn_Type ev_irqn;
|
||||
IRQn_Type er_irqn;
|
||||
switch (i2c->id) {
|
||||
#if defined(I2C1)
|
||||
#if defined(I2C1_ID)
|
||||
case 1: {
|
||||
ev_irqn = I2C1_EV_IRQn;
|
||||
er_irqn = I2C1_ER_IRQn;
|
||||
break;
|
||||
}
|
||||
#endif
|
||||
#if defined(I2C2)
|
||||
#if defined(I2C2_ID)
|
||||
case 2: {
|
||||
ev_irqn = I2C2_EV_IRQn;
|
||||
er_irqn = I2C2_ER_IRQn;
|
||||
break;
|
||||
}
|
||||
#endif
|
||||
#if defined(I2C3)
|
||||
#if defined(I2C3_ID)
|
||||
case 3: {
|
||||
ev_irqn = I2C3_EV_IRQn;
|
||||
er_irqn = I2C3_ER_IRQn;
|
||||
break;
|
||||
}
|
||||
#endif
|
||||
#if defined(I2C4)
|
||||
#if defined(I2C4_ID)
|
||||
case 4: {
|
||||
ev_irqn = I2C4_EV_IRQn;
|
||||
er_irqn = I2C4_ER_IRQn;
|
||||
|
||||
@ -214,40 +214,33 @@ void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c) {
|
||||
omv_gpio_t scl_pin = NULL;
|
||||
omv_gpio_t sda_pin = NULL;
|
||||
|
||||
if (hi2c->Instance == ISC_I2C) {
|
||||
// Enable I2C clock.
|
||||
ISC_I2C_CLK_ENABLE();
|
||||
scl_pin = ISC_I2C_SCL_PIN;
|
||||
sda_pin = ISC_I2C_SDA_PIN;
|
||||
#if defined(FIR_I2C)
|
||||
} else if (hi2c->Instance == FIR_I2C) {
|
||||
// Enable I2C clock.
|
||||
FIR_I2C_CLK_ENABLE();
|
||||
scl_pin = FIR_I2C_SCL_PIN;
|
||||
sda_pin = FIR_I2C_SDA_PIN;
|
||||
if (0) {
|
||||
#if defined(I2C1_ID)
|
||||
} else if (hi2c->Instance == I2C1) {
|
||||
__HAL_RCC_I2C1_CLK_ENABLE();
|
||||
scl_pin = I2C1_SCL_PIN;
|
||||
sda_pin = I2C1_SDA_PIN;
|
||||
#endif
|
||||
#if defined(TOF_I2C)
|
||||
} else if (hi2c->Instance == TOF_I2C) {
|
||||
// Enable I2C clock.
|
||||
TOF_I2C_CLK_ENABLE();
|
||||
scl_pin = TOF_I2C_SCL_PIN;
|
||||
sda_pin = TOF_I2C_SDA_PIN;
|
||||
#if defined(I2C2_ID)
|
||||
} else if (hi2c->Instance == I2C2) {
|
||||
__HAL_RCC_I2C2_CLK_ENABLE();
|
||||
scl_pin = I2C2_SCL_PIN;
|
||||
sda_pin = I2C2_SDA_PIN;
|
||||
#endif
|
||||
#if defined(IMU_I2C)
|
||||
} else if (hi2c->Instance == IMU_I2C) {
|
||||
// Enable I2C clock.
|
||||
IMU_I2C_CLK_ENABLE();
|
||||
scl_pin = IMU_I2C_SCL_PIN;
|
||||
sda_pin = IMU_I2C_SDA_PIN;
|
||||
#if defined(I2C3_ID)
|
||||
} else if (hi2c->Instance == I2C3) {
|
||||
__HAL_RCC_I2C3_CLK_ENABLE();
|
||||
scl_pin = I2C3_SCL_PIN;
|
||||
sda_pin = I2C3_SDA_PIN;
|
||||
#endif
|
||||
#if defined(ISC_I2C_ALT)
|
||||
} else if (hi2c->Instance == ISC_I2C_ALT) {
|
||||
// Enable I2C clock.
|
||||
ISC_I2C_ALT_CLK_ENABLE();
|
||||
scl_pin = ISC_I2C_ALT_SCL_PIN;
|
||||
sda_pin = ISC_I2C_ALT_SDA_PIN;
|
||||
#if defined(I2C4_ID)
|
||||
} else if (hi2c->Instance == I2C4) {
|
||||
__HAL_RCC_I2C4_CLK_ENABLE();
|
||||
scl_pin = I2C4_SCL_PIN;
|
||||
sda_pin = I2C4_SDA_PIN;
|
||||
#endif
|
||||
}
|
||||
|
||||
if (scl_pin && sda_pin) {
|
||||
omv_gpio_config(scl_pin, OMV_GPIO_MODE_ALT_OD, OMV_GPIO_PULL_NONE, OMV_GPIO_SPEED_LOW, -1);
|
||||
omv_gpio_config(sda_pin, OMV_GPIO_MODE_ALT_OD, OMV_GPIO_PULL_NONE, OMV_GPIO_SPEED_LOW, -1);
|
||||
@ -255,33 +248,30 @@ void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c) {
|
||||
}
|
||||
|
||||
void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c) {
|
||||
if (hi2c->Instance == ISC_I2C) {
|
||||
ISC_I2C_FORCE_RESET();
|
||||
ISC_I2C_RELEASE_RESET();
|
||||
ISC_I2C_CLK_DISABLE();
|
||||
#if defined(FIR_I2C)
|
||||
} else if (hi2c->Instance == FIR_I2C) {
|
||||
FIR_I2C_FORCE_RESET();
|
||||
FIR_I2C_RELEASE_RESET();
|
||||
FIR_I2C_CLK_DISABLE();
|
||||
if (0) {
|
||||
#if defined(I2C1_ID)
|
||||
} else if (hi2c->Instance == I2C1) {
|
||||
__HAL_RCC_I2C1_FORCE_RESET();
|
||||
__HAL_RCC_I2C1_RELEASE_RESET();
|
||||
__HAL_RCC_I2C1_CLK_DISABLE();
|
||||
#endif
|
||||
#if defined(TOF_I2C)
|
||||
} else if (hi2c->Instance == TOF_I2C) {
|
||||
TOF_I2C_FORCE_RESET();
|
||||
TOF_I2C_RELEASE_RESET();
|
||||
TOF_I2C_CLK_DISABLE();
|
||||
#if defined(I2C2_ID)
|
||||
} else if (hi2c->Instance == I2C2) {
|
||||
__HAL_RCC_I2C2_FORCE_RESET();
|
||||
__HAL_RCC_I2C2_RELEASE_RESET();
|
||||
__HAL_RCC_I2C2_CLK_DISABLE();
|
||||
#endif
|
||||
#if defined(IMU_I2C)
|
||||
} else if (hi2c->Instance == IMU_I2C) {
|
||||
IMU_I2C_FORCE_RESET();
|
||||
IMU_I2C_RELEASE_RESET();
|
||||
IMU_I2C_CLK_DISABLE();
|
||||
#if defined(I2C3_ID)
|
||||
} else if (hi2c->Instance == I2C3) {
|
||||
__HAL_RCC_I2C3_FORCE_RESET();
|
||||
__HAL_RCC_I2C3_RELEASE_RESET();
|
||||
__HAL_RCC_I2C3_CLK_DISABLE();
|
||||
#endif
|
||||
#if defined(ISC_I2C_ALT)
|
||||
} else if (hi2c->Instance == ISC_I2C_ALT) {
|
||||
ISC_I2C_ALT_FORCE_RESET();
|
||||
ISC_I2C_ALT_RELEASE_RESET();
|
||||
ISC_I2C_ALT_CLK_DISABLE();
|
||||
#if defined(I2C4_ID)
|
||||
} else if (hi2c->Instance == I2C4) {
|
||||
__HAL_RCC_I2C4_FORCE_RESET();
|
||||
__HAL_RCC_I2C4_RELEASE_RESET();
|
||||
__HAL_RCC_I2C4_CLK_DISABLE();
|
||||
#endif
|
||||
}
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue
Block a user