Merge pull request #2518 from kwagyeman/kwabena/genx320_historgram

sensors/genx320: Enable histogram mode.
This commit is contained in:
Ibrahim Abdelkader 2024-12-04 17:58:47 +02:00 committed by GitHub
commit 093e6b7f5f
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GPG Key ID: B5690EEEBB952194
16 changed files with 3324 additions and 956 deletions

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@ -4,7 +4,8 @@
"examples/01-Camera/00-Snapshot", ".+", "^(?!None).*$", ""
"examples/01-Camera/01-Video-Recording", ".+", "^(?!None).*$", ""
"examples/01-Camera/02-Optical-Flow", ".+", "^(?!None).*$", ""
"examples/01-Camera/03-Event-Cameras", ".+", "(FROGEYE2020)", ""
"examples/01-Camera/03-Event-Cameras/01-Frogeye2020", ".+", "(FROGEYE2020)", ""
"examples/01-Camera/03-Event-Cameras/02-Genx320", ".+", "(GENX320)", ""
"examples/01-Camera/04-Global-Shutter", ".+", "(MT9V0X2|MT9V0X2-C|MT9V0X4|MT9V0X4-C)", ""
"examples/01-Camera/05-FLIR-Lepton", ".+", "(LEPTON|LEPTON-1.5|LEPTON-1.6|LEPTON-2.0|LEPTON-2.5|LEPTON-3.0|LEPTON-3.5)", ""
"examples/01-Camera/06-Time-of-Flight", ".+", "^(?!None).*$", ""

Can't render this file because it contains an unexpected character in line 1 and column 3.

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@ -13,58 +13,96 @@
#define __GENX320_H
/* Standard Includes */
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <stdint.h>
#include <math.h>
#include <stdint.h>
#include <stdio.h>
/* User Includes*/
#include "genx320_all_pub_registers.h"
#include "psee_issd.h"
/* Sensor I2C Address */
#define I2C_ADDRESS 0x3C
#define I2C_ADDRESS 0x3C
/* Sensor Chip ID */
#define SAPHIR_CHIP_ID 0x0014
#define SAPHIR_ES_ID 0x30501C01
#define SAPHIR_MP_ID 0xB0602003
#define SAPHIR_CHIP_ID 0x0014
#define SAPHIR_ES_ID 0x30501C01
#define SAPHIR_MP_ID 0xB0602003
/* Memory Bank Defines */
#define IMEM_START (0x00200000UL)
#define DMEM_START (0x00300000UL)
#define MEM_BANK_SELECT (0x0000F800UL)
#define MEM_BANK_MEM0 (0x0000F900UL)
#define IMEM_START 0x00200000UL
#define DMEM_START 0x00300000UL
#define MEM_BANK_SELECT 0x0000F800UL
#define MEM_BANK_MEM0 0x0000F900UL
#define GENX_MEM_BANK_IMEM 0b10
#define GENX_MEM_BANK_DMEM 0b11
/* RISC-V Defines */
#define RISC_BOOT_DONE 0x0ABCDEF
#define RISC_BOOT_DONE 0x0ABCDEF
/**
* @brief RISCV FW status structures definition
* @brief GenX320 Histomode pin structure definition
*/
typedef enum
{
fw_OK = 0U,
fw_Error_InvalidSize = 1U,
fw_Error_InvalidPointer = 2U,
fw_Flash_Error = 3U,
fw_Start_Error = 4U,
fw_Flashed_Already = 5U
typedef enum {
HM_EVT = 0U,
HM_HISTO = 1U,
} GenX320_Histomode;
/**
* @brief GenX320 Mipimode pin structure definition
*/
typedef enum {
MM_CPI = 0U,
MM_MIPI = 1U,
} GenX320_Mipimode;
/**
* @brief GenX320 Rommode pin structure definition
*/
typedef enum {
RM_IMEM = 0U,
RM_ROM = 1U,
} GenX320_Rommode;
/**
* @brief GenX320 Modules structures definition
*/
typedef enum {
EHC = 0U,
AFK = 1U,
STC = 2U,
ERC = 3U,
ERC_DFIFO = 4U,
ERC_ILG = 5U,
ERC_TDROP = 6U,
MIPI = 7U,
CPI = 8U,
CPU = 9U,
} GenX320_ModulesTypeDef;
/**
* @brief RISCV FW status structures definition
*/
typedef enum {
fw_OK = 0U,
fw_Error_InvalidSize = 1U,
fw_Error_InvalidPointer = 2U,
fw_Flash_Error = 3U,
fw_Start_Error = 4U,
fw_Flashed_Already = 5U
} FW_StatusTypeDef;
/**
* @brief Shadow register status structures definition
*/
typedef enum
{
shadow_valid = 0U,
shadow_not_valid = 01
* @brief Shadow register status structures definition
*/
typedef enum {
shadow_valid = 0U,
shadow_not_valid = 01
} Shadow_StatusTypeDef;
/**
* @brief Structure to hold the parameters for the bias
*/
* @brief Structure to hold the parameters for the bias
*/
typedef struct {
uint8_t pr;
uint8_t fo;
@ -78,11 +116,11 @@ typedef struct {
uint8_t invp;
uint8_t req_pu;
uint8_t sm_pdy;
}BIAS_Params_t;
} BIAS_Params_t;
/**
* @brief Structure to hold the border value for the Activity Map
*/
* @brief Structure to hold the border value for the Activity Map
*/
typedef struct {
uint16_t x0;
uint16_t x1;
@ -94,66 +132,247 @@ typedef struct {
uint16_t y2;
uint16_t y3;
uint16_t y4;
}AM_Borders_t;
} AM_Borders_t;
/**
* @brief Structure to hold the risc-v firmware
*/
typedef struct {
uint32_t address;
uint32_t value;
uint32_t address;
uint32_t value;
} Firmware;
/**
* @brief Structure to hold AFK Invalidation
* @brief Structure to hold the sensor clock frequencies
*/
typedef struct {
uint32_t df_wait_time;
uint32_t df_timeout;
} Invalidation;
/**
* @brief Structure to hold the sensor clock frequencies
*/
typedef struct {
uint32_t in_freq;
uint32_t sys_freq;
uint32_t evt_icn_freq;
uint32_t cpu_ss_freq;
uint32_t pll_in_freq;
uint32_t pll_vco_freq;
uint32_t phy_freq;
uint32_t mipi_freq;
uint32_t esc_freq;
uint32_t in_freq;
uint32_t sys_freq;
uint32_t evt_icn_freq;
uint32_t cpu_ss_freq;
uint32_t pll_in_freq;
uint32_t pll_vco_freq;
uint32_t phy_freq;
uint32_t mipi_freq;
uint32_t esc_freq;
} clk_freq_dict;
/**
* @brief Sensor Boot mode structure definition
*/
typedef enum
{
ROM_BOOT = 0U,
IMEM_BOOT = 1U
} Boot_Mode;
/**
* @brief Enum to hold the parameters for the bias
*/
typedef enum {
PR,
FO,
FES,
HPF,
DIFF_ON,
DIFF,
DIFF_OFF,
INV,
REFR,
INVP,
REQ_PU,
SM_PDY,
PR,
FO,
FES,
HPF,
DIFF_ON,
DIFF,
DIFF_OFF,
INV,
REFR,
INVP,
REQ_PU,
SM_PDY,
} BIAS_Name_t;
/**
* @brief Structure to hold AFK Invalidation
*/
typedef struct {
uint32_t dt_fifo_wait_time;
uint32_t dt_fifo_timeout;
} AFK_InvalidationTypeDef;
/**
* @brief AFK Init structures definition
*/
typedef enum {
AFK_INIT_NOT_DONE = 0x00U,
AFK_INIT_DONE = 0x01U,
} AFK_InitTypeDef;
/**
* @brief AFK Status structures definition
*/
typedef enum {
AFK_OK = 0x00U,
AFK_BUSY = 0x01U,
AFK_ERROR = 0x02U,
AFK_STATE_ERROR = 0x03U,
AFK_STATS_ERROR = 0x04U,
AFK_FREQ_ERROR = 0x05U,
AFK_CLK_ERROR = 0x06U,
} AFK_StatusTypeDef;
/**
* @brief EHC State structures definition
*/
typedef enum {
AFK_STATE_RESET = 0x00U,
AFK_STATE_READY = 0x01U,
AFK_STATE_BUSY = 0x02U,
} AFK_StateTypeDef;
/**
* @brief EHC Statistics structures definition
*/
typedef enum {
AFK_STATS_RESET = 0x00U,
AFK_STATS_READY = 0x01U,
} AFK_StatisticsTypeDef;
/**
* @brief AFK Handle Structure definition
*/
typedef struct
{
AFK_InitTypeDef Init; /*!< AFK Init */
AFK_StateTypeDef State; /*!< AFK State */
AFK_StatisticsTypeDef Stats; /*!< AFK Statistics */
uint16_t f_min; /*!< AFK Minimum frequency */
uint16_t f_max; /*!< AFK Maximum frequency */
uint32_t stats_acc; /*!< AFK Statistics Accumulation time */
} AFK_HandleTypeDef;
/**
* @brief EHC Init structures definition
*/
typedef enum {
EHC_INIT_NOT_DONE = 0x00U,
EHC_INIT_DONE = 0x01U,
} EHC_InitTypeDef;
/**
* @brief EHC Status structures definition
*/
typedef enum {
EHC_OK = 0x00U,
EHC_BUSY = 0x01U,
EHC_ERROR = 0x02U,
EHC_STATE_ERROR = 0x03U,
EHC_PARAM_ERROR = 0x04U,
} EHC_StatusTypeDef;
/**
* @brief EHC State structures definition
*/
typedef enum {
EHC_STATE_RESET = 0x00U,
EHC_STATE_READY = 0x01U,
EHC_STATE_BUSY = 0x02U,
} EHC_StateTypeDef;
/**
* @brief EHC Algo structures definition
*/
typedef enum {
EHC_ALGO_DIFF3D = 0x00U,
EHC_ALGO_HISTO3D = 0x01U,
EHC_ALGO_RESET = 0x02U,
} EHC_AlgoTypeDef;
/**
* @brief EHC Trigger structures definition
*/
typedef enum {
EHC_TRIGGER_EVENT_RATE = 0x00U,
EHC_TRIGGER_INTEGRATION_PERIOD = 0x01U,
EHC_TRIGGER_RESET = 0x02U,
} EHC_TriggerTypeDef;
/**
* @brief EHC Padding structures definition
*/
typedef enum {
EHC_WITHOUT_PADDING = 0x00U,
EHC_WITH_PADDING = 0x01U,
EHC_PADDING_RESET = 0x02U,
} EHC_PaddingTypeDef;
/**
* @brief EHC Override structures definition
*/
typedef enum {
EHC_NO_OVERRIDE = 0x00U,
EHC_OVERRIDE = 0x01U,
EHC_OVERRIDE_RESET = 0x02U,
} EHC_OverrideTypeDef;
/**
* @brief EHC Handle Structure definition
*/
typedef struct
{
EHC_InitTypeDef Init; /*!< EHC Init */
EHC_StateTypeDef State; /*!< EHC State */
EHC_AlgoTypeDef Algo; /*!< EHC Algo */
EHC_TriggerTypeDef Trigger; /*!< EHC Trigger */
EHC_PaddingTypeDef Padding; /*!< EHC Padding */
EHC_OverrideTypeDef Override; /*!< EHC Override */
uint32_t accumulation_period; /*!< EHC Accumulation Period */
uint8_t p_bits_size; /*!< EHC Positive bits size */
uint8_t n_bits_size; /*!< EHC Negative bits size */
} EHC_HandleTypeDef;
/**
* @brief STC Params structures definition
*/
typedef struct {
uint16_t Presc;
uint16_t Mult;
uint16_t Timeout;
} STC_ParamsTypeDef;
/**
* @brief STC Init structures definition
*/
typedef enum {
STC_INIT_NOT_DONE = 0x00U,
STC_INIT_DONE = 0x01U,
} STC_InitTypeDef;
/**
* @brief STC Status structures definition
*/
typedef enum {
STC_OK = 0x00U,
STC_BUSY = 0x01U,
STC_ERROR = 0x02U,
STC_STATE_ERROR = 0x03U,
STC_THRESHOLD_ERROR = 0x04U,
STC_CLK_ERROR = 0x05U,
} STC_StatusTypeDef;
/**
* @brief STC State structures definition
*/
typedef enum {
STC_STATE_RESET = 0x00U,
STC_STATE_READY = 0x01U,
STC_STATE_BUSY = 0x02U,
} STC_StateTypeDef;
/**
* @brief STC Mode structures definition
*/
typedef enum {
STC_MODE_RESET = 0x00U,
STC_MODE_STC = 0x01U,
STC_MODE_TRAIL = 0x02U,
STC_MODE_STC_TRAIL = 0x03U,
} STC_ModeTypeDef;
/**
* @brief STC Handle Structure definition
*/
typedef struct
{
STC_InitTypeDef Init; /*!< STC block Init */
STC_StateTypeDef State; /*!< STC block State */
STC_ModeTypeDef Mode; /*!< STC Mode */
STC_ParamsTypeDef Params; /*!< STC Params */
} STC_HandleTypeDef;
/* Constants/Variables to hold default bias */
extern const BIAS_Params_t genx320es_default_biases;
extern const BIAS_Params_t genx320mp_default_biases;
@ -168,7 +387,7 @@ extern const struct issd dcmi_histo;
extern const struct issd *current_issd;
/* Variable to hold the current boot mode */
extern Boot_Mode genx320_boot_mode;
extern GenX320_Rommode genx320_boot_mode;
/* Sensor Register Manipulation Functions */
extern void psee_sensor_read(uint16_t register_address, uint32_t *buf);
@ -176,26 +395,29 @@ extern void psee_sensor_write(uint16_t register_address, uint32_t register_data)
/* Sensor Bring Up Functions */
extern void psee_sensor_init(const struct issd *);
extern void psee_sensor_destroy(const struct issd *);
extern void psee_sensor_start(const struct issd *);
extern void psee_sensor_stop(const struct issd *);
extern Boot_Mode psee_detect_boot_mode();
extern const struct issd *psee_open_evt();
extern void psee_sensor_set_bias(BIAS_Name_t bias, uint32_t val);
extern void psee_sensor_set_biases(const BIAS_Params_t *bias);
extern void psee_sensor_set_CPI_EVT20();
extern void psee_sensor_set_CPI_HISTO();
extern void psee_sensor_set_flip(uint32_t flip_x, uint32_t flip_y);
extern void psee_sensor_powerdown();
extern void psee_sensor_destroy();
/* Operating Mode Control Functions */
extern void psee_PM3C_config();
extern void psee_PM3C_Histo_config();
extern void psee_PM2_config();
extern void psee_PM2_Histo_config();
/* Firmware flashing functions */
extern FW_StatusTypeDef psee_write_firmware(const Firmware *firmwareArray, uint32_t n_bytes);
extern FW_StatusTypeDef psee_start_firmware(Boot_Mode boot_mode);
extern FW_StatusTypeDef psee_reset_firmware(Boot_Mode boot_mode);
extern FW_StatusTypeDef psee_write_firmware_single(const Firmware *firmwareArray, uint32_t n_bytes);
extern FW_StatusTypeDef psee_test_firmware_single(const Firmware *firmwareArray, uint32_t n_bytes);
extern uint32_t psee_read_firmware_register(uint32_t reg_address);
extern FW_StatusTypeDef psee_write_firmware_burst(const Firmware *firmwareArray, uint32_t n_bytes);
extern FW_StatusTypeDef psee_start_firmware(GenX320_Rommode boot_mode, uint32_t jump_add);
extern FW_StatusTypeDef psee_reset_firmware(GenX320_Rommode boot_mode);
/* Mailbox Communication Functions */
extern uint32_t psee_get_mbx_cmd_ptr();
@ -219,15 +441,72 @@ extern uint32_t psee_sensor_read_imem(uint32_t address);
/* Statistics Register Read Functions */
extern void psee_read_ro_lp_evt_cnt(uint32_t *p_data);
extern uint32_t psee_read_ro_evt_cd_cnt();
extern uint32_t psee_read_afk_flicker_evt_cnt();
extern uint32_t psee_read_afk_total_evt_cnt();
/* Activity Map Configuration Functions */
extern void psee_configure_activity_map();
extern void psee_set_default_XY_borders(AM_Borders_t *border);
/* AFK Configuration Functions */
extern void psee_enable_afk(uint16_t min_freq, uint16_t max_freq);
extern void psee_disable_afk();
extern AFK_StatusTypeDef psee_afk_init(AFK_HandleTypeDef *afk);
extern AFK_StatusTypeDef psee_afk_activate(AFK_HandleTypeDef *afk,
uint16_t f_min,
uint16_t f_max,
uint16_t evt_clk_freq);
extern AFK_StatusTypeDef psee_afk_deactivate(AFK_HandleTypeDef *afk);
extern AFK_StatusTypeDef psee_afk_start_statistics(AFK_HandleTypeDef *afk,
uint32_t acc_time);
extern AFK_StatusTypeDef psee_afk_stop_statistics(AFK_HandleTypeDef *afk);
extern uint32_t psee_afk_read_total_evt_cnt(AFK_HandleTypeDef *afk);
extern uint32_t psee_afk_read_flicker_evt_cnt(AFK_HandleTypeDef *afk);
extern uint16_t psee_afk_get_f_min(AFK_HandleTypeDef *afk);
extern uint16_t psee_afk_get_f_max(AFK_HandleTypeDef *afk);
extern AFK_StateTypeDef psee_afk_get_state(AFK_HandleTypeDef *afk);
extern AFK_StatisticsTypeDef psee_afk_get_stats(AFK_HandleTypeDef *afk);
extern uint32_t psee_afk_get_stats_acc_time(AFK_HandleTypeDef *afk);
/* EHC Configuration Functions */
extern const struct issd *psee_open_ehc();
extern EHC_StatusTypeDef psee_ehc_init(EHC_HandleTypeDef *ehc);
extern EHC_StatusTypeDef psee_ehc_activate(EHC_HandleTypeDef *ehc,
EHC_AlgoTypeDef sel_algo,
uint8_t p_bits_size,
uint8_t n_bits_size,
uint32_t integration_period,
EHC_PaddingTypeDef bits_padding);
extern EHC_StatusTypeDef psee_ehc_deactivate(EHC_HandleTypeDef *ehc);
extern EHC_AlgoTypeDef psee_ehc_get_algo(EHC_HandleTypeDef *ehc);
extern uint8_t psee_ehc_get_p_bits_size(EHC_HandleTypeDef *ehc);
extern uint8_t psee_ehc_get_n_bits_size(EHC_HandleTypeDef *ehc);
extern uint32_t psee_ehc_get_accumulation_period(EHC_HandleTypeDef *ehc);
extern EHC_PaddingTypeDef psee_ehc_get_bits_padding(EHC_HandleTypeDef *ehc);
extern EHC_StatusTypeDef psee_ehc_activate_override(EHC_HandleTypeDef *ehc,
EHC_AlgoTypeDef sel_algo,
uint8_t p_bits_size,
uint8_t n_bits_size,
uint32_t integration_period,
EHC_PaddingTypeDef bits_padding,
EHC_OverrideTypeDef override);
extern EHC_StatusTypeDef psee_ehc_start_histo_acc(EHC_HandleTypeDef *ehc);
extern EHC_StatusTypeDef psee_ehc_drain_histo(EHC_HandleTypeDef *ehc);
extern void psee_close_ehc(const struct issd *issd);
/* STC Configuration Functions */
extern STC_StatusTypeDef psee_stc_init(STC_HandleTypeDef *stc);
extern STC_StatusTypeDef psee_stc_only_activate(STC_HandleTypeDef *stc,
uint32_t stc_threshold,
uint8_t evt_clk_freq);
extern STC_StatusTypeDef psee_trail_only_activate(STC_HandleTypeDef *stc,
uint32_t trail_threshold,
uint8_t evt_clk_freq);
extern STC_StatusTypeDef psee_stc_trail_activate(STC_HandleTypeDef *stc,
uint32_t stc_threshold,
uint32_t trail_threshold,
uint8_t evt_clk_freq);
extern STC_StatusTypeDef psee_stc_trail_deactivate(STC_HandleTypeDef *stc);
extern STC_StateTypeDef psee_stc_get_state(STC_HandleTypeDef *stc);
extern STC_ModeTypeDef psee_stc_get_mode(STC_HandleTypeDef *stc);
extern uint16_t psee_stc_get_params_mult(STC_HandleTypeDef *stc);
extern uint16_t psee_stc_get_params_presc(STC_HandleTypeDef *stc);
extern uint16_t psee_stc_get_params_timeout(STC_HandleTypeDef *stc);
#endif

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@ -11,8 +11,8 @@
* This is an automatically generated file *
**********************************************************************************************************************/
#ifndef __ISSD_CPI_H
#define __ISSD_CPI_H
#ifndef __ISSD_CPI_EVT_H
#define __ISSD_CPI_EVT_H
#include "psee_issd.h"

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@ -0,0 +1,161 @@
/**********************************************************************************************************************
* Copyright (c) Prophesee S.A. *
* *
* Licensed under the Apache License, Version 2.0 (the "License"); *
* you may not use this file except in compliance with the License. *
* You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 *
* Unless required by applicable law or agreed to in writing, software distributed under the License is distributed *
* on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. *
* See the License for the specific language governing permissions and limitations under the License. *
* *
* This is an automatically generated file *
**********************************************************************************************************************/
#ifndef __ISSD_CPI_HISTO_H
#define __ISSD_CPI_HISTO_H
#include "psee_issd.h"
static const struct reg_op dcmi_init_seq[] = {
{.op = WRITE, .args = {.write = {0x00B8UL, 0x00000002}} }, // saphir/sram_initn
{.op = WRITE, .args = {.write = {0x00BCUL, 0x00007FFF}} }, // saphir/sram_pd0
{.op = WRITE, .args = {.write = {0x9008UL, 0x00000320}} }, // saphir/ro/time_base_ctrl Write fields: time_base_enable
{.op = WRITE, .args = {.write = {0x9008UL, 0x00010320}} }, // saphir/ro/time_base_ctrl Write fields: time_base_srst
{.op = WRITE, .args = {.write = {0x020CUL, 0x00000015}} }, // saphir/rtc_clk_ctrl Write fields: rtc_clk_en|rtc_clk_div
{.op = WRITE, .args = {.write = {0x0204UL, 0x00004D6C}} }, // saphir/sys_clk_ctrl Write fields: sys_clk_auto_mode
{.op = WRITE, .args = {.write = {0x0210UL, 0x00000C00}} }, // saphir/evt_icn_clk_ctrl Write fields: ro_clk_en|esp_clk_en
{.op = WRITE, .args = {.write = {0x9008UL, 0x000000A0}} }, // saphir/ro/time_base_ctrl Write fields: us_counter_max
{.op = WRITE, .args = {.write = {0x004CUL, 0x00201F40}} }, // saphir/adc_control
{.op = WRITE, .args = {.write = {0x00B8UL, 0x00000042}} }, // saphir/sram_initn Write fields: cpi_initn
{.op = WRITE, .args = {.write = {0x00C0UL, 0x00000078}} }, // saphir/sram_pd1 Write fields: cpi_pd
{.op = WRITE, .args = {.write = {0x800CUL, 0x0001014A}} }, // saphir/cpi/packet_time_control Write fields: packet_period
{.op = WRITE, .args = {.write = {0x8008UL, 0x00000140}} }, // saphir/cpi/packet_size_control Write fields: packet_size
{.op = WRITE, .args = {.write = {0x8010UL, 0x00000140}} }, // saphir/cpi/frame_size_control Write fields: frame_size
{.op = WRITE, .args = {.write = {0x8000UL, 0x0001EEA1}} }, // saphir/cpi/pipeline_control Write fields: enable|clk_out_en|clk_control_inversion|packet_fixed_size_enable|packet_fixed_rate_enable|frame_fixed_size_enable|output_if_mode|output_data_format|output_width|clk_out_gating_enable
{.op = WRITE, .args = {.write = {0x8000UL, 0x0001FEA1}} }, // saphir/cpi/pipeline_control Write fields: clk_out_gating_enable
{.op = WRITE, .args = {.write = {0xE000UL, 0x00000005}} }, // saphir/nfl/pipeline_control Write fields: enable|bypass
{.op = WRITE, .args = {.write = {0xC000UL, 0x00000005}} }, // saphir/afk/pipeline_control Write fields: enable|bypass
{.op = WRITE, .args = {.write = {0x4040UL, 0x00000003}} }, // saphir/ehc/ehc_control
{.op = WRITE, .args = {.write = {0x4044UL, 0x00000044}} }, // saphir/ehc/bits_splitting
{.op = WRITE, .args = {.write = {0x4048UL, 0x00002EE0}} }, // saphir/ehc/integration_period
{.op = WRITE, .args = {.write = {0x4000UL, 0x00000001}} }, // saphir/ehc/pipeline_control
{.op = WRITE, .args = {.write = {0x9008UL, 0x000000A4}} }, // saphir/ro/time_base_ctrl Write fields: time_base_mode|external_mode|external_mode_enable|us_counter_max
{.op = WRITE, .args = {.write = {0x9000UL, 0x00000200}} }, // saphir/ro/readout_ctrl Write fields: ro_digital_pipe_en
{.op = WRITE, .args = {.write = {0x001CUL, 0x00000004}} }, // saphir/dig_soft_reset Write fields: analog_rstn
{.op = WRITE, .args = {.write = {0xA000UL, 0x00000406}} }, // saphir/ldo/bg Write fields: bg_en|bg_buf_en|bg_bypass|bg_chk|bg_adj
{.op = WRITE, .args = {.write = {0xA01CUL, 0x0007641F}} }, // saphir/ldo/pmu Write fields: pmu_icgm_en|pmu_v2i_en|pmu_v2i_cal_en|mipi_v2i_en
{.op = DELAY, .args = {.delay = {1000}} }, // us
{.op = WRITE, .args = {.write = {0xB030UL, 0x00000010}} }, // saphir/mipi_csi/power Write fields: cur_en
{.op = WRITE, .args = {.write = {0x004CUL, 0x00201F42}} }, // saphir/adc_control Write fields: adc_clk_en
{.op = DELAY, .args = {.delay = {1000}} }, // us
{.op = WRITE, .args = {.write = {0xA01CUL, 0x0007E41F}} }, // saphir/ldo/pmu Write fields: pmu_v2i_en|pmu_v2i_adj|pmu_v2i_cal_en
{.op = DELAY, .args = {.delay = {1000}} }, // us
{.op = WRITE, .args = {.write = {0x004CUL, 0x00201F40}} }, // saphir/adc_control
{.op = WRITE, .args = {.write = {0x1218UL, 0x00000111}} }, // saphir/bias/bgen_cgm_sub Write fields: bias_cgm_sub_en
{.op = WRITE, .args = {.write = {0x1218UL, 0x00000111}} }, // saphir/bias/bgen_cgm_sub Write fields: bias_cgm_sub_trim
{.op = WRITE, .args = {.write = {0x1218UL, 0x00000111}} }, // saphir/bias/bgen_cgm_sub Write fields: bias_cgm_sub_slp_ctl
{.op = DELAY, .args = {.delay = {1000}} }, // us
{.op = WRITE, .args = {.write = {0x1220UL, 0x00000001}} }, // saphir/bias/bgen_cc_en Write fields: bias_cc_hv_en
{.op = DELAY, .args = {.delay = {1000}} }, // us
{.op = WRITE, .args = {.write = {0xA008UL, 0x00008085}} }, // saphir/ldo/ldo_lv Write fields: ldo_lv_en|ldo_lv_climit_en|ldo_lv_climit|ldo_lv_ind_en|ldo_lv_adj|ldo_lv_ind_vth_ok|ldo_lv_ind_vth_bo
{.op = WRITE, .args = {.write = {0xA004UL, 0x00008055}} }, // saphir/ldo/ldo_hv Write fields: ldo_hv_en|ldo_hv_climit_en|ldo_hv_climit|ldo_hv_ind_en|ldo_hv_adj|ldo_hv_ind_vth_ok|ldo_hv_ind_vth_bo
{.op = DELAY, .args = {.delay = {1000}} }, // us
{.op = WRITE, .args = {.write = {0x0070UL, 0x0000051F}} }, // saphir/cp_ctrl Write fields: cp_en|cp_clk_en|cp_adj|cp_cfly|cp_mphase|cp_clk_divider
{.op = DELAY, .args = {.delay = {1000}} }, // us
{.op = WRITE, .args = {.write = {0x1220UL, 0x00000003}} }, // saphir/bias/bgen_cc_en Write fields: bias_cc_lv_en
{.op = DELAY, .args = {.delay = {1000}} }, // us
{.op = WRITE, .args = {.write = {0x1208UL, 0x00000030}} }, // saphir/bias/bgen_ctrl Write fields: bias_rstn_hv|bias_rstn_lv
{.op = DELAY, .args = {.delay = {1000}} }, // us
{.op = WRITE, .args = {.write = {0x0000UL, 0x00000420}} }, // saphir/roi_ctrl Write fields: roi_td_en|roi_td_shadow_trigger
{.op = WRITE, .args = {.write = {0x0000UL, 0x00000400}} }, // saphir/roi_ctrl Write fields: roi_td_en|roi_td_shadow_trigger
{.op = WRITE, .args = {.write = {0x0000UL, 0x00000802}} }, // saphir/roi_ctrl Write fields: roi_td_en|px_sw_rstn|px_roi_halt_programming
{.op = WRITE, .args = {.write = {0x0000UL, 0x00000822}} }, // saphir/roi_ctrl Write fields: roi_td_en|roi_td_shadow_trigger
{.op = WRITE, .args = {.write = {0x0000UL, 0x00000802}} }, // saphir/roi_ctrl Write fields: roi_td_en|roi_td_shadow_trigger
{.op = WRITE, .args = {.write = {0x3000UL, 0x00000000}} }, // saphir/roi/td_roi_y00
{.op = WRITE, .args = {.write = {0x3004UL, 0x00000000}} }, // saphir/roi/td_roi_y01
{.op = WRITE, .args = {.write = {0x3008UL, 0x00000000}} }, // saphir/roi/td_roi_y02
{.op = WRITE, .args = {.write = {0x300CUL, 0x00000000}} }, // saphir/roi/td_roi_y03
{.op = WRITE, .args = {.write = {0x3010UL, 0x00000000}} }, // saphir/roi/td_roi_y04
{.op = WRITE, .args = {.write = {0x3014UL, 0x00000000}} }, // saphir/roi/td_roi_y05
{.op = WRITE, .args = {.write = {0x3018UL, 0x00000000}} }, // saphir/roi/td_roi_y06
{.op = WRITE, .args = {.write = {0x301CUL, 0x00000000}} }, // saphir/roi/td_roi_y07
{.op = WRITE, .args = {.write = {0x3020UL, 0x00000000}} }, // saphir/roi/td_roi_y08
{.op = WRITE, .args = {.write = {0x3024UL, 0x00000000}} }, // saphir/roi/td_roi_y09
{.op = WRITE, .args = {.write = {0x3028UL, 0x00000000}} }, // saphir/roi/td_roi_y10
{.op = WRITE, .args = {.write = {0x0000UL, 0x00000822}} }, // saphir/roi_ctrl Write fields: roi_td_shadow_trigger
{.op = WRITE, .args = {.write = {0x0000UL, 0x00000802}} }, // saphir/roi_ctrl Write fields: roi_td_shadow_trigger
{.op = WRITE, .args = {.write = {0x2000UL, 0x00000000}} }, // saphir/roi/td_roi_x00 Write fields: effective
{.op = WRITE, .args = {.write = {0x2004UL, 0x00000000}} }, // saphir/roi/td_roi_x01 Write fields: effective
{.op = WRITE, .args = {.write = {0x2008UL, 0x00000000}} }, // saphir/roi/td_roi_x02 Write fields: effective
{.op = WRITE, .args = {.write = {0x200CUL, 0x00000000}} }, // saphir/roi/td_roi_x03 Write fields: effective
{.op = WRITE, .args = {.write = {0x2010UL, 0x00000000}} }, // saphir/roi/td_roi_x04 Write fields: effective
{.op = WRITE, .args = {.write = {0x2014UL, 0x00000000}} }, // saphir/roi/td_roi_x05 Write fields: effective
{.op = WRITE, .args = {.write = {0x2018UL, 0x00000000}} }, // saphir/roi/td_roi_x06 Write fields: effective
{.op = WRITE, .args = {.write = {0x201CUL, 0x00000000}} }, // saphir/roi/td_roi_x07 Write fields: effective
{.op = WRITE, .args = {.write = {0x2020UL, 0x00000000}} }, // saphir/roi/td_roi_x08 Write fields: effective
{.op = WRITE, .args = {.write = {0x2024UL, 0x00000000}} }, // saphir/roi/td_roi_x09 Write fields: effective
{.op = WRITE, .args = {.write = {0x3000UL, 0xFFFFFFFF}} }, // saphir/roi/td_roi_y00 Write fields: effective
{.op = WRITE, .args = {.write = {0x3004UL, 0xFFFFFFFF}} }, // saphir/roi/td_roi_y01 Write fields: effective
{.op = WRITE, .args = {.write = {0x3008UL, 0xFFFFFFFF}} }, // saphir/roi/td_roi_y02 Write fields: effective
{.op = WRITE, .args = {.write = {0x300CUL, 0xFFFFFFFF}} }, // saphir/roi/td_roi_y03 Write fields: effective
{.op = WRITE, .args = {.write = {0x3010UL, 0xFFFFFFFF}} }, // saphir/roi/td_roi_y04 Write fields: effective
{.op = WRITE, .args = {.write = {0x3014UL, 0xFFFFFFFF}} }, // saphir/roi/td_roi_y05 Write fields: effective
{.op = WRITE, .args = {.write = {0x3018UL, 0xFFFFFFFF}} }, // saphir/roi/td_roi_y06 Write fields: effective
{.op = WRITE, .args = {.write = {0x301CUL, 0xFFFFFFFF}} }, // saphir/roi/td_roi_y07 Write fields: effective
{.op = WRITE, .args = {.write = {0x3020UL, 0xFFFFFFFF}} }, // saphir/roi/td_roi_y08 Write fields: effective
{.op = WRITE, .args = {.write = {0x3024UL, 0xFFFFFFFF}} }, // saphir/roi/td_roi_y09 Write fields: effective
{.op = WRITE, .args = {.write = {0x0000UL, 0x00000822}} }, // saphir/roi_ctrl Write fields: roi_td_shadow_trigger
{.op = WRITE, .args = {.write = {0x0000UL, 0x00000802}} }, // saphir/roi_ctrl Write fields: roi_td_shadow_trigger
{.op = DELAY, .args = {.delay = {1000}} }, // us
{.op = WRITE, .args = {.write = {0x1000UL, 0x0301003D}} }, // saphir/bias/bias_pr_hv0 Write fields: bias_en|bias_ctl
{.op = WRITE, .args = {.write = {0x1004UL, 0x03010027}} }, // saphir/bias/bias_fo_hv0 Write fields: bias_en|bias_ctl
{.op = WRITE, .args = {.write = {0x1008UL, 0x0101003F}} }, // saphir/bias/bias_fes_hv0 Write fields: bias_en|bias_ctl
{.op = WRITE, .args = {.write = {0x1100UL, 0x03010000}} }, // saphir/bias/bias_hpf_lv0 Write fields: bias_en|bias_ctl
{.op = WRITE, .args = {.write = {0x1104UL, 0x01090018}} }, // saphir/bias/bias_diff_on_lv0 Write fields: bias_en|bias_ctl
{.op = WRITE, .args = {.write = {0x1108UL, 0x01010033}} }, // saphir/bias/bias_diff_lv0 Write fields: bias_en|bias_ctl
{.op = WRITE, .args = {.write = {0x110CUL, 0x01090013}} }, // saphir/bias/bias_diff_off_lv0 Write fields: bias_en|bias_ctl
{.op = WRITE, .args = {.write = {0x1110UL, 0x01010039}} }, // saphir/bias/bias_inv_lv0 Write fields: bias_en|bias_ctl
{.op = WRITE, .args = {.write = {0x1114UL, 0x03010052}} }, // saphir/bias/bias_refr_lv0 Write fields: bias_en|bias_ctl
{.op = WRITE, .args = {.write = {0x1118UL, 0x03010042}} }, // saphir/bias/bias_invp_lv0 Write fields: bias_en|bias_ctl
{.op = WRITE, .args = {.write = {0x111CUL, 0x03000074}} }, // saphir/bias/bias_req_pu_lv0 Write fields: bias_en|bias_ctl
{.op = WRITE, .args = {.write = {0x1120UL, 0x010000A4}} }, // saphir/bias/bias_sm_pdy_lv0 Write fields: bias_en|bias_ctl
{.op = WRITE, .args = {.write = {0x1208UL, 0x00000035}} }, // saphir/bias/bgen_ctrl Write fields: burst_transfer_hv_bank_0|burst_transfer_lv_bank_0
{.op = WRITE, .args = {.write = {0x0000UL, 0x00000802}} } // saphir/roi_ctrl Write fields: roi_td_en
};
static const struct reg_op dcmi_start_seq[] = {
{.op = WRITE, .args = {.write = {0x8000UL, 0x0001FEA1}} }, // saphir/cpi/pipeline_control
{.op = WRITE, .args = {.write = {0x9028UL, 0x00000000}} }, // saphir/ro/ro_lp_ctrl Write fields: lp_output_disable
{.op = WRITE, .args = {.write = {0x9008UL, 0x000000A5}} }, // saphir/ro/time_base_ctrl Write fields: time_base_enable
{.op = DELAY, .args = {.delay = {1000}} }, // us
{.op = WRITE, .args = {.write = {0x002CUL, 0x0022C724}} }, // saphir/ro_td_ctrl Write fields: ro_td_ack_y_rstn|ro_td_arb_y_rstn|ro_td_addr_y_rstn|ro_td_sendreq_y_rstn
{.op = WRITE, .args = {.write = {0x0000UL, 0x00000C02}} }, // saphir/roi_ctrl Write fields: roi_td_en|px_sw_rstn
{.op = DELAY, .args = {.delay = {1000}} } // us
};
static const struct reg_op dcmi_stop_seq[] = {
{.op = WRITE, .args = {.write = {0x0000UL, 0x00000802}} }, // saphir/roi_ctrl Write fields: roi_td_en|px_sw_rstn
{.op = WRITE, .args = {.write = {0x002CUL, 0x00200624}} }, // saphir/ro_td_ctrl Write fields: ro_td_ack_y_rstn|ro_td_arb_y_rstn|ro_td_addr_y_rstn|ro_td_sendreq_y_rstn
{.op = WRITE, .args = {.write = {0x9028UL, 0x00000002}} }, // saphir/ro/ro_lp_ctrl Write fields: lp_output_disable|lp_keep_th
{.op = DELAY, .args = {.delay = {1000}} }, // us
{.op = WRITE, .args = {.write = {0x9008UL, 0x000000A4}} }, // saphir/ro/time_base_ctrl Write fields: time_base_enable
{.op = WRITE, .args = {.write = {0x8000UL, 0x0001FFA2}} }, // saphir/cpi/pipeline_control Write fields: enable|drop_nbackpressure|hot_disable_enable
{.op = READ, .args = {.read = {0x8004UL, 0x00000002}} }, // saphir/cpi/pipeline_status Read fields: busy
{.op = DELAY, .args = {.delay = {1000}} } // us
};
static const struct reg_op dcmi_destroy_seq[] = {
};
const struct issd dcmi_histo = {
.init = {
.ops = dcmi_init_seq,
.len = ARRAY_SIZE(dcmi_init_seq)},
.start = {
.ops = dcmi_start_seq,
.len = ARRAY_SIZE(dcmi_start_seq)},
.stop = {
.ops = dcmi_stop_seq,
.len = ARRAY_SIZE(dcmi_stop_seq)},
.destroy = {
.ops = dcmi_destroy_seq,
.len = ARRAY_SIZE(dcmi_destroy_seq)},
};
#endif

File diff suppressed because it is too large Load Diff

View File

@ -49,6 +49,7 @@
#define OMV_MT9V0XX_ENABLE (1)
#define OMV_LEPTON_ENABLE (1)
#define OMV_GENX320_ENABLE (1)
#define OMV_GENX320_EHC_ENABLE (1)
#define OMV_PAG7920_ENABLE (1)
#define OMV_PAJ6100_ENABLE (1)
#define OMV_FROGEYE2020_ENABLE (1)

View File

@ -43,6 +43,7 @@
#define OMV_MT9V0XX_ENABLE (1)
#define OMV_LEPTON_ENABLE (1)
#define OMV_GENX320_ENABLE (1)
#define OMV_GENX320_EHC_ENABLE (1)
#define OMV_PAG7920_ENABLE (1)
#define OMV_PAJ6100_ENABLE (1)
#define OMV_FROGEYE2020_ENABLE (1)

View File

@ -56,9 +56,8 @@
#define BRIGHTNESS_DEFAULT 128
#define I2C_TIMEOUT 1000
#define SRAM_INIT_TIMEOUT 100
#define INTEGRATION_DEF_PREIOD 10000 // 10ms (100 FPS)
#define INTEGRATION_DEF_PREIOD 20000 // 20ms (50 FPS)
#define INTEGRATION_MIN_PREIOD 0x10 // 16us
#define INTEGRATION_MAX_PREIOD 0x1FFF0 // 131056us
@ -67,6 +66,18 @@
#define EVENT_THRESHOLD_TO_CALIBRATE 100000
#define EVENT_THRESHOLD_SIGMA 10
#define EVT_CLK_FREQ (omv_csi_get_xclk_frequency() / 1000000)
#define EVT_SCALE_PERIOD(period) (((period) * EVT_CLK_FREQ) / 10)
#define AFK_50_HZ (50)
#define AFK_60_HZ (60)
#define AFK_LOW_FREQ IM_MIN(AFK_50_HZ, AFK_60_HZ)
#define AFK_HIGH_FREQ IM_MAX(AFK_50_HZ, AFK_60_HZ)
#define AFK_LOW_BAND ((AFK_LOW_FREQ * 2) - 10)
#define AFK_HIGH_BAND ((AFK_HIGH_FREQ * 2) + 10)
#define EHC_DIFF3D_N_BITS_SIZE (7) // signed 8-bit value
#if (OMV_GENX320_CAL_ENABLE == 1)
static bool hot_pixels_disabled = false;
#endif // (OMV_GENX320_CAL_ENABLE == 1)
@ -95,6 +106,9 @@ static int reset(omv_csi_t *csi) {
I2C_TIMEOUT << TOP_CHICKEN_I2C_TIMEOUT_Pos);
// Start the Init sequence
#if (OMV_GENX320_EHC_ENABLE == 1)
psee_sensor_init(&dcmi_histo);
#else
psee_sensor_init(&dcmi_evt);
// Set EVT20 mode
@ -106,6 +120,7 @@ static int reset(omv_csi_t *csi) {
HSYNC_CLOCK_CYCLES << CPI_PACKET_TIME_CONTROL_BLANKING_Pos);
psee_sensor_write(CPI_FRAME_SIZE_CONTROL, ACTIVE_SENSOR_HEIGHT);
psee_sensor_write(CPI_FRAME_TIME_CONTROL, VSYNC_CLOCK_CYCLES);
#endif // (OMV_GENX320_EHC_ENABLE == 1)
// Enable dropping
psee_sensor_write(RO_READOUT_CTRL, RO_READOUT_CTRL_DIGITAL_PIPE_EN |
@ -113,11 +128,23 @@ static int reset(omv_csi_t *csi) {
RO_READOUT_CTRL_DROP_EN |
RO_READOUT_CTRL_DROP_ON_FULL_EN);
// Disable the Anti-FlicKering filter
psee_disable_afk();
// Enable the Anti-FlicKering filter
AFK_HandleTypeDef psee_afk;
if (psee_afk_init(&psee_afk) != AFK_OK) {
return -1;
}
if (psee_afk_activate(&psee_afk, AFK_LOW_BAND, AFK_HIGH_BAND, EVT_CLK_FREQ) != AFK_OK) {
return -1;
}
// Operation Mode Configuration
#if (OMV_GENX320_EHC_ENABLE == 1)
psee_PM3C_Histo_config();
#else
psee_PM3C_config();
#endif // (OMV_GENX320_EHC_ENABLE == 1)
// Set the default border for the Activity map
psee_set_default_XY_borders(&genx320mp_default_am_borders);
@ -129,54 +156,39 @@ static int reset(omv_csi_t *csi) {
psee_sensor_set_biases(&biases);
// Start the csi
psee_sensor_start(&dcmi_evt);
#if (OMV_GENX320_EHC_ENABLE == 1)
// Bypass Filter
psee_sensor_write(EHC_PIPELINE_CONTROL, 0);
psee_sensor_start(&dcmi_histo);
// Start sram init
psee_sensor_write(SRAM_INITN, SRAM_INITN_EHC_STC);
uint32_t reg;
psee_sensor_read(SRAM_PD0, &reg);
psee_sensor_write(SRAM_PD0, reg & ~(SRAM_PD0_EHC_PD | SRAM_PD0_STC0_PD | SRAM_PD0_STC1_PD));
psee_sensor_write(EHC_INITIALISATION, EHC_INITIALISATION_REQ_INIT);
EHC_HandleTypeDef psee_ehc;
// Configure the block
psee_sensor_write(EHC_EHC_CONTROL, 0 << EHC_CONTROL_ALGO_SEL_Pos | // diff3
1 << EHC_CONTROL_TRIG_SEL_Pos); // integration period
psee_sensor_write(EHC_BITS_SPLITTING, INT8_T_BITS << EHC_BITS_SPLITTING_NEGATIVE_BIT_LENGTH_Pos |
0 << EHC_BITS_SPLITTING_POSITIVE_BIT_LENGTH_Pos |
0 << EHC_BITS_SPLITTING_OUT_16BITS_PADDING_MODE_Pos);
psee_sensor_write(EHC_INTEGRATION_PERIOD, INTEGRATION_DEF_PREIOD);
// Check SRAM INIT done
for (mp_uint_t start = mp_hal_ticks_ms();; mp_hal_delay_ms(1)) {
uint32_t reg;
psee_sensor_read(EHC_INITIALISATION, &reg);
if (reg & EHC_INITIALISATION_FLAG_INIT_DONE) {
psee_sensor_write(EHC_INITIALISATION, EHC_INITIALISATION_FLAG_INIT_DONE);
break;
}
if ((mp_hal_ticks_ms() - start) >= SRAM_INIT_TIMEOUT) {
return -1;
}
if (psee_ehc_init(&psee_ehc) != EHC_OK) {
return -1;
}
// Re-enable filter
psee_sensor_write(EHC_PIPELINE_CONTROL, EHC_PIPELINE_CONTROL_ENABLE);
#endif // (OMV_GENX320_EHC_ENABLE == 1)
if (psee_ehc_activate(&psee_ehc, EHC_ALGO_DIFF3D, 0, EHC_DIFF3D_N_BITS_SIZE,
EVT_SCALE_PERIOD(INTEGRATION_DEF_PREIOD), EHC_WITHOUT_PADDING) != EHC_OK) {
return -1;
}
#else
psee_sensor_start(&dcmi_evt);
#endif // (OMV_GENX320_EHC_ENABLE == 1)
return 0;
}
static int sleep(omv_csi_t *csi, int enable) {
if (enable) {
#if (OMV_GENX320_EHC_ENABLE == 1)
psee_PM2_Histo_config();
#else
psee_PM2_config();
#endif // (OMV_GENX320_EHC_ENABLE == 1)
} else {
#if (OMV_GENX320_EHC_ENABLE == 1)
psee_PM3C_Histo_config();
#else
psee_PM3C_config();
#endif // (OMV_GENX320_EHC_ENABLE == 1)
}
return 0;
}
@ -219,7 +231,7 @@ static int set_framerate(omv_csi_t *csi, int framerate) {
return -1;
}
psee_sensor_write(EHC_INTEGRATION_PERIOD, us);
psee_sensor_write(EHC_INTEGRATION_PERIOD, EVT_SCALE_PERIOD(us));
#endif // (OMV_GENX320_EHC_ENABLE == 1)
return 0;
}