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Lower pixel clock frequency to 54MHz
* Lower pixel clock frequency to be within the DCMI specs (max 54MHz)
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@ -24,7 +24,7 @@
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#define OV9650_PID 0x96
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#define OV2640_PID 0x26
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#define XCLK_FREQ (12000000)
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#define XCLK_FREQ (13000000)
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#define BREAK() __asm__ volatile ("BKPT")
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struct sensor_dev sensor;
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@ -174,13 +174,18 @@ int sensor_init()
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SCCB_Init();
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systick_sleep(10);
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/* Configure the external clock (XCLK) */
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#ifdef OPENMV1
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/* Configure the sensor external clock (XCLK) to XCLK_FREQ (13MHz).
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Note: The sensor's internal PLL (when CLKRC=0x80) doubles the XCLK_FREQ
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(XCLK=XCLK_FREQ*2), and the unscaled PIXCLK output is XCLK_FREQ*4 */
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extclk_config(XCLK_FREQ);
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#else
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(void) extclk_config;
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HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI, RCC_MCODIV_1);
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#endif
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/* Uncomment this to pass through the MCO1 clock (HSI=16MHz) this results in a
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64MHz PIXCLK output from the sensor.
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Note: The maximum pixel clock input on the STM32F4xx is 54MHz,
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the STM32F7 can probably handle higher input pixel clock.
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*/
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//(void) extclk_config;
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//HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI, RCC_MCODIV_1);
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/* Reset the sesnor state */
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memset(&sensor, 0, sizeof(struct sensor_dev));
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