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Use new cache alignment for flir lepton
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900477383e
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@ -455,22 +455,8 @@ int fir_lepton_init(cambus_t *bus, int *w, int *h, int *refresh, int *resolution
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FB_ALLOC_NO_HINT);
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}
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size_t size = VOSPI_BUFFER_SIZE * sizeof(uint16_t);
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// The DMA buffer must not start/end partially on a cache line.
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#if defined(MCU_SERIES_F7) || defined(MCU_SERIES_H7)
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size = ((size + __SCB_DCACHE_LINE_SIZE - 1) / __SCB_DCACHE_LINE_SIZE) * __SCB_DCACHE_LINE_SIZE;
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size += __SCB_DCACHE_LINE_SIZE;
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#endif
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fir_lepton_spi_rx_cb_dma_buffer = (uint16_t *) fb_alloc(size, FB_ALLOC_PREFER_SPEED);
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#if defined(MCU_SERIES_F7) || defined(MCU_SERIES_H7)
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int offset = ((uint32_t) fir_lepton_spi_rx_cb_dma_buffer) % __SCB_DCACHE_LINE_SIZE;
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if (offset) {
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fir_lepton_spi_rx_cb_dma_buffer += __SCB_DCACHE_LINE_SIZE - offset;
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}
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#endif
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fir_lepton_spi_rx_cb_dma_buffer = (uint16_t *) fb_alloc(VOSPI_BUFFER_SIZE * sizeof(uint16_t),
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FB_ALLOC_PREFER_SPEED | FB_ALLOC_CACHE_ALIGN);
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dma_init(&fir_lepton_spi_rx_dma,
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OMV_FIR_LEPTON_CONTROLLER->rx_dma_descr,
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