From 112ea40cfe027d17ef3e4ef29601e76e7d665dbc Mon Sep 17 00:00:00 2001 From: iabdalkader Date: Mon, 12 Oct 2020 19:21:48 +0200 Subject: [PATCH] PORTENTA: Update FMC/SDRAM and QSPI PLL settings. --- src/micropython | 2 +- src/omv/boards/PORTENTA/omv_boardconfig.h | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/src/micropython b/src/micropython index c294f8404..9992c24f3 160000 --- a/src/micropython +++ b/src/micropython @@ -1 +1 @@ -Subproject commit c294f8404c3f21fdc4841636a8a42378365262ef +Subproject commit 9992c24f3088e5ebe2138f0651cc962cb9439ef6 diff --git a/src/omv/boards/PORTENTA/omv_boardconfig.h b/src/omv/boards/PORTENTA/omv_boardconfig.h index 16620062e..a1f0a0e8f 100644 --- a/src/omv/boards/PORTENTA/omv_boardconfig.h +++ b/src/omv/boards/PORTENTA/omv_boardconfig.h @@ -87,9 +87,9 @@ #define OMV_OSC_PLL1VCO (RCC_PLL1VCOWIDE) #define OMV_OSC_PLL1FRAC (0) -// PLL2 180MHz for FMC and QSPI. +// PLL2 200MHz for FMC and QSPI. #define OMV_OSC_PLL2M (5) -#define OMV_OSC_PLL2N (72) +#define OMV_OSC_PLL2N (80) #define OMV_OSC_PLL2P (2) #define OMV_OSC_PLL2Q (2) #define OMV_OSC_PLL2R (2)