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Merge pull request #1190 from kwagyeman/kwabena/tv_dma_speed_improvment
Use the most efficient data transfers for TV DMA
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commit
115a443086
@ -497,12 +497,48 @@ static void spi_config_init(bool triple_buffer)
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framebuffer_tail = 0;
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for (int i = 0; i < FRAMEBUFFER_COUNT; i++) {
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framebuffers[i] = (uint16_t *) fb_alloc0(TV_WIDTH_RGB565 * TV_HEIGHT, FB_ALLOC_NO_HINT);
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framebuffers[i] = (uint16_t *) fb_alloc0(TV_WIDTH_RGB565 * TV_HEIGHT, FB_ALLOC_CACHE_ALIGN);
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}
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dma_init(&spi_tx_dma, OMV_SPI_LCD_CONTROLLER->tx_dma_descr, DMA_MEMORY_TO_PERIPH, OMV_SPI_LCD_CONTROLLER->spi);
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OMV_SPI_LCD_CONTROLLER->spi->hdmatx = &spi_tx_dma;
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OMV_SPI_LCD_CONTROLLER->spi->hdmarx = NULL;
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#if defined(MCU_SERIES_H7)
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spi_tx_dma.Init.PeriphDataAlignment = DMA_PDATAALIGN_WORD;
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#else
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spi_tx_dma.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;
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#endif
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spi_tx_dma.Init.MemDataAlignment = DMA_MDATAALIGN_WORD;
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spi_tx_dma.Init.FIFOMode = DMA_FIFOMODE_ENABLE;
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spi_tx_dma.Init.FIFOThreshold = DMA_FIFO_THRESHOLD_FULL;
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spi_tx_dma.Init.MemBurst = DMA_MBURST_INC4;
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#if defined(MCU_SERIES_H7)
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spi_tx_dma.Init.PeriphBurst = DMA_PBURST_INC4;
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#else
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spi_tx_dma.Init.PeriphBurst = DMA_PBURST_SINGLE;
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#endif
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#if defined(MCU_SERIES_H7)
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((DMA_Stream_TypeDef *) spi_tx_dma.Instance)->CR =
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(((DMA_Stream_TypeDef *) spi_tx_dma.Instance)->CR & ~DMA_SxCR_PSIZE_Msk) | DMA_PDATAALIGN_WORD;
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#else
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((DMA_Stream_TypeDef *) spi_tx_dma.Instance)->CR =
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(((DMA_Stream_TypeDef *) spi_tx_dma.Instance)->CR & ~DMA_SxCR_PSIZE_Msk) | DMA_PDATAALIGN_BYTE;
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#endif
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((DMA_Stream_TypeDef *) spi_tx_dma.Instance)->CR =
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(((DMA_Stream_TypeDef *) spi_tx_dma.Instance)->CR & ~DMA_SxCR_MSIZE_Msk) | DMA_MDATAALIGN_WORD;
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((DMA_Stream_TypeDef *) spi_tx_dma.Instance)->FCR =
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(((DMA_Stream_TypeDef *) spi_tx_dma.Instance)->FCR & ~DMA_SxFCR_DMDIS_Msk) | DMA_FIFOMODE_ENABLE;
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((DMA_Stream_TypeDef *) spi_tx_dma.Instance)->FCR =
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(((DMA_Stream_TypeDef *) spi_tx_dma.Instance)->FCR & ~DMA_SxFCR_FTH_Msk) | DMA_FIFO_THRESHOLD_FULL;
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((DMA_Stream_TypeDef *) spi_tx_dma.Instance)->CR =
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(((DMA_Stream_TypeDef *) spi_tx_dma.Instance)->CR & ~DMA_SxCR_MBURST_Msk) | DMA_MBURST_INC4;
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#if defined(MCU_SERIES_H7)
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((DMA_Stream_TypeDef *) spi_tx_dma.Instance)->CR =
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(((DMA_Stream_TypeDef *) spi_tx_dma.Instance)->CR & ~DMA_SxCR_PBURST_Msk) | DMA_PBURST_INC4;
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#else
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((DMA_Stream_TypeDef *) spi_tx_dma.Instance)->CR =
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(((DMA_Stream_TypeDef *) spi_tx_dma.Instance)->CR & ~DMA_SxCR_PBURST_Msk) | DMA_PBURST_SINGLE;
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#endif
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fb_alloc_mark_permanent();
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}
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}
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@ -527,6 +563,10 @@ static void spi_tv_callback(SPI_HandleTypeDef *hspi)
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spi_tx_cb_state_memory_write_addr = (uint8_t *) framebuffers[framebuffer_head];
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spi_tx_cb_state_memory_write_count = PICLINE_LENGTH_BYTES * TV_HEIGHT;
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framebuffer_tail = framebuffer_head;
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#if defined(MCU_SERIES_H7)
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OMV_SPI_LCD_CONTROLLER->spi->Instance->CFG1 =
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(OMV_SPI_LCD_CONTROLLER->spi->Instance->CFG1 & ~SPI_CFG1_FTHLV_Msk) | SPI_FIFO_THRESHOLD_01DATA;
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#endif
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OMV_SPI_LCD_CS_LOW();
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// When starting the interrupt chain the first HAL_SPI_Transmit_IT is not executed
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// in interrupt context. So, disable interrupts for the first HAL_SPI_Transmit_IT so
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@ -539,12 +579,16 @@ static void spi_tv_callback(SPI_HandleTypeDef *hspi)
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}
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case SPI_TX_CB_MEMORY_WRITE: {
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uint8_t *addr = spi_tx_cb_state_memory_write_addr;
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size_t count = IM_MIN(spi_tx_cb_state_memory_write_count, 65535);
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spi_tx_cb_state = (spi_tx_cb_state_memory_write_count > 65535)
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size_t count = IM_MIN(spi_tx_cb_state_memory_write_count, (65536-16));
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spi_tx_cb_state = (spi_tx_cb_state_memory_write_count > (65536-16))
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? SPI_TX_CB_MEMORY_WRITE
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: SPI_TX_CB_MEMORY_WRITE_CMD;
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spi_tx_cb_state_memory_write_addr += count;
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spi_tx_cb_state_memory_write_count -= count;
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#if defined(MCU_SERIES_H7)
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OMV_SPI_LCD_CONTROLLER->spi->Instance->CFG1 =
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(OMV_SPI_LCD_CONTROLLER->spi->Instance->CFG1 & ~SPI_CFG1_FTHLV_Msk) | SPI_FIFO_THRESHOLD_16DATA;
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#endif
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HAL_SPI_Transmit_DMA(OMV_SPI_LCD_CONTROLLER->spi, addr, count);
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break;
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}
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