mirror of
https://github.com/openmv/openmv.git
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Merge pull request #732 from openmv/portenta
Add support for the Portenta board.
This commit is contained in:
commit
123ba0b376
@ -98,8 +98,9 @@ include $(OMV_BOARD_CONFIG_DIR)/omv_boardconfig.mk
|
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CFLAGS += -std=gnu99 -Wall -Werror -Warray-bounds -mthumb -nostartfiles -fdata-sections -ffunction-sections
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CFLAGS += -D$(MCU) -D$(CFLAGS_MCU) -D$(ARM_MATH) -DARM_NN_TRUNCATE\
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-fsingle-precision-constant -Wdouble-promotion -mcpu=$(CPU) -mtune=$(CPU) -mfpu=$(FPU) -mfloat-abi=hard
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||||
CFLAGS += -D__FPU_PRESENT=1 -D__VFP_FP__ -DUSE_USB_FS -DUSE_DEVICE_MODE -DUSE_USB_OTG_ID=0 -DHSE_VALUE=12000000\
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||||
CFLAGS += -D__FPU_PRESENT=1 -D__VFP_FP__ -DUSE_USB_FS -DUSE_DEVICE_MODE -DUSE_USB_OTG_ID=0 -DHSE_VALUE=$(OMV_HSE_VALUE)\
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-D$(TARGET) -DSTM32_HAL_H=$(HAL_INC) -DVECT_TAB_OFFSET=$(VECT_TAB_OFFSET) -DMAIN_APP_ADDR=$(MAIN_APP_ADDR)
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CFLAGS += $(OMV_BOARD_EXTRA_CFLAGS)
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ST_CFLAGS += -I. -Iinclude
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ST_CFLAGS += -I$(TOP_DIR)/$(CMSIS_DIR)/include/
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30118
src/cmsis/include/st/stm32h747xx.h
Normal file
30118
src/cmsis/include/st/stm32h747xx.h
Normal file
File diff suppressed because it is too large
Load Diff
@ -2,8 +2,6 @@
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******************************************************************************
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* @file stm32h7xx.h
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* @author MCD Application Team
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* @version V1.2.0
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* @date 29-December-2017
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* @brief CMSIS STM32H7xx Device Peripheral Access Layer Header File.
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*
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* The file is the unique include file that the application programmer
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@ -18,29 +16,13 @@
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******************************************************************************
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* @attention
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*
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||||
* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
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* <h2><center>© Copyright (c) 2017 STMicroelectronics.
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* All rights reserved.</center></h2>
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*
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted provided that the following conditions are met:
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||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
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* 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
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||||
*
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||||
******************************************************************************
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*/
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@ -71,19 +53,31 @@
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#define STM32H7
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#endif /* STM32H7 */
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/* Uncomment the line below according to the target STM32H7 device used in your
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application
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*/
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#if !defined (STM32H743xx) && !defined (STM32H753xx)
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/* #define STM32H743xx */ /*!< STM32H743VI, STM32H743ZI, STM32H743II, STM32H743BI, STM32H743XI Devices */
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/* #define STM32H753xx */ /*!< STM32H753VI, STM32H753ZI, STM32H753II, STM32H753BI, STM32H753XI Devices */
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#if !defined (STM32H743xx) && !defined (STM32H753xx) && !defined (STM32H750xx) && !defined (STM32H742xx) && \
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!defined (STM32H745xx) && !defined (STM32H755xx) && !defined (STM32H747xx) && !defined (STM32H757xx)
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/* #define STM32H742xx */ /*!< STM32H742VI, STM32H742ZI, STM32H742AI, STM32H742II, STM32H742BI, STM32H742XI Devices */
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/* #define STM32H743xx */ /*!< STM32H743VI, STM32H743ZI, STM32H743AI, STM32H743II, STM32H743BI, STM32H743XI Devices */
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/* #define STM32H753xx */ /*!< STM32H753VI, STM32H753ZI, STM32H753AI, STM32H753II, STM32H753BI, STM32H753XI Devices */
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/* #define STM32H750xx */ /*!< STM32H750V, STM32H750I, STM32H750X Devices */
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/* #define STM32H747xx */ /*!< STM32H747ZI, STM32H747AI, STM32H747II, STM32H747BI, STM32H747XI Devices */
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/* #define STM32H757xx */ /*!< STM32H757ZI, STM32H757AI, STM32H757II, STM32H757BI, STM32H757XI Devices */
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/* #define STM32H745xx */ /*!< STM32H745ZI, STM32H745II, STM32H745BI, STM32H745XI Devices */
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/* #define STM32H755xx */ /*!< STM32H755ZI, STM32H755II, STM32H755BI, STM32H755XI Devices */
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#endif
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/* Tip: To avoid modifying this file each time you need to switch between these
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devices, you can define the device in your toolchain compiler preprocessor.
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*/
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#if defined(DUAL_CORE) && !defined(CORE_CM4) && !defined(CORE_CM7)
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#error "Dual core device, please select CORE_CM4 or CORE_CM7"
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#endif
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#if !defined (USE_HAL_DRIVER)
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/**
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* @brief Comment the line below if you will not use the peripherals drivers.
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@ -94,10 +88,10 @@
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#endif /* USE_HAL_DRIVER */
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/**
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* @brief CMSIS Device version number V1.2.0
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* @brief CMSIS Device version number V1.6.0
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*/
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#define __STM32H7xx_CMSIS_DEVICE_VERSION_MAIN (0x01) /*!< [31:24] main version */
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#define __STM32H7xx_CMSIS_DEVICE_VERSION_SUB1 (0x02) /*!< [23:16] sub1 version */
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#define __STM32H7xx_CMSIS_DEVICE_VERSION_SUB1 (0x06) /*!< [23:16] sub1 version */
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#define __STM32H7xx_CMSIS_DEVICE_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
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#define __STM32H7xx_CMSIS_DEVICE_VERSION_RC (0x00) /*!< [7:0] release candidate */
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#define __STM32H7xx_CMSIS_DEVICE_VERSION ((__CMSIS_DEVICE_VERSION_MAIN << 24)\
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@ -117,6 +111,18 @@
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#include "stm32h743xx.h"
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#elif defined(STM32H753xx)
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#include "stm32h753xx.h"
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#elif defined(STM32H750xx)
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#include "stm32h750xx.h"
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#elif defined(STM32H742xx)
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#include "stm32h742xx.h"
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#elif defined(STM32H745xx)
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#include "stm32h745xx.h"
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#elif defined(STM32H755xx)
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#include "stm32h755xx.h"
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#elif defined(STM32H747xx)
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#include "stm32h747xx.h"
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#elif defined(STM32H757xx)
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#include "stm32h757xx.h"
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#else
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#error "Please select first the target STM32H7xx device used in your application (in stm32h7xx.h file)"
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#endif
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766
src/cmsis/src/st/startup_stm32h747xx.s
Normal file
766
src/cmsis/src/st/startup_stm32h747xx.s
Normal file
@ -0,0 +1,766 @@
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/**
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******************************************************************************
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* @file startup_stm32h747xx.s
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* @author MCD Application Team
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* @brief STM32H747xx Devices vector table for GCC based toolchain.
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* This module performs:
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* - Set the initial SP
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* - Set the initial PC == Reset_Handler,
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* - Set the vector table entries with the exceptions ISR address
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* - Branches to main in the C library (which eventually
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* calls main()).
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* After Reset the Cortex-M processor is in Thread mode,
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* priority is Privileged, and the Stack is set to Main.
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******************************************************************************
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* @attention
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*
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* <h2><center>© Copyright (c) 2019 STMicroelectronics.
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* All rights reserved.</center></h2>
|
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*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
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*
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******************************************************************************
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*/
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.syntax unified
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.cpu cortex-m7
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.fpu softvfp
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.thumb
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.global g_pfnVectors
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.global Default_Handler
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/* start address for the initialization values of the .data section.
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defined in linker script */
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.word _sidata
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/* start address for the .data section. defined in linker script */
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.word _sdata
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/* end address for the .data section. defined in linker script */
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.word _edata
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/* start address for the .bss section. defined in linker script */
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.word _sbss
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/* end address for the .bss section. defined in linker script */
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.word _ebss
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/* stack used for SystemInit_ExtMemCtl; always internal RAM used */
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/**
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* @brief This is the code that gets called when the processor first
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* starts execution following a reset event. Only the absolutely
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* necessary set is performed, after which the application
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* supplied main() routine is called.
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* @param None
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* @retval : None
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*/
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.section .text.Reset_Handler
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.weak Reset_Handler
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.type Reset_Handler, %function
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Reset_Handler:
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ldr sp, =_estack /* set stack pointer */
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/* Copy the data segment initializers from flash to SRAM */
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movs r1, #0
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b LoopCopyDataInit
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CopyDataInit:
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ldr r3, =_sidata
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ldr r3, [r3, r1]
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str r3, [r0, r1]
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adds r1, r1, #4
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LoopCopyDataInit:
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ldr r0, =_sdata
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ldr r3, =_edata
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adds r2, r0, r1
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cmp r2, r3
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bcc CopyDataInit
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ldr r2, =_sbss
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b LoopFillZerobss
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/* Zero fill the bss segment. */
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FillZerobss:
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movs r3, #0
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str r3, [r2], #4
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LoopFillZerobss:
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ldr r3, = _ebss
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cmp r2, r3
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bcc FillZerobss
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/* Call the clock system intitialization function.*/
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bl SystemInit
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/* Call static constructors */
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/* bl __libc_init_array */
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/* Call the application's entry point.*/
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bl main
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bx lr
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.size Reset_Handler, .-Reset_Handler
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/**
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* @brief This is the code that gets called when the processor receives an
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* unexpected interrupt. This simply enters an infinite loop, preserving
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* the system state for examination by a debugger.
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* @param None
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* @retval None
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*/
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.section .text.Default_Handler,"ax",%progbits
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Default_Handler:
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Infinite_Loop:
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b Infinite_Loop
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.size Default_Handler, .-Default_Handler
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/******************************************************************************
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*
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* The minimal vector table for a Cortex M. Note that the proper constructs
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* must be placed on this to ensure that it ends up at physical address
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* 0x0000.0000.
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*
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*******************************************************************************/
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.section .isr_vector,"a",%progbits
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.type g_pfnVectors, %object
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.size g_pfnVectors, .-g_pfnVectors
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g_pfnVectors:
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.word _estack
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.word Reset_Handler
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.word NMI_Handler
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.word HardFault_Handler
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.word MemManage_Handler
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.word BusFault_Handler
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.word UsageFault_Handler
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.word 0
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.word 0
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.word 0
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.word 0
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.word SVC_Handler
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.word DebugMon_Handler
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.word 0
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.word PendSV_Handler
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.word SysTick_Handler
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/* External Interrupts */
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.word WWDG_IRQHandler /* Window WatchDog Interrupt ( wwdg1_it, wwdg2_it) */
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.word PVD_AVD_IRQHandler /* PVD/AVD through EXTI Line detection */
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.word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */
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.word RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */
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.word FLASH_IRQHandler /* FLASH */
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.word RCC_IRQHandler /* RCC */
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.word EXTI0_IRQHandler /* EXTI Line0 */
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.word EXTI1_IRQHandler /* EXTI Line1 */
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.word EXTI2_IRQHandler /* EXTI Line2 */
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.word EXTI3_IRQHandler /* EXTI Line3 */
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.word EXTI4_IRQHandler /* EXTI Line4 */
|
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.word DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */
|
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.word DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */
|
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.word DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */
|
||||
.word DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */
|
||||
.word DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */
|
||||
.word DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */
|
||||
.word DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */
|
||||
.word ADC_IRQHandler /* ADC1, ADC2 and ADC3s */
|
||||
.word FDCAN1_IT0_IRQHandler /* FDCAN1 interrupt line 0 */
|
||||
.word FDCAN2_IT0_IRQHandler /* FDCAN2 interrupt line 0 */
|
||||
.word FDCAN1_IT1_IRQHandler /* FDCAN1 interrupt line 1 */
|
||||
.word FDCAN2_IT1_IRQHandler /* FDCAN2 interrupt line 1 */
|
||||
.word EXTI9_5_IRQHandler /* External Line[9:5]s */
|
||||
.word TIM1_BRK_IRQHandler /* TIM1 Break interrupt */
|
||||
.word TIM1_UP_IRQHandler /* TIM1 Update interrupt */
|
||||
.word TIM1_TRG_COM_IRQHandler /* TIM1 Trigger and Commutation interrupt */
|
||||
.word TIM1_CC_IRQHandler /* TIM1 Capture Compare */
|
||||
.word TIM2_IRQHandler /* TIM2 */
|
||||
.word TIM3_IRQHandler /* TIM3 */
|
||||
.word TIM4_IRQHandler /* TIM4 */
|
||||
.word I2C1_EV_IRQHandler /* I2C1 Event */
|
||||
.word I2C1_ER_IRQHandler /* I2C1 Error */
|
||||
.word I2C2_EV_IRQHandler /* I2C2 Event */
|
||||
.word I2C2_ER_IRQHandler /* I2C2 Error */
|
||||
.word SPI1_IRQHandler /* SPI1 */
|
||||
.word SPI2_IRQHandler /* SPI2 */
|
||||
.word USART1_IRQHandler /* USART1 */
|
||||
.word USART2_IRQHandler /* USART2 */
|
||||
.word USART3_IRQHandler /* USART3 */
|
||||
.word EXTI15_10_IRQHandler /* External Line[15:10]s */
|
||||
.word RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */
|
||||
.word 0 /* Reserved */
|
||||
.word TIM8_BRK_TIM12_IRQHandler /* TIM8 Break and TIM12 */
|
||||
.word TIM8_UP_TIM13_IRQHandler /* TIM8 Update and TIM13 */
|
||||
.word TIM8_TRG_COM_TIM14_IRQHandler /* TIM8 Trigger and Commutation and TIM14 */
|
||||
.word TIM8_CC_IRQHandler /* TIM8 Capture Compare */
|
||||
.word DMA1_Stream7_IRQHandler /* DMA1 Stream7 */
|
||||
.word FMC_IRQHandler /* FMC */
|
||||
.word SDMMC1_IRQHandler /* SDMMC1 */
|
||||
.word TIM5_IRQHandler /* TIM5 */
|
||||
.word SPI3_IRQHandler /* SPI3 */
|
||||
.word UART4_IRQHandler /* UART4 */
|
||||
.word UART5_IRQHandler /* UART5 */
|
||||
.word TIM6_DAC_IRQHandler /* TIM6 and DAC1&2 underrun errors */
|
||||
.word TIM7_IRQHandler /* TIM7 */
|
||||
.word DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */
|
||||
.word DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */
|
||||
.word DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */
|
||||
.word DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */
|
||||
.word DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */
|
||||
.word ETH_IRQHandler /* Ethernet */
|
||||
.word ETH_WKUP_IRQHandler /* Ethernet Wakeup through EXTI line */
|
||||
.word FDCAN_CAL_IRQHandler /* FDCAN calibration unit interrupt */
|
||||
.word CM7_SEV_IRQHandler /* CM7 Send event interrupt for CM4 */
|
||||
.word CM4_SEV_IRQHandler /* CM4 Send event interrupt for CM7 */
|
||||
.word 0 /* Reserved */
|
||||
.word 0 /* Reserved */
|
||||
.word DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */
|
||||
.word DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */
|
||||
.word DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */
|
||||
.word USART6_IRQHandler /* USART6 */
|
||||
.word I2C3_EV_IRQHandler /* I2C3 event */
|
||||
.word I2C3_ER_IRQHandler /* I2C3 error */
|
||||
.word OTG_HS_EP1_OUT_IRQHandler /* USB OTG HS End Point 1 Out */
|
||||
.word OTG_HS_EP1_IN_IRQHandler /* USB OTG HS End Point 1 In */
|
||||
.word OTG_HS_WKUP_IRQHandler /* USB OTG HS Wakeup through EXTI */
|
||||
.word OTG_HS_IRQHandler /* USB OTG HS */
|
||||
.word DCMI_IRQHandler /* DCMI */
|
||||
.word 0 /* Reserved */
|
||||
.word RNG_IRQHandler /* Rng */
|
||||
.word FPU_IRQHandler /* FPU */
|
||||
.word UART7_IRQHandler /* UART7 */
|
||||
.word UART8_IRQHandler /* UART8 */
|
||||
.word SPI4_IRQHandler /* SPI4 */
|
||||
.word SPI5_IRQHandler /* SPI5 */
|
||||
.word SPI6_IRQHandler /* SPI6 */
|
||||
.word SAI1_IRQHandler /* SAI1 */
|
||||
.word LTDC_IRQHandler /* LTDC */
|
||||
.word LTDC_ER_IRQHandler /* LTDC error */
|
||||
.word DMA2D_IRQHandler /* DMA2D */
|
||||
.word SAI2_IRQHandler /* SAI2 */
|
||||
.word QUADSPI_IRQHandler /* QUADSPI */
|
||||
.word LPTIM1_IRQHandler /* LPTIM1 */
|
||||
.word CEC_IRQHandler /* HDMI_CEC */
|
||||
.word I2C4_EV_IRQHandler /* I2C4 Event */
|
||||
.word I2C4_ER_IRQHandler /* I2C4 Error */
|
||||
.word SPDIF_RX_IRQHandler /* SPDIF_RX */
|
||||
.word OTG_FS_EP1_OUT_IRQHandler /* USB OTG FS End Point 1 Out */
|
||||
.word OTG_FS_EP1_IN_IRQHandler /* USB OTG FS End Point 1 In */
|
||||
.word OTG_FS_WKUP_IRQHandler /* USB OTG FS Wakeup through EXTI */
|
||||
.word OTG_FS_IRQHandler /* USB OTG FS */
|
||||
.word DMAMUX1_OVR_IRQHandler /* DMAMUX1 Overrun interrupt */
|
||||
.word HRTIM1_Master_IRQHandler /* HRTIM Master Timer global Interrupt */
|
||||
.word HRTIM1_TIMA_IRQHandler /* HRTIM Timer A global Interrupt */
|
||||
.word HRTIM1_TIMB_IRQHandler /* HRTIM Timer B global Interrupt */
|
||||
.word HRTIM1_TIMC_IRQHandler /* HRTIM Timer C global Interrupt */
|
||||
.word HRTIM1_TIMD_IRQHandler /* HRTIM Timer D global Interrupt */
|
||||
.word HRTIM1_TIME_IRQHandler /* HRTIM Timer E global Interrupt */
|
||||
.word HRTIM1_FLT_IRQHandler /* HRTIM Fault global Interrupt */
|
||||
.word DFSDM1_FLT0_IRQHandler /* DFSDM Filter0 Interrupt */
|
||||
.word DFSDM1_FLT1_IRQHandler /* DFSDM Filter1 Interrupt */
|
||||
.word DFSDM1_FLT2_IRQHandler /* DFSDM Filter2 Interrupt */
|
||||
.word DFSDM1_FLT3_IRQHandler /* DFSDM Filter3 Interrupt */
|
||||
.word SAI3_IRQHandler /* SAI3 global Interrupt */
|
||||
.word SWPMI1_IRQHandler /* Serial Wire Interface 1 global interrupt */
|
||||
.word TIM15_IRQHandler /* TIM15 global Interrupt */
|
||||
.word TIM16_IRQHandler /* TIM16 global Interrupt */
|
||||
.word TIM17_IRQHandler /* TIM17 global Interrupt */
|
||||
.word MDIOS_WKUP_IRQHandler /* MDIOS Wakeup Interrupt */
|
||||
.word MDIOS_IRQHandler /* MDIOS global Interrupt */
|
||||
.word JPEG_IRQHandler /* JPEG global Interrupt */
|
||||
.word MDMA_IRQHandler /* MDMA global Interrupt */
|
||||
.word DSI_IRQHandler /* DSI global Interrupt */
|
||||
.word SDMMC2_IRQHandler /* SDMMC2 global Interrupt */
|
||||
.word HSEM1_IRQHandler /* HSEM1 global Interrupt */
|
||||
.word HSEM2_IRQHandler /* HSEM1 global Interrupt */
|
||||
.word ADC3_IRQHandler /* ADC3 global Interrupt */
|
||||
.word DMAMUX2_OVR_IRQHandler /* DMAMUX Overrun interrupt */
|
||||
.word BDMA_Channel0_IRQHandler /* BDMA Channel 0 global Interrupt */
|
||||
.word BDMA_Channel1_IRQHandler /* BDMA Channel 1 global Interrupt */
|
||||
.word BDMA_Channel2_IRQHandler /* BDMA Channel 2 global Interrupt */
|
||||
.word BDMA_Channel3_IRQHandler /* BDMA Channel 3 global Interrupt */
|
||||
.word BDMA_Channel4_IRQHandler /* BDMA Channel 4 global Interrupt */
|
||||
.word BDMA_Channel5_IRQHandler /* BDMA Channel 5 global Interrupt */
|
||||
.word BDMA_Channel6_IRQHandler /* BDMA Channel 6 global Interrupt */
|
||||
.word BDMA_Channel7_IRQHandler /* BDMA Channel 7 global Interrupt */
|
||||
.word COMP1_IRQHandler /* COMP1 global Interrupt */
|
||||
.word LPTIM2_IRQHandler /* LP TIM2 global interrupt */
|
||||
.word LPTIM3_IRQHandler /* LP TIM3 global interrupt */
|
||||
.word LPTIM4_IRQHandler /* LP TIM4 global interrupt */
|
||||
.word LPTIM5_IRQHandler /* LP TIM5 global interrupt */
|
||||
.word LPUART1_IRQHandler /* LP UART1 interrupt */
|
||||
.word WWDG_RST_IRQHandler /* Window Watchdog reset interrupt (exti_d2_wwdg_it, exti_d1_wwdg_it) */
|
||||
.word CRS_IRQHandler /* Clock Recovery Global Interrupt */
|
||||
.word ECC_IRQHandler /* ECC diagnostic Global Interrupt */
|
||||
.word SAI4_IRQHandler /* SAI4 global interrupt */
|
||||
.word 0 /* Reserved */
|
||||
.word HOLD_CORE_IRQHandler /* Hold core interrupt */
|
||||
.word WAKEUP_PIN_IRQHandler /* Interrupt for all 6 wake-up pins */
|
||||
|
||||
/*******************************************************************************
|
||||
*
|
||||
* Provide weak aliases for each Exception handler to the Default_Handler.
|
||||
* As they are weak aliases, any function with the same name will override
|
||||
* this definition.
|
||||
*
|
||||
*******************************************************************************/
|
||||
.weak NMI_Handler
|
||||
.thumb_set NMI_Handler,Default_Handler
|
||||
|
||||
.weak HardFault_Handler
|
||||
.thumb_set HardFault_Handler,Default_Handler
|
||||
|
||||
.weak MemManage_Handler
|
||||
.thumb_set MemManage_Handler,Default_Handler
|
||||
|
||||
.weak BusFault_Handler
|
||||
.thumb_set BusFault_Handler,Default_Handler
|
||||
|
||||
.weak UsageFault_Handler
|
||||
.thumb_set UsageFault_Handler,Default_Handler
|
||||
|
||||
.weak SVC_Handler
|
||||
.thumb_set SVC_Handler,Default_Handler
|
||||
|
||||
.weak DebugMon_Handler
|
||||
.thumb_set DebugMon_Handler,Default_Handler
|
||||
|
||||
.weak PendSV_Handler
|
||||
.thumb_set PendSV_Handler,Default_Handler
|
||||
|
||||
.weak SysTick_Handler
|
||||
.thumb_set SysTick_Handler,Default_Handler
|
||||
|
||||
.weak WWDG_IRQHandler
|
||||
.thumb_set WWDG_IRQHandler,Default_Handler
|
||||
|
||||
.weak PVD_AVD_IRQHandler
|
||||
.thumb_set PVD_AVD_IRQHandler,Default_Handler
|
||||
|
||||
.weak TAMP_STAMP_IRQHandler
|
||||
.thumb_set TAMP_STAMP_IRQHandler,Default_Handler
|
||||
|
||||
.weak RTC_WKUP_IRQHandler
|
||||
.thumb_set RTC_WKUP_IRQHandler,Default_Handler
|
||||
|
||||
.weak FLASH_IRQHandler
|
||||
.thumb_set FLASH_IRQHandler,Default_Handler
|
||||
|
||||
.weak RCC_IRQHandler
|
||||
.thumb_set RCC_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI0_IRQHandler
|
||||
.thumb_set EXTI0_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI1_IRQHandler
|
||||
.thumb_set EXTI1_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI2_IRQHandler
|
||||
.thumb_set EXTI2_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI3_IRQHandler
|
||||
.thumb_set EXTI3_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI4_IRQHandler
|
||||
.thumb_set EXTI4_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Stream0_IRQHandler
|
||||
.thumb_set DMA1_Stream0_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Stream1_IRQHandler
|
||||
.thumb_set DMA1_Stream1_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Stream2_IRQHandler
|
||||
.thumb_set DMA1_Stream2_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Stream3_IRQHandler
|
||||
.thumb_set DMA1_Stream3_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Stream4_IRQHandler
|
||||
.thumb_set DMA1_Stream4_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Stream5_IRQHandler
|
||||
.thumb_set DMA1_Stream5_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Stream6_IRQHandler
|
||||
.thumb_set DMA1_Stream6_IRQHandler,Default_Handler
|
||||
|
||||
.weak ADC_IRQHandler
|
||||
.thumb_set ADC_IRQHandler,Default_Handler
|
||||
|
||||
.weak FDCAN1_IT0_IRQHandler
|
||||
.thumb_set FDCAN1_IT0_IRQHandler,Default_Handler
|
||||
|
||||
.weak FDCAN2_IT0_IRQHandler
|
||||
.thumb_set FDCAN2_IT0_IRQHandler,Default_Handler
|
||||
|
||||
.weak FDCAN1_IT1_IRQHandler
|
||||
.thumb_set FDCAN1_IT1_IRQHandler,Default_Handler
|
||||
|
||||
.weak FDCAN2_IT1_IRQHandler
|
||||
.thumb_set FDCAN2_IT1_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI9_5_IRQHandler
|
||||
.thumb_set EXTI9_5_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM1_BRK_IRQHandler
|
||||
.thumb_set TIM1_BRK_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM1_UP_IRQHandler
|
||||
.thumb_set TIM1_UP_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM1_TRG_COM_IRQHandler
|
||||
.thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM1_CC_IRQHandler
|
||||
.thumb_set TIM1_CC_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM2_IRQHandler
|
||||
.thumb_set TIM2_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM3_IRQHandler
|
||||
.thumb_set TIM3_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM4_IRQHandler
|
||||
.thumb_set TIM4_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C1_EV_IRQHandler
|
||||
.thumb_set I2C1_EV_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C1_ER_IRQHandler
|
||||
.thumb_set I2C1_ER_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C2_EV_IRQHandler
|
||||
.thumb_set I2C2_EV_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C2_ER_IRQHandler
|
||||
.thumb_set I2C2_ER_IRQHandler,Default_Handler
|
||||
|
||||
.weak SPI1_IRQHandler
|
||||
.thumb_set SPI1_IRQHandler,Default_Handler
|
||||
|
||||
.weak SPI2_IRQHandler
|
||||
.thumb_set SPI2_IRQHandler,Default_Handler
|
||||
|
||||
.weak USART1_IRQHandler
|
||||
.thumb_set USART1_IRQHandler,Default_Handler
|
||||
|
||||
.weak USART2_IRQHandler
|
||||
.thumb_set USART2_IRQHandler,Default_Handler
|
||||
|
||||
.weak USART3_IRQHandler
|
||||
.thumb_set USART3_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI15_10_IRQHandler
|
||||
.thumb_set EXTI15_10_IRQHandler,Default_Handler
|
||||
|
||||
.weak RTC_Alarm_IRQHandler
|
||||
.thumb_set RTC_Alarm_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM8_BRK_TIM12_IRQHandler
|
||||
.thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM8_UP_TIM13_IRQHandler
|
||||
.thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM8_TRG_COM_TIM14_IRQHandler
|
||||
.thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM8_CC_IRQHandler
|
||||
.thumb_set TIM8_CC_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Stream7_IRQHandler
|
||||
.thumb_set DMA1_Stream7_IRQHandler,Default_Handler
|
||||
|
||||
.weak FMC_IRQHandler
|
||||
.thumb_set FMC_IRQHandler,Default_Handler
|
||||
|
||||
.weak SDMMC1_IRQHandler
|
||||
.thumb_set SDMMC1_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM5_IRQHandler
|
||||
.thumb_set TIM5_IRQHandler,Default_Handler
|
||||
|
||||
.weak SPI3_IRQHandler
|
||||
.thumb_set SPI3_IRQHandler,Default_Handler
|
||||
|
||||
.weak UART4_IRQHandler
|
||||
.thumb_set UART4_IRQHandler,Default_Handler
|
||||
|
||||
.weak UART5_IRQHandler
|
||||
.thumb_set UART5_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM6_DAC_IRQHandler
|
||||
.thumb_set TIM6_DAC_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM7_IRQHandler
|
||||
.thumb_set TIM7_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA2_Stream0_IRQHandler
|
||||
.thumb_set DMA2_Stream0_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA2_Stream1_IRQHandler
|
||||
.thumb_set DMA2_Stream1_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA2_Stream2_IRQHandler
|
||||
.thumb_set DMA2_Stream2_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA2_Stream3_IRQHandler
|
||||
.thumb_set DMA2_Stream3_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA2_Stream4_IRQHandler
|
||||
.thumb_set DMA2_Stream4_IRQHandler,Default_Handler
|
||||
|
||||
.weak ETH_IRQHandler
|
||||
.thumb_set ETH_IRQHandler,Default_Handler
|
||||
|
||||
.weak ETH_WKUP_IRQHandler
|
||||
.thumb_set ETH_WKUP_IRQHandler,Default_Handler
|
||||
|
||||
.weak FDCAN_CAL_IRQHandler
|
||||
.thumb_set FDCAN_CAL_IRQHandler,Default_Handler
|
||||
|
||||
.weak CM7_SEV_IRQHandler
|
||||
.thumb_set CM7_SEV_IRQHandler,Default_Handler
|
||||
|
||||
.weak CM4_SEV_IRQHandler
|
||||
.thumb_set CM4_SEV_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA2_Stream5_IRQHandler
|
||||
.thumb_set DMA2_Stream5_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA2_Stream6_IRQHandler
|
||||
.thumb_set DMA2_Stream6_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA2_Stream7_IRQHandler
|
||||
.thumb_set DMA2_Stream7_IRQHandler,Default_Handler
|
||||
|
||||
.weak USART6_IRQHandler
|
||||
.thumb_set USART6_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C3_EV_IRQHandler
|
||||
.thumb_set I2C3_EV_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C3_ER_IRQHandler
|
||||
.thumb_set I2C3_ER_IRQHandler,Default_Handler
|
||||
|
||||
.weak OTG_HS_EP1_OUT_IRQHandler
|
||||
.thumb_set OTG_HS_EP1_OUT_IRQHandler,Default_Handler
|
||||
|
||||
.weak OTG_HS_EP1_IN_IRQHandler
|
||||
.thumb_set OTG_HS_EP1_IN_IRQHandler,Default_Handler
|
||||
|
||||
.weak OTG_HS_WKUP_IRQHandler
|
||||
.thumb_set OTG_HS_WKUP_IRQHandler,Default_Handler
|
||||
|
||||
.weak OTG_HS_IRQHandler
|
||||
.thumb_set OTG_HS_IRQHandler,Default_Handler
|
||||
|
||||
.weak DCMI_IRQHandler
|
||||
.thumb_set DCMI_IRQHandler,Default_Handler
|
||||
|
||||
.weak RNG_IRQHandler
|
||||
.thumb_set RNG_IRQHandler,Default_Handler
|
||||
|
||||
.weak FPU_IRQHandler
|
||||
.thumb_set FPU_IRQHandler,Default_Handler
|
||||
|
||||
.weak UART7_IRQHandler
|
||||
.thumb_set UART7_IRQHandler,Default_Handler
|
||||
|
||||
.weak UART8_IRQHandler
|
||||
.thumb_set UART8_IRQHandler,Default_Handler
|
||||
|
||||
.weak SPI4_IRQHandler
|
||||
.thumb_set SPI4_IRQHandler,Default_Handler
|
||||
|
||||
.weak SPI5_IRQHandler
|
||||
.thumb_set SPI5_IRQHandler,Default_Handler
|
||||
|
||||
.weak SPI6_IRQHandler
|
||||
.thumb_set SPI6_IRQHandler,Default_Handler
|
||||
|
||||
.weak SAI1_IRQHandler
|
||||
.thumb_set SAI1_IRQHandler,Default_Handler
|
||||
|
||||
.weak LTDC_IRQHandler
|
||||
.thumb_set LTDC_IRQHandler,Default_Handler
|
||||
|
||||
.weak LTDC_ER_IRQHandler
|
||||
.thumb_set LTDC_ER_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA2D_IRQHandler
|
||||
.thumb_set DMA2D_IRQHandler,Default_Handler
|
||||
|
||||
.weak SAI2_IRQHandler
|
||||
.thumb_set SAI2_IRQHandler,Default_Handler
|
||||
|
||||
.weak QUADSPI_IRQHandler
|
||||
.thumb_set QUADSPI_IRQHandler,Default_Handler
|
||||
|
||||
.weak LPTIM1_IRQHandler
|
||||
.thumb_set LPTIM1_IRQHandler,Default_Handler
|
||||
|
||||
.weak CEC_IRQHandler
|
||||
.thumb_set CEC_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C4_EV_IRQHandler
|
||||
.thumb_set I2C4_EV_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C4_ER_IRQHandler
|
||||
.thumb_set I2C4_ER_IRQHandler,Default_Handler
|
||||
|
||||
.weak SPDIF_RX_IRQHandler
|
||||
.thumb_set SPDIF_RX_IRQHandler,Default_Handler
|
||||
|
||||
.weak OTG_FS_EP1_OUT_IRQHandler
|
||||
.thumb_set OTG_FS_EP1_OUT_IRQHandler,Default_Handler
|
||||
|
||||
.weak OTG_FS_EP1_IN_IRQHandler
|
||||
.thumb_set OTG_FS_EP1_IN_IRQHandler,Default_Handler
|
||||
|
||||
.weak OTG_FS_WKUP_IRQHandler
|
||||
.thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler
|
||||
|
||||
.weak OTG_FS_IRQHandler
|
||||
.thumb_set OTG_FS_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMAMUX1_OVR_IRQHandler
|
||||
.thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler
|
||||
|
||||
.weak HRTIM1_Master_IRQHandler
|
||||
.thumb_set HRTIM1_Master_IRQHandler,Default_Handler
|
||||
|
||||
.weak HRTIM1_TIMA_IRQHandler
|
||||
.thumb_set HRTIM1_TIMA_IRQHandler,Default_Handler
|
||||
|
||||
.weak HRTIM1_TIMB_IRQHandler
|
||||
.thumb_set HRTIM1_TIMB_IRQHandler,Default_Handler
|
||||
|
||||
.weak HRTIM1_TIMC_IRQHandler
|
||||
.thumb_set HRTIM1_TIMC_IRQHandler,Default_Handler
|
||||
|
||||
.weak HRTIM1_TIMD_IRQHandler
|
||||
.thumb_set HRTIM1_TIMD_IRQHandler,Default_Handler
|
||||
|
||||
.weak HRTIM1_TIME_IRQHandler
|
||||
.thumb_set HRTIM1_TIME_IRQHandler,Default_Handler
|
||||
|
||||
.weak HRTIM1_FLT_IRQHandler
|
||||
.thumb_set HRTIM1_FLT_IRQHandler,Default_Handler
|
||||
|
||||
.weak DFSDM1_FLT0_IRQHandler
|
||||
.thumb_set DFSDM1_FLT0_IRQHandler,Default_Handler
|
||||
|
||||
.weak DFSDM1_FLT1_IRQHandler
|
||||
.thumb_set DFSDM1_FLT1_IRQHandler,Default_Handler
|
||||
|
||||
.weak DFSDM1_FLT2_IRQHandler
|
||||
.thumb_set DFSDM1_FLT2_IRQHandler,Default_Handler
|
||||
|
||||
.weak DFSDM1_FLT3_IRQHandler
|
||||
.thumb_set DFSDM1_FLT3_IRQHandler,Default_Handler
|
||||
|
||||
.weak SAI3_IRQHandler
|
||||
.thumb_set SAI3_IRQHandler,Default_Handler
|
||||
|
||||
.weak SWPMI1_IRQHandler
|
||||
.thumb_set SWPMI1_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM15_IRQHandler
|
||||
.thumb_set TIM15_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM16_IRQHandler
|
||||
.thumb_set TIM16_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM17_IRQHandler
|
||||
.thumb_set TIM17_IRQHandler,Default_Handler
|
||||
|
||||
.weak MDIOS_WKUP_IRQHandler
|
||||
.thumb_set MDIOS_WKUP_IRQHandler,Default_Handler
|
||||
|
||||
.weak MDIOS_IRQHandler
|
||||
.thumb_set MDIOS_IRQHandler,Default_Handler
|
||||
|
||||
.weak JPEG_IRQHandler
|
||||
.thumb_set JPEG_IRQHandler,Default_Handler
|
||||
|
||||
.weak MDMA_IRQHandler
|
||||
.thumb_set MDMA_IRQHandler,Default_Handler
|
||||
|
||||
.weak DSI_IRQHandler
|
||||
.thumb_set DSI_IRQHandler,Default_Handler
|
||||
|
||||
.weak SDMMC2_IRQHandler
|
||||
.thumb_set SDMMC2_IRQHandler,Default_Handler
|
||||
|
||||
.weak HSEM1_IRQHandler
|
||||
.thumb_set HSEM1_IRQHandler,Default_Handler
|
||||
|
||||
.weak HSEM2_IRQHandler
|
||||
.thumb_set HSEM2_IRQHandler,Default_Handler
|
||||
|
||||
.weak ADC3_IRQHandler
|
||||
.thumb_set ADC3_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMAMUX2_OVR_IRQHandler
|
||||
.thumb_set DMAMUX2_OVR_IRQHandler,Default_Handler
|
||||
|
||||
.weak BDMA_Channel0_IRQHandler
|
||||
.thumb_set BDMA_Channel0_IRQHandler,Default_Handler
|
||||
|
||||
.weak BDMA_Channel1_IRQHandler
|
||||
.thumb_set BDMA_Channel1_IRQHandler,Default_Handler
|
||||
|
||||
.weak BDMA_Channel2_IRQHandler
|
||||
.thumb_set BDMA_Channel2_IRQHandler,Default_Handler
|
||||
|
||||
.weak BDMA_Channel3_IRQHandler
|
||||
.thumb_set BDMA_Channel3_IRQHandler,Default_Handler
|
||||
|
||||
.weak BDMA_Channel4_IRQHandler
|
||||
.thumb_set BDMA_Channel4_IRQHandler,Default_Handler
|
||||
|
||||
.weak BDMA_Channel5_IRQHandler
|
||||
.thumb_set BDMA_Channel5_IRQHandler,Default_Handler
|
||||
|
||||
.weak BDMA_Channel6_IRQHandler
|
||||
.thumb_set BDMA_Channel6_IRQHandler,Default_Handler
|
||||
|
||||
.weak BDMA_Channel7_IRQHandler
|
||||
.thumb_set BDMA_Channel7_IRQHandler,Default_Handler
|
||||
|
||||
.weak COMP1_IRQHandler
|
||||
.thumb_set COMP1_IRQHandler,Default_Handler
|
||||
|
||||
.weak LPTIM2_IRQHandler
|
||||
.thumb_set LPTIM2_IRQHandler,Default_Handler
|
||||
|
||||
.weak LPTIM3_IRQHandler
|
||||
.thumb_set LPTIM3_IRQHandler,Default_Handler
|
||||
|
||||
.weak LPTIM4_IRQHandler
|
||||
.thumb_set LPTIM4_IRQHandler,Default_Handler
|
||||
|
||||
.weak LPTIM5_IRQHandler
|
||||
.thumb_set LPTIM5_IRQHandler,Default_Handler
|
||||
|
||||
.weak LPUART1_IRQHandler
|
||||
.thumb_set LPUART1_IRQHandler,Default_Handler
|
||||
|
||||
.weak WWDG_RST_IRQHandler
|
||||
.thumb_set WWDG_RST_IRQHandler,Default_Handler
|
||||
|
||||
.weak CRS_IRQHandler
|
||||
.thumb_set CRS_IRQHandler,Default_Handler
|
||||
|
||||
.weak ECC_IRQHandler
|
||||
.thumb_set ECC_IRQHandler,Default_Handler
|
||||
|
||||
.weak SAI4_IRQHandler
|
||||
.thumb_set SAI4_IRQHandler,Default_Handler
|
||||
|
||||
.weak HOLD_CORE_IRQHandler
|
||||
.thumb_set HOLD_CORE_IRQHandler,Default_Handler
|
||||
|
||||
.weak WAKEUP_PIN_IRQHandler
|
||||
.thumb_set WAKEUP_PIN_IRQHandler,Default_Handler
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
||||
@ -213,10 +213,14 @@ void SystemClock_Config(void)
|
||||
#endif
|
||||
|
||||
/* Enable HSE Oscillator and activate PLL with HSE as source */
|
||||
RCC_OscInitStruct.HSEState = RCC_HSE_ON;
|
||||
RCC_OscInitStruct.HSIState = RCC_HSI_OFF;
|
||||
#if defined(MCU_SERIES_H7)
|
||||
RCC_OscInitStruct.CSIState = RCC_CSI_OFF;
|
||||
#if defined(OMV_OSC_HSE_STATE)
|
||||
RCC_OscInitStruct.HSEState = OMV_OSC_HSE_STATE;
|
||||
#endif
|
||||
#if defined(OMV_OSC_HSI_STATE)
|
||||
RCC_OscInitStruct.HSIState = OMV_OSC_HSI_STATE;
|
||||
#endif
|
||||
#if defined(OMV_OSC_CSI_STATE)
|
||||
RCC_OscInitStruct.CSIState = OMV_OSC_CSI_STATE;
|
||||
#endif
|
||||
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
|
||||
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
|
||||
|
||||
@ -35,6 +35,12 @@
|
||||
#define OMV_OSC_PLL1N (336)
|
||||
#define OMV_OSC_PLL1P (2)
|
||||
#define OMV_OSC_PLL1Q (7)
|
||||
|
||||
// HSE/HSI/CSI State
|
||||
#define OMV_OSC_HSE_STATE (RCC_HSE_ON)
|
||||
#define OMV_OSC_HSI_STATE (RCC_HSI_OFF)
|
||||
|
||||
// Flash Latency
|
||||
#define OMV_FLASH_LATENCY (FLASH_LATENCY_5)
|
||||
|
||||
// Linker script constants (see the linker script template stm32fxxx.ld.S).
|
||||
|
||||
@ -8,4 +8,5 @@ CFLAGS_MCU=MCU_SERIES_F4
|
||||
STARTUP=startup_stm32f407xx
|
||||
VECT_TAB_OFFSET=0x10000
|
||||
MAIN_APP_ADDR=0x08010000
|
||||
OMV_HSE_VALUE=12000000
|
||||
MICROPY_PY_WINC1500 = 1
|
||||
|
||||
@ -61,6 +61,12 @@
|
||||
#define OMV_OSC_PLL1N (384)
|
||||
#define OMV_OSC_PLL1P (2)
|
||||
#define OMV_OSC_PLL1Q (8)
|
||||
|
||||
// HSE/HSI/CSI State
|
||||
#define OMV_OSC_HSE_STATE (RCC_HSE_ON)
|
||||
#define OMV_OSC_HSI_STATE (RCC_HSI_OFF)
|
||||
|
||||
// Flash Latency
|
||||
#define OMV_FLASH_LATENCY (FLASH_LATENCY_7)
|
||||
|
||||
// Linker script constants (see the linker script template stm32fxxx.ld.S).
|
||||
|
||||
@ -8,4 +8,5 @@ CFLAGS_MCU=MCU_SERIES_F4
|
||||
STARTUP=startup_stm32f427xx
|
||||
VECT_TAB_OFFSET=0x10000
|
||||
MAIN_APP_ADDR=0x08010000
|
||||
OMV_HSE_VALUE=12000000
|
||||
MICROPY_PY_WINC1500 = 1
|
||||
|
||||
@ -62,6 +62,12 @@
|
||||
#define OMV_OSC_PLL1P (2)
|
||||
#define OMV_OSC_PLL1Q (9)
|
||||
#define OMV_OSC_PLL1R (2)
|
||||
|
||||
// HSE/HSI/CSI State
|
||||
#define OMV_OSC_HSE_STATE (RCC_HSE_ON)
|
||||
#define OMV_OSC_HSI_STATE (RCC_HSI_OFF)
|
||||
|
||||
// Flash Latency
|
||||
#define OMV_FLASH_LATENCY (FLASH_LATENCY_7)
|
||||
|
||||
// Linker script constants (see the linker script template stm32fxxx.ld.S).
|
||||
|
||||
@ -8,6 +8,7 @@ CFLAGS_MCU=MCU_SERIES_F7
|
||||
STARTUP=startup_stm32f765xx
|
||||
VECT_TAB_OFFSET=0x20000
|
||||
MAIN_APP_ADDR=0x08020000
|
||||
OMV_HSE_VALUE=12000000
|
||||
FROZEN_MPY_DIR=$(TOP_DIR)/../scripts/libraries
|
||||
MICROPY_PY_ULAB = 1
|
||||
MICROPY_PY_WINC1500 = 1
|
||||
|
||||
@ -99,6 +99,12 @@
|
||||
#define OMV_OSC_PLL3VCO (RCC_PLL3VCOWIDE)
|
||||
#define OMV_OSC_PLL3FRAC (0)
|
||||
|
||||
// HSE/HSI/CSI State
|
||||
#define OMV_OSC_HSE_STATE (RCC_HSE_ON)
|
||||
#define OMV_OSC_HSI_STATE (RCC_HSI_OFF)
|
||||
#define OMV_OSC_CSI_STATE (RCC_CSI_OFF)
|
||||
|
||||
// Flash Latency
|
||||
#define OMV_FLASH_LATENCY (FLASH_LATENCY_2)
|
||||
|
||||
// Linker script constants (see the linker script template stm32fxxx.ld.S).
|
||||
|
||||
@ -8,6 +8,7 @@ CFLAGS_MCU=MCU_SERIES_H7
|
||||
STARTUP=startup_stm32h743xx
|
||||
VECT_TAB_OFFSET=0x40000
|
||||
MAIN_APP_ADDR=0x08040000
|
||||
OMV_HSE_VALUE=12000000
|
||||
FROZEN_MPY_DIR=$(TOP_DIR)/../scripts/libraries
|
||||
MICROPY_PY_ULAB = 1
|
||||
MICROPY_PY_WINC1500 = 1
|
||||
|
||||
@ -100,6 +100,12 @@
|
||||
#define OMV_OSC_PLL3VCO (RCC_PLL3VCOWIDE)
|
||||
#define OMV_OSC_PLL3FRAC (0)
|
||||
|
||||
// HSE/HSI/CSI State
|
||||
#define OMV_OSC_HSE_STATE (RCC_HSE_ON)
|
||||
#define OMV_OSC_HSI_STATE (RCC_HSI_OFF)
|
||||
#define OMV_OSC_CSI_STATE (RCC_CSI_OFF)
|
||||
|
||||
// Flash Latency
|
||||
#define OMV_FLASH_LATENCY (FLASH_LATENCY_2)
|
||||
|
||||
// Linker script constants (see the linker script template stm32fxxx.ld.S).
|
||||
@ -340,9 +346,9 @@
|
||||
#define QSPIF_D3_GPIO_CLK_ENABLE() __HAL_RCC_GPIOF_CLK_ENABLE()
|
||||
|
||||
// Enable additional GPIO banks for DRAM...
|
||||
#define ENABLE_GPIO_BANK_F
|
||||
#define ENABLE_GPIO_BANK_G
|
||||
#define ENABLE_GPIO_BANK_H
|
||||
#define ENABLE_GPIO_BANK_I
|
||||
#define OMV_ENABLE_GPIO_BANK_F
|
||||
#define OMV_ENABLE_GPIO_BANK_G
|
||||
#define OMV_ENABLE_GPIO_BANK_H
|
||||
#define OMV_ENABLE_GPIO_BANK_I
|
||||
|
||||
#endif //__OMV_BOARDCONFIG_H__
|
||||
|
||||
@ -8,6 +8,7 @@ CFLAGS_MCU=MCU_SERIES_H7
|
||||
STARTUP=startup_stm32h743xx
|
||||
VECT_TAB_OFFSET=0x40000
|
||||
MAIN_APP_ADDR=0x08040000
|
||||
OMV_HSE_VALUE=12000000
|
||||
FROZEN_MPY_DIR=$(TOP_DIR)/../scripts/libraries
|
||||
MICROPY_PY_ULAB = 1
|
||||
MICROPY_PY_WINC1500 = 1
|
||||
|
||||
162
src/omv/boards/PORTENTA/imlib_config.h
Normal file
162
src/omv/boards/PORTENTA/imlib_config.h
Normal file
@ -0,0 +1,162 @@
|
||||
/*
|
||||
* This file is part of the OpenMV project.
|
||||
*
|
||||
* Copyright (c) 2013-2019 Ibrahim Abdelkader <iabdalkader@openmv.io>
|
||||
* Copyright (c) 2013-2019 Kwabena W. Agyeman <kwagyeman@openmv.io>
|
||||
*
|
||||
* This work is licensed under the MIT license, see the file LICENSE for details.
|
||||
*
|
||||
* Image library configuration.
|
||||
*/
|
||||
#ifndef __IMLIB_CONFIG_H__
|
||||
#define __IMLIB_CONFIG_H__
|
||||
|
||||
// Enable LAB LUT
|
||||
#define IMLIB_ENABLE_LAB_LUT
|
||||
|
||||
// Enable YUV LUT
|
||||
//#define IMLIB_ENABLE_YUV_LUT
|
||||
|
||||
// Enable mean pooling
|
||||
#define IMLIB_ENABLE_MEAN_POOLING
|
||||
|
||||
// Enable midpoint pooling
|
||||
#define IMLIB_ENABLE_MIDPOINT_POOLING
|
||||
|
||||
// Enable binary ops
|
||||
#define IMLIB_ENABLE_BINARY_OPS
|
||||
|
||||
// Enable math ops
|
||||
#define IMLIB_ENABLE_MATH_OPS
|
||||
|
||||
// Enable flood_fill()
|
||||
#define IMLIB_ENABLE_FLOOD_FILL
|
||||
|
||||
// Enable mean()
|
||||
#define IMLIB_ENABLE_MEAN
|
||||
|
||||
// Enable median()
|
||||
#define IMLIB_ENABLE_MEDIAN
|
||||
|
||||
// Enable mode()
|
||||
#define IMLIB_ENABLE_MODE
|
||||
|
||||
// Enable midpoint()
|
||||
#define IMLIB_ENABLE_MIDPOINT
|
||||
|
||||
// Enable morph()
|
||||
#define IMLIB_ENABLE_MORPH
|
||||
|
||||
// Enable Gaussian
|
||||
#define IMLIB_ENABLE_GAUSSIAN
|
||||
|
||||
// Enable Laplacian
|
||||
#define IMLIB_ENABLE_LAPLACIAN
|
||||
|
||||
// Enable bilateral()
|
||||
#define IMLIB_ENABLE_BILATERAL
|
||||
|
||||
// Enable cartoon()
|
||||
#define IMLIB_ENABLE_CARTOON
|
||||
|
||||
// Enable remove_shadows()
|
||||
#define IMLIB_ENABLE_REMOVE_SHADOWS
|
||||
|
||||
// Enable linpolar()
|
||||
#define IMLIB_ENABLE_LINPOLAR
|
||||
|
||||
// Enable logpolar()
|
||||
#define IMLIB_ENABLE_LOGPOLAR
|
||||
|
||||
// Enable chrominvar()
|
||||
#define IMLIB_ENABLE_CHROMINVAR
|
||||
|
||||
// Enable illuminvar()
|
||||
#define IMLIB_ENABLE_ILLUMINVAR
|
||||
|
||||
// Enable invariant table
|
||||
//#define IMLIB_ENABLE_INVARIANT_TABLE
|
||||
|
||||
// Enable rotation_corr()
|
||||
#define IMLIB_ENABLE_ROTATION_CORR
|
||||
|
||||
// Enable phasecorrelate()
|
||||
#define IMLIB_ENABLE_FIND_DISPLACEMENT
|
||||
|
||||
// rotation_corr() is required by phasecorrelate()
|
||||
#if defined(IMLIB_ENABLE_FIND_DISPLACEMENT)\
|
||||
&& !defined(IMLIB_ENABLE_ROTATION_CORR)
|
||||
#define IMLIB_ENABLE_ROTATION_CORR
|
||||
#endif
|
||||
|
||||
// Enable get_similarity()
|
||||
#define IMLIB_ENABLE_GET_SIMILARITY
|
||||
|
||||
// Enable find_lines()
|
||||
#define IMLIB_ENABLE_FIND_LINES
|
||||
|
||||
// Enable find_line_segments()
|
||||
#define IMLIB_ENABLE_FIND_LINE_SEGMENTS
|
||||
|
||||
// find_lines() is required by the old find_line_segments()
|
||||
#if defined(IMLIB_ENABLE_FIND_LINE_SEGMENTS)\
|
||||
&& !defined(IMLIB_ENABLE_FIND_LINES)
|
||||
#define IMLIB_ENABLE_FIND_LINES
|
||||
#endif
|
||||
|
||||
// Enable find_circles()
|
||||
#define IMLIB_ENABLE_FIND_CIRCLES
|
||||
|
||||
// Enable find_rects()
|
||||
#define IMLIB_ENABLE_FIND_RECTS
|
||||
|
||||
// Enable find_qrcodes() (14 KB)
|
||||
#define IMLIB_ENABLE_QRCODES
|
||||
|
||||
// Enable find_apriltags() (64 KB)
|
||||
#define IMLIB_ENABLE_APRILTAGS
|
||||
|
||||
// Enable fine find_apriltags() - (8-way connectivity versus 4-way connectivity)
|
||||
// #define IMLIB_ENABLE_FINE_APRILTAGS
|
||||
|
||||
// Enable high res find_apriltags() - uses more RAM
|
||||
// #define IMLIB_ENABLE_HIGH_RES_APRILTAGS
|
||||
|
||||
// Enable find_datamatrices() (26 KB)
|
||||
#define IMLIB_ENABLE_DATAMATRICES
|
||||
|
||||
// Enable find_barcodes() (42 KB)
|
||||
#define IMLIB_ENABLE_BARCODES
|
||||
|
||||
// Enable LENET (200+ KB).
|
||||
#define IMLIB_ENABLE_LENET
|
||||
|
||||
// Enable CMSIS NN
|
||||
#define IMLIB_ENABLE_CNN
|
||||
|
||||
// Enable Tensor Flow
|
||||
#define IMLIB_ENABLE_TF
|
||||
|
||||
// Enable FAST (20+ KBs).
|
||||
#define IMLIB_ENABLE_FAST
|
||||
|
||||
// Enable find_template()
|
||||
#define IMLIB_FIND_TEMPLATE
|
||||
|
||||
// Enable find_lbp()
|
||||
#define IMLIB_ENABLE_FIND_LBP
|
||||
|
||||
// Enable find_keypoints()
|
||||
#define IMLIB_ENABLE_FIND_KEYPOINTS
|
||||
|
||||
#if defined(IMLIB_ENABLE_FIND_LBP) || defined(IMLIB_ENABLE_FIND_KEYPOINTS)
|
||||
#define IMLIB_ENABLE_DESCRIPTOR
|
||||
#endif
|
||||
|
||||
// Enable find_hog()
|
||||
#define IMLIB_ENABLE_HOG
|
||||
|
||||
// Enable selective_search()
|
||||
#define IMLIB_ENABLE_SELECTIVE_SEARCH
|
||||
|
||||
#endif //__IMLIB_CONFIG_H__
|
||||
236
src/omv/boards/PORTENTA/omv_boardconfig.h
Normal file
236
src/omv/boards/PORTENTA/omv_boardconfig.h
Normal file
@ -0,0 +1,236 @@
|
||||
/*
|
||||
* This file is part of the OpenMV project.
|
||||
*
|
||||
* Copyright (c) 2013-2019 Ibrahim Abdelkader <iabdalkader@openmv.io>
|
||||
* Copyright (c) 2013-2019 Kwabena W. Agyeman <kwagyeman@openmv.io>
|
||||
*
|
||||
* This work is licensed under the MIT license, see the file LICENSE for details.
|
||||
*
|
||||
* Board configuration and pin definitions.
|
||||
*/
|
||||
#ifndef __OMV_BOARDCONFIG_H__
|
||||
#define __OMV_BOARDCONFIG_H__
|
||||
|
||||
// Architecture info
|
||||
#define OMV_ARCH_STR "PORTENTA H7 8192 SDRAM" // 33 chars max
|
||||
#define OMV_BOARD_TYPE "H7"
|
||||
#define OMV_UNIQUE_ID_ADDR 0x1FF1E800
|
||||
|
||||
// Flash sectors for the bootloader.
|
||||
// Flash FS sector, main FW sector, max sector.
|
||||
#define OMV_FLASH_LAYOUT {1, 2, 15}
|
||||
|
||||
#define OMV_XCLK_MCO (0U)
|
||||
#define OMV_XCLK_TIM (1U)
|
||||
#define OMV_XCLK_OSC (2U)
|
||||
|
||||
// Sensor external clock source.
|
||||
#define OMV_XCLK_SOURCE (OMV_XCLK_OSC)
|
||||
|
||||
// Sensor external clock timer frequency.
|
||||
#define OMV_XCLK_FREQUENCY (12000000)
|
||||
|
||||
// Sensor PLL register value.
|
||||
#define OMV_OV7725_PLL_CONFIG (0x41) // x4
|
||||
|
||||
// Sensor Banding Filter Value
|
||||
#define OMV_OV7725_BANDING (0x7F)
|
||||
|
||||
// Bootloader LED GPIO port/pin
|
||||
#define OMV_BOOTLDR_LED_PIN (GPIO_PIN_1)
|
||||
#define OMV_BOOTLDR_LED_PORT (GPIOC)
|
||||
|
||||
// RAW buffer size
|
||||
#define OMV_RAW_BUF_SIZE (409600)
|
||||
|
||||
// Enable hardware JPEG
|
||||
#define OMV_HARDWARE_JPEG (1)
|
||||
|
||||
// Enable HIMAX HM01B0 sensor
|
||||
#define OMV_ENABLE_HM01B0 (1)
|
||||
|
||||
// Enable WiFi debug
|
||||
#define OMV_ENABLE_WIFIDBG (0)
|
||||
|
||||
// If buffer size is bigger than this threshold, the quality is reduced.
|
||||
// This is only used for JPEG images sent to the IDE not normal compression.
|
||||
#define JPEG_QUALITY_THRESH (320*240*2)
|
||||
|
||||
// Low and high JPEG QS.
|
||||
#define JPEG_QUALITY_LOW 50
|
||||
#define JPEG_QUALITY_HIGH 90
|
||||
|
||||
// FB Heap Block Size
|
||||
#define OMV_UMM_BLOCK_SIZE 16
|
||||
|
||||
//PLL1 480MHz/48MHz for USB, SDMMC and FDCAN
|
||||
#define OMV_OSC_PLL1M (9)
|
||||
#define OMV_OSC_PLL1N (320)
|
||||
#define OMV_OSC_PLL1P (2)
|
||||
#define OMV_OSC_PLL1Q (20)
|
||||
#define OMV_OSC_PLL1R (2)
|
||||
#define OMV_OSC_PLL1VCI (RCC_PLL1VCIRANGE_2)
|
||||
#define OMV_OSC_PLL1VCO (RCC_PLL1VCOWIDE)
|
||||
#define OMV_OSC_PLL1FRAC (0)
|
||||
|
||||
// Core VBAT for selftests
|
||||
#define OMV_CORE_VBAT "3.0"
|
||||
|
||||
// PLL2 180MHz for FMC and QSPI.
|
||||
#define OMV_OSC_PLL2M (3)
|
||||
#define OMV_OSC_PLL2N (40)
|
||||
#define OMV_OSC_PLL2P (2)
|
||||
#define OMV_OSC_PLL2Q (2)
|
||||
#define OMV_OSC_PLL2R (2)
|
||||
#define OMV_OSC_PLL2VCI (RCC_PLL2VCIRANGE_2)
|
||||
#define OMV_OSC_PLL2VCO (RCC_PLL2VCOWIDE)
|
||||
#define OMV_OSC_PLL2FRAC (0)
|
||||
|
||||
// PLL3 160MHz for ADC and SPI123
|
||||
#define OMV_OSC_PLL3M (9)
|
||||
#define OMV_OSC_PLL3N (320)
|
||||
#define OMV_OSC_PLL3P (2)
|
||||
#define OMV_OSC_PLL3Q (6)
|
||||
#define OMV_OSC_PLL3R (2)
|
||||
#define OMV_OSC_PLL3VCI (RCC_PLL3VCIRANGE_2)
|
||||
#define OMV_OSC_PLL3VCO (RCC_PLL3VCOWIDE)
|
||||
#define OMV_OSC_PLL3FRAC (0)
|
||||
|
||||
// HSE/HSI/CSI State
|
||||
#define OMV_OSC_HSE_STATE (RCC_HSE_BYPASS)
|
||||
#define OMV_OSC_HSI_STATE (RCC_HSI_OFF)
|
||||
#define OMV_OSC_CSI_STATE (RCC_CSI_OFF)
|
||||
|
||||
// Flash Latency
|
||||
#define OMV_FLASH_LATENCY (FLASH_LATENCY_2)
|
||||
|
||||
// Linker script constants (see the linker script template stm32fxxx.ld.S).
|
||||
// Note: fb_alloc is a stack-based, dynamically allocated memory on FB.
|
||||
// The maximum available fb_alloc memory = FB_ALLOC_SIZE + FB_SIZE - (w*h*bpp).
|
||||
#define OMV_FFS_MEMORY CCM // Flash filesystem cache memory
|
||||
#define OMV_MAIN_MEMORY SRAM1 // data, bss, stack and heap
|
||||
#define OMV_DMA_MEMORY AXI_SRAM // DMA buffers memory.
|
||||
#define OMV_FB_MEMORY AXI_SRAM // Framebuffer, fb_alloc
|
||||
#define OMV_JPEG_MEMORY SRAM3 // JPEG buffer memory.
|
||||
#define OMV_VOSPI_MEMORY SRAM4 // VoSPI buffer memory.
|
||||
|
||||
#define OMV_FB_SIZE (400K) // FB memory: header + VGA/GS image
|
||||
#define OMV_FB_ALLOC_SIZE (96K) // minimum fb alloc size
|
||||
#define OMV_STACK_SIZE (8K)
|
||||
#define OMV_HEAP_SIZE (234K)
|
||||
|
||||
#define OMV_LINE_BUF_SIZE (3K) // Image line buffer round(640 * 2BPP * 2 buffers).
|
||||
#define OMV_MSC_BUF_SIZE (12K) // USB MSC bot data
|
||||
#define OMV_VFS_BUF_SIZE (1K) // VFS sturct + FATFS file buffer (624 bytes)
|
||||
#define OMV_JPEG_BUF_SIZE (32 * 1024) // IDE JPEG buffer (header + data).
|
||||
|
||||
#define OMV_BOOT_ORIGIN 0x08000000
|
||||
#define OMV_BOOT_LENGTH 128K
|
||||
#define OMV_TEXT_ORIGIN 0x08040000
|
||||
#define OMV_TEXT_LENGTH 1792K
|
||||
#define OMV_CCM_ORIGIN 0x20000000 // Note accessible by CPU and MDMA only.
|
||||
#define OMV_CCM_LENGTH 128K
|
||||
#define OMV_SRAM1_ORIGIN 0x30000000
|
||||
#define OMV_SRAM1_LENGTH 256K
|
||||
#define OMV_SRAM3_ORIGIN 0x30040000
|
||||
#define OMV_SRAM3_LENGTH 32K
|
||||
#define OMV_SRAM4_ORIGIN 0x38000000
|
||||
#define OMV_SRAM4_LENGTH 64K
|
||||
#define OMV_AXI_SRAM_ORIGIN 0x24000000
|
||||
#define OMV_AXI_SRAM_LENGTH 512K
|
||||
|
||||
// Use the MPU to set an uncacheable memory region.
|
||||
#define OMV_DMA_REGION_BASE (OMV_AXI_SRAM_ORIGIN+(496*1024))
|
||||
#define OMV_DMA_REGION_SIZE MPU_REGION_SIZE_16KB
|
||||
|
||||
/* SCCB/I2C */
|
||||
#define SCCB_I2C (I2C1)
|
||||
#define SCCB_AF (GPIO_AF4_I2C1)
|
||||
#define SCCB_CLK_ENABLE() __I2C1_CLK_ENABLE()
|
||||
#define SCCB_CLK_DISABLE() __I2C1_CLK_DISABLE()
|
||||
#define SCCB_PORT (GPIOB)
|
||||
#define SCCB_SCL_PIN (GPIO_PIN_6)
|
||||
#define SCCB_SDA_PIN (GPIO_PIN_7)
|
||||
#define SCCB_TIMING (0x20D09DE7) // Frequency: 100KHz Rise Time: 100ns Fall Time: 20ns
|
||||
|
||||
#define DCMI_PWDN_PIN (GPIO_PIN_4)
|
||||
#define DCMI_PWDN_PORT (GPIOD)
|
||||
|
||||
#define DCMI_FSIN_PIN (GPIO_PIN_13)
|
||||
#define DCMI_FSIN_PORT (GPIOC)
|
||||
|
||||
#define DCMI_D0_PIN (GPIO_PIN_9)
|
||||
#define DCMI_D1_PIN (GPIO_PIN_10)
|
||||
#define DCMI_D2_PIN (GPIO_PIN_11)
|
||||
#define DCMI_D3_PIN (GPIO_PIN_12)
|
||||
#define DCMI_D4_PIN (GPIO_PIN_14)
|
||||
#define DCMI_D5_PIN (GPIO_PIN_4)
|
||||
#define DCMI_D6_PIN (GPIO_PIN_6)
|
||||
#define DCMI_D7_PIN (GPIO_PIN_7)
|
||||
|
||||
#define DCMI_D0_PORT (GPIOH)
|
||||
#define DCMI_D1_PORT (GPIOH)
|
||||
#define DCMI_D2_PORT (GPIOH)
|
||||
#define DCMI_D3_PORT (GPIOH)
|
||||
#define DCMI_D4_PORT (GPIOH)
|
||||
#define DCMI_D5_PORT (GPIOI)
|
||||
#define DCMI_D6_PORT (GPIOI)
|
||||
#define DCMI_D7_PORT (GPIOI)
|
||||
|
||||
#define DCMI_HSYNC_PIN (GPIO_PIN_4)
|
||||
#define DCMI_VSYNC_PIN (GPIO_PIN_5)
|
||||
#define DCMI_PXCLK_PIN (GPIO_PIN_6)
|
||||
|
||||
#define DCMI_HSYNC_PORT (GPIOA)
|
||||
#define DCMI_VSYNC_PORT (GPIOI)
|
||||
#define DCMI_PXCLK_PORT (GPIOA)
|
||||
|
||||
#if defined(DCMI_RESET_PIN)
|
||||
#define DCMI_RESET_LOW() HAL_GPIO_WritePin(DCMI_RESET_PORT, DCMI_RESET_PIN, GPIO_PIN_RESET)
|
||||
#define DCMI_RESET_HIGH() HAL_GPIO_WritePin(DCMI_RESET_PORT, DCMI_RESET_PIN, GPIO_PIN_SET)
|
||||
#else
|
||||
#define DCMI_RESET_LOW()
|
||||
#define DCMI_RESET_HIGH()
|
||||
#endif
|
||||
|
||||
#if defined(DCMI_PWDN_PIN)
|
||||
#define DCMI_PWDN_LOW() HAL_GPIO_WritePin(DCMI_PWDN_PORT, DCMI_PWDN_PIN, GPIO_PIN_RESET)
|
||||
#define DCMI_PWDN_HIGH() HAL_GPIO_WritePin(DCMI_PWDN_PORT, DCMI_PWDN_PIN, GPIO_PIN_SET)
|
||||
#else
|
||||
#define DCMI_PWDN_LOW()
|
||||
#define DCMI_PWDN_HIGH()
|
||||
#endif
|
||||
|
||||
#if defined(DCMI_FSIN_PIN)
|
||||
#define DCMI_FSIN_LOW() HAL_GPIO_WritePin(DCMI_FSIN_PORT, DCMI_FSIN_PIN, GPIO_PIN_RESET)
|
||||
#define DCMI_FSIN_HIGH() HAL_GPIO_WritePin(DCMI_FSIN_PORT, DCMI_FSIN_PIN, GPIO_PIN_SET)
|
||||
#else
|
||||
#define DCMI_FSIN_LOW()
|
||||
#define DCMI_FSIN_HIGH()
|
||||
#endif
|
||||
|
||||
#define DCMI_VSYNC_IRQN EXTI9_5_IRQn
|
||||
#define DCMI_VSYNC_IRQ_LINE (7)
|
||||
|
||||
#define I2C_PORT GPIOB
|
||||
#define I2C_SIOC_PIN GPIO_PIN_10
|
||||
#define I2C_SIOD_PIN GPIO_PIN_11
|
||||
|
||||
#define I2C_SIOC_H() HAL_GPIO_WritePin(I2C_PORT, I2C_SIOC_PIN, GPIO_PIN_SET)
|
||||
#define I2C_SIOC_L() HAL_GPIO_WritePin(I2C_PORT, I2C_SIOC_PIN, GPIO_PIN_RESET)
|
||||
|
||||
#define I2C_SIOD_H() HAL_GPIO_WritePin(I2C_PORT, I2C_SIOD_PIN, GPIO_PIN_SET)
|
||||
#define I2C_SIOD_L() HAL_GPIO_WritePin(I2C_PORT, I2C_SIOD_PIN, GPIO_PIN_RESET)
|
||||
|
||||
#define I2C_SIOD_READ() HAL_GPIO_ReadPin(I2C_PORT, I2C_SIOD_PIN)
|
||||
#define I2C_SIOD_WRITE(bit) HAL_GPIO_WritePin(I2C_PORT, I2C_SIOD_PIN, bit);
|
||||
|
||||
#define I2C_SPIN_DELAY 32
|
||||
|
||||
// Enable additional GPIO banks for DRAM...
|
||||
#define OMV_ENABLE_GPIO_BANK_F
|
||||
#define OMV_ENABLE_GPIO_BANK_G
|
||||
#define OMV_ENABLE_GPIO_BANK_H
|
||||
#define OMV_ENABLE_GPIO_BANK_I
|
||||
#define OMV_ENABLE_GPIO_BANK_J
|
||||
#endif //__OMV_BOARDCONFIG_H__
|
||||
15
src/omv/boards/PORTENTA/omv_boardconfig.mk
Executable file
15
src/omv/boards/PORTENTA/omv_boardconfig.mk
Executable file
@ -0,0 +1,15 @@
|
||||
MCU=STM32H747xx
|
||||
CPU=cortex-m7
|
||||
FPU=fpv5-sp-d16
|
||||
STHAL_DIR=sthal/h7
|
||||
ARM_MATH=ARM_MATH_CM7
|
||||
HAL_INC='<stm32h7xx_hal.h>'
|
||||
CFLAGS_MCU=MCU_SERIES_H7
|
||||
STARTUP=startup_stm32h747xx
|
||||
VECT_TAB_OFFSET=0x40000
|
||||
MAIN_APP_ADDR=0x08040000
|
||||
OMV_HSE_VALUE=27000000
|
||||
FROZEN_MPY_DIR=$(TOP_DIR)/../scripts/libraries
|
||||
OMV_BOARD_EXTRA_CFLAGS = -DCORE_CM7
|
||||
MICROPY_PY_ULAB = 1
|
||||
MICROPY_PY_WINC1500 = 0
|
||||
@ -45,7 +45,7 @@ int cambus_init()
|
||||
|
||||
int cambus_scan()
|
||||
{
|
||||
for (uint8_t addr=0x08; addr<=0x77; addr++) {
|
||||
for (uint8_t addr=0x09; addr<=0x77; addr++) {
|
||||
__disable_irq();
|
||||
if (HAL_I2C_IsDeviceReady(&I2CHandle, addr << 1, 10, I2C_TIMEOUT) == HAL_OK) {
|
||||
__enable_irq();
|
||||
|
||||
@ -19,7 +19,7 @@
|
||||
#include "omv_boardconfig.h"
|
||||
#define HIMAX_BOOT_RETRY (10)
|
||||
|
||||
#if (OMV_SENSOR_HM01B0 == 1)
|
||||
#if (OMV_ENABLE_HM01B0 == 1)
|
||||
static const uint16_t default_regs[][2] = {
|
||||
{BLC_TGT, 0x08}, // BLC target :8 at 8 bit mode
|
||||
{BLC2_TGT, 0x08}, // BLI target :8 at 8 bit mode
|
||||
@ -174,10 +174,8 @@ static int set_pixformat(sensor_t *sensor, pixformat_t pixformat)
|
||||
static int set_framesize(sensor_t *sensor, framesize_t framesize)
|
||||
{
|
||||
int ret=0;
|
||||
uint16_t w = resolution[framesize][0];
|
||||
uint16_t h = resolution[framesize][1];
|
||||
|
||||
if ((w != 320) || (h != 240)) {
|
||||
if (framesize != FRAMESIZE_QVGA) {
|
||||
ret = -1;
|
||||
}
|
||||
|
||||
@ -213,12 +211,12 @@ int hm01b0_init(sensor_t *sensor)
|
||||
sensor->set_vflip = set_vflip;
|
||||
|
||||
// Set sensor flags
|
||||
SENSOR_HW_FLAGS_SET(sensor, SENSOR_HW_FLAGS_VSYNC, 1);
|
||||
SENSOR_HW_FLAGS_SET(sensor, SENSOR_HW_FLAGS_HSYNC, 1);
|
||||
SENSOR_HW_FLAGS_SET(sensor, SENSOR_HW_FLAGS_PIXCK, 0);
|
||||
SENSOR_HW_FLAGS_SET(sensor, SENSOR_HW_FLAGS_FSYNC, 1);
|
||||
SENSOR_HW_FLAGS_SET(sensor, SENSOR_HW_FLAGS_VSYNC, 0);
|
||||
SENSOR_HW_FLAGS_SET(sensor, SENSOR_HW_FLAGS_HSYNC, 0);
|
||||
SENSOR_HW_FLAGS_SET(sensor, SENSOR_HW_FLAGS_PIXCK, 1);
|
||||
SENSOR_HW_FLAGS_SET(sensor, SENSOR_HW_FLAGS_FSYNC, 0);
|
||||
SENSOR_HW_FLAGS_SET(sensor, SENSOR_HW_FLAGS_JPEGE, 0);
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif //(OMV_SENSOR_HM01B0 == 1)
|
||||
#endif //(OMV_ENABLE_HM01B0 == 1)
|
||||
|
||||
@ -415,6 +415,10 @@ int main(void)
|
||||
#endif
|
||||
bool first_soft_reset = true;
|
||||
|
||||
#if defined(MICROPY_BOARD_EARLY_INIT)
|
||||
MICROPY_BOARD_EARLY_INIT();
|
||||
#endif
|
||||
|
||||
// Uncomment to disable write buffer to get precise faults.
|
||||
// NOTE: Cache should be disabled on M7.
|
||||
//SCnSCB->ACTLR |= SCnSCB_ACTLR_DISDEFWBUF_Msk;
|
||||
@ -442,7 +446,9 @@ int main(void)
|
||||
__enable_irq();
|
||||
|
||||
soft_reset:
|
||||
#if defined(MICROPY_HW_LED4)
|
||||
led_state(LED_IR, 0);
|
||||
#endif
|
||||
led_state(LED_RED, 1);
|
||||
led_state(LED_GREEN, 1);
|
||||
led_state(LED_BLUE, 1);
|
||||
@ -471,7 +477,9 @@ soft_reset:
|
||||
pin_init0();
|
||||
extint_init0();
|
||||
timer_init0();
|
||||
#if MICROPY_HW_ENABLE_CAN
|
||||
can_init0();
|
||||
#endif
|
||||
i2c_init0();
|
||||
spi_init0();
|
||||
uart_init0();
|
||||
|
||||
@ -334,11 +334,11 @@ int sensor_init()
|
||||
case LEPTON_SLV_ADDR:
|
||||
sensor.chip_id = LEPTON_ID;
|
||||
break;
|
||||
#if (OMV_SENSOR_HM01B0 == 1)
|
||||
#if (OMV_ENABLE_HM01B0 == 1)
|
||||
case HM01B0_SLV_ADDR:
|
||||
cambus_readb2(sensor.slv_addr, HIMAX_CHIP_ID, &sensor.chip_id);
|
||||
break;
|
||||
#endif //(OMV_SENSOR_HM01B0 == 1)
|
||||
#endif //(OMV_ENABLE_HM01B0 == 1)
|
||||
default:
|
||||
return -3;
|
||||
break;
|
||||
@ -380,11 +380,11 @@ int sensor_init()
|
||||
}
|
||||
init_ret = lepton_init(&sensor);
|
||||
break;
|
||||
#if (OMV_SENSOR_HM01B0 == 1)
|
||||
#if (OMV_ENABLE_HM01B0 == 1)
|
||||
case HM01B0_ID:
|
||||
init_ret = hm01b0_init(&sensor);
|
||||
break;
|
||||
#endif //(OMV_SENSOR_HM01B0 == 1)
|
||||
#endif //(OMV_ENABLE_HM01B0 == 1)
|
||||
default:
|
||||
return -3;
|
||||
break;
|
||||
|
||||
@ -18,7 +18,7 @@
|
||||
#define OV7725_SLV_ADDR (0x42)
|
||||
#define MT9V034_SLV_ADDR (0xB8)
|
||||
#define LEPTON_SLV_ADDR (0x54)
|
||||
#define HM01B0_SLV_ADDR (0x24)
|
||||
#define HM01B0_SLV_ADDR (0x48)
|
||||
|
||||
// Chip ID Registers
|
||||
#define OV5640_CHIP_ID (0x300A)
|
||||
|
||||
@ -68,11 +68,15 @@ void HAL_MspInit(void)
|
||||
/* Enable I/D cache */
|
||||
#if defined(MCU_SERIES_F7) ||\
|
||||
defined(MCU_SERIES_H7)
|
||||
// Invalidate CPU cache
|
||||
/* Disable and Invalidate I-Cache */
|
||||
SCB_DisableICache();
|
||||
SCB_InvalidateICache();
|
||||
SCB_InvalidateDCache();
|
||||
|
||||
// Enable the CPU Cache
|
||||
/* Disable, Clean and Invalidate D-Cache */
|
||||
SCB_DisableDCache();
|
||||
SCB_CleanInvalidateDCache();
|
||||
|
||||
// Enable the CPU Caches
|
||||
SCB_EnableICache();
|
||||
SCB_EnableDCache();
|
||||
#endif
|
||||
@ -86,27 +90,26 @@ void HAL_MspInit(void)
|
||||
__GPIOC_CLK_ENABLE();
|
||||
__GPIOD_CLK_ENABLE();
|
||||
__GPIOE_CLK_ENABLE();
|
||||
#ifdef ENABLE_GPIO_BANK_F
|
||||
#ifdef OMV_ENABLE_GPIO_BANK_F
|
||||
__GPIOF_CLK_ENABLE();
|
||||
#endif
|
||||
#ifdef ENABLE_GPIO_BANK_G
|
||||
#ifdef OMV_ENABLE_GPIO_BANK_G
|
||||
__GPIOG_CLK_ENABLE();
|
||||
#endif
|
||||
#ifdef ENABLE_GPIO_BANK_H
|
||||
#ifdef OMV_ENABLE_GPIO_BANK_H
|
||||
__GPIOH_CLK_ENABLE();
|
||||
#endif
|
||||
#ifdef ENABLE_GPIO_BANK_I
|
||||
#ifdef OMV_ENABLE_GPIO_BANK_I
|
||||
__GPIOI_CLK_ENABLE();
|
||||
#endif
|
||||
|
||||
#if defined(STM32F769xx)
|
||||
__GPIOF_CLK_ENABLE();
|
||||
__GPIOG_CLK_ENABLE();
|
||||
__GPIOH_CLK_ENABLE();
|
||||
__GPIOI_CLK_ENABLE();
|
||||
#ifdef OMV_ENABLE_GPIO_BANK_J
|
||||
__GPIOJ_CLK_ENABLE();
|
||||
#endif
|
||||
#ifdef OMV_ENABLE_GPIO_BANK_K
|
||||
__GPIOK_CLK_ENABLE();
|
||||
#endif
|
||||
|
||||
#if defined (OMV_HARDWARE_JPEG)
|
||||
/* Enable JPEG clock */
|
||||
__HAL_RCC_JPEG_CLK_ENABLE();
|
||||
#endif
|
||||
@ -131,11 +134,15 @@ void HAL_MspInit(void)
|
||||
GPIO_InitStructure.Speed = GPIO_SPEED_LOW;
|
||||
GPIO_InitStructure.Mode = GPIO_MODE_OUTPUT_PP;
|
||||
|
||||
#if defined(DCMI_RESET_PIN)
|
||||
GPIO_InitStructure.Pin = DCMI_RESET_PIN;
|
||||
HAL_GPIO_Init(DCMI_RESET_PORT, &GPIO_InitStructure);
|
||||
#endif
|
||||
|
||||
#if defined(DCMI_PWDN_PIN)
|
||||
GPIO_InitStructure.Pin = DCMI_PWDN_PIN;
|
||||
HAL_GPIO_Init(DCMI_PWDN_PORT, &GPIO_InitStructure);
|
||||
#endif
|
||||
|
||||
#if defined(DCMI_FSYNC_PIN)
|
||||
GPIO_InitStructure.Pin = DCMI_FSYNC_PIN;
|
||||
|
||||
Loading…
Reference in New Issue
Block a user