mirror of
https://github.com/openmv/openmv.git
synced 2025-11-04 14:49:50 +08:00
Merge pull request #2494 from openmv/stm32_updates
Some checks are pending
🔎 Check Code Formatting / formatting-check (push) Waiting to run
🔥 Firmware Build / build-firmware (ARDUINO_GIGA) (push) Waiting to run
🔥 Firmware Build / build-firmware (ARDUINO_NANO_33_BLE_SENSE) (push) Waiting to run
🔥 Firmware Build / build-firmware (ARDUINO_NANO_RP2040_CONNECT) (push) Waiting to run
🔥 Firmware Build / build-firmware (ARDUINO_NICLA_VISION) (push) Waiting to run
🔥 Firmware Build / build-firmware (ARDUINO_PORTENTA_H7) (push) Waiting to run
🔥 Firmware Build / build-firmware (OPENMV2) (push) Waiting to run
🔥 Firmware Build / build-firmware (OPENMV3) (push) Waiting to run
🔥 Firmware Build / build-firmware (OPENMV4) (push) Waiting to run
🔥 Firmware Build / build-firmware (OPENMV4P) (push) Waiting to run
🔥 Firmware Build / build-firmware (OPENMVPT) (push) Waiting to run
🔥 Firmware Build / build-firmware (OPENMV_RT1060) (push) Waiting to run
🔥 Firmware Build / code-size-report (push) Blocked by required conditions
🔥 Firmware Build / stable-release (push) Blocked by required conditions
🔥 Firmware Build / development-release (push) Blocked by required conditions
Some checks are pending
🔎 Check Code Formatting / formatting-check (push) Waiting to run
🔥 Firmware Build / build-firmware (ARDUINO_GIGA) (push) Waiting to run
🔥 Firmware Build / build-firmware (ARDUINO_NANO_33_BLE_SENSE) (push) Waiting to run
🔥 Firmware Build / build-firmware (ARDUINO_NANO_RP2040_CONNECT) (push) Waiting to run
🔥 Firmware Build / build-firmware (ARDUINO_NICLA_VISION) (push) Waiting to run
🔥 Firmware Build / build-firmware (ARDUINO_PORTENTA_H7) (push) Waiting to run
🔥 Firmware Build / build-firmware (OPENMV2) (push) Waiting to run
🔥 Firmware Build / build-firmware (OPENMV3) (push) Waiting to run
🔥 Firmware Build / build-firmware (OPENMV4) (push) Waiting to run
🔥 Firmware Build / build-firmware (OPENMV4P) (push) Waiting to run
🔥 Firmware Build / build-firmware (OPENMVPT) (push) Waiting to run
🔥 Firmware Build / build-firmware (OPENMV_RT1060) (push) Waiting to run
🔥 Firmware Build / code-size-report (push) Blocked by required conditions
🔥 Firmware Build / stable-release (push) Blocked by required conditions
🔥 Firmware Build / development-release (push) Blocked by required conditions
ports/stm32: Misc updates.
This commit is contained in:
commit
1855cd2f50
@ -73,8 +73,8 @@ CFLAGS += -D$(MCU) \
|
|||||||
-D__VFP_FP__ \
|
-D__VFP_FP__ \
|
||||||
-DUSE_DEVICE_MODE \
|
-DUSE_DEVICE_MODE \
|
||||||
-DHSE_VALUE=$(OMV_HSE_VALUE)\
|
-DHSE_VALUE=$(OMV_HSE_VALUE)\
|
||||||
-DOMV_VTOR_BASE=$(OMV_BOOT_BASE) \
|
-DOMV_VTOR_BASE=$(OMV_BOOT_ADDR) \
|
||||||
-DOMV_BOOT_JUMP=$(OMV_FIRM_BASE) \
|
-DOMV_BOOT_JUMP=$(OMV_FIRM_ADDR) \
|
||||||
-DCMSIS_MCU_H='<$(MCU_LOWER).h>' \
|
-DCMSIS_MCU_H='<$(MCU_LOWER).h>' \
|
||||||
-DSTM32_HAL_H='<stm32$(MCU_SERIES)xx_hal.h>' \
|
-DSTM32_HAL_H='<stm32$(MCU_SERIES)xx_hal.h>' \
|
||||||
-DUSE_FULL_LL_DRIVER \
|
-DUSE_FULL_LL_DRIVER \
|
||||||
|
|||||||
@ -127,20 +127,20 @@
|
|||||||
// Linker script constants (see the linker script template stm32.ld.S).
|
// Linker script constants (see the linker script template stm32.ld.S).
|
||||||
// Note: fb_alloc is a stack-based, dynamically allocated memory on FB.
|
// Note: fb_alloc is a stack-based, dynamically allocated memory on FB.
|
||||||
// The maximum available fb_alloc memory = FB_ALLOC_SIZE + FB_SIZE - (w*h*bpp).
|
// The maximum available fb_alloc memory = FB_ALLOC_SIZE + FB_SIZE - (w*h*bpp).
|
||||||
#define OMV_MAIN_MEMORY AXI_SRAM // Data, BSS memory.
|
#define OMV_MAIN_MEMORY SRAM0 // Data, BSS memory.
|
||||||
#define OMV_STACK_MEMORY DTCM // stack memory
|
#define OMV_STACK_MEMORY DTCM // stack memory
|
||||||
#define OMV_STACK_SIZE (64K)
|
#define OMV_STACK_SIZE (64K)
|
||||||
#define OMV_FB_MEMORY DRAM // Framebuffer, fb_alloc
|
#define OMV_FB_MEMORY DRAM // Framebuffer, fb_alloc
|
||||||
#define OMV_FB_SIZE (3M) // FB memory: header + VGA/GS image
|
#define OMV_FB_SIZE (3M) // FB memory: header + VGA/GS image
|
||||||
#define OMV_FB_ALLOC_SIZE (1M) // minimum fb alloc size
|
#define OMV_FB_ALLOC_SIZE (1M) // minimum fb alloc size
|
||||||
#define OMV_FB_OVERLAY_MEMORY AXI_SRAM // Fast fb_alloc memory.
|
#define OMV_FB_OVERLAY_MEMORY SRAM0 // Fast fb_alloc memory.
|
||||||
#define OMV_FB_OVERLAY_SIZE (448K) // Fast fb_alloc memory size.
|
#define OMV_FB_OVERLAY_SIZE (448K) // Fast fb_alloc memory size.
|
||||||
#define OMV_JPEG_MEMORY DRAM // JPEG buffer memory buffer.
|
#define OMV_JPEG_MEMORY DRAM // JPEG buffer memory buffer.
|
||||||
#define OMV_JPEG_SIZE (1M) // IDE JPEG buffer (header + data).
|
#define OMV_JPEG_SIZE (1M) // IDE JPEG buffer (header + data).
|
||||||
#define OMV_VOSPI_MEMORY DTCM // VoSPI buffer memory.
|
#define OMV_VOSPI_MEMORY DTCM // VoSPI buffer memory.
|
||||||
#define OMV_VOSPI_SIZE (38K)
|
#define OMV_VOSPI_SIZE (38K)
|
||||||
#define OMV_DMA_MEMORY SRAM3 // Misc DMA buffers memory.
|
#define OMV_DMA_MEMORY SRAM3 // Misc DMA buffers memory.
|
||||||
#define OMV_DMA_MEMORY_D1 AXI_SRAM // Domain 1 DMA buffers.
|
#define OMV_DMA_MEMORY_D1 SRAM0 // Domain 1 DMA buffers.
|
||||||
#define OMV_DMA_MEMORY_D2 SRAM3 // Domain 2 DMA buffers.
|
#define OMV_DMA_MEMORY_D2 SRAM3 // Domain 2 DMA buffers.
|
||||||
#define OMV_OPENAMP_MEMORY SRAM4
|
#define OMV_OPENAMP_MEMORY SRAM4
|
||||||
#define OMV_OPENAMP_SIZE (64K)
|
#define OMV_OPENAMP_SIZE (64K)
|
||||||
@ -160,14 +160,14 @@
|
|||||||
#define OMV_FLASH_LENGTH 2048K
|
#define OMV_FLASH_LENGTH 2048K
|
||||||
#define OMV_DTCM_ORIGIN 0x20000000 // Note accessible by CPU and MDMA only.
|
#define OMV_DTCM_ORIGIN 0x20000000 // Note accessible by CPU and MDMA only.
|
||||||
#define OMV_DTCM_LENGTH 128K
|
#define OMV_DTCM_LENGTH 128K
|
||||||
|
#define OMV_SRAM0_ORIGIN 0x24000000
|
||||||
|
#define OMV_SRAM0_LENGTH 512K
|
||||||
#define OMV_SRAM1_ORIGIN 0x30000000
|
#define OMV_SRAM1_ORIGIN 0x30000000
|
||||||
#define OMV_SRAM1_LENGTH 256K
|
#define OMV_SRAM1_LENGTH 256K
|
||||||
#define OMV_SRAM3_ORIGIN 0x30040000
|
#define OMV_SRAM3_ORIGIN 0x30040000
|
||||||
#define OMV_SRAM3_LENGTH 32K
|
#define OMV_SRAM3_LENGTH 32K
|
||||||
#define OMV_SRAM4_ORIGIN 0x38000000
|
#define OMV_SRAM4_ORIGIN 0x38000000
|
||||||
#define OMV_SRAM4_LENGTH 64K
|
#define OMV_SRAM4_LENGTH 64K
|
||||||
#define OMV_AXI_SRAM_ORIGIN 0x24000000
|
|
||||||
#define OMV_AXI_SRAM_LENGTH 512K
|
|
||||||
#define OMV_DRAM_ORIGIN 0xC0000000
|
#define OMV_DRAM_ORIGIN 0xC0000000
|
||||||
#define OMV_DRAM_LENGTH 8M
|
#define OMV_DRAM_LENGTH 8M
|
||||||
|
|
||||||
|
|||||||
@ -2,7 +2,7 @@ MCU=STM32H747xx
|
|||||||
CPU=cortex-m7
|
CPU=cortex-m7
|
||||||
FPU=fpv5-sp-d16
|
FPU=fpv5-sp-d16
|
||||||
PORT=stm32
|
PORT=stm32
|
||||||
OMV_FIRM_BASE=0x08040000
|
OMV_FIRM_ADDR=0x08040000
|
||||||
OMV_HSE_VALUE=16000000
|
OMV_HSE_VALUE=16000000
|
||||||
DFU_DEVICE=0x2341:0x035b
|
DFU_DEVICE=0x2341:0x035b
|
||||||
OMV_BOARD_CFLAGS = -DCORE_CM7 \
|
OMV_BOARD_CFLAGS = -DCORE_CM7 \
|
||||||
|
|||||||
@ -4,7 +4,7 @@ FPU=fpv4-sp-d16
|
|||||||
PORT=nrf
|
PORT=nrf
|
||||||
SD=s140
|
SD=s140
|
||||||
NRF_SOFTDEV=s140_nrf52_6.1.1
|
NRF_SOFTDEV=s140_nrf52_6.1.1
|
||||||
OMV_FIRM_BASE=0x00026000
|
OMV_FIRM_ADDR=0x00026000
|
||||||
OMV_HSE_VALUE=12000000
|
OMV_HSE_VALUE=12000000
|
||||||
OMV_BOARD_CFLAGS = -DNRF52_SERIES \
|
OMV_BOARD_CFLAGS = -DNRF52_SERIES \
|
||||||
-DNRF52840_XXAA \
|
-DNRF52840_XXAA \
|
||||||
|
|||||||
@ -121,13 +121,13 @@
|
|||||||
#define OMV_MAIN_MEMORY DTCM // Data/BSS memory.
|
#define OMV_MAIN_MEMORY DTCM // Data/BSS memory.
|
||||||
#define OMV_STACK_MEMORY DTCM // stack memory
|
#define OMV_STACK_MEMORY DTCM // stack memory
|
||||||
#define OMV_STACK_SIZE (32K)
|
#define OMV_STACK_SIZE (32K)
|
||||||
#define OMV_FB_MEMORY AXI_SRAM // Framebuffer, fb_alloc
|
#define OMV_FB_MEMORY SRAM0 // Framebuffer, fb_alloc
|
||||||
#define OMV_FB_SIZE (400K) // FB memory: header + VGA/GS image
|
#define OMV_FB_SIZE (400K) // FB memory: header + VGA/GS image
|
||||||
#define OMV_FB_ALLOC_SIZE (76K) // minimum fb alloc size
|
#define OMV_FB_ALLOC_SIZE (76K) // minimum fb alloc size
|
||||||
#define OMV_JPEG_MEMORY AXI_SRAM // JPEG buffer memory buffer.
|
#define OMV_JPEG_MEMORY SRAM0 // JPEG buffer memory buffer.
|
||||||
#define OMV_JPEG_SIZE (32K) // IDE JPEG buffer (header + data).
|
#define OMV_JPEG_SIZE (32K) // IDE JPEG buffer (header + data).
|
||||||
#define OMV_DMA_MEMORY SRAM2 // DMA buffers memory.
|
#define OMV_DMA_MEMORY SRAM2 // DMA buffers memory.
|
||||||
#define OMV_DMA_MEMORY_D1 AXI_SRAM // Domain 1 DMA buffers.
|
#define OMV_DMA_MEMORY_D1 SRAM0 // Domain 1 DMA buffers.
|
||||||
#define OMV_DMA_MEMORY_D2 SRAM2 // Domain 2 DMA buffers.
|
#define OMV_DMA_MEMORY_D2 SRAM2 // Domain 2 DMA buffers.
|
||||||
#define OMV_CM4_BOOT_MEMORY SRAM4 // Use to boot CM4 for low-power mode.
|
#define OMV_CM4_BOOT_MEMORY SRAM4 // Use to boot CM4 for low-power mode.
|
||||||
#define OMV_CM4_BOOT_SIZE 1K
|
#define OMV_CM4_BOOT_SIZE 1K
|
||||||
@ -148,14 +148,14 @@
|
|||||||
#define OMV_DTCM_LENGTH 128K
|
#define OMV_DTCM_LENGTH 128K
|
||||||
#define OMV_ITCM_ORIGIN 0x00000000
|
#define OMV_ITCM_ORIGIN 0x00000000
|
||||||
#define OMV_ITCM_LENGTH 64K
|
#define OMV_ITCM_LENGTH 64K
|
||||||
|
#define OMV_SRAM0_ORIGIN 0x24000000
|
||||||
|
#define OMV_SRAM0_LENGTH 512K
|
||||||
#define OMV_SRAM1_ORIGIN 0x30000000
|
#define OMV_SRAM1_ORIGIN 0x30000000
|
||||||
#define OMV_SRAM1_LENGTH 276K
|
#define OMV_SRAM1_LENGTH 276K
|
||||||
#define OMV_SRAM2_ORIGIN 0x30045000
|
#define OMV_SRAM2_ORIGIN 0x30045000
|
||||||
#define OMV_SRAM2_LENGTH 12K
|
#define OMV_SRAM2_LENGTH 12K
|
||||||
#define OMV_SRAM4_ORIGIN 0x38000000
|
#define OMV_SRAM4_ORIGIN 0x38000000
|
||||||
#define OMV_SRAM4_LENGTH 64K
|
#define OMV_SRAM4_LENGTH 64K
|
||||||
#define OMV_AXI_SRAM_ORIGIN 0x24000000
|
|
||||||
#define OMV_AXI_SRAM_LENGTH 512K
|
|
||||||
|
|
||||||
// Flash configuration.
|
// Flash configuration.
|
||||||
#define OMV_FLASH_FFS_ORIGIN 0x08020000
|
#define OMV_FLASH_FFS_ORIGIN 0x08020000
|
||||||
|
|||||||
@ -2,7 +2,7 @@ MCU=STM32H747xx
|
|||||||
CPU=cortex-m7
|
CPU=cortex-m7
|
||||||
FPU=fpv5-sp-d16
|
FPU=fpv5-sp-d16
|
||||||
PORT=stm32
|
PORT=stm32
|
||||||
OMV_FIRM_BASE=0x08040000
|
OMV_FIRM_ADDR=0x08040000
|
||||||
OMV_HSE_VALUE=25000000
|
OMV_HSE_VALUE=25000000
|
||||||
DFU_DEVICE=0x2341:0x035b
|
DFU_DEVICE=0x2341:0x035b
|
||||||
USERMOD_OPT = -Os
|
USERMOD_OPT = -Os
|
||||||
|
|||||||
@ -135,14 +135,14 @@
|
|||||||
#define OMV_FB_MEMORY DRAM // Framebuffer, fb_alloc
|
#define OMV_FB_MEMORY DRAM // Framebuffer, fb_alloc
|
||||||
#define OMV_FB_SIZE (3M) // FB memory: header + VGA/GS image
|
#define OMV_FB_SIZE (3M) // FB memory: header + VGA/GS image
|
||||||
#define OMV_FB_ALLOC_SIZE (1M) // minimum fb alloc size
|
#define OMV_FB_ALLOC_SIZE (1M) // minimum fb alloc size
|
||||||
#define OMV_FB_OVERLAY_MEMORY AXI_SRAM // Fast fb_alloc memory.
|
#define OMV_FB_OVERLAY_MEMORY SRAM0 // Fast fb_alloc memory.
|
||||||
#define OMV_FB_OVERLAY_SIZE (480K) // Fast fb_alloc memory size.
|
#define OMV_FB_OVERLAY_SIZE (480K) // Fast fb_alloc memory size.
|
||||||
#define OMV_JPEG_MEMORY DRAM // JPEG buffer memory buffer.
|
#define OMV_JPEG_MEMORY DRAM // JPEG buffer memory buffer.
|
||||||
#define OMV_JPEG_SIZE (1M) // IDE JPEG buffer (header + data).
|
#define OMV_JPEG_SIZE (1M) // IDE JPEG buffer (header + data).
|
||||||
#define OMV_VOSPI_MEMORY SRAM4 // VoSPI buffer memory.
|
#define OMV_VOSPI_MEMORY SRAM4 // VoSPI buffer memory.
|
||||||
#define OMV_VOSPI_SIZE (38K)
|
#define OMV_VOSPI_SIZE (38K)
|
||||||
#define OMV_DMA_MEMORY SRAM3 // Misc DMA buffers memory.
|
#define OMV_DMA_MEMORY SRAM3 // Misc DMA buffers memory.
|
||||||
#define OMV_DMA_MEMORY_D1 AXI_SRAM // Domain 1 DMA buffers.
|
#define OMV_DMA_MEMORY_D1 SRAM0 // Domain 1 DMA buffers.
|
||||||
#define OMV_DMA_MEMORY_D2 SRAM3 // Domain 2 DMA buffers.
|
#define OMV_DMA_MEMORY_D2 SRAM3 // Domain 2 DMA buffers.
|
||||||
#define OMV_DMA_MEMORY_D3 SRAM4 // Domain 3 DMA buffers.
|
#define OMV_DMA_MEMORY_D3 SRAM4 // Domain 3 DMA buffers.
|
||||||
#define OMV_OPENAMP_MEMORY SRAM1
|
#define OMV_OPENAMP_MEMORY SRAM1
|
||||||
@ -163,14 +163,14 @@
|
|||||||
#define OMV_FLASH_LENGTH 2048K
|
#define OMV_FLASH_LENGTH 2048K
|
||||||
#define OMV_DTCM_ORIGIN 0x20000000 // Note accessible by CPU and MDMA only.
|
#define OMV_DTCM_ORIGIN 0x20000000 // Note accessible by CPU and MDMA only.
|
||||||
#define OMV_DTCM_LENGTH 128K
|
#define OMV_DTCM_LENGTH 128K
|
||||||
|
#define OMV_SRAM0_ORIGIN 0x24000000
|
||||||
|
#define OMV_SRAM0_LENGTH 512K
|
||||||
#define OMV_SRAM1_ORIGIN 0x30000000
|
#define OMV_SRAM1_ORIGIN 0x30000000
|
||||||
#define OMV_SRAM1_LENGTH 256K // SRAM1 + SRAM2
|
#define OMV_SRAM1_LENGTH 256K // SRAM1 + SRAM2
|
||||||
#define OMV_SRAM3_ORIGIN 0x30040000 // Second half of SRAM3 reserved for M4.
|
#define OMV_SRAM3_ORIGIN 0x30040000 // Second half of SRAM3 reserved for M4.
|
||||||
#define OMV_SRAM3_LENGTH 16K
|
#define OMV_SRAM3_LENGTH 16K
|
||||||
#define OMV_SRAM4_ORIGIN 0x38000000
|
#define OMV_SRAM4_ORIGIN 0x38000000
|
||||||
#define OMV_SRAM4_LENGTH 64K
|
#define OMV_SRAM4_LENGTH 64K
|
||||||
#define OMV_AXI_SRAM_ORIGIN 0x24000000
|
|
||||||
#define OMV_AXI_SRAM_LENGTH 512K
|
|
||||||
#define OMV_DRAM_ORIGIN 0xC0000000
|
#define OMV_DRAM_ORIGIN 0xC0000000
|
||||||
#define OMV_DRAM_LENGTH 8M
|
#define OMV_DRAM_LENGTH 8M
|
||||||
|
|
||||||
|
|||||||
@ -2,7 +2,7 @@ MCU=STM32H747xx
|
|||||||
CPU=cortex-m7
|
CPU=cortex-m7
|
||||||
FPU=fpv5-sp-d16
|
FPU=fpv5-sp-d16
|
||||||
PORT=stm32
|
PORT=stm32
|
||||||
OMV_FIRM_BASE=0x08040000
|
OMV_FIRM_ADDR=0x08040000
|
||||||
OMV_HSE_VALUE=25000000
|
OMV_HSE_VALUE=25000000
|
||||||
DFU_DEVICE=0x2341:0x035b
|
DFU_DEVICE=0x2341:0x035b
|
||||||
OMV_BOARD_CFLAGS = -DCORE_CM7 \
|
OMV_BOARD_CFLAGS = -DCORE_CM7 \
|
||||||
|
|||||||
@ -2,8 +2,9 @@ MCU=STM32F407xx
|
|||||||
CPU=cortex-m4
|
CPU=cortex-m4
|
||||||
FPU=fpv4-sp-d16
|
FPU=fpv4-sp-d16
|
||||||
PORT=stm32
|
PORT=stm32
|
||||||
OMV_BOOT_BASE=0x08000000
|
OMV_FIRM_BASE=0x08000000
|
||||||
OMV_FIRM_BASE=0x08010000
|
OMV_FIRM_ADDR=0x08010000
|
||||||
|
OMV_BOOT_ADDR=0x08000000
|
||||||
OMV_HSE_VALUE=12000000
|
OMV_HSE_VALUE=12000000
|
||||||
DFU_DEVICE=0x0483:0xdf11
|
DFU_DEVICE=0x0483:0xdf11
|
||||||
OMV_ENABLE_BL=1
|
OMV_ENABLE_BL=1
|
||||||
|
|||||||
@ -2,8 +2,9 @@ MCU=STM32F427xx
|
|||||||
CPU=cortex-m4
|
CPU=cortex-m4
|
||||||
FPU=fpv4-sp-d16
|
FPU=fpv4-sp-d16
|
||||||
PORT=stm32
|
PORT=stm32
|
||||||
OMV_BOOT_BASE=0x08000000
|
OMV_FIRM_BASE=0x08000000
|
||||||
OMV_FIRM_BASE=0x08010000
|
OMV_FIRM_ADDR=0x08010000
|
||||||
|
OMV_BOOT_ADDR=0x08000000
|
||||||
OMV_HSE_VALUE=12000000
|
OMV_HSE_VALUE=12000000
|
||||||
DFU_DEVICE=0x0483:0xdf11
|
DFU_DEVICE=0x0483:0xdf11
|
||||||
OMV_ENABLE_BL=1
|
OMV_ENABLE_BL=1
|
||||||
|
|||||||
@ -2,8 +2,9 @@ MCU=STM32F765xx
|
|||||||
CPU=cortex-m7
|
CPU=cortex-m7
|
||||||
FPU=fpv5-sp-d16
|
FPU=fpv5-sp-d16
|
||||||
PORT=stm32
|
PORT=stm32
|
||||||
OMV_BOOT_BASE=0x08000000
|
OMV_FIRM_BASE=0x08000000
|
||||||
OMV_FIRM_BASE=0x08020000
|
OMV_FIRM_ADDR=0x08020000
|
||||||
|
OMV_BOOT_ADDR=0x08000000
|
||||||
OMV_HSE_VALUE=12000000
|
OMV_HSE_VALUE=12000000
|
||||||
DFU_DEVICE=0x0483:0xdf11
|
DFU_DEVICE=0x0483:0xdf11
|
||||||
OMV_ENABLE_BL=1
|
OMV_ENABLE_BL=1
|
||||||
|
|||||||
@ -136,10 +136,10 @@
|
|||||||
#define OMV_FFS_MEMORY DTCM // Flash filesystem cache memory
|
#define OMV_FFS_MEMORY DTCM // Flash filesystem cache memory
|
||||||
#define OMV_STACK_MEMORY ITCM // stack memory
|
#define OMV_STACK_MEMORY ITCM // stack memory
|
||||||
#define OMV_STACK_SIZE (64K)
|
#define OMV_STACK_SIZE (64K)
|
||||||
#define OMV_FB_MEMORY AXI_SRAM // Framebuffer, fb_alloc
|
#define OMV_FB_MEMORY SRAM0 // Framebuffer, fb_alloc
|
||||||
#define OMV_FB_SIZE (400K) // FB memory: header + VGA/GS image
|
#define OMV_FB_SIZE (400K) // FB memory: header + VGA/GS image
|
||||||
#define OMV_FB_ALLOC_SIZE (80K) // minimum fb alloc size
|
#define OMV_FB_ALLOC_SIZE (80K) // minimum fb alloc size
|
||||||
#define OMV_JPEG_MEMORY AXI_SRAM // JPEG buffer memory.
|
#define OMV_JPEG_MEMORY SRAM0 // JPEG buffer memory.
|
||||||
#define OMV_JPEG_SIZE (32K) // IDE JPEG buffer (header + data).
|
#define OMV_JPEG_SIZE (32K) // IDE JPEG buffer (header + data).
|
||||||
#define OMV_VOSPI_MEMORY SRAM4 // VoSPI buffer memory.
|
#define OMV_VOSPI_MEMORY SRAM4 // VoSPI buffer memory.
|
||||||
#define OMV_VOSPI_SIZE (38K)
|
#define OMV_VOSPI_SIZE (38K)
|
||||||
@ -159,14 +159,14 @@
|
|||||||
#define OMV_DTCM_LENGTH 128K
|
#define OMV_DTCM_LENGTH 128K
|
||||||
#define OMV_ITCM_ORIGIN 0x00000000
|
#define OMV_ITCM_ORIGIN 0x00000000
|
||||||
#define OMV_ITCM_LENGTH 64K
|
#define OMV_ITCM_LENGTH 64K
|
||||||
|
#define OMV_SRAM0_ORIGIN 0x24000000
|
||||||
|
#define OMV_SRAM0_LENGTH 512K
|
||||||
#define OMV_SRAM1_ORIGIN 0x30000000
|
#define OMV_SRAM1_ORIGIN 0x30000000
|
||||||
#define OMV_SRAM1_LENGTH 280K
|
#define OMV_SRAM1_LENGTH 280K
|
||||||
#define OMV_SRAM2_ORIGIN 0x30046000
|
#define OMV_SRAM2_ORIGIN 0x30046000
|
||||||
#define OMV_SRAM2_LENGTH 8K
|
#define OMV_SRAM2_LENGTH 8K
|
||||||
#define OMV_SRAM4_ORIGIN 0x38000000
|
#define OMV_SRAM4_ORIGIN 0x38000000
|
||||||
#define OMV_SRAM4_LENGTH 64K
|
#define OMV_SRAM4_LENGTH 64K
|
||||||
#define OMV_AXI_SRAM_ORIGIN 0x24000000
|
|
||||||
#define OMV_AXI_SRAM_LENGTH 512K
|
|
||||||
|
|
||||||
// Flash configuration.
|
// Flash configuration.
|
||||||
#define OMV_FLASH_BOOT_ORIGIN 0x08000000
|
#define OMV_FLASH_BOOT_ORIGIN 0x08000000
|
||||||
|
|||||||
@ -2,8 +2,9 @@ MCU=STM32H743xx
|
|||||||
CPU=cortex-m7
|
CPU=cortex-m7
|
||||||
FPU=fpv5-sp-d16
|
FPU=fpv5-sp-d16
|
||||||
PORT=stm32
|
PORT=stm32
|
||||||
OMV_BOOT_BASE=0x08000000
|
OMV_FIRM_BASE=0x08000000
|
||||||
OMV_FIRM_BASE=0x08040000
|
OMV_FIRM_ADDR=0x08040000
|
||||||
|
OMV_BOOT_ADDR=0x08000000
|
||||||
OMV_HSE_VALUE=12000000
|
OMV_HSE_VALUE=12000000
|
||||||
DFU_DEVICE=0x0483:0xdf11
|
DFU_DEVICE=0x0483:0xdf11
|
||||||
OMV_ENABLE_BL=1
|
OMV_ENABLE_BL=1
|
||||||
|
|||||||
@ -125,14 +125,14 @@
|
|||||||
#define OMV_FB_MEMORY DRAM // Framebuffer, fb_alloc
|
#define OMV_FB_MEMORY DRAM // Framebuffer, fb_alloc
|
||||||
#define OMV_FB_SIZE (16M) // FB memory: header + VGA/GS image
|
#define OMV_FB_SIZE (16M) // FB memory: header + VGA/GS image
|
||||||
#define OMV_FB_ALLOC_SIZE (11M) // minimum fb alloc size
|
#define OMV_FB_ALLOC_SIZE (11M) // minimum fb alloc size
|
||||||
#define OMV_FB_OVERLAY_MEMORY AXI_SRAM // Fast fb_alloc memory.
|
#define OMV_FB_OVERLAY_MEMORY SRAM0 // Fast fb_alloc memory.
|
||||||
#define OMV_FB_OVERLAY_SIZE (496K) // Fast fb_alloc memory size.
|
#define OMV_FB_OVERLAY_SIZE (496K) // Fast fb_alloc memory size.
|
||||||
#define OMV_JPEG_MEMORY DRAM // JPEG buffer memory buffer.
|
#define OMV_JPEG_MEMORY DRAM // JPEG buffer memory buffer.
|
||||||
#define OMV_JPEG_SIZE (1M) // IDE JPEG buffer (header + data).
|
#define OMV_JPEG_SIZE (1M) // IDE JPEG buffer (header + data).
|
||||||
#define OMV_VOSPI_MEMORY SRAM4 // VoSPI buffer memory.
|
#define OMV_VOSPI_MEMORY SRAM4 // VoSPI buffer memory.
|
||||||
#define OMV_VOSPI_SIZE (38K)
|
#define OMV_VOSPI_SIZE (38K)
|
||||||
#define OMV_DMA_MEMORY SRAM3 // Misc DMA buffers memory.
|
#define OMV_DMA_MEMORY SRAM3 // Misc DMA buffers memory.
|
||||||
#define OMV_DMA_MEMORY_D1 AXI_SRAM // Domain 1 DMA buffers.
|
#define OMV_DMA_MEMORY_D1 SRAM0 // Domain 1 DMA buffers.
|
||||||
#define OMV_DMA_MEMORY_D2 SRAM3 // Domain 2 DMA buffers.
|
#define OMV_DMA_MEMORY_D2 SRAM3 // Domain 2 DMA buffers.
|
||||||
#define OMV_DMA_MEMORY_D3 SRAM4 // Domain 3 DMA buffers.
|
#define OMV_DMA_MEMORY_D3 SRAM4 // Domain 3 DMA buffers.
|
||||||
#define OMV_GC_BLOCK0_MEMORY SRAM1 // Main GC block
|
#define OMV_GC_BLOCK0_MEMORY SRAM1 // Main GC block
|
||||||
@ -151,14 +151,14 @@
|
|||||||
#define OMV_DTCM_LENGTH 128K
|
#define OMV_DTCM_LENGTH 128K
|
||||||
#define OMV_ITCM_ORIGIN 0x00000000
|
#define OMV_ITCM_ORIGIN 0x00000000
|
||||||
#define OMV_ITCM_LENGTH 64K
|
#define OMV_ITCM_LENGTH 64K
|
||||||
|
#define OMV_SRAM0_ORIGIN 0x24000000
|
||||||
|
#define OMV_SRAM0_LENGTH 512K
|
||||||
#define OMV_SRAM1_ORIGIN 0x30000000
|
#define OMV_SRAM1_ORIGIN 0x30000000
|
||||||
#define OMV_SRAM1_LENGTH 256K // SRAM1 + SRAM2 + 1/2 SRAM3
|
#define OMV_SRAM1_LENGTH 256K // SRAM1 + SRAM2 + 1/2 SRAM3
|
||||||
#define OMV_SRAM3_ORIGIN 0x30040000
|
#define OMV_SRAM3_ORIGIN 0x30040000
|
||||||
#define OMV_SRAM3_LENGTH 32K
|
#define OMV_SRAM3_LENGTH 32K
|
||||||
#define OMV_SRAM4_ORIGIN 0x38000000
|
#define OMV_SRAM4_ORIGIN 0x38000000
|
||||||
#define OMV_SRAM4_LENGTH 64K
|
#define OMV_SRAM4_LENGTH 64K
|
||||||
#define OMV_AXI_SRAM_ORIGIN 0x24000000
|
|
||||||
#define OMV_AXI_SRAM_LENGTH 512K
|
|
||||||
#define OMV_DRAM_ORIGIN 0xC0000000
|
#define OMV_DRAM_ORIGIN 0xC0000000
|
||||||
#define OMV_DRAM_LENGTH 32M
|
#define OMV_DRAM_LENGTH 32M
|
||||||
|
|
||||||
|
|||||||
@ -2,8 +2,9 @@ MCU=STM32H743xx
|
|||||||
CPU=cortex-m7
|
CPU=cortex-m7
|
||||||
FPU=fpv5-sp-d16
|
FPU=fpv5-sp-d16
|
||||||
PORT=stm32
|
PORT=stm32
|
||||||
OMV_BOOT_BASE=0x08000000
|
OMV_FIRM_BASE=0x08000000
|
||||||
OMV_FIRM_BASE=0x08040000
|
OMV_FIRM_ADDR=0x08040000
|
||||||
|
OMV_BOOT_ADDR=0x08000000
|
||||||
OMV_HSE_VALUE=12000000
|
OMV_HSE_VALUE=12000000
|
||||||
DFU_DEVICE=0x0483:0xdf11
|
DFU_DEVICE=0x0483:0xdf11
|
||||||
OMV_ENABLE_BL=1
|
OMV_ENABLE_BL=1
|
||||||
|
|||||||
@ -116,14 +116,14 @@
|
|||||||
#define OMV_FB_MEMORY DRAM // Framebuffer, fb_alloc
|
#define OMV_FB_MEMORY DRAM // Framebuffer, fb_alloc
|
||||||
#define OMV_FB_SIZE (32M) // FB memory: header + VGA/GS image
|
#define OMV_FB_SIZE (32M) // FB memory: header + VGA/GS image
|
||||||
#define OMV_FB_ALLOC_SIZE (23M) // minimum fb alloc size
|
#define OMV_FB_ALLOC_SIZE (23M) // minimum fb alloc size
|
||||||
#define OMV_FB_OVERLAY_MEMORY AXI_SRAM // Fast fb_alloc memory.
|
#define OMV_FB_OVERLAY_MEMORY SRAM0 // Fast fb_alloc memory.
|
||||||
#define OMV_FB_OVERLAY_SIZE (496K) // Fast fb_alloc memory size.
|
#define OMV_FB_OVERLAY_SIZE (496K) // Fast fb_alloc memory size.
|
||||||
#define OMV_JPEG_MEMORY DRAM // JPEG buffer memory buffer.
|
#define OMV_JPEG_MEMORY DRAM // JPEG buffer memory buffer.
|
||||||
#define OMV_JPEG_SIZE (1M) // IDE JPEG buffer (header + data).
|
#define OMV_JPEG_SIZE (1M) // IDE JPEG buffer (header + data).
|
||||||
#define OMV_VOSPI_MEMORY SRAM4 // VoSPI buffer memory.
|
#define OMV_VOSPI_MEMORY SRAM4 // VoSPI buffer memory.
|
||||||
#define OMV_VOSPI_SIZE (38K)
|
#define OMV_VOSPI_SIZE (38K)
|
||||||
#define OMV_DMA_MEMORY SRAM3 // DMA buffers memory.
|
#define OMV_DMA_MEMORY SRAM3 // DMA buffers memory.
|
||||||
#define OMV_DMA_MEMORY_D1 AXI_SRAM // Domain 1 DMA buffers.
|
#define OMV_DMA_MEMORY_D1 SRAM0 // Domain 1 DMA buffers.
|
||||||
#define OMV_DMA_MEMORY_D2 SRAM3 // Domain 2 DMA buffers.
|
#define OMV_DMA_MEMORY_D2 SRAM3 // Domain 2 DMA buffers.
|
||||||
#define OMV_DMA_MEMORY_D3 SRAM4 // Domain 3 DMA buffers.
|
#define OMV_DMA_MEMORY_D3 SRAM4 // Domain 3 DMA buffers.
|
||||||
#define OMV_GC_BLOCK0_MEMORY SRAM1 // Main GC block.
|
#define OMV_GC_BLOCK0_MEMORY SRAM1 // Main GC block.
|
||||||
@ -142,14 +142,14 @@
|
|||||||
#define OMV_DTCM_LENGTH 128K
|
#define OMV_DTCM_LENGTH 128K
|
||||||
#define OMV_ITCM_ORIGIN 0x00000000
|
#define OMV_ITCM_ORIGIN 0x00000000
|
||||||
#define OMV_ITCM_LENGTH 64K
|
#define OMV_ITCM_LENGTH 64K
|
||||||
|
#define OMV_SRAM0_ORIGIN 0x24000000
|
||||||
|
#define OMV_SRAM0_LENGTH 512K
|
||||||
#define OMV_SRAM1_ORIGIN 0x30000000
|
#define OMV_SRAM1_ORIGIN 0x30000000
|
||||||
#define OMV_SRAM1_LENGTH 272K // SRAM1 + SRAM2 + 1/2 SRAM3
|
#define OMV_SRAM1_LENGTH 272K // SRAM1 + SRAM2 + 1/2 SRAM3
|
||||||
#define OMV_SRAM3_ORIGIN 0x30044000
|
#define OMV_SRAM3_ORIGIN 0x30044000
|
||||||
#define OMV_SRAM3_LENGTH 16K
|
#define OMV_SRAM3_LENGTH 16K
|
||||||
#define OMV_SRAM4_ORIGIN 0x38000000
|
#define OMV_SRAM4_ORIGIN 0x38000000
|
||||||
#define OMV_SRAM4_LENGTH 64K
|
#define OMV_SRAM4_LENGTH 64K
|
||||||
#define OMV_AXI_SRAM_ORIGIN 0x24000000
|
|
||||||
#define OMV_AXI_SRAM_LENGTH 512K
|
|
||||||
#define OMV_DRAM_ORIGIN 0xC0000000
|
#define OMV_DRAM_ORIGIN 0xC0000000
|
||||||
#define OMV_DRAM_LENGTH 64M
|
#define OMV_DRAM_LENGTH 64M
|
||||||
|
|
||||||
|
|||||||
@ -2,8 +2,9 @@ MCU=STM32H743xx
|
|||||||
CPU=cortex-m7
|
CPU=cortex-m7
|
||||||
FPU=fpv5-sp-d16
|
FPU=fpv5-sp-d16
|
||||||
PORT=stm32
|
PORT=stm32
|
||||||
OMV_BOOT_BASE=0x08000000
|
OMV_FIRM_BASE=0x08000000
|
||||||
OMV_FIRM_BASE=0x08040000
|
OMV_FIRM_ADDR=0x08040000
|
||||||
|
OMV_BOOT_ADDR=0x08000000
|
||||||
OMV_HSE_VALUE=12000000
|
OMV_HSE_VALUE=12000000
|
||||||
DFU_DEVICE=0x0483:0xdf11
|
DFU_DEVICE=0x0483:0xdf11
|
||||||
OMV_ENABLE_BL=1
|
OMV_ENABLE_BL=1
|
||||||
|
|||||||
@ -5,6 +5,7 @@ FABI=hard
|
|||||||
PORT=mimxrt
|
PORT=mimxrt
|
||||||
OMV_BOARD_CFLAGS=-DBOARD_FLASH_SIZE=0x800000
|
OMV_BOARD_CFLAGS=-DBOARD_FLASH_SIZE=0x800000
|
||||||
OMV_FIRM_BASE=0x60000000
|
OMV_FIRM_BASE=0x60000000
|
||||||
|
OMV_FIRM_ADDR=0x60000000
|
||||||
OMV_HSE_VALUE=12000000
|
OMV_HSE_VALUE=12000000
|
||||||
OMV_ENABLE_BL=0
|
OMV_ENABLE_BL=0
|
||||||
OMV_ENABLE_UVC=0
|
OMV_ENABLE_UVC=0
|
||||||
|
|||||||
@ -27,7 +27,15 @@ STARTUP ?= st/startup_$(shell echo $(MCU) | tr '[:upper:]' '[:lower:]')
|
|||||||
UVC_DIR := $(OMV_DIR)/ports/$(PORT)/uvc
|
UVC_DIR := $(OMV_DIR)/ports/$(PORT)/uvc
|
||||||
MCU_SERIES := $(shell echo $(MCU) | cut -c6-7 | tr '[:upper:]' '[:lower:]')
|
MCU_SERIES := $(shell echo $(MCU) | cut -c6-7 | tr '[:upper:]' '[:lower:]')
|
||||||
MCU_LOWER := $(shell echo $(MCU) | tr '[:upper:]' '[:lower:]')
|
MCU_LOWER := $(shell echo $(MCU) | tr '[:upper:]' '[:lower:]')
|
||||||
HAL_DIR = hal/stm32/$(MCU_SERIES)
|
HAL_DIR := hal/stm32/$(MCU_SERIES)
|
||||||
|
TFLM_CORE := $(CPU)
|
||||||
|
ifeq ($(CPU),$(filter $(CPU),cortex-m4 cortex-m7))
|
||||||
|
TFLM_CORE := $(CPU)+fp
|
||||||
|
endif
|
||||||
|
|
||||||
|
SIGN_TOOL = $(TOOLS)/st/cubeprog/bin/STM32MP_SigningTool_CLI
|
||||||
|
PROG_TOOL = $(TOOLS)/st/cubeprog/bin/STM32_Programmer.sh
|
||||||
|
STLDR_DIR = $(TOOLS)/st/cubeprog/bin/ExternalLoader/
|
||||||
|
|
||||||
# Compiler Flags
|
# Compiler Flags
|
||||||
CFLAGS += -std=gnu99 \
|
CFLAGS += -std=gnu99 \
|
||||||
@ -49,11 +57,10 @@ CFLAGS += -std=gnu99 \
|
|||||||
CFLAGS += -D$(MCU) \
|
CFLAGS += -D$(MCU) \
|
||||||
-D$(TARGET) \
|
-D$(TARGET) \
|
||||||
-DARM_NN_TRUNCATE \
|
-DARM_NN_TRUNCATE \
|
||||||
-D__FPU_PRESENT=1 \
|
|
||||||
-D__VFP_FP__ \
|
-D__VFP_FP__ \
|
||||||
-DUSE_FULL_LL_DRIVER \
|
-DUSE_FULL_LL_DRIVER \
|
||||||
-DHSE_VALUE=$(OMV_HSE_VALUE)\
|
-DHSE_VALUE=$(OMV_HSE_VALUE)\
|
||||||
-DOMV_VTOR_BASE=$(OMV_FIRM_BASE) \
|
-DOMV_VTOR_BASE=$(OMV_FIRM_ADDR) \
|
||||||
-DCMSIS_MCU_H='<$(MCU_LOWER).h>' \
|
-DCMSIS_MCU_H='<$(MCU_LOWER).h>' \
|
||||||
-DSTM32_HAL_H='<stm32$(MCU_SERIES)xx_hal.h>' \
|
-DSTM32_HAL_H='<stm32$(MCU_SERIES)xx_hal.h>' \
|
||||||
$(OMV_BOARD_CFLAGS)
|
$(OMV_BOARD_CFLAGS)
|
||||||
@ -145,7 +152,7 @@ CFLAGS += $(HAL_CFLAGS) $(MPY_CFLAGS) $(OMV_CFLAGS)
|
|||||||
ifeq ($(MICROPY_PY_AUDIO), 1)
|
ifeq ($(MICROPY_PY_AUDIO), 1)
|
||||||
LIBS += $(TOP_DIR)/$(LIBPDM_DIR)/libPDMFilter_CM7_GCC_wc32.a
|
LIBS += $(TOP_DIR)/$(LIBPDM_DIR)/libPDMFilter_CM7_GCC_wc32.a
|
||||||
endif
|
endif
|
||||||
LIBS += $(TOP_DIR)/$(TENSORFLOW_DIR)/libtflm/lib/libtflm-$(CPU)+fp-release.a
|
LIBS += $(TOP_DIR)/$(TENSORFLOW_DIR)/libtflm/lib/libtflm-$(TFLM_CORE)-release.a
|
||||||
|
|
||||||
#------------- Firmware Objects ----------------#
|
#------------- Firmware Objects ----------------#
|
||||||
FIRM_OBJ += $(wildcard $(BUILD)/$(CMSIS_DIR)/src/dsp/*/*.o)
|
FIRM_OBJ += $(wildcard $(BUILD)/$(CMSIS_DIR)/src/dsp/*/*.o)
|
||||||
@ -688,40 +695,45 @@ UVC_OBJS: FIRMWARE_OBJS
|
|||||||
$(MAKE) -C $(UVC_DIR) BUILD=$(BUILD)/$(UVC_DIR) CFLAGS="$(UVC_CFLAGS) -MMD"
|
$(MAKE) -C $(UVC_DIR) BUILD=$(BUILD)/$(UVC_DIR) CFLAGS="$(UVC_CFLAGS) -MMD"
|
||||||
endif
|
endif
|
||||||
|
|
||||||
# This target generates the bootloader.
|
# This target builds the UVC firmware.
|
||||||
ifeq ($(OMV_ENABLE_BL), 1)
|
|
||||||
BOOTLOADER = bootloader
|
|
||||||
$(BOOTLOADER): | $(BUILD) $(FW_DIR)
|
|
||||||
$(MAKE) -C $(TOP_DIR)/$(BOOT_DIR) BUILD=$(BUILD)/$(BOOT_DIR)
|
|
||||||
$(OBJCOPY) -Obinary $(FW_DIR)/$(BOOTLOADER).elf $(FW_DIR)/$(BOOTLOADER).bin
|
|
||||||
$(PYTHON) $(MKDFU) -D $(DFU_DEVICE) -b $(OMV_BOOT_BASE):$(FW_DIR)/$(BOOTLOADER).bin $(FW_DIR)/$(BOOTLOADER).dfu
|
|
||||||
endif
|
|
||||||
|
|
||||||
# This target generates the UVC firmware.
|
|
||||||
ifeq ($(OMV_ENABLE_UVC), 1)
|
ifeq ($(OMV_ENABLE_UVC), 1)
|
||||||
$(UVC): FIRMWARE_OBJS UVC_OBJS
|
$(UVC): FIRMWARE_OBJS UVC_OBJS
|
||||||
$(CPP) -P -E -I$(OMV_COMMON_DIR) -I$(OMV_BOARD_CONFIG_DIR) \
|
$(CPP) -P -E -I$(OMV_COMMON_DIR) -I$(OMV_BOARD_CONFIG_DIR) \
|
||||||
$(UVC_DIR)/stm32.ld.S > $(BUILD)/$(UVC_DIR)/stm32.lds
|
$(UVC_DIR)/stm32.ld.S > $(BUILD)/$(UVC_DIR)/stm32.lds
|
||||||
$(CC) $(UVC_LDFLAGS) $(UVC_OBJ) -o $(FW_DIR)/$(UVC).elf -lgcc
|
$(CC) $(UVC_LDFLAGS) $(UVC_OBJ) -o $(FW_DIR)/$(UVC).elf -lgcc
|
||||||
$(OBJCOPY) -Obinary $(FW_DIR)/$(UVC).elf $(FW_DIR)/$(UVC).bin
|
$(OBJCOPY) -Obinary $(FW_DIR)/$(UVC).elf $(FW_DIR)/$(UVC).bin
|
||||||
$(PYTHON) $(MKDFU) -D $(DFU_DEVICE) -b $(OMV_FIRM_BASE):$(FW_DIR)/$(UVC).bin $(FW_DIR)/$(UVC).dfu
|
$(PYTHON) $(MKDFU) -D $(DFU_DEVICE) -b $(OMV_FIRM_ADDR):$(FW_DIR)/$(UVC).bin $(FW_DIR)/$(UVC).dfu
|
||||||
endif
|
endif
|
||||||
|
|
||||||
# This target generates the main/app firmware image located at 0x08010000
|
# This target builds the bootloader.
|
||||||
|
ifeq ($(OMV_ENABLE_BL), 1)
|
||||||
|
BOOTLOADER = bootloader
|
||||||
|
$(BOOTLOADER): | $(BUILD) $(FW_DIR)
|
||||||
|
$(MAKE) -C $(TOP_DIR)/$(BOOT_DIR) BUILD=$(BUILD)/$(BOOT_DIR)
|
||||||
|
$(OBJCOPY) -Obinary $(FW_DIR)/$(BOOTLOADER).elf $(FW_DIR)/$(BOOTLOADER).bin
|
||||||
|
ifeq ($(OMV_SIGN_BOOT), 1)
|
||||||
|
$(SIGN_TOOL) -bin $(FW_DIR)/$(BOOTLOADER).bin -s -nk -t fsbl \
|
||||||
|
-of $(OMV_SIGN_FLAGS) -hv $(OMV_SIGN_HDRV) -o $(FW_DIR)/$(BOOTLOADER).bin
|
||||||
|
chmod +rw $(FW_DIR)/$(BOOTLOADER).bin
|
||||||
|
endif
|
||||||
|
$(PYTHON) $(MKDFU) -D $(DFU_DEVICE) -b $(OMV_BOOT_ADDR):$(FW_DIR)/$(BOOTLOADER).bin $(FW_DIR)/$(BOOTLOADER).dfu
|
||||||
|
endif
|
||||||
|
|
||||||
|
# This target builds the main/app firmware image.
|
||||||
$(FIRMWARE): FIRMWARE_OBJS
|
$(FIRMWARE): FIRMWARE_OBJS
|
||||||
$(CPP) -P -E -I$(OMV_COMMON_DIR) -I$(OMV_BOARD_CONFIG_DIR) \
|
$(CPP) -P -E -I$(OMV_COMMON_DIR) -I$(OMV_BOARD_CONFIG_DIR) \
|
||||||
$(OMV_DIR)/ports/$(PORT)/$(LDSCRIPT).ld.S > $(BUILD)/$(LDSCRIPT).lds
|
$(OMV_DIR)/ports/$(PORT)/$(LDSCRIPT).ld.S > $(BUILD)/$(LDSCRIPT).lds
|
||||||
$(CC) $(LDFLAGS) $(FIRM_OBJ) -o $(FW_DIR)/$(FIRMWARE).elf $(LIBS) -lm
|
$(CC) $(LDFLAGS) $(FIRM_OBJ) -o $(FW_DIR)/$(FIRMWARE).elf $(LIBS) -lm
|
||||||
$(OBJCOPY) -Obinary $(FW_DIR)/$(FIRMWARE).elf $(FW_DIR)/$(FIRMWARE).bin
|
$(OBJCOPY) -Obinary $(FW_DIR)/$(FIRMWARE).elf $(FW_DIR)/$(FIRMWARE).bin
|
||||||
$(PYTHON) $(MKDFU) -D $(DFU_DEVICE) -b $(OMV_FIRM_BASE):$(FW_DIR)/$(FIRMWARE).bin $(FW_DIR)/$(FIRMWARE).dfu
|
$(PYTHON) $(MKDFU) -D $(DFU_DEVICE) -b $(OMV_FIRM_ADDR):$(FW_DIR)/$(FIRMWARE).bin $(FW_DIR)/$(FIRMWARE).dfu
|
||||||
|
|
||||||
# This target generates the uvc, bootloader and firmware images.
|
# This target builds a contiguous firmware image.
|
||||||
$(OPENMV): $(BOOTLOADER) $(UVC) $(FIRMWARE)
|
$(OPENMV): $(BOOTLOADER) $(UVC) $(FIRMWARE)
|
||||||
ifeq ($(OMV_ENABLE_BL), 1)
|
ifeq ($(OMV_ENABLE_BL), 1)
|
||||||
# Generate a contiguous firmware image for factory programming
|
# Pad the bootloader binary with 0xFF up to the firmware start.
|
||||||
$(OBJCOPY) -Obinary --pad-to=$(OMV_FIRM_BASE) --gap-fill=0xFF $(FW_DIR)/$(BOOTLOADER).elf $(FW_DIR)/$(BOOTLOADER)_padded.bin
|
$(OBJCOPY) -I binary -O binary --pad-to $$(($(OMV_FIRM_ADDR) - $(OMV_FIRM_BASE))) \
|
||||||
$(CAT) $(FW_DIR)/$(BOOTLOADER)_padded.bin $(FW_DIR)/$(FIRMWARE).bin > $(FW_DIR)/$(OPENMV).bin
|
--gap-fill 0xFF $(FW_DIR)/$(BOOTLOADER).bin $(FW_DIR)/$(BOOTLOADER).bin
|
||||||
$(RM) $(FW_DIR)/$(BOOTLOADER)_padded.bin
|
$(CAT) $(FW_DIR)/$(BOOTLOADER).bin $(FW_DIR)/$(FIRMWARE).bin > $(FW_DIR)/$(OPENMV).bin
|
||||||
$(SIZE) $(FW_DIR)/$(BOOTLOADER).elf
|
$(SIZE) $(FW_DIR)/$(BOOTLOADER).elf
|
||||||
endif
|
endif
|
||||||
$(SIZE) $(FW_DIR)/$(FIRMWARE).elf
|
$(SIZE) $(FW_DIR)/$(FIRMWARE).elf
|
||||||
@ -747,3 +759,7 @@ flash_boot_dfu_util::
|
|||||||
# Flash the main firmware image using dfu_util
|
# Flash the main firmware image using dfu_util
|
||||||
flash_image_dfu_util::
|
flash_image_dfu_util::
|
||||||
dfu-util -a 0 -d $(DFU_DEVICE) -D $(FW_DIR)/$(FIRMWARE).dfu
|
dfu-util -a 0 -d $(DFU_DEVICE) -D $(FW_DIR)/$(FIRMWARE).dfu
|
||||||
|
|
||||||
|
deploy: $(OPENMV)
|
||||||
|
$(PROG_TOOL) -c port=SWD mode=HOTPLUG ap=1 \
|
||||||
|
-el $(STLDR_DIR)/$(OMV_PROG_STLDR) -w $(FW_DIR)/$(OPENMV).bin $(OMV_FIRM_BASE) -hardRst
|
||||||
|
|||||||
@ -36,7 +36,12 @@ MEMORY
|
|||||||
#if defined(OMV_ITCM_ORIGIN)
|
#if defined(OMV_ITCM_ORIGIN)
|
||||||
ITCM (xrw) : ORIGIN = OMV_ITCM_ORIGIN, LENGTH = OMV_ITCM_LENGTH
|
ITCM (xrw) : ORIGIN = OMV_ITCM_ORIGIN, LENGTH = OMV_ITCM_LENGTH
|
||||||
#endif
|
#endif
|
||||||
|
#if defined(OMV_SRAM0_ORIGIN)
|
||||||
|
SRAM0 (xrw) : ORIGIN = OMV_SRAM0_ORIGIN, LENGTH = OMV_SRAM0_LENGTH
|
||||||
|
#endif
|
||||||
|
#if defined(OMV_SRAM1_ORIGIN)
|
||||||
SRAM1 (xrw) : ORIGIN = OMV_SRAM1_ORIGIN, LENGTH = OMV_SRAM1_LENGTH
|
SRAM1 (xrw) : ORIGIN = OMV_SRAM1_ORIGIN, LENGTH = OMV_SRAM1_LENGTH
|
||||||
|
#endif
|
||||||
#if defined(OMV_SRAM2_ORIGIN)
|
#if defined(OMV_SRAM2_ORIGIN)
|
||||||
SRAM2 (xrw) : ORIGIN = OMV_SRAM2_ORIGIN, LENGTH = OMV_SRAM2_LENGTH
|
SRAM2 (xrw) : ORIGIN = OMV_SRAM2_ORIGIN, LENGTH = OMV_SRAM2_LENGTH
|
||||||
#endif
|
#endif
|
||||||
@ -46,8 +51,11 @@ MEMORY
|
|||||||
#if defined(OMV_SRAM4_ORIGIN)
|
#if defined(OMV_SRAM4_ORIGIN)
|
||||||
SRAM4 (xrw) : ORIGIN = OMV_SRAM4_ORIGIN, LENGTH = OMV_SRAM4_LENGTH
|
SRAM4 (xrw) : ORIGIN = OMV_SRAM4_ORIGIN, LENGTH = OMV_SRAM4_LENGTH
|
||||||
#endif
|
#endif
|
||||||
#if defined(OMV_AXI_SRAM_ORIGIN)
|
#if defined(OMV_SRAM5_ORIGIN)
|
||||||
AXI_SRAM (xrw) : ORIGIN = OMV_AXI_SRAM_ORIGIN, LENGTH = OMV_AXI_SRAM_LENGTH
|
SRAM5 (xrw) : ORIGIN = OMV_SRAM5_ORIGIN, LENGTH = OMV_SRAM5_LENGTH
|
||||||
|
#endif
|
||||||
|
#if defined(OMV_SRAM6_ORIGIN)
|
||||||
|
SRAM6 (xrw) : ORIGIN = OMV_SRAM6_ORIGIN, LENGTH = OMV_SRAM6_LENGTH
|
||||||
#endif
|
#endif
|
||||||
#if defined(OMV_DRAM_ORIGIN)
|
#if defined(OMV_DRAM_ORIGIN)
|
||||||
DRAM (xrw) : ORIGIN = OMV_DRAM_ORIGIN, LENGTH = OMV_DRAM_LENGTH
|
DRAM (xrw) : ORIGIN = OMV_DRAM_ORIGIN, LENGTH = OMV_DRAM_LENGTH
|
||||||
|
|||||||
@ -21,7 +21,12 @@ MEMORY
|
|||||||
#if defined(OMV_ITCM_ORIGIN)
|
#if defined(OMV_ITCM_ORIGIN)
|
||||||
ITCM (xrw) : ORIGIN = OMV_ITCM_ORIGIN, LENGTH = OMV_ITCM_LENGTH
|
ITCM (xrw) : ORIGIN = OMV_ITCM_ORIGIN, LENGTH = OMV_ITCM_LENGTH
|
||||||
#endif
|
#endif
|
||||||
|
#if defined(OMV_SRAM0_ORIGIN)
|
||||||
|
SRAM0 (xrw) : ORIGIN = OMV_SRAM0_ORIGIN, LENGTH = OMV_SRAM0_LENGTH
|
||||||
|
#endif
|
||||||
|
#if defined(OMV_SRAM1_ORIGIN)
|
||||||
SRAM1 (xrw) : ORIGIN = OMV_SRAM1_ORIGIN, LENGTH = OMV_SRAM1_LENGTH
|
SRAM1 (xrw) : ORIGIN = OMV_SRAM1_ORIGIN, LENGTH = OMV_SRAM1_LENGTH
|
||||||
|
#endif
|
||||||
#if defined(OMV_SRAM2_ORIGIN)
|
#if defined(OMV_SRAM2_ORIGIN)
|
||||||
SRAM2 (xrw) : ORIGIN = OMV_SRAM2_ORIGIN, LENGTH = OMV_SRAM2_LENGTH
|
SRAM2 (xrw) : ORIGIN = OMV_SRAM2_ORIGIN, LENGTH = OMV_SRAM2_LENGTH
|
||||||
#endif
|
#endif
|
||||||
@ -31,9 +36,6 @@ MEMORY
|
|||||||
#if defined(OMV_SRAM4_ORIGIN)
|
#if defined(OMV_SRAM4_ORIGIN)
|
||||||
SRAM4 (xrw) : ORIGIN = OMV_SRAM4_ORIGIN, LENGTH = OMV_SRAM4_LENGTH
|
SRAM4 (xrw) : ORIGIN = OMV_SRAM4_ORIGIN, LENGTH = OMV_SRAM4_LENGTH
|
||||||
#endif
|
#endif
|
||||||
#if defined(OMV_AXI_SRAM_ORIGIN)
|
|
||||||
AXI_SRAM (xrw) : ORIGIN = OMV_AXI_SRAM_ORIGIN, LENGTH = OMV_AXI_SRAM_LENGTH
|
|
||||||
#endif
|
|
||||||
#if defined(OMV_DRAM_ORIGIN)
|
#if defined(OMV_DRAM_ORIGIN)
|
||||||
DRAM (xrw) : ORIGIN = OMV_DRAM_ORIGIN, LENGTH = OMV_DRAM_LENGTH
|
DRAM (xrw) : ORIGIN = OMV_DRAM_ORIGIN, LENGTH = OMV_DRAM_LENGTH
|
||||||
#endif
|
#endif
|
||||||
|
|||||||
Loading…
Reference in New Issue
Block a user