Merge pull request #2499 from openmv/stm32_port_updates

ports/stm32: Misc updates.
This commit is contained in:
Ibrahim Abdelkader 2024-11-14 12:27:05 +02:00 committed by GitHub
commit 1b980234ae
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5 changed files with 282 additions and 177 deletions

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@ -24,81 +24,38 @@
* STM32 DMA helper functions.
*/
#include <stdbool.h>
#include STM32_HAL_H
#include "py/mphal.h"
#include "omv_boardconfig.h"
#include "omv_common.h"
#include "dma_utils.h"
// Defined in micropython/ports/stm32/dma.c
// or in uvc/src/main.c
#if defined(GPDMA1)
DMA_HandleTypeDef *dma_handle[32];
#else
// Defined in micropython/ports/stm32/dma.c or in uvc/src/main.c
extern DMA_HandleTypeDef *dma_handle[16];
#endif
uint8_t dma_utils_channel_to_irqn(DMA_Stream_TypeDef *dma_channel) {
uint8_t dma_utils_channel_to_irqn(void *dma_channel) {
uint32_t dma_base = ((uint32_t) dma_channel) & 0xFFFFF000;
if (0) {
#if defined(DMA1_Stream0)
} else if (dma_channel == DMA1_Stream0) {
return DMA1_Stream0_IRQn;
#endif
#if defined(DMA1_Stream1)
} else if (dma_channel == DMA1_Stream1) {
return DMA1_Stream1_IRQn;
#endif
#if defined(DMA1_Stream2)
} else if (dma_channel == DMA1_Stream2) {
return DMA1_Stream2_IRQn;
#endif
#if defined(DMA1_Stream3)
} else if (dma_channel == DMA1_Stream3) {
return DMA1_Stream3_IRQn;
#endif
#if defined(DMA1_Stream4)
} else if (dma_channel == DMA1_Stream4) {
return DMA1_Stream4_IRQn;
#endif
#if defined(DMA1_Stream5)
} else if (dma_channel == DMA1_Stream5) {
return DMA1_Stream5_IRQn;
#endif
#if defined(DMA1_Stream6)
} else if (dma_channel == DMA1_Stream6) {
return DMA1_Stream6_IRQn;
#endif
#if defined(DMA1_Stream7)
} else if (dma_channel == DMA1_Stream7) {
return DMA1_Stream7_IRQn;
} else if (dma_base == DMA1_BASE) {
return ((DMA_Stream_TypeDef *) dma_channel - DMA1_Stream0) + DMA1_Stream0_IRQn;
#endif
#if defined(DMA2_Stream0)
} else if (dma_channel == DMA2_Stream0) {
return DMA2_Stream0_IRQn;
} else if (dma_base == DMA2_BASE) {
return ((DMA_Stream_TypeDef *) dma_channel - DMA2_Stream0) + DMA2_Stream0_IRQn;
#endif
#if defined(DMA2_Stream1)
} else if (dma_channel == DMA2_Stream1) {
return DMA2_Stream1_IRQn;
#if defined(GPDMA1_Channel0)
} else if (dma_base == GPDMA1_BASE) {
return ((DMA_Channel_TypeDef *) dma_channel - GPDMA1_Channel0) + GPDMA1_Channel0_IRQn;
#endif
#if defined(DMA2_Stream2)
} else if (dma_channel == DMA2_Stream2) {
return DMA2_Stream2_IRQn;
#endif
#if defined(DMA2_Stream3)
} else if (dma_channel == DMA2_Stream3) {
return DMA2_Stream3_IRQn;
#endif
#if defined(DMA2_Stream4)
} else if (dma_channel == DMA2_Stream4) {
return DMA2_Stream4_IRQn;
#endif
#if defined(DMA2_Stream5)
} else if (dma_channel == DMA2_Stream5) {
return DMA2_Stream5_IRQn;
#endif
#if defined(DMA2_Stream6)
} else if (dma_channel == DMA2_Stream6) {
return DMA2_Stream6_IRQn;
#endif
#if defined(DMA2_Stream7)
} else if (dma_channel == DMA2_Stream7) {
return DMA2_Stream7_IRQn;
#if defined(HPDMA1_Channel0)
} else if (dma_base == HPDMA1_BASE) {
return ((DMA_Channel_TypeDef *) dma_channel - HPDMA1_Channel0) + HPDMA1_Channel0_IRQn;
#endif
}
return 0;
@ -107,80 +64,30 @@ uint8_t dma_utils_channel_to_irqn(DMA_Stream_TypeDef *dma_channel) {
// This returns a DMA ID that can be used to index into the dma_handle
// array defined in micropython. Setting a DMA handle in that array allows
// DMA IRQ handlers (which are all defined in micropython) to use it.
uint8_t dma_utils_channel_to_id(DMA_Stream_TypeDef *dma_channel) {
uint8_t dma_id = -1;
uint8_t dma_utils_channel_to_id(void *dma_channel) {
uint32_t dma_base = ((uint32_t) dma_channel) & 0xFFFFF000;
if (0) {
#if defined(DMA1_Stream0)
} else if (dma_channel == DMA1_Stream0) {
dma_id = 0;
#endif
#if defined(DMA1_Stream1)
} else if (dma_channel == DMA1_Stream1) {
dma_id = 1;
#endif
#if defined(DMA1_Stream2)
} else if (dma_channel == DMA1_Stream2) {
dma_id = 2;
#endif
#if defined(DMA1_Stream3)
} else if (dma_channel == DMA1_Stream3) {
dma_id = 3;
#endif
#if defined(DMA1_Stream4)
} else if (dma_channel == DMA1_Stream4) {
dma_id = 4;
#endif
#if defined(DMA1_Stream5)
} else if (dma_channel == DMA1_Stream5) {
dma_id = 5;
#endif
#if defined(DMA1_Stream6)
} else if (dma_channel == DMA1_Stream6) {
dma_id = 6;
#endif
#if defined(DMA1_Stream7)
} else if (dma_channel == DMA1_Stream7) {
dma_id = 7;
} else if (dma_base == DMA1_BASE) {
return ((DMA_Stream_TypeDef *) dma_channel - DMA1_Stream0);
#endif
#if defined(DMA2_Stream0)
} else if (dma_channel == DMA2_Stream0) {
dma_id = 8;
} else if (dma_base == DMA2_BASE) {
return ((DMA_Stream_TypeDef *) dma_channel - DMA2_Stream0) + 8;
#endif
#if defined(DMA2_Stream1)
} else if (dma_channel == DMA2_Stream1) {
dma_id = 9;
#if defined(GPDMA1_Channel0)
} else if (dma_base == GPDMA1_BASE) {
return ((DMA_Channel_TypeDef *) dma_channel - GPDMA1_Channel0);
#endif
#if defined(DMA2_Stream2)
} else if (dma_channel == DMA2_Stream2) {
dma_id = 10;
#endif
#if defined(DMA2_Stream3)
} else if (dma_channel == DMA2_Stream3) {
dma_id = 11;
#endif
#if defined(DMA2_Stream4)
} else if (dma_channel == DMA2_Stream4) {
dma_id = 12;
#endif
#if defined(DMA2_Stream5)
} else if (dma_channel == DMA2_Stream5) {
dma_id = 13;
#endif
#if defined(DMA2_Stream6)
} else if (dma_channel == DMA2_Stream6) {
dma_id = 14;
#endif
#if defined(DMA2_Stream7)
} else if (dma_channel == DMA2_Stream7) {
dma_id = 15;
#if defined(HPDMA1_Channel0)
} else if (dma_base == HPDMA1_BASE) {
return ((DMA_Channel_TypeDef *) dma_channel - HPDMA1_Channel0) + 16;
#endif
}
return dma_id;
return -1;
}
int dma_utils_set_irq_descr(DMA_Stream_TypeDef *dma_channel, DMA_HandleTypeDef *dma_descr) {
int dma_utils_set_irq_descr(void *dma_channel, DMA_HandleTypeDef *dma_descr) {
uint8_t dma_id = dma_utils_channel_to_id(dma_channel);
if (dma_id != -1) {
dma_handle[dma_id] = dma_descr;
@ -190,6 +97,7 @@ int dma_utils_set_irq_descr(DMA_Stream_TypeDef *dma_channel, DMA_HandleTypeDef *
}
uint8_t dma_utils_mpu_region_size(uint32_t size) {
#if (__ARM_ARCH <= 7)
switch (size) {
case 0x00000020U: {
return MPU_REGION_SIZE_32B;
@ -276,4 +184,142 @@ uint8_t dma_utils_mpu_region_size(uint32_t size) {
return MPU_REGION_SIZE_4GB;
}
}
#endif
return -1;
}
#if defined(GPDMA1)
static inline void dma_utils_irq_handler(size_t irqn) {
if (dma_handle[irqn] != NULL) {
HAL_DMA_IRQHandler(dma_handle[irqn]);
}
}
void GPDMA1_Channel0_IRQHandler(void) {
dma_utils_irq_handler(0);
}
void GPDMA1_Channel1_IRQHandler(void) {
dma_utils_irq_handler(1);
}
void GPDMA1_Channel2_IRQHandler(void) {
dma_utils_irq_handler(2);
}
void GPDMA1_Channel3_IRQHandler(void) {
dma_utils_irq_handler(3);
}
void GPDMA1_Channel4_IRQHandler(void) {
dma_utils_irq_handler(4);
}
void GPDMA1_Channel5_IRQHandler(void) {
dma_utils_irq_handler(5);
}
void GPDMA1_Channel6_IRQHandler(void) {
dma_utils_irq_handler(6);
}
void GPDMA1_Channel7_IRQHandler(void) {
dma_utils_irq_handler(7);
}
void GPDMA1_Channel8_IRQHandler(void) {
dma_utils_irq_handler(8);
}
void GPDMA1_Channel9_IRQHandler(void) {
dma_utils_irq_handler(9);
}
void GPDMA1_Channel10_IRQHandler(void) {
dma_utils_irq_handler(10);
}
void GPDMA1_Channel11_IRQHandler(void) {
dma_utils_irq_handler(11);
}
void GPDMA1_Channel12_IRQHandler(void) {
dma_utils_irq_handler(12);
}
void GPDMA1_Channel13_IRQHandler(void) {
dma_utils_irq_handler(13);
}
void GPDMA1_Channel14_IRQHandler(void) {
dma_utils_irq_handler(14);
}
void GPDMA1_Channel15_IRQHandler(void) {
dma_utils_irq_handler(15);
}
void HPDMA1_Channel0_IRQHandler(void) {
dma_utils_irq_handler(16);
}
void HPDMA1_Channel1_IRQHandler(void) {
dma_utils_irq_handler(17);
}
void HPDMA1_Channel2_IRQHandler(void) {
dma_utils_irq_handler(18);
}
void HPDMA1_Channel3_IRQHandler(void) {
dma_utils_irq_handler(19);
}
void HPDMA1_Channel4_IRQHandler(void) {
dma_utils_irq_handler(20);
}
void HPDMA1_Channel5_IRQHandler(void) {
dma_utils_irq_handler(21);
}
void HPDMA1_Channel6_IRQHandler(void) {
dma_utils_irq_handler(22);
}
void HPDMA1_Channel7_IRQHandler(void) {
dma_utils_irq_handler(23);
}
void HPDMA1_Channel8_IRQHandler(void) {
dma_utils_irq_handler(24);
}
void HPDMA1_Channel9_IRQHandler(void) {
dma_utils_irq_handler(25);
}
void HPDMA1_Channel10_IRQHandler(void) {
dma_utils_irq_handler(26);
}
void HPDMA1_Channel11_IRQHandler(void) {
dma_utils_irq_handler(27);
}
void HPDMA1_Channel12_IRQHandler(void) {
dma_utils_irq_handler(28);
}
void HPDMA1_Channel13_IRQHandler(void) {
dma_utils_irq_handler(29);
}
void HPDMA1_Channel14_IRQHandler(void) {
dma_utils_irq_handler(30);
}
void HPDMA1_Channel15_IRQHandler(void) {
dma_utils_irq_handler(31);
}
#endif

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@ -31,8 +31,8 @@
(MDMA_Channel_TypeDef *) (MDMA_Channel0_BASE + ((MDMA_Channel1_BASE - MDMA_Channel0_BASE) * x))
#endif
uint8_t dma_utils_channel_to_irqn(DMA_Stream_TypeDef *dma_channel);
uint8_t dma_utils_channel_to_id(DMA_Stream_TypeDef *dma_channel);
int dma_utils_set_irq_descr(DMA_Stream_TypeDef *dma_channel, DMA_HandleTypeDef *dma_descr);
uint8_t dma_utils_channel_to_irqn(void *dma_channel);
uint8_t dma_utils_channel_to_id(void *dma_channel);
int dma_utils_set_irq_descr(void *dma_channel, DMA_HandleTypeDef *dma_descr);
uint8_t dma_utils_mpu_region_size(uint32_t size);
#endif // __DMA_UTILS_H__

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@ -57,6 +57,12 @@ MEMORY
#if defined(OMV_SRAM6_ORIGIN)
SRAM6 (xrw) : ORIGIN = OMV_SRAM6_ORIGIN, LENGTH = OMV_SRAM6_LENGTH
#endif
#if defined(OMV_SRAM7_ORIGIN)
SRAM7 (xrw) : ORIGIN = OMV_SRAM7_ORIGIN, LENGTH = OMV_SRAM7_LENGTH
#endif
#if defined(OMV_SRAM8_ORIGIN)
SRAM8 (xrw) : ORIGIN = OMV_SRAM8_ORIGIN, LENGTH = OMV_SRAM8_LENGTH
#endif
#if defined(OMV_DRAM_ORIGIN)
DRAM (xrw) : ORIGIN = OMV_DRAM_ORIGIN, LENGTH = OMV_DRAM_LENGTH
#endif

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@ -40,14 +40,49 @@
#define MPU_REGION_NUMBER_MAX (MPU_REGION_NUMBER7)
#endif
#define MEM_ATTR_NORMAL_NON_CACHEABLE 0
extern void SystemClock_Config(void);
extern uint32_t omv_exti_get_gpio(uint32_t line);
void HAL_MspInit(void) {
/* Set the system clock */
// Set the system clock
SystemClock_Config();
#if (__DCACHE_PRESENT == 1) && defined(OMV_DMA_MEMORY)
#if __DCACHE_PRESENT && defined(OMV_DMA_MEMORY)
// Configure MPU regions.
typedef struct {
uint32_t addr;
uint32_t size;
} dma_memory_table_t;
// Start from the last region.
uint8_t region_number = (MPU->TYPE >> 8) - 1;
extern const dma_memory_table_t _dma_memory_table_start;
extern const dma_memory_table_t _dma_memory_table_end;
#if (__ARM_ARCH == 8)
ARM_MPU_Disable();
// Clear all regions.
for (size_t i = 0; i < (MPU->TYPE >> 8); i++) {
ARM_MPU_ClrRegion(i);
}
ARM_MPU_SetMemAttr(MEM_ATTR_NORMAL_NON_CACHEABLE, ARM_MPU_ATTR(
ARM_MPU_ATTR_NON_CACHEABLE,
ARM_MPU_ATTR_NON_CACHEABLE));
for (dma_memory_table_t const *buf = &_dma_memory_table_start; buf < &_dma_memory_table_end; buf++) {
uint32_t region_base = buf->addr;
uint32_t region_size = buf->size;
if (region_size) {
MPU->RNR = region_number--;
MPU->RBAR = ARM_MPU_RBAR(region_base, ARM_MPU_SH_NON, 0, 1, 0); // RO-0, NP-1, XN-0
MPU->RLAR = ARM_MPU_RLAR(region_base + region_size - 1, MEM_ATTR_NORMAL_NON_CACHEABLE);
}
}
ARM_MPU_Enable(MPU_CTRL_PRIVDEFENA_Msk | MPU_CTRL_HFNMIENA_Msk);
#elif (__ARM_ARCH == 7)
HAL_MPU_Disable();
// Configure the MPU attributes to disable caching DMA buffers.
@ -61,21 +96,12 @@ void HAL_MspInit(void) {
MPU_InitStruct.DisableExec = MPU_INSTRUCTION_ACCESS_ENABLE;
// Disable all regions.
for (int i = MPU_REGION_NUMBER0; i <= MPU_REGION_NUMBER_MAX; i++) {
for (int i = 0; i < (MPU->TYPE >> 8); i++) {
MPU_InitStruct.Number = i;
MPU_InitStruct.Enable = MPU_REGION_DISABLE;
HAL_MPU_ConfigRegion(&MPU_InitStruct);
}
typedef struct {
uint32_t addr;
uint32_t size;
} dma_memory_table_t;
uint8_t region_number = MPU_REGION_NUMBER_MAX;
extern const dma_memory_table_t _dma_memory_table_start;
extern const dma_memory_table_t _dma_memory_table_end;
for (dma_memory_table_t const *buf = &_dma_memory_table_start; buf < &_dma_memory_table_end; buf++) {
if (buf->size >= 32) {
MPU_InitStruct.Number = region_number--;
@ -89,15 +115,13 @@ void HAL_MspInit(void) {
// Enable the MPU.
HAL_MPU_Enable(MPU_PRIVILEGED_DEFAULT);
__DSB(); __ISB();
#endif // defined(OMV_DMA_MEMORY)
#else
#error Unsupported ARM architecture
#endif // __ARM_ARCH
#endif // defined(OMV_DMA_MEMORY)
// Enable I/D cache.
#if defined(STM32F7) || defined(STM32H7)
#ifdef OMV_DISABLE_CACHE
// Disable caches for testing.
SCB_DisableICache();
SCB_DisableDCache();
#else
#ifdef __DCACHE_PRESENT
// Enable caches if not enabled, or clean and invalidate.
if (!(SCB->CCR & (uint32_t) SCB_CCR_IC_Msk)) {
SCB_EnableICache();
@ -113,42 +137,63 @@ void HAL_MspInit(void) {
__ISB(); __DSB(); __DMB();
}
#endif
#endif
// Config Systick.
HAL_NVIC_SetPriority(SysTick_IRQn, 0, 0);
// Enable GPIO clocks.
__GPIOA_CLK_ENABLE();
__GPIOB_CLK_ENABLE();
__GPIOC_CLK_ENABLE();
__GPIOD_CLK_ENABLE();
__GPIOE_CLK_ENABLE();
__HAL_RCC_GPIOA_CLK_ENABLE();
__HAL_RCC_GPIOB_CLK_ENABLE();
__HAL_RCC_GPIOC_CLK_ENABLE();
__HAL_RCC_GPIOD_CLK_ENABLE();
__HAL_RCC_GPIOE_CLK_ENABLE();
#if OMV_GPIO_PORT_F_ENABLE
__GPIOF_CLK_ENABLE();
__HAL_RCC_GPIOF_CLK_ENABLE();
#endif
#if OMV_GPIO_PORT_G_ENABLE
__GPIOG_CLK_ENABLE();
__HAL_RCC_GPIOG_CLK_ENABLE();
#endif
#if OMV_GPIO_PORT_H_ENABLE
__GPIOH_CLK_ENABLE();
__HAL_RCC_GPIOH_CLK_ENABLE();
#endif
#if OMV_GPIO_PORT_I_ENABLE
__GPIOI_CLK_ENABLE();
__HAL_RCC_GPIOI_CLK_ENABLE();
#endif
#if OMV_GPIO_PORT_J_ENABLE
__GPIOJ_CLK_ENABLE();
__HAL_RCC_GPIOJ_CLK_ENABLE();
#endif
#if OMV_GPIO_PORT_K_ENABLE
__GPIOK_CLK_ENABLE();
__HAL_RCC_GPIOK_CLK_ENABLE();
#endif
#if OMV_GPIO_PORT_N_ENABLE
__HAL_RCC_GPION_CLK_ENABLE();
#endif
#if OMV_GPIO_PORT_O_ENABLE
__HAL_RCC_GPIOO_CLK_ENABLE();
#endif
#if OMV_GPIO_PORT_P_ENABLE
__HAL_RCC_GPIOP_CLK_ENABLE();
#endif
#if OMV_GPIO_PORT_Q_ENABLE
__HAL_RCC_GPIOQ_CLK_ENABLE();
#endif
// Enable DMA clocks.
__DMA1_CLK_ENABLE();
__DMA2_CLK_ENABLE();
#if defined(STM32H7)
// MDMA clock.
#if defined(__HAL_RCC_DMA1_CLK_ENABLE)
__HAL_RCC_DMA1_CLK_ENABLE();
#endif
#if defined(__HAL_RCC_DMA2_CLK_ENABLE)
__HAL_RCC_DMA2_CLK_ENABLE();
#endif
#if defined(__HAL_RCC_GPDMA1_CLK_ENABLE)
__HAL_RCC_GPDMA1_CLK_ENABLE();
__HAL_RCC_GPDMA1_CLK_SLEEP_ENABLE();
#endif
#if defined(__HAL_RCC_HPDMA1_CLK_ENABLE)
__HAL_RCC_HPDMA1_CLK_ENABLE();
__HAL_RCC_HPDMA1_CLK_SLEEP_ENABLE();
#endif
#if defined(__HAL_RCC_MDMA_CLK_ENABLE)
__HAL_RCC_MDMA_CLK_ENABLE();
NVIC_SetPriority(MDMA_IRQn, IRQ_PRI_MDMA);
HAL_NVIC_EnableIRQ(MDMA_IRQn);
@ -293,7 +338,7 @@ void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c) {
}
void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim) {
#if (OMV_CSI_CLK_SOURCE == OMV_CSI_CLK_SOURCE_TIM)
#if defined(OMV_CSI_TIM)
if (htim->Instance == OMV_CSI_TIM) {
// Enable DCMI timer clock.
OMV_CSI_TIM_CLK_ENABLE();
@ -303,7 +348,7 @@ void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim) {
omv_gpio_config(OMV_CSI_TIM_EXT_PIN, OMV_GPIO_MODE_ALT, OMV_GPIO_PULL_UP, OMV_GPIO_SPEED_HIGH, -1);
#endif
}
#endif // (OMV_CSI_CLK_SOURCE == OMV_CSI_CLK_SOURCE_TIM)
#endif // (OMV_CSI_TIM)
#if defined(OMV_BUZZER_TIM)
if (htim->Instance == OMV_BUZZER_TIM) {

View File

@ -366,12 +366,12 @@ static int reset(omv_csi_t *csi) {
lepton.max_temp = LEPTON_MAX_TEMP_DEFAULT;
if (lepton_reset(csi, false, false) != 0) {
return -1;
return OMV_CSI_ERROR_CTL_FAILED;
}
if (vospi_initialized == false) {
if (vospi_init(lepton.v_res, _vospi_buf) != 0) {
return -1;
return OMV_CSI_ERROR_CTL_FAILED;
}
vospi_initialized = true;
}
@ -386,19 +386,27 @@ static int snapshot(omv_csi_t *csi, image_t *image, uint32_t flags) {
framebuffer_set_buffers(1);
}
if (omv_csi_check_framebuffer_size(csi) == -1) {
return -1;
if (csi->pixformat == PIXFORMAT_INVALID) {
return OMV_CSI_ERROR_INVALID_PIXFORMAT;
}
if ((!lepton.h_res) || (!lepton.v_res) || (!csi->framesize) || (!csi->pixformat)) {
return -1;
if (csi->framesize == OMV_CSI_FRAMESIZE_INVALID) {
return OMV_CSI_ERROR_INVALID_FRAMESIZE;
}
if (!lepton.h_res || !lepton.v_res) {
return OMV_CSI_ERROR_INVALID_FRAMESIZE;
}
if (omv_csi_check_framebuffer_size(csi) == -1) {
return OMV_CSI_ERROR_FRAMEBUFFER_OVERFLOW;
}
framebuffer_free_current_buffer();
vbuffer_t *buffer = framebuffer_get_tail(FB_NO_FLAGS);
if (!buffer) {
return -1;
return OMV_CSI_ERROR_FRAMEBUFFER_ERROR;
}
for (int i = 0; i < LEPTON_SNAPSHOT_RETRY; i++) {
@ -406,11 +414,11 @@ static int snapshot(omv_csi_t *csi, image_t *image, uint32_t flags) {
break;
}
if (i + 1 == LEPTON_SNAPSHOT_RETRY) {
return -1;
return OMV_CSI_ERROR_CAPTURE_TIMEOUT;
}
// The FLIR lepton might have crashed so reset it (it does this).
if (lepton_reset(csi, lepton.measurement_mode, lepton.high_temp_mode) != 0) {
return -1;
return OMV_CSI_ERROR_CTL_FAILED;
}
}
@ -432,7 +440,7 @@ static int snapshot(omv_csi_t *csi, image_t *image, uint32_t flags) {
LEP_SYS_FPA_TEMPERATURE_KELVIN_T kelvin;
if (lepton.measurement_mode && (!lepton.radiometry)) {
if (LEP_GetSysFpaTemperatureKelvin(&lepton.port, &kelvin) != LEP_OK) {
return -1;
return OMV_CSI_ERROR_IO_ERROR;
}
}
@ -530,7 +538,7 @@ int lepton_init(omv_csi_t *csi) {
LEP_OEM_PART_NUMBER_T part;
if (LEP_GetOemFlirPartNumber(&lepton.port, &part) != LEP_OK) {
return -1;
return OMV_CSI_ERROR_CSI_INIT_FAILED;
}
// 500 == Lepton