From 22154c2badd986bc45f4e2a90ed4626fc9b2f646 Mon Sep 17 00:00:00 2001 From: iabdalkader Date: Thu, 4 Feb 2016 00:01:15 +0200 Subject: [PATCH] Adjust PLL setting. * XCLK=12MHz PCLK=48MHz --- src/omv/ov7725.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/omv/ov7725.c b/src/omv/ov7725.c index 3a717f0dc..bc756c37b 100644 --- a/src/omv/ov7725.c +++ b/src/omv/ov7725.c @@ -25,8 +25,8 @@ static const uint8_t default_regs[][2] = { {COM3, COM3_SWAP_YUV}, {COM7, COM7_RES_VGA | COM7_FMT_RGB565 | COM7_FMT_RGB}, - {COM4, 0x81}, /* PLL */ - {CLKRC, 0x01}, + {COM4, 0xC1}, /* PLL */ + {CLKRC, 0x00}, // VGA Window Size {HSTART, 0x23},