Adjust PLL setting.

* XCLK=12MHz PCLK=48MHz
This commit is contained in:
iabdalkader 2016-02-04 00:01:15 +02:00
parent fd418576c0
commit 22154c2bad

View File

@ -25,8 +25,8 @@ static const uint8_t default_regs[][2] = {
{COM3, COM3_SWAP_YUV}, {COM3, COM3_SWAP_YUV},
{COM7, COM7_RES_VGA | COM7_FMT_RGB565 | COM7_FMT_RGB}, {COM7, COM7_RES_VGA | COM7_FMT_RGB565 | COM7_FMT_RGB},
{COM4, 0x81}, /* PLL */ {COM4, 0xC1}, /* PLL */
{CLKRC, 0x01}, {CLKRC, 0x00},
// VGA Window Size // VGA Window Size
{HSTART, 0x23}, {HSTART, 0x23},