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Merge pull request #2767 from openmv/clean_up_align
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misc: Add common alignment macros.
This commit is contained in:
commit
25f9dc1e12
@ -39,14 +39,14 @@ static uint32_t alloc_bytes_peak;
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#endif
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#if defined(OMV_FB_OVERLAY_MEMORY)
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#define FB_OVERLAY_MEMORY_FLAG 0x1
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#define FB_OVERLAY_MEMORY_FLAG 0x1
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extern char _fballoc_overlay_end, _fballoc_overlay_start;
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static char *pointer_overlay = &_fballoc_overlay_end;
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#endif
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// fb_alloc_free_till_mark() will not free past this.
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// Use fb_alloc_free_till_mark_permanent() instead.
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#define FB_PERMANENT_FLAG 0x2
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#define FB_PERMANENT_FLAG 0x2
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char *fb_alloc_stack_pointer() {
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return pointer;
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@ -146,7 +146,7 @@ void *fb_alloc(uint32_t size, int hints) {
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size = ((size + sizeof(uint32_t) - 1) / sizeof(uint32_t)) * sizeof(uint32_t); // Round Up
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if (hints & FB_ALLOC_CACHE_ALIGN) {
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size = ((size + OMV_ALLOC_ALIGNMENT - 1) / OMV_ALLOC_ALIGNMENT) * OMV_ALLOC_ALIGNMENT;
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size = OMV_ALIGN_TO(size, OMV_ALLOC_ALIGNMENT);
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size += OMV_ALLOC_ALIGNMENT - sizeof(uint32_t);
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}
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@ -30,6 +30,11 @@
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#define FB_ALLOC_PREFER_SPEED 1
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#define FB_ALLOC_PREFER_SIZE 2
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#define FB_ALLOC_CACHE_ALIGN 4
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#ifndef OMV_ALLOC_ALIGNMENT
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#define OMV_ALLOC_ALIGNMENT (OMV_CACHE_LINE_SIZE)
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#endif
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char *fb_alloc_stack_pointer();
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void fb_alloc_fail();
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void fb_alloc_init0();
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@ -26,20 +26,25 @@
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#ifndef __OMV_COMMON_H__
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#define __OMV_COMMON_H__
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#define OMV_ATTR_ALIGNED(x, a) x __attribute__((aligned(a)))
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#define OMV_ATTR_SECTION(x, s) x __attribute__((section(s)))
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#define OMV_ATTR_ALWAYS_INLINE inline __attribute__((always_inline))
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#define OMV_ATTR_OPTIMIZE(o) __attribute__((optimize(o)))
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#define OMV_BREAK() __asm__ volatile ("BKPT")
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#define OMV_ATTR_ALIGNED(x, a) x __attribute__((aligned(a)))
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#define OMV_ATTR_SECTION(x, s) x __attribute__((section(s)))
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#define OMV_ATTR_ALWAYS_INLINE inline __attribute__((always_inline))
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#define OMV_ATTR_OPTIMIZE(o) __attribute__((optimize(o)))
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#define OMV_ATTR_SEC_ALIGN(x, s, a) x __attribute__((section(s), aligned(a)))
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#define OMV_DEBUG_BREAKPOINT() __asm__ volatile ("BKPT")
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// Use 32-byte alignment on MCUs with no cache for DMA buffer alignment.
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#ifndef __DCACHE_PRESENT
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#define OMV_ALLOC_ALIGNMENT (32)
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#define OMV_CACHE_LINE_SIZE (32)
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#else
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#define OMV_ALLOC_ALIGNMENT (__SCB_DCACHE_LINE_SIZE)
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#define OMV_CACHE_LINE_SIZE (__SCB_DCACHE_LINE_SIZE)
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#endif
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#define OMV_ATTR_ALIGNED_DMA(x) OMV_ATTR_ALIGNED(x, OMV_ALLOC_ALIGNMENT)
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#ifndef OMV_DMA_ALIGNMENT
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#define OMV_DMA_ALIGNMENT (OMV_CACHE_LINE_SIZE)
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#endif
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#define OMV_ALIGN_TO(x, alignment) \
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((((uintptr_t)(x)) + (alignment) - 1) & ~((uintptr_t)((alignment) - 1)))
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#ifdef OMV_DEBUG_PRINTF
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#define debug_printf(fmt, ...) \
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@ -68,7 +68,7 @@ typedef struct _vospi_state {
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static vospi_state_t vospi;
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static uint16_t OMV_ATTR_SECTION(OMV_ATTR_ALIGNED_DMA(vospi_buf[VOSPI_BUFFER_SIZE]), OMV_VOSPI_DMA_BUFFER);
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static uint16_t OMV_ATTR_SEC_ALIGN(vospi_buf[VOSPI_BUFFER_SIZE], OMV_VOSPI_DMA_BUFFER, OMV_DMA_ALIGNMENT);
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static void vospi_callback(omv_spi_t *spi, void *userdata, void *buf);
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static void vospi_resync() {
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@ -241,12 +241,12 @@ void rectangle_united(rectangle_t *dst, rectangle_t *src) {
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/////////////////
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void image_alloc(image_t *img, size_t size) {
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// Round the size up to ensure that the allocation is a multiple of the alignment in bytes.
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// This ensures after address alignment that the data can be modified without affecting other cache lines.
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size = ((size + OMV_ALLOC_ALIGNMENT - 1) / OMV_ALLOC_ALIGNMENT) * OMV_ALLOC_ALIGNMENT;
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img->_raw = m_malloc(size + OMV_ALLOC_ALIGNMENT - 1);
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// Offset the data pointer to ensure it is aligned.
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img->data = (void *) (((uintptr_t) img->_raw + OMV_ALLOC_ALIGNMENT - 1) & ~(OMV_ALLOC_ALIGNMENT - 1));
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// Align the memory size to cache line.
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size = OMV_ALIGN_TO(size, OMV_CACHE_LINE_SIZE);
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// Allocate extra to align the pointer.
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img->_raw = m_malloc(size + OMV_CACHE_LINE_SIZE - 1);
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// Align the memory address to cache line.
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img->data = (void *) OMV_ALIGN_TO(img->_raw, OMV_CACHE_LINE_SIZE);
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}
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void image_alloc0(image_t *img, size_t size) {
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@ -33,6 +33,7 @@
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#include <string.h>
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#include <stdint.h>
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#include "imlib_config.h"
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#include "omv_common.h"
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#include STM32_HAL_H
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#include "py/runtime.h"
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@ -48,8 +49,7 @@
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#include "ll_aton_caches_interface.h"
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#include "ll_aton_reloc_network.h"
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#define AI_RELOC_ALIGNMENT (32 - 1)
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#define AI_RELOC_ALIGN(x) (((x) + (AI_RELOC_ALIGNMENT)) & ~(AI_RELOC_ALIGNMENT))
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#define AI_RELOC_ALIGNMENT (32)
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typedef struct ml_backend_state {
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void *exec_ram_addr;
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@ -133,19 +133,19 @@ int ml_backend_init_model(py_ml_model_obj_t *model) {
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}
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// Allocate executable memory.
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state->exec_ram_size = AI_RELOC_ALIGN(rt.rt_ram_xip);
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state->exec_ram_size = OMV_ALIGN_TO(rt.rt_ram_xip, AI_RELOC_ALIGNMENT);
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state->exec_ram_addr = m_new(uint8_t, state->exec_ram_size + AI_RELOC_ALIGNMENT);
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// Allocate external memory.
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state->ext_ram_size = AI_RELOC_ALIGN(rt.ext_ram_sz);
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state->ext_ram_size = OMV_ALIGN_TO(rt.ext_ram_sz, AI_RELOC_ALIGNMENT);
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state->ext_ram_addr = m_new(uint8_t, state->ext_ram_size + AI_RELOC_ALIGNMENT);
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// Create and install the relocatable model.
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ll_aton_reloc_config config = {
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.ext_ram_size = state->ext_ram_size,
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.ext_ram_addr = AI_RELOC_ALIGN((uintptr_t) state->ext_ram_addr),
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.ext_ram_addr = OMV_ALIGN_TO(state->ext_ram_addr, AI_RELOC_ALIGNMENT),
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.exec_ram_size = state->exec_ram_size,
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.exec_ram_addr = AI_RELOC_ALIGN((uintptr_t) state->exec_ram_addr),
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.exec_ram_addr = OMV_ALIGN_TO(state->exec_ram_addr, AI_RELOC_ALIGNMENT),
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.ext_param_addr = (uintptr_t) NULL,
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// For COPY mode - XIP region is expected, else only RW region is requested.
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// In the case where the HW epoch blob is embedded in the binary image, this
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@ -35,6 +35,8 @@
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#include <stdint.h>
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#include "imlib_config.h"
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#include "omv_common.h"
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#include "tensorflow/lite/micro/micro_op_resolver.h"
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#include "tensorflow/lite/micro/micro_mutable_op_resolver.h"
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#include "tensorflow/lite/micro/cortex_m_generic/debug_log_callback.h"
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@ -52,8 +54,7 @@ extern "C" {
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using namespace tflite;
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#define TF_ARENA_EXTRA (512)
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#define TF_ARENA_ALIGN (16 - 1)
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#define TF_ARENA_ROUND(x) (((x) + TF_ARENA_ALIGN) & ~(TF_ARENA_ALIGN))
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#define TF_ARENA_ALIGN (16)
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typedef MicroMutableOpResolver<113> MicroOpsResolver;
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typedef struct ml_backend_state {
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@ -238,7 +239,7 @@ int ml_backend_init_model(py_ml_model_obj_t *model) {
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mp_raise_msg(&mp_type_ValueError, MP_ERROR_TEXT("Failed to allocate tensors"));
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}
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// Round up the optimal arena size to a multiple of the alignment.
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arena_size = TF_ARENA_ROUND(interpreter.arena_used_bytes()) + TF_ARENA_EXTRA;
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arena_size = OMV_ALIGN_TO(interpreter.arena_used_bytes(), TF_ARENA_ALIGN) + TF_ARENA_EXTRA;
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m_free(arena_memory);
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// Allocate the persistent model state and interpreter.
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@ -81,7 +81,7 @@ static soft_timer_entry_t flir_lepton_spi_rx_timer = {};
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static int fir_lepton_spi_rx_cb_tail = 0;
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static int fir_lepton_spi_rx_cb_expected_pid = 0;
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static int fir_lepton_spi_rx_cb_expected_sid = 0;
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static uint16_t OMV_ATTR_SECTION(OMV_ATTR_ALIGNED_DMA(fir_lepton_buf[VOSPI_BUFFER_SIZE]), OMV_VOSPI_DMA_BUFFER);
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static uint16_t OMV_ATTR_SEC_ALIGN(fir_lepton_buf[VOSPI_BUFFER_SIZE], OMV_VOSPI_DMA_BUFFER, OMV_DMA_ALIGNMENT);
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static void fir_lepton_spi_callback(omv_spi_t *spi, void *userdata, void *buf);
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static mp_obj_t fir_lepton_spi_resync_callback(mp_obj_t unused) {
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@ -56,20 +56,12 @@
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#define RGB565_FIXED_VER 11
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#define NEW_PIXFORMAT_VER 20
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#ifndef __DCACHE_PRESENT
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#define IMAGE_ALIGNMENT 32 // Use 32-byte alignment on MCUs with no cache for DMA buffer alignment.
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#else
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#define IMAGE_ALIGNMENT __SCB_DCACHE_LINE_SIZE
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#endif
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#define IMAGE_ALIGNMENT OMV_CACHE_LINE_SIZE
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#define IMAGE_T_SIZE_ALIGNED (((sizeof(uint32_t) + sizeof(image_t) + (IMAGE_ALIGNMENT) -1) \
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/ (IMAGE_ALIGNMENT)) \
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* (IMAGE_ALIGNMENT))
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static size_t image_size_aligned(image_t *image) {
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return ((image_size(image) + (IMAGE_ALIGNMENT) -1) / (IMAGE_ALIGNMENT)) * (IMAGE_ALIGNMENT);
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}
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typedef enum image_io_stream_type {
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IMAGE_IO_FILE_STREAM,
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IMAGE_IO_MEMORY_STREAM,
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@ -579,7 +571,7 @@ static mp_obj_t py_imageio_make_new(const mp_obj_type_t *type, size_t n_args, si
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}
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stream->count = mp_obj_get_int(args[1]);
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stream->size = IMAGE_T_SIZE_ALIGNED + image_size_aligned(&image);
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stream->size = IMAGE_T_SIZE_ALIGNED + OMV_ALIGN_TO(image_size(&image), IMAGE_ALIGNMENT);
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fb_alloc_mark();
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stream->buffer = fb_alloc(stream->count * stream->size, FB_ALLOC_PREFER_SIZE | FB_ALLOC_CACHE_ALIGN);
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@ -51,13 +51,7 @@
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#include "py_ml.h"
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#include "ulab/code/ndarray.h"
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#ifndef IMLIB_ML_MODEL_ALIGN
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#ifndef __DCACHE_PRESENT
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#define IMLIB_ML_MODEL_ALIGN (32 - 1)
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#else
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#define IMLIB_ML_MODEL_ALIGN (__SCB_DCACHE_LINE_SIZE - 1)
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#endif
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#endif
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#define IMLIB_ML_MODEL_ALIGN (OMV_CACHE_LINE_SIZE)
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static size_t py_ml_tuple_sum(mp_obj_tuple_t *o) {
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if (o->len < 1) {
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@ -372,9 +366,9 @@ mp_obj_t py_ml_model_make_new(const mp_obj_type_t *type, size_t n_args, size_t n
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fb_alloc_mark_permanent();
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} else {
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// Align size and memory and keep a reference to the GC block.
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size_t size = (model->size + IMLIB_ML_MODEL_ALIGN) & ~IMLIB_ML_MODEL_ALIGN;
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model->_raw = m_malloc(size + IMLIB_ML_MODEL_ALIGN);
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model->data = (void *) (((uintptr_t) model->_raw + IMLIB_ML_MODEL_ALIGN) & ~IMLIB_ML_MODEL_ALIGN);
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size_t size = OMV_ALIGN_TO(model->size, IMLIB_ML_MODEL_ALIGN);
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model->_raw = m_malloc(size + IMLIB_ML_MODEL_ALIGN - 1);
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model->data = (void *) OMV_ALIGN_TO(model->_raw, IMLIB_ML_MODEL_ALIGN);
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}
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// Read file data.
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@ -52,7 +52,7 @@ static PDM_Filter_Config_t PDM_FilterConfig[OMV_AUDIO_MAX_CHANNELS];
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static PDM_Filter_Handler_t PDM_FilterHandler[OMV_AUDIO_MAX_CHANNELS];
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// NOTE: BDMA can only access D3 SRAM4 memory.
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#define PDM_BUFFER_SIZE (16384)
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uint8_t OMV_ATTR_SECTION(OMV_ATTR_ALIGNED(PDM_BUFFER[PDM_BUFFER_SIZE], 32), ".d3_dma_buffer");
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uint8_t OMV_ATTR_SEC_ALIGN(PDM_BUFFER[PDM_BUFFER_SIZE], ".d3_dma_buffer", OMV_DMA_ALIGNMENT);
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#elif defined(OMV_DFSDM)
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static DFSDM_Channel_HandleTypeDef hdfsdm;
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@ -63,7 +63,7 @@ static DMA_HandleTypeDef hdma_filter[OMV_AUDIO_MAX_CHANNELS];
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// NOTE: placed in D2 memory.
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#define PDM_BUFFER_SIZE (512 * 2)
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int32_t OMV_ATTR_SECTION(OMV_ATTR_ALIGNED(PDM_BUFFER[PDM_BUFFER_SIZE], 32), ".d2_dma_buffer");
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int32_t OMV_ATTR_SEC_ALIGN(PDM_BUFFER[PDM_BUFFER_SIZE], ".d2_dma_buffer", OMV_DMA_ALIGNMENT);
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#define DFSDM_GAIN_FRAC_BITS (3)
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static int32_t dfsdm_gain = 1;
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@ -74,11 +74,11 @@ static MDF_FilterConfigTypeDef hmdf_filter[OMV_AUDIO_MAX_CHANNELS];
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// NOTE: Only 1 filter is supported right now.
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static DMA_QListTypeDef dma_queue;
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static DMA_NodeTypeDef OMV_ATTR_SECTION(OMV_ATTR_ALIGNED(dma_nodes, 32), ".dma_buffer");
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static DMA_NodeTypeDef OMV_ATTR_SEC_ALIGN(dma_nodes, ".dma_buffer", OMV_DMA_ALIGNMENT);
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static DMA_HandleTypeDef hdma_filter[OMV_AUDIO_MAX_CHANNELS];
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#define PDM_BUFFER_SIZE (512 * 2)
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int32_t OMV_ATTR_SECTION(OMV_ATTR_ALIGNED(PDM_BUFFER[PDM_BUFFER_SIZE], 32), ".dma_buffer");
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int32_t OMV_ATTR_SEC_ALIGN(PDM_BUFFER[PDM_BUFFER_SIZE], ".dma_buffer", OMV_DMA_ALIGNMENT);
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#else
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#error "No audio driver defined for this board"
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#endif
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@ -148,7 +148,7 @@ void nema_host_free(void *ptr) {
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}
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void *nema_host_malloc(unsigned size) {
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return aligned_alloc(__SCB_DCACHE_LINE_SIZE, (size + (__SCB_DCACHE_LINE_SIZE - 1)) & ~(__SCB_DCACHE_LINE_SIZE - 1));
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return aligned_alloc(OMV_CACHE_LINE_SIZE, OMV_ALIGN_TO(size, OMV_CACHE_LINE_SIZE));
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}
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int nema_mutex_lock(int mutex_id) {
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