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synced 2025-11-04 14:49:50 +08:00
Massively reduces bus usage for SPI LCD
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parent
067fd87498
commit
2ac0480e99
@ -184,16 +184,48 @@ static void spi_config_init(int w, int h, int refresh_rate, bool triple_buffer,
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framebuffer_tail = 0;
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for (int i = 0; i < FRAMEBUFFER_COUNT; i++) {
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framebuffers[i] = (uint16_t *) fb_alloc0(w * h * sizeof(uint16_t), FB_ALLOC_NO_HINT);
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framebuffers[i] = (uint16_t *) fb_alloc0(w * h * sizeof(uint16_t), FB_ALLOC_NO_HINT | FB_ALLOC_CACHE_ALIGN);
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}
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dma_init(&spi_tx_dma, OMV_SPI_LCD_CONTROLLER->tx_dma_descr, DMA_MEMORY_TO_PERIPH, OMV_SPI_LCD_CONTROLLER->spi);
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OMV_SPI_LCD_CONTROLLER->spi->hdmatx = &spi_tx_dma;
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OMV_SPI_LCD_CONTROLLER->spi->hdmarx = NULL;
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#if defined(MCU_SERIES_H7)
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spi_tx_dma.Init.PeriphDataAlignment = DMA_PDATAALIGN_WORD;
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#else
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spi_tx_dma.Init.PeriphDataAlignment = DMA_PDATAALIGN_HALFWORD;
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spi_tx_dma.Init.MemDataAlignment = DMA_MDATAALIGN_HALFWORD;
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((DMA_Stream_TypeDef *) spi_tx_dma.Instance)->CR = (((DMA_Stream_TypeDef *) spi_tx_dma.Instance)->CR & ~DMA_SxCR_PSIZE_Msk) | DMA_PDATAALIGN_HALFWORD;
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((DMA_Stream_TypeDef *) spi_tx_dma.Instance)->CR = (((DMA_Stream_TypeDef *) spi_tx_dma.Instance)->CR & ~DMA_SxCR_MSIZE_Msk) | DMA_MDATAALIGN_HALFWORD;
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#endif
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spi_tx_dma.Init.MemDataAlignment = DMA_MDATAALIGN_WORD;
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spi_tx_dma.Init.FIFOMode = DMA_FIFOMODE_ENABLE;
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spi_tx_dma.Init.FIFOThreshold = DMA_FIFO_THRESHOLD_FULL;
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spi_tx_dma.Init.MemBurst = DMA_MBURST_INC4;
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#if defined(MCU_SERIES_H7)
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spi_tx_dma.Init.PeriphBurst = DMA_PBURST_INC4;
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#else
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spi_tx_dma.Init.PeriphBurst = DMA_PBURST_SINGLE;
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#endif
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#if defined(MCU_SERIES_H7)
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((DMA_Stream_TypeDef *) spi_tx_dma.Instance)->CR =
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(((DMA_Stream_TypeDef *) spi_tx_dma.Instance)->CR & ~DMA_SxCR_PSIZE_Msk) | DMA_PDATAALIGN_WORD;
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#else
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((DMA_Stream_TypeDef *) spi_tx_dma.Instance)->CR =
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(((DMA_Stream_TypeDef *) spi_tx_dma.Instance)->CR & ~DMA_SxCR_PSIZE_Msk) | DMA_PDATAALIGN_HALFWORD;
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#endif
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((DMA_Stream_TypeDef *) spi_tx_dma.Instance)->CR =
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(((DMA_Stream_TypeDef *) spi_tx_dma.Instance)->CR & ~DMA_SxCR_MSIZE_Msk) | DMA_MDATAALIGN_WORD;
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((DMA_Stream_TypeDef *) spi_tx_dma.Instance)->FCR =
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(((DMA_Stream_TypeDef *) spi_tx_dma.Instance)->FCR & ~DMA_SxFCR_DMDIS_Msk) | DMA_FIFOMODE_ENABLE;
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((DMA_Stream_TypeDef *) spi_tx_dma.Instance)->FCR =
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(((DMA_Stream_TypeDef *) spi_tx_dma.Instance)->FCR & ~DMA_SxFCR_FTH_Msk) | DMA_FIFO_THRESHOLD_FULL;
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((DMA_Stream_TypeDef *) spi_tx_dma.Instance)->CR =
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(((DMA_Stream_TypeDef *) spi_tx_dma.Instance)->CR & ~DMA_SxCR_MBURST_Msk) | DMA_MBURST_INC4;
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#if defined(MCU_SERIES_H7)
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((DMA_Stream_TypeDef *) spi_tx_dma.Instance)->CR =
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(((DMA_Stream_TypeDef *) spi_tx_dma.Instance)->CR & ~DMA_SxCR_PBURST_Msk) | DMA_PBURST_INC4;
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#else
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((DMA_Stream_TypeDef *) spi_tx_dma.Instance)->CR =
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(((DMA_Stream_TypeDef *) spi_tx_dma.Instance)->CR & ~DMA_SxCR_PBURST_Msk) | DMA_PBURST_SINGLE;
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#endif
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fb_alloc_mark_permanent();
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}
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}
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@ -251,11 +283,16 @@ static void spi_lcd_callback(SPI_HandleTypeDef *hspi)
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spi_tx_cb_state_memory_write_first = false;
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OMV_SPI_LCD_CONTROLLER->spi->Init.DataSize = SPI_DATASIZE_16BIT;
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#if defined(MCU_SERIES_H7)
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OMV_SPI_LCD_CONTROLLER->spi->Instance->CFG1 = (OMV_SPI_LCD_CONTROLLER->spi->Instance->CFG1 & ~SPI_CFG1_DSIZE_Msk) | SPI_DATASIZE_16BIT;
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OMV_SPI_LCD_CONTROLLER->spi->Instance->CFG1 =
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(OMV_SPI_LCD_CONTROLLER->spi->Instance->CFG1 & ~SPI_CFG1_DSIZE_Msk) | SPI_DATASIZE_16BIT;
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OMV_SPI_LCD_CONTROLLER->spi->Instance->CFG1 =
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(OMV_SPI_LCD_CONTROLLER->spi->Instance->CFG1 & ~SPI_CFG1_FTHLV_Msk) | SPI_FIFO_THRESHOLD_08DATA;
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#elif defined(MCU_SERIES_F7)
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OMV_SPI_LCD_CONTROLLER->spi->Instance->CR2 = (OMV_SPI_LCD_CONTROLLER->spi->Instance->CR2 & ~SPI_CR2_DS_Msk) | SPI_DATASIZE_16BIT;
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OMV_SPI_LCD_CONTROLLER->spi->Instance->CR2 =
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(OMV_SPI_LCD_CONTROLLER->spi->Instance->CR2 & ~SPI_CR2_DS_Msk) | SPI_DATASIZE_16BIT;
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#elif defined(MCU_SERIES_F4)
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OMV_SPI_LCD_CONTROLLER->spi->Instance->CR1 = (OMV_SPI_LCD_CONTROLLER->spi->Instance->CR1 & ~SPI_CR1_DFF_Msk) | SPI_DATASIZE_16BIT;
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OMV_SPI_LCD_CONTROLLER->spi->Instance->CR1 =
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(OMV_SPI_LCD_CONTROLLER->spi->Instance->CR1 & ~SPI_CR1_DFF_Msk) | SPI_DATASIZE_16BIT;
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#endif
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OMV_SPI_LCD_CS_LOW();
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}
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@ -268,11 +305,16 @@ static void spi_lcd_callback(SPI_HandleTypeDef *hspi)
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spi_tx_cb_state = SPI_TX_CB_MEMORY_WRITE_CMD;
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OMV_SPI_LCD_CONTROLLER->spi->Init.DataSize = SPI_DATASIZE_8BIT;
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#if defined(MCU_SERIES_H7)
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OMV_SPI_LCD_CONTROLLER->spi->Instance->CFG1 = (OMV_SPI_LCD_CONTROLLER->spi->Instance->CFG1 & ~SPI_CFG1_DSIZE_Msk) | SPI_DATASIZE_8BIT;
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OMV_SPI_LCD_CONTROLLER->spi->Instance->CFG1 =
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(OMV_SPI_LCD_CONTROLLER->spi->Instance->CFG1 & ~SPI_CFG1_DSIZE_Msk) | SPI_DATASIZE_8BIT;
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OMV_SPI_LCD_CONTROLLER->spi->Instance->CFG1 =
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(OMV_SPI_LCD_CONTROLLER->spi->Instance->CFG1 & ~SPI_CFG1_FTHLV_Msk) | SPI_FIFO_THRESHOLD_01DATA;
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#elif defined(MCU_SERIES_F7)
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OMV_SPI_LCD_CONTROLLER->spi->Instance->CR2 = (OMV_SPI_LCD_CONTROLLER->spi->Instance->CR2 & ~SPI_CR2_DS_Msk) | SPI_DATASIZE_8BIT;
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OMV_SPI_LCD_CONTROLLER->spi->Instance->CR2 =
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(OMV_SPI_LCD_CONTROLLER->spi->Instance->CR2 & ~SPI_CR2_DS_Msk) | SPI_DATASIZE_8BIT;
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#elif defined(MCU_SERIES_F4)
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OMV_SPI_LCD_CONTROLLER->spi->Instance->CR1 = (OMV_SPI_LCD_CONTROLLER->spi->Instance->CR1 & ~SPI_CR1_DFF_Msk) | SPI_DATASIZE_8BIT;
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OMV_SPI_LCD_CONTROLLER->spi->Instance->CR1 =
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(OMV_SPI_LCD_CONTROLLER->spi->Instance->CR1 & ~SPI_CR1_DFF_Msk) | SPI_DATASIZE_8BIT;
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#endif
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OMV_SPI_LCD_CS_LOW();
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HAL_SPI_Transmit_IT(OMV_SPI_LCD_CONTROLLER->spi, (uint8_t *) display_on, sizeof(display_on));
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@ -899,7 +941,7 @@ static void ltdc_config_init(int frame_size, int refresh_rate)
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framebuffer_tail = 0;
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for (int i = 0; i < FRAMEBUFFER_COUNT; i++) {
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framebuffers[i] = (uint16_t *) fb_alloc0(w * h * sizeof(uint16_t), FB_ALLOC_NO_HINT);
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framebuffers[i] = (uint16_t *) fb_alloc0(w * h * sizeof(uint16_t), FB_ALLOC_NO_HINT | FB_ALLOC_CACHE_ALIGN);
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ltdc_framebuffer_layers[i].WindowX0 = 0;
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ltdc_framebuffer_layers[i].WindowX1 = w;
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ltdc_framebuffer_layers[i].WindowY0 = 0;
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