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Merge pull request #2526 from kwagyeman/kwabena/fix_vospi_phase
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common/vospi: Set vospi bus CPOL=1 and CPHA=1.
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commit
33eb5f9f14
@ -187,7 +187,6 @@
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// FIR Lepton
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#define OMV_FIR_LEPTON_I2C_BUS (OMV_FIR_I2C_ID)
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#define OMV_FIR_LEPTON_I2C_BUS_SPEED (OMV_FIR_I2C_SPEED)
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#define OMV_FIR_LEPTON_RX_CLK_DIV (8)
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#define OMV_FIR_LEPTON_SPI_BUS (OMV_SPI3_ID)
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#define OMV_FIR_LEPTON_MOSI_PIN (&omv_pin_LPSPI3_MOSI)
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@ -179,6 +179,8 @@ int vospi_init(uint32_t n_packets, void *buffer) {
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spi_config.bus_mode = OMV_SPI_BUS_RX;
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spi_config.datasize = 16;
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spi_config.baudrate = VOSPI_CLOCK_SPEED;
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spi_config.clk_pol = OMV_SPI_CPOL_HIGH;
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spi_config.clk_pha = OMV_SPI_CPHA_2EDGE;
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spi_config.dma_flags = OMV_SPI_DMA_CIRCULAR | OMV_SPI_DMA_DOUBLE;
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if (omv_spi_init(&vospi.spi_bus, &spi_config) != 0) {
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@ -254,15 +254,13 @@ int fir_lepton_init(omv_i2c_t *bus, int *w, int *h, int *refresh, int *resolutio
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omv_spi_config_t spi_config;
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omv_spi_default_config(&spi_config, OMV_FIR_LEPTON_SPI_BUS);
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#if OMV_FIR_LEPTON_RX_CLK_DIV
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spi_config.baudrate = VOSPI_CLOCK_SPEED / OMV_FIR_LEPTON_RX_CLK_DIV;
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#else
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spi_config.baudrate = VOSPI_CLOCK_SPEED;
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#endif
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spi_config.datasize = 16;
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spi_config.bus_mode = OMV_SPI_BUS_RX;
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spi_config.nss_enable = false;
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spi_config.clk_pol = OMV_SPI_CPOL_HIGH;
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spi_config.clk_pha = OMV_SPI_CPHA_2EDGE;
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spi_config.dma_flags = OMV_SPI_DMA_CIRCULAR | OMV_SPI_DMA_DOUBLE;
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omv_spi_init(&spi_bus, &spi_config);
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@ -114,8 +114,8 @@ typedef LPI2C_Type *omv_i2c_dev_t;
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#define OMV_SPI_BUS_RX (1 << 1)
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#define OMV_SPI_BUS_TX_RX (OMV_SPI_BUS_TX | OMV_SPI_BUS_RX)
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#define OMV_SPI_CPOL_LOW (kLPSPI_ClockPolarityActiveLow)
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#define OMV_SPI_CPOL_HIGH (kLPSPI_ClockPolarityActiveHigh)
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#define OMV_SPI_CPOL_LOW (kLPSPI_ClockPolarityActiveHigh)
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#define OMV_SPI_CPOL_HIGH (kLPSPI_ClockPolarityActiveLow)
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#define OMV_SPI_CPHA_1EDGE (kLPSPI_ClockPhaseFirstEdge)
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#define OMV_SPI_CPHA_2EDGE (kLPSPI_ClockPhaseSecondEdge)
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@ -313,7 +313,7 @@ int omv_spi_default_config(omv_spi_config_t *config, uint32_t bus_id) {
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config->spi_mode = OMV_SPI_MODE_MASTER;
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config->bus_mode = OMV_SPI_BUS_TX_RX;
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config->bit_order = OMV_SPI_MSB_FIRST;
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config->clk_pol = OMV_SPI_CPOL_HIGH;
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config->clk_pol = OMV_SPI_CPOL_LOW;
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config->clk_pha = OMV_SPI_CPHA_1EDGE;
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config->nss_pol = OMV_SPI_NSS_LOW;
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config->nss_enable = true;
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