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Merge F7 SRAM1 and SRAM2.
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@ -62,9 +62,7 @@
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#define OMV_CCM_ORIGIN 0x20000000
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#define OMV_CCM_LENGTH 128K // Note DTCM/ITCM memory is not cacheable on M7
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#define OMV_SRAM1_ORIGIN 0x20020000
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#define OMV_SRAM1_LENGTH 368K
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#define OMV_SRAM2_ORIGIN 0x2007C000
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#define OMV_SRAM2_LENGTH 16K
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#define OMV_SRAM1_LENGTH 384K
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/* SCCB/I2C */
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#define SCCB_I2C (I2C1)
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