mirror of
https://github.com/openmv/openmv.git
synced 2025-09-26 23:09:13 +08:00
boards/all: Switch to new protocol.
Signed-off-by: iabdalkader <i.abdalkader@gmail.com>
This commit is contained in:
parent
d5c1bd59c9
commit
35d0d6c363
@ -74,6 +74,11 @@
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#define OMV_USB_IRQN (OTG_FS_IRQn)
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#define OMV_USB_IRQN (OTG_FS_IRQn)
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#define OMV_USB_ULPI (0)
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#define OMV_USB_ULPI (0)
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// OpenMV protocol configuration.
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#define OMV_PROTOCOL_MAX_BUFFER_SIZE (4096)
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#define OMV_PROTOCOL_HW_CAPS OMV_PROTOCOL_HW_CAPS_MAKE( \
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HAS_JPEG, HAS_DRAM, HAS_CRC, HAS_WIFI, HAS_BT, HAS_SD, HAS_ETH, HAS_USB_HS)
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// PLL1 480MHz/48MHz SDMMC and FDCAN
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// PLL1 480MHz/48MHz SDMMC and FDCAN
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// USB and RNG are clocked from the HSI48
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// USB and RNG are clocked from the HSI48
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#define OMV_OSC_PLL1M (4)
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#define OMV_OSC_PLL1M (4)
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@ -138,7 +143,7 @@
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#define OMV_FB_SIZE (3M) // FB memory: header + VGA/GS image
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#define OMV_FB_SIZE (3M) // FB memory: header + VGA/GS image
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#define OMV_FB_ALLOC_SIZE (1M) // minimum fb alloc size
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#define OMV_FB_ALLOC_SIZE (1M) // minimum fb alloc size
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#define OMV_FB_OVERLAY_MEMORY SRAM0 // Fast fb_alloc memory.
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#define OMV_FB_OVERLAY_MEMORY SRAM0 // Fast fb_alloc memory.
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#define OMV_FB_OVERLAY_SIZE (448K) // Fast fb_alloc memory size.
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#define OMV_FB_OVERLAY_SIZE (443K) // Fast fb_alloc memory size.
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#define OMV_SB_MEMORY DRAM // Streaming buffer memory.
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#define OMV_SB_MEMORY DRAM // Streaming buffer memory.
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#define OMV_SB_SIZE (1M) // Streaming buffer size.
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#define OMV_SB_SIZE (1M) // Streaming buffer size.
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#define OMV_DMA_MEMORY SRAM3 // Misc DMA buffers memory.
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#define OMV_DMA_MEMORY SRAM3 // Misc DMA buffers memory.
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@ -13,6 +13,7 @@ OMV_BOARD_CFLAGS = -DCORE_CM7 \
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-DCYW43_BT_FIRMWARE_ADDRESS=0x90FC0000 \
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-DCYW43_BT_FIRMWARE_ADDRESS=0x90FC0000 \
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-DCYW43_BT_FIRMWARE_INCLUDE_FILE="\"$(TOP_DIR)/$(CYW4343_FW_DIR)/cyw4343_btfw.h\""
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-DCYW43_BT_FIRMWARE_INCLUDE_FILE="\"$(TOP_DIR)/$(CYW4343_FW_DIR)/cyw4343_btfw.h\""
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OMV_ENABLE_BL=0
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OMV_ENABLE_BL=0
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OMV_USB_STACK_STMUSB=1
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MICROPY_PY_CSI = 1
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MICROPY_PY_CSI = 1
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MICROPY_PY_CSI_NG = 1
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MICROPY_PY_CSI_NG = 1
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MICROPY_PY_FIR = 1
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MICROPY_PY_FIR = 1
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@ -50,10 +50,6 @@
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#define OMV_FIR_MLX90641_ENABLE (1)
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#define OMV_FIR_MLX90641_ENABLE (1)
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#define OMV_FIR_AMG8833_ENABLE (1)
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#define OMV_FIR_AMG8833_ENABLE (1)
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// Debugging configuration.
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#define OMV_TUSBDBG_ENABLE (1)
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#define OMV_TUSBDBG_BUFFER (512)
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// UMM heap block size
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// UMM heap block size
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#define OMV_UMM_BLOCK_SIZE 16
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#define OMV_UMM_BLOCK_SIZE 16
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@ -49,10 +49,6 @@ extern unsigned char *OMV_BOARD_UID_ADDR; // Unique address.
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// FIR drivers configuration.
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// FIR drivers configuration.
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#define OMV_FIR_AMG8833_ENABLE (1)
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#define OMV_FIR_AMG8833_ENABLE (1)
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// Debugging configuration.
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#define OMV_TUSBDBG_ENABLE (1)
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#define OMV_TUSBDBG_BUFFER (2048)
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// UMM heap block size
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// UMM heap block size
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#define OMV_UMM_BLOCK_SIZE 16
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#define OMV_UMM_BLOCK_SIZE 16
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@ -61,6 +61,11 @@
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#define OMV_USB_ULPI_STP_PIN (&omv_pin_C0_OTG_HS)
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#define OMV_USB_ULPI_STP_PIN (&omv_pin_C0_OTG_HS)
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#define OMV_USB_ULPI_DIR_PIN (&omv_pin_C2_OTG_HS)
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#define OMV_USB_ULPI_DIR_PIN (&omv_pin_C2_OTG_HS)
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// OpenMV protocol configuration.
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#define OMV_PROTOCOL_MAX_BUFFER_SIZE (4096)
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#define OMV_PROTOCOL_HW_CAPS OMV_PROTOCOL_HW_CAPS_MAKE( \
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HAS_JPEG, HAS_DRAM, HAS_CRC, HAS_WIFI, HAS_BT, HAS_SD, HAS_ETH, HAS_USB_HS)
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// Defined for cpu frequency scaling to override the revid.
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// Defined for cpu frequency scaling to override the revid.
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#define OMV_MAX_CPU_FREQ (400)
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#define OMV_MAX_CPU_FREQ (400)
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@ -131,7 +136,7 @@
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#define OMV_CM4_BOOT_MEMORY SRAM4 // Use to boot CM4 for low-power mode.
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#define OMV_CM4_BOOT_MEMORY SRAM4 // Use to boot CM4 for low-power mode.
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#define OMV_CM4_BOOT_SIZE 1K
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#define OMV_CM4_BOOT_SIZE 1K
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#define OMV_GC_BLOCK0_MEMORY DTCM // Main GC block 0.
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#define OMV_GC_BLOCK0_MEMORY DTCM // Main GC block 0.
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#define OMV_GC_BLOCK0_SIZE (32K)
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#define OMV_GC_BLOCK0_SIZE (31K)
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#define OMV_GC_BLOCK1_MEMORY SRAM4 // Extra GC block 1.
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#define OMV_GC_BLOCK1_MEMORY SRAM4 // Extra GC block 1.
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#define OMV_GC_BLOCK1_SIZE (63K)
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#define OMV_GC_BLOCK1_SIZE (63K)
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#define OMV_GC_BLOCK2_MEMORY SRAM1 // Extra GC block 2.
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#define OMV_GC_BLOCK2_MEMORY SRAM1 // Extra GC block 2.
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@ -15,6 +15,7 @@ OMV_BOARD_CFLAGS = -DCORE_CM7 \
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-DCYW43_BT_FIRMWARE_INCLUDE_FILE="\"$(TOP_DIR)/$(CYW4343_FW_DIR)/cyw4343_btfw.h\""
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-DCYW43_BT_FIRMWARE_INCLUDE_FILE="\"$(TOP_DIR)/$(CYW4343_FW_DIR)/cyw4343_btfw.h\""
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OMV_ENABLE_BL = 0
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OMV_ENABLE_BL = 0
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OMV_LEPTON_SDK_ENABLE=1
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OMV_LEPTON_SDK_ENABLE=1
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OMV_USB_STACK_STMUSB=1
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MICROPY_PY_CSI = 1
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MICROPY_PY_CSI = 1
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MICROPY_PY_CSI_NG = 1
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MICROPY_PY_CSI_NG = 1
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MICROPY_PY_FIR = 1
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MICROPY_PY_FIR = 1
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@ -70,6 +70,11 @@
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#define OMV_USB_ULPI_STP_PIN (&omv_pin_C0_OTG_HS)
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#define OMV_USB_ULPI_STP_PIN (&omv_pin_C0_OTG_HS)
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#define OMV_USB_ULPI_DIR_PIN (&omv_pin_I11_OTG_HS)
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#define OMV_USB_ULPI_DIR_PIN (&omv_pin_I11_OTG_HS)
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// OpenMV protocol configuration.
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#define OMV_PROTOCOL_MAX_BUFFER_SIZE (4096)
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#define OMV_PROTOCOL_HW_CAPS OMV_PROTOCOL_HW_CAPS_MAKE( \
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HAS_JPEG, HAS_DRAM, HAS_CRC, HAS_WIFI, HAS_BT, HAS_SD, HAS_ETH, HAS_USB_HS)
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// Defined for cpu frequency scaling to override the revid.
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// Defined for cpu frequency scaling to override the revid.
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#define OMV_MAX_CPU_FREQ (400)
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#define OMV_MAX_CPU_FREQ (400)
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@ -14,6 +14,7 @@ OMV_BOARD_CFLAGS = -DCORE_CM7 \
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-DCYW43_BT_FIRMWARE_INCLUDE_FILE="\"$(TOP_DIR)/$(CYW4343_FW_DIR)/cyw4343_btfw.h\""
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-DCYW43_BT_FIRMWARE_INCLUDE_FILE="\"$(TOP_DIR)/$(CYW4343_FW_DIR)/cyw4343_btfw.h\""
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OMV_ENABLE_BL=0
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OMV_ENABLE_BL=0
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OMV_LEPTON_SDK_ENABLE=1
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OMV_LEPTON_SDK_ENABLE=1
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OMV_USB_STACK_STMUSB=1
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MICROPY_PY_CSI = 1
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MICROPY_PY_CSI = 1
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MICROPY_PY_CSI_NG = 1
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MICROPY_PY_CSI_NG = 1
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MICROPY_PY_FIR = 1
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MICROPY_PY_FIR = 1
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@ -60,6 +60,10 @@
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// USB IRQn.
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// USB IRQn.
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#define OMV_USB_IRQN (OTG_FS_IRQn)
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#define OMV_USB_IRQN (OTG_FS_IRQn)
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// OpenMV protocol configuration.
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#define OMV_PROTOCOL_MAX_BUFFER_SIZE (512)
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#define OMV_PROTOCOL_HW_CAPS OMV_PROTOCOL_HW_CAPS_MAKE(HAS_SD)
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//PLL1 192MHz/48MHz
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//PLL1 192MHz/48MHz
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#define OMV_OSC_PLL1M (12)
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#define OMV_OSC_PLL1M (12)
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#define OMV_OSC_PLL1N (384)
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#define OMV_OSC_PLL1N (384)
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@ -9,6 +9,7 @@ OMV_HSE_VALUE=12000000
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DFU_DEVICE=0x0483:0xdf11
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DFU_DEVICE=0x0483:0xdf11
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OMV_ENABLE_BL=1
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OMV_ENABLE_BL=1
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OMV_LEPTON_SDK_ENABLE=1
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OMV_LEPTON_SDK_ENABLE=1
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OMV_USB_STACK_STMUSB=1
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MICROPY_PY_CSI = 1
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MICROPY_PY_CSI = 1
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MICROPY_PY_CSI_NG = 1
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MICROPY_PY_CSI_NG = 1
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MICROPY_PY_FIR = 1
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MICROPY_PY_FIR = 1
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@ -60,6 +60,10 @@
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// USB IRQn.
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// USB IRQn.
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#define OMV_USB_IRQN (OTG_FS_IRQn)
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#define OMV_USB_IRQN (OTG_FS_IRQn)
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// OpenMV protocol configuration.
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#define OMV_PROTOCOL_MAX_BUFFER_SIZE (512)
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#define OMV_PROTOCOL_HW_CAPS OMV_PROTOCOL_HW_CAPS_MAKE(HAS_JPEG, HAS_CRC, HAS_SD)
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//PLL1 216MHz/48MHz
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//PLL1 216MHz/48MHz
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#define OMV_OSC_PLL1M (12)
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#define OMV_OSC_PLL1M (12)
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#define OMV_OSC_PLL1N (432)
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#define OMV_OSC_PLL1N (432)
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@ -87,7 +91,7 @@
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#define OMV_FB_ALLOC_SIZE (84K) // minimum fb alloc size
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#define OMV_FB_ALLOC_SIZE (84K) // minimum fb alloc size
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#define OMV_DMA_MEMORY DTCM // Misc DMA buffers
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#define OMV_DMA_MEMORY DTCM // Misc DMA buffers
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#define OMV_GC_BLOCK0_MEMORY DTCM // Main GC block
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#define OMV_GC_BLOCK0_MEMORY DTCM // Main GC block
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#define OMV_GC_BLOCK0_SIZE (53K)
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#define OMV_GC_BLOCK0_SIZE (52K)
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#define OMV_SB_SIZE (22K) // IDE JPEG buffer (header + data).
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#define OMV_SB_SIZE (22K) // IDE JPEG buffer (header + data).
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#define OMV_MSC_BUF_SIZE (2K) // USB MSC bot data
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#define OMV_MSC_BUF_SIZE (2K) // USB MSC bot data
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#define OMV_FFS_BUF_SIZE (32K) // Flash filesystem cache
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#define OMV_FFS_BUF_SIZE (32K) // Flash filesystem cache
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@ -9,6 +9,7 @@ OMV_HSE_VALUE=12000000
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DFU_DEVICE=0x0483:0xdf11
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DFU_DEVICE=0x0483:0xdf11
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OMV_ENABLE_BL=1
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OMV_ENABLE_BL=1
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OMV_LEPTON_SDK_ENABLE=1
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OMV_LEPTON_SDK_ENABLE=1
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OMV_USB_STACK_STMUSB=1
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MICROPY_PY_CSI = 1
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MICROPY_PY_CSI = 1
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MICROPY_PY_CSI_NG = 1
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MICROPY_PY_CSI_NG = 1
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MICROPY_PY_FIR = 1
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MICROPY_PY_FIR = 1
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@ -74,6 +74,10 @@
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// USB IRQn.
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// USB IRQn.
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#define OMV_USB_IRQN (OTG_FS_IRQn)
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#define OMV_USB_IRQN (OTG_FS_IRQn)
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// OpenMV protocol configuration.
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#define OMV_PROTOCOL_MAX_BUFFER_SIZE (512)
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#define OMV_PROTOCOL_HW_CAPS OMV_PROTOCOL_HW_CAPS_MAKE(HAS_JPEG, HAS_CRC, HAS_SD)
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//PLL1 480MHz/48MHz for USB, SDMMC and FDCAN
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//PLL1 480MHz/48MHz for USB, SDMMC and FDCAN
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#define OMV_OSC_PLL1M (3)
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#define OMV_OSC_PLL1M (3)
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#define OMV_OSC_PLL1N (240)
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#define OMV_OSC_PLL1N (240)
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@ -10,6 +10,7 @@ OMV_BOOT_ADDR=0x08000000
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OMV_HSE_VALUE=12000000
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OMV_HSE_VALUE=12000000
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OMV_ENABLE_BL=1
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OMV_ENABLE_BL=1
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OMV_LEPTON_SDK_ENABLE=1
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OMV_LEPTON_SDK_ENABLE=1
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OMV_USB_STACK_STMUSB=1
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MICROPY_PY_CSI = 1
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MICROPY_PY_CSI = 1
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MICROPY_PY_CSI_NG = 1
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MICROPY_PY_CSI_NG = 1
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MICROPY_PY_FIR = 1
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MICROPY_PY_FIR = 1
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@ -60,6 +60,10 @@
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// USB IRQn.
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// USB IRQn.
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#define OMV_USB_IRQN (OTG_FS_IRQn)
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#define OMV_USB_IRQN (OTG_FS_IRQn)
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// OpenMV protocol configuration.
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#define OMV_PROTOCOL_MAX_BUFFER_SIZE (4096)
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#define OMV_PROTOCOL_HW_CAPS OMV_PROTOCOL_HW_CAPS_MAKE(HAS_JPEG, HAS_DRAM, HAS_CRC, HAS_SD)
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//PLL1 48MHz for USB, SDMMC and FDCAN
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//PLL1 48MHz for USB, SDMMC and FDCAN
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#define OMV_OSC_PLL1M (3)
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#define OMV_OSC_PLL1M (3)
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#define OMV_OSC_PLL1N (240)
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#define OMV_OSC_PLL1N (240)
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@ -125,7 +129,7 @@
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#define OMV_DMA_MEMORY_D2 SRAM3 // Domain 2 DMA buffers.
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#define OMV_DMA_MEMORY_D2 SRAM3 // Domain 2 DMA buffers.
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#define OMV_DMA_MEMORY_D3 SRAM4 // Domain 3 DMA buffers.
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#define OMV_DMA_MEMORY_D3 SRAM4 // Domain 3 DMA buffers.
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#define OMV_GC_BLOCK0_MEMORY SRAM1 // Main GC block
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#define OMV_GC_BLOCK0_MEMORY SRAM1 // Main GC block
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#define OMV_GC_BLOCK0_SIZE (239K)
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#define OMV_GC_BLOCK0_SIZE (235K)
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#define OMV_GC_BLOCK1_MEMORY DRAM // Extra GC block 0.
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#define OMV_GC_BLOCK1_MEMORY DRAM // Extra GC block 0.
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#define OMV_GC_BLOCK1_SIZE (4M)
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#define OMV_GC_BLOCK1_SIZE (4M)
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#define OMV_MSC_BUF_SIZE (2K) // USB MSC bot data
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#define OMV_MSC_BUF_SIZE (2K) // USB MSC bot data
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@ -12,6 +12,7 @@ OMV_ENABLE_BL=1
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OMV_BOSON_ENABLE=1
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OMV_BOSON_ENABLE=1
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OMV_GENX320_ENABLE=1
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OMV_GENX320_ENABLE=1
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OMV_LEPTON_SDK_ENABLE=1
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OMV_LEPTON_SDK_ENABLE=1
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OMV_USB_STACK_STMUSB=1
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MICROPY_PY_CSI = 1
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MICROPY_PY_CSI = 1
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MICROPY_PY_CSI_NG = 1
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MICROPY_PY_CSI_NG = 1
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MICROPY_PY_FIR = 1
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MICROPY_PY_FIR = 1
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@ -47,6 +47,10 @@
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// USB IRQn.
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// USB IRQn.
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#define OMV_USB_IRQN (OTG_FS_IRQn)
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#define OMV_USB_IRQN (OTG_FS_IRQn)
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// OpenMV protocol configuration.
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#define OMV_PROTOCOL_MAX_BUFFER_SIZE (4096)
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#define OMV_PROTOCOL_HW_CAPS OMV_PROTOCOL_HW_CAPS_MAKE(HAS_JPEG, HAS_DRAM, HAS_CRC, HAS_SD)
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//PLL1 48MHz for USB, SDMMC and FDCAN
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//PLL1 48MHz for USB, SDMMC and FDCAN
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#define OMV_OSC_PLL1M (3)
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#define OMV_OSC_PLL1M (3)
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#define OMV_OSC_PLL1N (240)
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#define OMV_OSC_PLL1N (240)
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@ -10,6 +10,7 @@ OMV_BOOT_ADDR=0x08000000
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OMV_HSE_VALUE=12000000
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OMV_HSE_VALUE=12000000
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OMV_ENABLE_BL=1
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OMV_ENABLE_BL=1
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OMV_LEPTON_SDK_ENABLE=1
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OMV_LEPTON_SDK_ENABLE=1
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OMV_USB_STACK_STMUSB=1
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MICROPY_PY_CSI = 1
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MICROPY_PY_CSI = 1
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MICROPY_PY_CSI_NG = 1
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MICROPY_PY_CSI_NG = 1
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MICROPY_PY_FIR = 1
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MICROPY_PY_FIR = 1
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@ -67,11 +67,6 @@ extern unsigned char OMV_BOARD_UID_ADDR[12]; // Unique address.
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#define OMV_FIR_MLX90641_ENABLE (0)
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#define OMV_FIR_MLX90641_ENABLE (0)
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#define OMV_FIR_AMG8833_ENABLE (1)
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#define OMV_FIR_AMG8833_ENABLE (1)
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// Debugging configuration.
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#define OMV_TUSBDBG_ENABLE (CORE_M55_HP)
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#define OMV_TUSBDBG_PACKET (512)
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#define OMV_TUSBDBG_BUFFER (4096)
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// UMM heap block size
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// UMM heap block size
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#define OMV_UMM_BLOCK_SIZE 256
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#define OMV_UMM_BLOCK_SIZE 256
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@ -80,6 +75,12 @@ extern unsigned char OMV_BOARD_UID_ADDR[12]; // Unique address.
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#define OMV_USB1_IRQ_HANDLER (USB_IRQHandler)
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#define OMV_USB1_IRQ_HANDLER (USB_IRQHandler)
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#define OMV_USB_SWITCH_PIN (&omv_pin_USB_SWITCH)
|
#define OMV_USB_SWITCH_PIN (&omv_pin_USB_SWITCH)
|
||||||
|
|
||||||
|
// OpenMV protocol configuration.
|
||||||
|
#define OMV_PROTOCOL_MAX_BUFFER_SIZE (8192)
|
||||||
|
#define OMV_PROTOCOL_HW_CAPS OMV_PROTOCOL_HW_CAPS_MAKE( \
|
||||||
|
HAS_GPU, HAS_NPU, HAS_JPEG, HAS_CRC, HAS_PMU, HAS_WIFI, \
|
||||||
|
HAS_BT, HAS_SD, HAS_ETH, HAS_USB_HS, HAS_MULTICORE)
|
||||||
|
|
||||||
// Linker script constants (see the linker script template alif.ld.S).
|
// Linker script constants (see the linker script template alif.ld.S).
|
||||||
// Note: fb_alloc is a stack-based, dynamically allocated memory on FB.
|
// Note: fb_alloc is a stack-based, dynamically allocated memory on FB.
|
||||||
// The maximum available fb_alloc memory = FB_ALLOC_SIZE + FB_SIZE - (w*h*bpp).
|
// The maximum available fb_alloc memory = FB_ALLOC_SIZE + FB_SIZE - (w*h*bpp).
|
||||||
|
@ -13,6 +13,7 @@ OMV_FIRM_ADDR=0x80020000
|
|||||||
OMV_HSE_VALUE=12000000
|
OMV_HSE_VALUE=12000000
|
||||||
OMV_LEPTON_SDK_ENABLE=1
|
OMV_LEPTON_SDK_ENABLE=1
|
||||||
OMV_TOF_VL53L8CX_ENABLE=1
|
OMV_TOF_VL53L8CX_ENABLE=1
|
||||||
|
OMV_USB_STACK_TINYUSB=$(CORE_M55_HP)
|
||||||
MICROPY_PY_CSI = $(CORE_M55_HP)
|
MICROPY_PY_CSI = $(CORE_M55_HP)
|
||||||
MICROPY_PY_CSI_NG = $(CORE_M55_HP)
|
MICROPY_PY_CSI_NG = $(CORE_M55_HP)
|
||||||
MICROPY_PY_FIR = 1
|
MICROPY_PY_FIR = 1
|
||||||
|
@ -62,6 +62,12 @@
|
|||||||
// USB IRQn.
|
// USB IRQn.
|
||||||
#define OMV_USB_IRQN (USB1_OTG_HS_IRQn)
|
#define OMV_USB_IRQN (USB1_OTG_HS_IRQn)
|
||||||
|
|
||||||
|
// OpenMV protocol configuration.
|
||||||
|
#define OMV_PROTOCOL_MAX_BUFFER_SIZE (8192)
|
||||||
|
#define OMV_PROTOCOL_HW_CAPS OMV_PROTOCOL_HW_CAPS_MAKE( \
|
||||||
|
HAS_GPU, HAS_NPU, HAS_ISP, HAS_VENC, HAS_JPEG, HAS_DRAM, \
|
||||||
|
HAS_CRC, HAS_PMU, HAS_WIFI, HAS_BT, HAS_SD, HAS_ETH, HAS_USB_HS)
|
||||||
|
|
||||||
//PLL1 800MHz
|
//PLL1 800MHz
|
||||||
#define OMV_OSC_PLL1M (3)
|
#define OMV_OSC_PLL1M (3)
|
||||||
#define OMV_OSC_PLL1N (50)
|
#define OMV_OSC_PLL1N (50)
|
||||||
|
@ -26,6 +26,7 @@ OMV_ENABLE_BL=1
|
|||||||
OMV_BOSON_ENABLE=1
|
OMV_BOSON_ENABLE=1
|
||||||
OMV_GENX320_ENABLE=1
|
OMV_GENX320_ENABLE=1
|
||||||
OMV_LEPTON_SDK_ENABLE=1
|
OMV_LEPTON_SDK_ENABLE=1
|
||||||
|
OMV_USB_STACK_STMUSB=1
|
||||||
MICROPY_PY_CSI = 1
|
MICROPY_PY_CSI = 1
|
||||||
MICROPY_PY_CSI_NG = 1
|
MICROPY_PY_CSI_NG = 1
|
||||||
MICROPY_PY_FIR = 1
|
MICROPY_PY_FIR = 1
|
||||||
|
@ -47,13 +47,13 @@
|
|||||||
#define OMV_FIR_MLX90641_ENABLE (1)
|
#define OMV_FIR_MLX90641_ENABLE (1)
|
||||||
#define OMV_FIR_AMG8833_ENABLE (1)
|
#define OMV_FIR_AMG8833_ENABLE (1)
|
||||||
|
|
||||||
// Debugging configuration.
|
|
||||||
#define OMV_TUSBDBG_ENABLE (1)
|
|
||||||
#define OMV_TUSBDBG_BUFFER (2048)
|
|
||||||
|
|
||||||
// UMM heap block size
|
// UMM heap block size
|
||||||
#define OMV_UMM_BLOCK_SIZE 256
|
#define OMV_UMM_BLOCK_SIZE 256
|
||||||
|
|
||||||
|
// Protocol hardware capabilities
|
||||||
|
#define OMV_PROTOCOL_HW_CAPS OMV_PROTOCOL_HW_CAPS_MAKE( \
|
||||||
|
HAS_DRAM, HAS_WIFI, HAS_BT, HAS_SD, HAS_ETH, HAS_USB_HS)
|
||||||
|
|
||||||
// USB config.
|
// USB config.
|
||||||
#define OMV_USB_IRQN (USB_OTG1_IRQn)
|
#define OMV_USB_IRQN (USB_OTG1_IRQn)
|
||||||
#define OMV_USB1_IRQ_HANDLER (USB_OTG1_IRQHandler)
|
#define OMV_USB1_IRQ_HANDLER (USB_OTG1_IRQHandler)
|
||||||
@ -81,7 +81,7 @@
|
|||||||
#define OMV_GC_BLOCK0_MEMORY OCRM2 // Extra GC block 0.
|
#define OMV_GC_BLOCK0_MEMORY OCRM2 // Extra GC block 0.
|
||||||
#define OMV_GC_BLOCK0_SIZE (64K)
|
#define OMV_GC_BLOCK0_SIZE (64K)
|
||||||
#define OMV_GC_BLOCK1_MEMORY DTCM // Main GC block
|
#define OMV_GC_BLOCK1_MEMORY DTCM // Main GC block
|
||||||
#define OMV_GC_BLOCK1_SIZE (272K)
|
#define OMV_GC_BLOCK1_SIZE (271K)
|
||||||
#define OMV_GC_BLOCK2_MEMORY DRAM // Extra GC block 1.
|
#define OMV_GC_BLOCK2_MEMORY DRAM // Extra GC block 1.
|
||||||
#define OMV_GC_BLOCK2_SIZE (8M)
|
#define OMV_GC_BLOCK2_SIZE (8M)
|
||||||
#define OMV_RAMFUNC_MEMORY ITCM2 // RAM code memory.
|
#define OMV_RAMFUNC_MEMORY ITCM2 // RAM code memory.
|
||||||
|
@ -11,6 +11,7 @@ OMV_HSE_VALUE=12000000
|
|||||||
OMV_BOSON_ENABLE=1
|
OMV_BOSON_ENABLE=1
|
||||||
OMV_GENX320_ENABLE=1
|
OMV_GENX320_ENABLE=1
|
||||||
OMV_LEPTON_SDK_ENABLE=1
|
OMV_LEPTON_SDK_ENABLE=1
|
||||||
|
OMV_USB_STACK_TINYUSB=1
|
||||||
MICROPY_PY_CSI = 1
|
MICROPY_PY_CSI = 1
|
||||||
MICROPY_PY_CSI_NG = 1
|
MICROPY_PY_CSI_NG = 1
|
||||||
MICROPY_PY_FIR = 1
|
MICROPY_PY_FIR = 1
|
||||||
|
Loading…
Reference in New Issue
Block a user