boards/all: Switch to new protocol.

Signed-off-by: iabdalkader <i.abdalkader@gmail.com>
This commit is contained in:
iabdalkader 2025-09-06 17:11:09 +02:00
parent d5c1bd59c9
commit 35d0d6c363
24 changed files with 67 additions and 22 deletions

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@ -74,6 +74,11 @@
#define OMV_USB_IRQN (OTG_FS_IRQn)
#define OMV_USB_ULPI (0)
// OpenMV protocol configuration.
#define OMV_PROTOCOL_MAX_BUFFER_SIZE (4096)
#define OMV_PROTOCOL_HW_CAPS OMV_PROTOCOL_HW_CAPS_MAKE( \
HAS_JPEG, HAS_DRAM, HAS_CRC, HAS_WIFI, HAS_BT, HAS_SD, HAS_ETH, HAS_USB_HS)
// PLL1 480MHz/48MHz SDMMC and FDCAN
// USB and RNG are clocked from the HSI48
#define OMV_OSC_PLL1M (4)
@ -138,7 +143,7 @@
#define OMV_FB_SIZE (3M) // FB memory: header + VGA/GS image
#define OMV_FB_ALLOC_SIZE (1M) // minimum fb alloc size
#define OMV_FB_OVERLAY_MEMORY SRAM0 // Fast fb_alloc memory.
#define OMV_FB_OVERLAY_SIZE (448K) // Fast fb_alloc memory size.
#define OMV_FB_OVERLAY_SIZE (443K) // Fast fb_alloc memory size.
#define OMV_SB_MEMORY DRAM // Streaming buffer memory.
#define OMV_SB_SIZE (1M) // Streaming buffer size.
#define OMV_DMA_MEMORY SRAM3 // Misc DMA buffers memory.

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@ -13,6 +13,7 @@ OMV_BOARD_CFLAGS = -DCORE_CM7 \
-DCYW43_BT_FIRMWARE_ADDRESS=0x90FC0000 \
-DCYW43_BT_FIRMWARE_INCLUDE_FILE="\"$(TOP_DIR)/$(CYW4343_FW_DIR)/cyw4343_btfw.h\""
OMV_ENABLE_BL=0
OMV_USB_STACK_STMUSB=1
MICROPY_PY_CSI = 1
MICROPY_PY_CSI_NG = 1
MICROPY_PY_FIR = 1

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@ -50,10 +50,6 @@
#define OMV_FIR_MLX90641_ENABLE (1)
#define OMV_FIR_AMG8833_ENABLE (1)
// Debugging configuration.
#define OMV_TUSBDBG_ENABLE (1)
#define OMV_TUSBDBG_BUFFER (512)
// UMM heap block size
#define OMV_UMM_BLOCK_SIZE 16

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@ -49,10 +49,6 @@ extern unsigned char *OMV_BOARD_UID_ADDR; // Unique address.
// FIR drivers configuration.
#define OMV_FIR_AMG8833_ENABLE (1)
// Debugging configuration.
#define OMV_TUSBDBG_ENABLE (1)
#define OMV_TUSBDBG_BUFFER (2048)
// UMM heap block size
#define OMV_UMM_BLOCK_SIZE 16

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@ -61,6 +61,11 @@
#define OMV_USB_ULPI_STP_PIN (&omv_pin_C0_OTG_HS)
#define OMV_USB_ULPI_DIR_PIN (&omv_pin_C2_OTG_HS)
// OpenMV protocol configuration.
#define OMV_PROTOCOL_MAX_BUFFER_SIZE (4096)
#define OMV_PROTOCOL_HW_CAPS OMV_PROTOCOL_HW_CAPS_MAKE( \
HAS_JPEG, HAS_DRAM, HAS_CRC, HAS_WIFI, HAS_BT, HAS_SD, HAS_ETH, HAS_USB_HS)
// Defined for cpu frequency scaling to override the revid.
#define OMV_MAX_CPU_FREQ (400)
@ -131,7 +136,7 @@
#define OMV_CM4_BOOT_MEMORY SRAM4 // Use to boot CM4 for low-power mode.
#define OMV_CM4_BOOT_SIZE 1K
#define OMV_GC_BLOCK0_MEMORY DTCM // Main GC block 0.
#define OMV_GC_BLOCK0_SIZE (32K)
#define OMV_GC_BLOCK0_SIZE (31K)
#define OMV_GC_BLOCK1_MEMORY SRAM4 // Extra GC block 1.
#define OMV_GC_BLOCK1_SIZE (63K)
#define OMV_GC_BLOCK2_MEMORY SRAM1 // Extra GC block 2.

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@ -15,6 +15,7 @@ OMV_BOARD_CFLAGS = -DCORE_CM7 \
-DCYW43_BT_FIRMWARE_INCLUDE_FILE="\"$(TOP_DIR)/$(CYW4343_FW_DIR)/cyw4343_btfw.h\""
OMV_ENABLE_BL = 0
OMV_LEPTON_SDK_ENABLE=1
OMV_USB_STACK_STMUSB=1
MICROPY_PY_CSI = 1
MICROPY_PY_CSI_NG = 1
MICROPY_PY_FIR = 1

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@ -70,6 +70,11 @@
#define OMV_USB_ULPI_STP_PIN (&omv_pin_C0_OTG_HS)
#define OMV_USB_ULPI_DIR_PIN (&omv_pin_I11_OTG_HS)
// OpenMV protocol configuration.
#define OMV_PROTOCOL_MAX_BUFFER_SIZE (4096)
#define OMV_PROTOCOL_HW_CAPS OMV_PROTOCOL_HW_CAPS_MAKE( \
HAS_JPEG, HAS_DRAM, HAS_CRC, HAS_WIFI, HAS_BT, HAS_SD, HAS_ETH, HAS_USB_HS)
// Defined for cpu frequency scaling to override the revid.
#define OMV_MAX_CPU_FREQ (400)

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@ -14,6 +14,7 @@ OMV_BOARD_CFLAGS = -DCORE_CM7 \
-DCYW43_BT_FIRMWARE_INCLUDE_FILE="\"$(TOP_DIR)/$(CYW4343_FW_DIR)/cyw4343_btfw.h\""
OMV_ENABLE_BL=0
OMV_LEPTON_SDK_ENABLE=1
OMV_USB_STACK_STMUSB=1
MICROPY_PY_CSI = 1
MICROPY_PY_CSI_NG = 1
MICROPY_PY_FIR = 1

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@ -60,6 +60,10 @@
// USB IRQn.
#define OMV_USB_IRQN (OTG_FS_IRQn)
// OpenMV protocol configuration.
#define OMV_PROTOCOL_MAX_BUFFER_SIZE (512)
#define OMV_PROTOCOL_HW_CAPS OMV_PROTOCOL_HW_CAPS_MAKE(HAS_SD)
//PLL1 192MHz/48MHz
#define OMV_OSC_PLL1M (12)
#define OMV_OSC_PLL1N (384)

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@ -9,6 +9,7 @@ OMV_HSE_VALUE=12000000
DFU_DEVICE=0x0483:0xdf11
OMV_ENABLE_BL=1
OMV_LEPTON_SDK_ENABLE=1
OMV_USB_STACK_STMUSB=1
MICROPY_PY_CSI = 1
MICROPY_PY_CSI_NG = 1
MICROPY_PY_FIR = 1

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@ -60,6 +60,10 @@
// USB IRQn.
#define OMV_USB_IRQN (OTG_FS_IRQn)
// OpenMV protocol configuration.
#define OMV_PROTOCOL_MAX_BUFFER_SIZE (512)
#define OMV_PROTOCOL_HW_CAPS OMV_PROTOCOL_HW_CAPS_MAKE(HAS_JPEG, HAS_CRC, HAS_SD)
//PLL1 216MHz/48MHz
#define OMV_OSC_PLL1M (12)
#define OMV_OSC_PLL1N (432)
@ -87,7 +91,7 @@
#define OMV_FB_ALLOC_SIZE (84K) // minimum fb alloc size
#define OMV_DMA_MEMORY DTCM // Misc DMA buffers
#define OMV_GC_BLOCK0_MEMORY DTCM // Main GC block
#define OMV_GC_BLOCK0_SIZE (53K)
#define OMV_GC_BLOCK0_SIZE (52K)
#define OMV_SB_SIZE (22K) // IDE JPEG buffer (header + data).
#define OMV_MSC_BUF_SIZE (2K) // USB MSC bot data
#define OMV_FFS_BUF_SIZE (32K) // Flash filesystem cache

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@ -9,6 +9,7 @@ OMV_HSE_VALUE=12000000
DFU_DEVICE=0x0483:0xdf11
OMV_ENABLE_BL=1
OMV_LEPTON_SDK_ENABLE=1
OMV_USB_STACK_STMUSB=1
MICROPY_PY_CSI = 1
MICROPY_PY_CSI_NG = 1
MICROPY_PY_FIR = 1

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@ -74,6 +74,10 @@
// USB IRQn.
#define OMV_USB_IRQN (OTG_FS_IRQn)
// OpenMV protocol configuration.
#define OMV_PROTOCOL_MAX_BUFFER_SIZE (512)
#define OMV_PROTOCOL_HW_CAPS OMV_PROTOCOL_HW_CAPS_MAKE(HAS_JPEG, HAS_CRC, HAS_SD)
//PLL1 480MHz/48MHz for USB, SDMMC and FDCAN
#define OMV_OSC_PLL1M (3)
#define OMV_OSC_PLL1N (240)

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@ -10,6 +10,7 @@ OMV_BOOT_ADDR=0x08000000
OMV_HSE_VALUE=12000000
OMV_ENABLE_BL=1
OMV_LEPTON_SDK_ENABLE=1
OMV_USB_STACK_STMUSB=1
MICROPY_PY_CSI = 1
MICROPY_PY_CSI_NG = 1
MICROPY_PY_FIR = 1

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@ -60,6 +60,10 @@
// USB IRQn.
#define OMV_USB_IRQN (OTG_FS_IRQn)
// OpenMV protocol configuration.
#define OMV_PROTOCOL_MAX_BUFFER_SIZE (4096)
#define OMV_PROTOCOL_HW_CAPS OMV_PROTOCOL_HW_CAPS_MAKE(HAS_JPEG, HAS_DRAM, HAS_CRC, HAS_SD)
//PLL1 48MHz for USB, SDMMC and FDCAN
#define OMV_OSC_PLL1M (3)
#define OMV_OSC_PLL1N (240)
@ -125,7 +129,7 @@
#define OMV_DMA_MEMORY_D2 SRAM3 // Domain 2 DMA buffers.
#define OMV_DMA_MEMORY_D3 SRAM4 // Domain 3 DMA buffers.
#define OMV_GC_BLOCK0_MEMORY SRAM1 // Main GC block
#define OMV_GC_BLOCK0_SIZE (239K)
#define OMV_GC_BLOCK0_SIZE (235K)
#define OMV_GC_BLOCK1_MEMORY DRAM // Extra GC block 0.
#define OMV_GC_BLOCK1_SIZE (4M)
#define OMV_MSC_BUF_SIZE (2K) // USB MSC bot data

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@ -12,6 +12,7 @@ OMV_ENABLE_BL=1
OMV_BOSON_ENABLE=1
OMV_GENX320_ENABLE=1
OMV_LEPTON_SDK_ENABLE=1
OMV_USB_STACK_STMUSB=1
MICROPY_PY_CSI = 1
MICROPY_PY_CSI_NG = 1
MICROPY_PY_FIR = 1

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@ -47,6 +47,10 @@
// USB IRQn.
#define OMV_USB_IRQN (OTG_FS_IRQn)
// OpenMV protocol configuration.
#define OMV_PROTOCOL_MAX_BUFFER_SIZE (4096)
#define OMV_PROTOCOL_HW_CAPS OMV_PROTOCOL_HW_CAPS_MAKE(HAS_JPEG, HAS_DRAM, HAS_CRC, HAS_SD)
//PLL1 48MHz for USB, SDMMC and FDCAN
#define OMV_OSC_PLL1M (3)
#define OMV_OSC_PLL1N (240)

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@ -10,6 +10,7 @@ OMV_BOOT_ADDR=0x08000000
OMV_HSE_VALUE=12000000
OMV_ENABLE_BL=1
OMV_LEPTON_SDK_ENABLE=1
OMV_USB_STACK_STMUSB=1
MICROPY_PY_CSI = 1
MICROPY_PY_CSI_NG = 1
MICROPY_PY_FIR = 1

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@ -67,11 +67,6 @@ extern unsigned char OMV_BOARD_UID_ADDR[12]; // Unique address.
#define OMV_FIR_MLX90641_ENABLE (0)
#define OMV_FIR_AMG8833_ENABLE (1)
// Debugging configuration.
#define OMV_TUSBDBG_ENABLE (CORE_M55_HP)
#define OMV_TUSBDBG_PACKET (512)
#define OMV_TUSBDBG_BUFFER (4096)
// UMM heap block size
#define OMV_UMM_BLOCK_SIZE 256
@ -80,6 +75,12 @@ extern unsigned char OMV_BOARD_UID_ADDR[12]; // Unique address.
#define OMV_USB1_IRQ_HANDLER (USB_IRQHandler)
#define OMV_USB_SWITCH_PIN (&omv_pin_USB_SWITCH)
// OpenMV protocol configuration.
#define OMV_PROTOCOL_MAX_BUFFER_SIZE (8192)
#define OMV_PROTOCOL_HW_CAPS OMV_PROTOCOL_HW_CAPS_MAKE( \
HAS_GPU, HAS_NPU, HAS_JPEG, HAS_CRC, HAS_PMU, HAS_WIFI, \
HAS_BT, HAS_SD, HAS_ETH, HAS_USB_HS, HAS_MULTICORE)
// Linker script constants (see the linker script template alif.ld.S).
// Note: fb_alloc is a stack-based, dynamically allocated memory on FB.
// The maximum available fb_alloc memory = FB_ALLOC_SIZE + FB_SIZE - (w*h*bpp).

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@ -13,6 +13,7 @@ OMV_FIRM_ADDR=0x80020000
OMV_HSE_VALUE=12000000
OMV_LEPTON_SDK_ENABLE=1
OMV_TOF_VL53L8CX_ENABLE=1
OMV_USB_STACK_TINYUSB=$(CORE_M55_HP)
MICROPY_PY_CSI = $(CORE_M55_HP)
MICROPY_PY_CSI_NG = $(CORE_M55_HP)
MICROPY_PY_FIR = 1

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@ -62,6 +62,12 @@
// USB IRQn.
#define OMV_USB_IRQN (USB1_OTG_HS_IRQn)
// OpenMV protocol configuration.
#define OMV_PROTOCOL_MAX_BUFFER_SIZE (8192)
#define OMV_PROTOCOL_HW_CAPS OMV_PROTOCOL_HW_CAPS_MAKE( \
HAS_GPU, HAS_NPU, HAS_ISP, HAS_VENC, HAS_JPEG, HAS_DRAM, \
HAS_CRC, HAS_PMU, HAS_WIFI, HAS_BT, HAS_SD, HAS_ETH, HAS_USB_HS)
//PLL1 800MHz
#define OMV_OSC_PLL1M (3)
#define OMV_OSC_PLL1N (50)

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@ -26,6 +26,7 @@ OMV_ENABLE_BL=1
OMV_BOSON_ENABLE=1
OMV_GENX320_ENABLE=1
OMV_LEPTON_SDK_ENABLE=1
OMV_USB_STACK_STMUSB=1
MICROPY_PY_CSI = 1
MICROPY_PY_CSI_NG = 1
MICROPY_PY_FIR = 1

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@ -47,13 +47,13 @@
#define OMV_FIR_MLX90641_ENABLE (1)
#define OMV_FIR_AMG8833_ENABLE (1)
// Debugging configuration.
#define OMV_TUSBDBG_ENABLE (1)
#define OMV_TUSBDBG_BUFFER (2048)
// UMM heap block size
#define OMV_UMM_BLOCK_SIZE 256
// Protocol hardware capabilities
#define OMV_PROTOCOL_HW_CAPS OMV_PROTOCOL_HW_CAPS_MAKE( \
HAS_DRAM, HAS_WIFI, HAS_BT, HAS_SD, HAS_ETH, HAS_USB_HS)
// USB config.
#define OMV_USB_IRQN (USB_OTG1_IRQn)
#define OMV_USB1_IRQ_HANDLER (USB_OTG1_IRQHandler)
@ -81,7 +81,7 @@
#define OMV_GC_BLOCK0_MEMORY OCRM2 // Extra GC block 0.
#define OMV_GC_BLOCK0_SIZE (64K)
#define OMV_GC_BLOCK1_MEMORY DTCM // Main GC block
#define OMV_GC_BLOCK1_SIZE (272K)
#define OMV_GC_BLOCK1_SIZE (271K)
#define OMV_GC_BLOCK2_MEMORY DRAM // Extra GC block 1.
#define OMV_GC_BLOCK2_SIZE (8M)
#define OMV_RAMFUNC_MEMORY ITCM2 // RAM code memory.

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@ -11,6 +11,7 @@ OMV_HSE_VALUE=12000000
OMV_BOSON_ENABLE=1
OMV_GENX320_ENABLE=1
OMV_LEPTON_SDK_ENABLE=1
OMV_USB_STACK_TINYUSB=1
MICROPY_PY_CSI = 1
MICROPY_PY_CSI_NG = 1
MICROPY_PY_FIR = 1