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Merge pull request #2514 from openmv/boot_xspi_dtr
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bootloader/stm32: Add support XSPI MMAP in DTR mode.
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commit
37ec53ca8e
@ -38,7 +38,7 @@ int axi_flash_write(uint32_t addr, const uint8_t *buf, size_t size);
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int spi_flash_deinit();
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int spi_flash_read(uint32_t addr, uint8_t *buf, uint32_t size);
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int spi_flash_write(uint32_t addr, const uint8_t *buf, uint32_t size);
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int spi_flash_memory_map();
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int spi_flash_memory_map(bool dtr);
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static inline int flash_read(uint32_t ptype, uint32_t addr, uint8_t *buf, uint32_t size) {
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#if OMV_BOOT_AXI_FLASH_ENABLE
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@ -142,7 +142,7 @@ int port_deinit(void) {
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// Deinitialize SPI Flash.
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#if OMV_BOOT_SPI_FLASH_MMAP
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spi_flash_memory_map();
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spi_flash_memory_map(OMV_BOOT_SPI_FLASH_MMAP_DTR);
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#elif OMV_BOOT_SPI_FLASH_ENABLE
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spi_flash_deinit();
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#endif
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@ -75,13 +75,13 @@
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#define XSPI_CMD_WRITE_ENABLE (0x06)
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#define XSPI_CMD_WRITE_DISABLE (0x04)
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#define XSPI_CMD_READ_STATUS (0x05)
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#define XSPI_CMD_WRITE_STATUS (0x01)
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#define XSPI_CMD_READ_SR (0x05)
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#define XSPI_CMD_READ_SR_DUMMY (0)
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#define XSPI_CMD_WRITE_CR2 (0x72)
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#define XSPI_SR_WIP_MASK (1 << 0)
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#define XSPI_SR_WEL_MASK (1 << 1)
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static XSPI_HandleTypeDef xspi = {0};
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static int xspi_flash_reset();
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@ -170,7 +170,7 @@ static int xspi_flash_poll_status_flag(uint32_t mask, uint32_t match, uint32_t t
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};
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XSPI_RegularCmdTypeDef command = {
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.Instruction = XSPI_CMD_READ_STATUS,
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.Instruction = XSPI_CMD_READ_SR,
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.InstructionMode = HAL_XSPI_INSTRUCTION_1_LINE,
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.InstructionWidth = HAL_XSPI_INSTRUCTION_8_BITS,
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.InstructionDTRMode = HAL_XSPI_INSTRUCTION_DTR_DISABLE,
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@ -181,7 +181,7 @@ static int xspi_flash_poll_status_flag(uint32_t mask, uint32_t match, uint32_t t
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.DataMode = HAL_XSPI_DATA_1_LINE,
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.DataLength = 1,
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.DataDTRMode = HAL_XSPI_DATA_DTR_DISABLE,
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.DummyCycles = 0,
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.DummyCycles = XSPI_CMD_READ_SR_DUMMY,
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.IOSelect = HAL_XSPI_SELECT_IO_7_0,
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.AlternateBytesMode = HAL_XSPI_ALT_BYTES_NONE,
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.DQSMode = HAL_XSPI_DQS_DISABLE,
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@ -198,6 +198,72 @@ static int xspi_flash_poll_status_flag(uint32_t mask, uint32_t match, uint32_t t
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return 0;
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}
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static int xspi_flash_write_enable() {
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XSPI_RegularCmdTypeDef command = {
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.Instruction = XSPI_CMD_WRITE_ENABLE,
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.InstructionMode = HAL_XSPI_INSTRUCTION_1_LINE,
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.InstructionWidth = HAL_XSPI_INSTRUCTION_8_BITS,
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.InstructionDTRMode = HAL_XSPI_INSTRUCTION_DTR_DISABLE,
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.Address = 0U,
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.AddressMode = HAL_XSPI_ADDRESS_NONE,
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.AddressWidth = HAL_XSPI_ADDRESS_32_BITS,
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.AddressDTRMode = HAL_XSPI_ADDRESS_DTR_DISABLE,
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.DataMode = HAL_XSPI_DATA_NONE,
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.DataLength = 0,
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.DataDTRMode = HAL_XSPI_DATA_DTR_DISABLE,
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.DummyCycles = 0,
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.IOSelect = HAL_XSPI_SELECT_IO_7_0,
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.AlternateBytesMode = HAL_XSPI_ALT_BYTES_NONE,
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.DQSMode = HAL_XSPI_DQS_DISABLE,
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.OperationType = HAL_XSPI_OPTYPE_COMMON_CFG,
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};
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if (HAL_XSPI_Command(&xspi, &command, XSPI_COMMAND_TIMEOUT) != HAL_OK) {
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return -1;
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}
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if (xspi_flash_poll_status_flag(XSPI_SR_WEL_MASK, XSPI_SR_WEL_MASK, XSPI_COMMAND_TIMEOUT) != 0) {
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return -1;
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}
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return 0;
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}
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static int spi_flash_write_cr2(uint8_t addr, uint8_t data) {
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XSPI_RegularCmdTypeDef command = {
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.OperationType = HAL_XSPI_OPTYPE_COMMON_CFG,
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.Instruction = XSPI_CMD_WRITE_CR2,
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.InstructionMode = HAL_XSPI_INSTRUCTION_1_LINE,
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.InstructionDTRMode = HAL_XSPI_INSTRUCTION_DTR_DISABLE,
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.InstructionWidth = HAL_XSPI_INSTRUCTION_8_BITS,
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.Address = addr,
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.AddressMode = HAL_XSPI_ADDRESS_1_LINE,
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.AddressDTRMode = HAL_XSPI_ADDRESS_DTR_DISABLE,
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.AddressWidth = HAL_XSPI_ADDRESS_32_BITS,
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.AlternateBytesMode = HAL_XSPI_ALT_BYTES_NONE,
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.DataLength = 1,
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.DataMode = HAL_XSPI_DATA_1_LINE,
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.DataDTRMode = HAL_XSPI_DATA_DTR_DISABLE,
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.IOSelect = HAL_XSPI_SELECT_IO_7_0,
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.DummyCycles = 0,
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.DQSMode = HAL_XSPI_DQS_DISABLE,
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};
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// Enable write operations
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if (xspi_flash_write_enable(&xspi) != 0) {
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return -1;
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}
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if (HAL_XSPI_Command(&xspi, &command, XSPI_COMMAND_TIMEOUT) != HAL_OK) {
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return -1;
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}
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if (HAL_XSPI_Transmit(&xspi, &data, XSPI_COMMAND_TIMEOUT) != HAL_OK) {
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return -1;
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}
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return 0;
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}
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static int xspi_flash_reset() {
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XSPI_RegularCmdTypeDef command = {
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.InstructionMode = HAL_XSPI_INSTRUCTION_1_LINE,
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@ -233,36 +299,6 @@ static int xspi_flash_reset() {
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return 0;
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}
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static int xspi_flash_write_enable() {
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XSPI_RegularCmdTypeDef command = {
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.Instruction = XSPI_CMD_WRITE_ENABLE,
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.InstructionMode = HAL_XSPI_INSTRUCTION_1_LINE,
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.InstructionWidth = HAL_XSPI_INSTRUCTION_8_BITS,
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.InstructionDTRMode = HAL_XSPI_INSTRUCTION_DTR_DISABLE,
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.Address = 0U,
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.AddressMode = HAL_XSPI_ADDRESS_NONE,
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.AddressWidth = HAL_XSPI_ADDRESS_32_BITS,
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.AddressDTRMode = HAL_XSPI_ADDRESS_DTR_DISABLE,
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.DataMode = HAL_XSPI_DATA_NONE,
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.DataLength = 0,
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.DataDTRMode = HAL_XSPI_DATA_DTR_DISABLE,
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.DummyCycles = 0,
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.IOSelect = HAL_XSPI_SELECT_IO_7_0,
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.AlternateBytesMode = HAL_XSPI_ALT_BYTES_NONE,
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.DQSMode = HAL_XSPI_DQS_DISABLE,
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.OperationType = HAL_XSPI_OPTYPE_COMMON_CFG,
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};
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if (HAL_XSPI_Command(&xspi, &command, XSPI_COMMAND_TIMEOUT) != HAL_OK) {
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return -1;
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}
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if (xspi_flash_poll_status_flag(XSPI_SR_WEL_MASK, XSPI_SR_WEL_MASK, XSPI_COMMAND_TIMEOUT) != 0) {
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return -1;
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}
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return 0;
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}
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static int xspi_flash_read_id(uint8_t *buf) {
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XSPI_RegularCmdTypeDef command = {
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.Instruction = XSPI_CMD_RDID,
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@ -455,26 +491,29 @@ static int xspi_flash_write_page(uint32_t addr, const uint8_t *buf, uint32_t siz
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return 0;
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}
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int spi_flash_memory_map() {
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int spi_flash_memory_map(bool dtr) {
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XSPI_RegularCmdTypeDef command = {
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.InstructionMode = HAL_XSPI_INSTRUCTION_1_LINE,
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.InstructionMode = (dtr) ? HAL_XSPI_INSTRUCTION_8_LINES : HAL_XSPI_INSTRUCTION_1_LINE,
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.InstructionWidth = HAL_XSPI_INSTRUCTION_8_BITS,
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.InstructionDTRMode = HAL_XSPI_INSTRUCTION_DTR_DISABLE,
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.AddressMode = HAL_XSPI_ADDRESS_1_LINE,
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.InstructionDTRMode = (dtr) ? HAL_XSPI_INSTRUCTION_DTR_ENABLE : HAL_XSPI_INSTRUCTION_DTR_DISABLE,
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.AddressMode = (dtr) ? HAL_XSPI_ADDRESS_8_LINES : HAL_XSPI_ADDRESS_1_LINE,
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.AddressWidth = HAL_XSPI_ADDRESS_32_BITS,
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.AddressDTRMode = HAL_XSPI_ADDRESS_DTR_DISABLE,
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.DataMode = HAL_XSPI_DATA_1_LINE,
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.DataDTRMode = HAL_XSPI_DATA_DTR_DISABLE,
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.AlternateBytesMode = HAL_XSPI_ALT_BYTES_NONE,
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.AddressDTRMode = (dtr) ? HAL_XSPI_ADDRESS_DTR_ENABLE : HAL_XSPI_ADDRESS_DTR_DISABLE,
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.DataMode = (dtr) ? HAL_XSPI_DATA_8_LINES : HAL_XSPI_DATA_1_LINE,
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.DataDTRMode = (dtr) ? HAL_XSPI_DATA_DTR_ENABLE : HAL_XSPI_DATA_DTR_DISABLE,
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};
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if (xspi_flash_init() != 0) {
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return -1;
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}
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if (dtr && spi_flash_write_cr2(0x0, 0x02) != 0) {
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return -1;
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}
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// Initialize the write command
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command.Instruction = XSPI_CMD_WRITE;
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command.DummyCycles = XSPI_CMD_WRITE_DUMMY;
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command.Instruction = (dtr) ? XSPI_CMD_WRITE_DTR : XSPI_CMD_WRITE;
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command.DummyCycles = (dtr) ? XSPI_CMD_WRITE_DTR_DUMMY : XSPI_CMD_WRITE_DUMMY;
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command.OperationType = HAL_XSPI_OPTYPE_WRITE_CFG;
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command.DQSMode = HAL_XSPI_DQS_DISABLE;
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if (HAL_XSPI_Command(&xspi, &command, XSPI_COMMAND_TIMEOUT) != HAL_OK) {
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@ -482,10 +521,10 @@ int spi_flash_memory_map() {
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}
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// Initialize the read command
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command.Instruction = XSPI_CMD_READ;
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command.DummyCycles = XSPI_CMD_READ_DUMMY;
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command.Instruction = (dtr) ? XSPI_CMD_READ_DTR : XSPI_CMD_READ;
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command.DummyCycles = (dtr) ? XSPI_CMD_READ_DTR_DUMMY : XSPI_CMD_READ_DUMMY;
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command.OperationType = HAL_XSPI_OPTYPE_READ_CFG;
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command.DQSMode = HAL_XSPI_DQS_DISABLE; // Enable for DTR HAL_XSPI_DQS_ENABLE
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command.DQSMode = (dtr) ? HAL_XSPI_DQS_ENABLE : HAL_XSPI_DQS_DISABLE;
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if (HAL_XSPI_Command(&xspi, &command, XSPI_COMMAND_TIMEOUT) != HAL_OK) {
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return -1;
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}
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