Moved all registers defintions to a separate file.

Added new enums for all resoultions and framerates.
Sensor configuration can be set via serial commands.
This commit is contained in:
iabdalkader 2013-11-21 00:19:18 +02:00
parent 8463773e63
commit 38d83381e6
4 changed files with 296 additions and 253 deletions

View File

@ -36,25 +36,16 @@ int main(void)
ov9650.id.PID != 0x96) {
goto error;
}
/* Configure image size and format and FPS */
if (ov9650_set_pixfmt(&ov9650, PIXFMT_RGB565) != 0) {
goto error;
}
/* Configure image size and format and FPS */
if (ov9650_set_framesize(&ov9650, FRAMESIZE_QQVGA) != 0) {
goto error;
}
/* Configure image size and format and FPS */
if (ov9650_set_framerate(&ov9650, FRAMERATE_30FPS) != 0) {
goto error;
}
/* Set sensor brightness level -3..+3 */
ov9650_set_brightness(&ov9650, 2);
/* The sensor needs time to stablize especially
when using the automatic functions of the camera */
rgb_led_set_color(LED_GREEN);
systick_sleep(5000);
rgb_led_set_color(LED_BLUE);
#if 0
/* FPS test */
while (1) {
@ -70,10 +61,30 @@ int main(void)
while (1) {
switch (usart_recv()) {
case OV9650_SNAPSHOT: {
case CMD_SET_PIXFORMAT:
/* Configure image size and format and FPS */
if (ov9650_set_pixformat(&ov9650, usart_recv()) != 0) {
goto error;
}
break;
case CMD_SET_FRAMESIZE:
/* Configure image size and format and FPS */
if (ov9650_set_framesize(&ov9650, usart_recv()) != 0) {
goto error;
}
break;
case CMD_SET_FRAMERATE:
/* Configure framerate */
if (ov9650_set_framerate(&ov9650, usart_recv()) != 0) {
goto error;
}
break;
case CMD_SNAPSHOT: {
int i;
struct frame_buffer *fb = &ov9650.frame_buffer;
if (ov9650_snapshot(&ov9650) != 0) {
goto error;
}
@ -83,29 +94,34 @@ int main(void)
}
break;
}
case OV9650_COLOR_TRACK: {
case CMD_COLOR_TRACK: {
struct point point= {0};
struct frame_buffer *fb = &ov9650.frame_buffer;
/* Color struct */
struct color hsv;
#if 0
/* red */
struct color color= {
.h = 0,
.s = 70,
.v = 25
};
#endif
hsv.h = usart_recv();
hsv.s = usart_recv();
hsv.v = usart_recv();
if (ov9650_snapshot(&ov9650) != 0) {
goto error;
}
imlib_color_track(&ov9650.frame_buffer, &color, &point, 10);
imlib_color_track(&ov9650.frame_buffer, &hsv, &point, 10);
/* Send point coords from 0%..100% */
usart_send(point.x*100/fb->width);
usart_send(point.y*100/fb->height);
break;
}
case OV9650_MOTION_DETECTION: {
case CMD_MOTION_DETECTION: {
int i;
int pixels;
struct frame_buffer *fb = &ov9650.frame_buffer;
@ -115,7 +131,7 @@ int main(void)
goto error;
}
if (ov9650.pixfmt != PIXFMT_YUV422) {
if (ov9650.pixformat != PIXFORMAT_YUV422) {
/* Switch sensor to YUV422 to get
a grayscale image from the Y channel */
// if (ov9650_config(&ov9650, OV9650_QQVGA_YUV422, OV9650_30FPS) != 0) {

View File

@ -10,6 +10,8 @@
#include <stm32f4xx_dcmi.h>
#include "sccb.h"
#include "ov9650.h"
#include "systick.h"
#include "ov9650_regs.h"
#define NUM_BR_LEVELS 7
#define DCMI_DR_ADDRESS (DCMI_BASE + 0x28)
#define BREAK() __asm__ volatile ("BKPT")
@ -17,63 +19,64 @@ static volatile int frame_ready = 0;
static uint8_t ov9650_init_regs[][2] = {
/* See Implementation Guide */
{OV9650_COM2, 0x01}, /* Output drive x2 */
{OV9650_COM5, 0x00}, /* System clock */
{OV9650_CLKRC, 0x81}, /* Clock control 30 FPS*/
{OV9650_MVFP, 0x00}, /* Mirror/VFlip */
{REG_COM2, 0x01}, /* Output drive x2 */
{REG_COM5, 0x00}, /* System clock */
{REG_CLKRC, 0x81}, /* Clock control 30 FPS*/
{REG_MVFP, 0x00}, /* Mirror/VFlip */
//{0x22, 0x7f}, // ff/7f/3f/1f for 60/30/15/7.5fps
//{0x23, 0x03}, // 01/03/07/0f for 60/30/15/7.5fps
{OV9650_COM7, 0x14}, /* QVGA/RGB565 */
{OV9650_COM1, 0x24}, /* QQVGA-QQCIF/Skip Option */
{OV9650_COM3, 0x04}, /* Vario Pixels */
{OV9650_COM4, 0x80}, /* Vario Pixels */
{OV9650_COM15, 0xD0}, /* Output range 0x00-0xFF/RGB565*/
/* Default QQVGA-RGB565 */
{REG_COM7, 0x14}, /* QVGA/RGB565 */
{REG_COM1, 0x24}, /* QQVGA/Skip Option */
{REG_COM3, 0x04}, /* Vario Pixels */
{REG_COM4, 0x80}, /* Vario Pixels */
{REG_COM15, 0xD0}, /* Output range 0x00-0xFF/RGB565*/
/* Dummy pixels settings */
{OV9650_EXHCH, 0x00}, /* Dummy Pixel Insert MSB */
{OV9650_EXHCL, 0x00}, /* Dummy Pixel Insert LSB */
{REG_EXHCH, 0x00}, /* Dummy Pixel Insert MSB */
{REG_EXHCL, 0x00}, /* Dummy Pixel Insert LSB */
{OV9650_ADVFH, 0x00}, /* Dummy Pixel Insert MSB */
{OV9650_ADVFL, 0x00}, /* Dummy Pixel Insert LSB */
{REG_ADVFH, 0x00}, /* Dummy Pixel Insert MSB */
{REG_ADVFL, 0x00}, /* Dummy Pixel Insert LSB */
/* See Implementation Guide Section 3.4.1.2 */
{OV9650_COM8, 0xA7}, /* Enable Fast Mode AEC/Auto Banding Filter/AGC/AWB/AEC */
{REG_COM8, 0xA7}, /* Enable Fast Mode AEC/Auto Banding Filter/AGC/AWB/AEC */
{0x60, 0x8C}, /* Normal AWB, 0x0C for Advanced AWB */
{OV9650_AEW, 0x74}, /* AGC/AEC Threshold Upper Limit */
{OV9650_AEB, 0x68}, /* AGC/AEC Threshold Lower Limit */
{OV9650_VPT, 0xC3}, /* Fast AEC operating region */
{REG_AEW, 0x74}, /* AGC/AEC Threshold Upper Limit */
{REG_AEB, 0x68}, /* AGC/AEC Threshold Lower Limit */
{REG_VPT, 0xC3}, /* Fast AEC operating region */
/* See OV9650 Implementation Guide */
{OV9650_CHLF, 0xE2}, /* External Regulator */
{OV9650_GRCOM, 0x3F}, /* Analog BLC/External Regulator */
{REG_CHLF, 0xE2}, /* External Regulator */
{REG_GRCOM, 0x3F}, /* Analog BLC/External Regulator */
/* See OV9650 Implementation Guide */
{OV9650_COM11, 0x01}, /* Automatic/Manual Banding Filter */
{OV9650_MBD, 0x1a}, /* Manual banding filter LSB */
{OV9650_COM12, 0x04}, /* HREF options/ UV average */
{OV9650_COM9, 0x48}, /* Gain ceiling [6:4]/Over-Exposure */
{OV9650_COM16, 0x02}, /* Color matrix coeff double option */
{OV9650_COM13, 0x10}, /* Gamma/Colour Matrix/UV delay */
{OV9650_COM23, 0x00}, /* Disable Color bar/Analog Color Gain */
{OV9650_PSHFT, 0x00}, /* Pixel delay after HREF */
{OV9650_COM10, 0x00}, /* Slave mode, HREF vs HSYNC, signals negate */
{OV9650_EDGE, 0xa6}, /* Edge enhancement treshhold and factor */
{OV9650_COM6, 0x43}, /* HREF & ADBLC options */
{OV9650_COM22, 0x00}, /* Edge enhancement/Denoising */
{REG_COM11, 0x01}, /* Automatic/Manual Banding Filter */
{REG_MBD, 0x1a}, /* Manual banding filter LSB */
{REG_COM12, 0x04}, /* HREF options/ UV average */
{REG_COM9, 0x48}, /* Gain ceiling [6:4]/Over-Exposure */
{REG_COM16, 0x02}, /* Color matrix coeff double option */
{REG_COM13, 0x10}, /* Gamma/Colour Matrix/UV delay */
{REG_COM23, 0x00}, /* Disable Color bar/Analog Color Gain */
{REG_PSHFT, 0x00}, /* Pixel delay after HREF */
{REG_COM10, 0x00}, /* Slave mode, HREF vs HSYNC, signals negate */
{REG_EDGE, 0xa6}, /* Edge enhancement treshhold and factor */
{REG_COM6, 0x43}, /* HREF & ADBLC options */
{REG_COM22, 0x00}, /* Edge enhancement/Denoising */
// {OV9650_AECH, 0x00}, /* Exposure Value MSB */
// {OV9650_AECHM, 0x00}, /* Exposure Value LSB */
// {REG_AECH, 0x00}, /* Exposure Value MSB */
// {REG_AECHM, 0x00}, /* Exposure Value LSB */
#if 0
/* Windowing Settings */
{OV9650_HSTART, 0x1d}, /* Horiz start high bits */
{OV9650_HSTOP, 0xbd}, /* Horiz stop high bits */
{OV9650_HREF, 0xbf}, /* HREF pieces */
{REG_HSTART, 0x1d}, /* Horiz start high bits */
{REG_HSTOP, 0xbd}, /* Horiz stop high bits */
{REG_HREF, 0xbf}, /* HREF pieces */
{OV9650_VSTART, 0x00}, /* Vert start high bits */
{OV9650_VSTOP, 0x80}, /* Vert stop high bits */
{OV9650_VREF, 0x12}, /* Pieces of GAIN, VSTART, VSTOP */
{REG_VSTART, 0x00}, /* Vert start high bits */
{REG_VSTOP, 0x80}, /* Vert stop high bits */
{REG_VREF, 0x12}, /* Pieces of GAIN, VSTART, VSTOP */
#endif
/* Gamma curve P */
@ -137,43 +140,41 @@ static uint8_t ov9650_init_regs[][2] = {
static uint8_t ov9650_rgb565_regs[][2] = {
/* See Implementation Guide */
{OV9650_COM7, 0x14}, /* QVGA/RGB565 */
{OV9650_COM1, 0x24}, /* QQVGA-QQCIF/Skip Option */
{OV9650_COM3, 0x04}, /* Vario Pixels */
{OV9650_COM4, 0x80}, /* Vario Pixels */
{OV9650_COM15, 0xD0}, /* Output range 0x00-0xFF/RGB565*/
{REG_COM3, 0x04}, /* Vario Pixels */
{REG_COM4, 0x80}, /* Vario Pixels */
{REG_COM15, 0xD0}, /* Output range 0x00-0xFF/RGB565*/
/* See Implementation Guide Section 3.4.1.2 */
#if 0
{OV9650_OFON, 0x43}, /* Power down register */
{OV9650_ACOM38, 0x12}, /* reserved */
{OV9650_ADC, 0x00}, /* reserved */
{OV9650_RSVD35, 0x91}, /* reserved */
{REG_OFON, 0x43}, /* Power down register */
{REG_ACOM38, 0x12}, /* reserved */
{REG_ADC, 0x00}, /* reserved */
{REG_RSVD35, 0x91}, /* reserved */
#else
/* for higher frame rates */
{OV9650_OFON, 0x50}, /* Power down register */
{OV9650_ACOM38, 0x12}, /* reserved */
{OV9650_ADC, 0x00}, /* reserved */
{OV9650_RSVD35, 0x81}, /* reserved */
{REG_OFON, 0x50}, /* Power down register */
{REG_ACOM38, 0x12}, /* reserved */
{REG_ADC, 0x00}, /* reserved */
{REG_RSVD35, 0x81}, /* reserved */
#endif
/* YUV fmt /Special Effects Controls */
{OV9650_TSLB, 0x01}, /* YUVU/DBLC Enable */
{OV9650_MANU, 0xC0}, /* Manual U */
{OV9650_MANV, 0x80}, /* Manual V */
{REG_TSLB, 0x01}, /* YUVU/DBLC Enable */
{REG_MANU, 0xC0}, /* Manual U */
{REG_MANV, 0x80}, /* Manual V */
/* RGB color matrix */
{OV9650_MTX1, 0x71},
{OV9650_MTX2, 0x3e},
{OV9650_MTX3, 0x0c},
{REG_MTX1, 0x71},
{REG_MTX2, 0x3e},
{REG_MTX3, 0x0c},
{OV9650_MTX4, 0x33},
{OV9650_MTX5, 0x72},
{OV9650_MTX6, 0x00},
{REG_MTX4, 0x33},
{REG_MTX5, 0x72},
{REG_MTX6, 0x00},
{OV9650_MTX7, 0x2b},
{OV9650_MTX8, 0x66},
{OV9650_MTX9, 0xd2},
{OV9650_MTXS, 0x65},
{REG_MTX7, 0x2b},
{REG_MTX8, 0x66},
{REG_MTX9, 0xd2},
{REG_MTXS, 0x65},
/* NULL reg */
{0x00, 0x00}
@ -181,36 +182,34 @@ static uint8_t ov9650_rgb565_regs[][2] = {
static uint8_t ov9650_yuv422_regs[][2] = {
/* See Implementation Guide */
{OV9650_COM7, 0x10}, /* QVGA */
{OV9650_COM1, 0x24}, /* QQVGA-QQCIF/Skip Option */
{OV9650_COM3, 0x04}, /* Vario Pixels */
{OV9650_COM4, 0x80}, /* Vario Pixels */
{OV9650_COM15, 0xC0}, /* Output range 0x00-0xFF */
{REG_COM3, 0x04}, /* Vario Pixels */
{REG_COM4, 0x80}, /* Vario Pixels */
{REG_COM15, 0xC0}, /* Output range 0x00-0xFF */
/* See Implementation Guide Section 3.4.1.2 */
{OV9650_OFON, 0x50}, /* Power down register */
{OV9650_ACOM38, 0x12}, /* reserved */
{OV9650_ADC, 0x00}, /* reserved */
{OV9650_RSVD35, 0x81}, /* reserved */
{REG_OFON, 0x50}, /* Power down register */
{REG_ACOM38, 0x12}, /* reserved */
{REG_ADC, 0x00}, /* reserved */
{REG_RSVD35, 0x81}, /* reserved */
/* YUV fmt /Special Effects Controls */
{OV9650_TSLB, 0x01}, /* YUVU/DBLC Enable */
{OV9650_MANU, 0xC0}, /* Manual U */
{OV9650_MANV, 0x80}, /* Manual V */
{REG_TSLB, 0x01}, /* YUVU/DBLC Enable */
{REG_MANU, 0xC0}, /* Manual U */
{REG_MANV, 0x80}, /* Manual V */
/* YUV color matrix */
{OV9650_MTX1, 0x3a},
{OV9650_MTX2, 0x3d},
{OV9650_MTX3, 0x03},
{REG_MTX1, 0x3a},
{REG_MTX2, 0x3d},
{REG_MTX3, 0x03},
{OV9650_MTX4, 0x12},
{OV9650_MTX5, 0x26},
{OV9650_MTX6, 0x38},
{REG_MTX4, 0x12},
{REG_MTX5, 0x26},
{REG_MTX6, 0x38},
{OV9650_MTX7, 0x40},
{OV9650_MTX8, 0x40},
{OV9650_MTX9, 0x40},
{OV9650_MTXS, 0x0d},
{REG_MTX7, 0x40},
{REG_MTX8, 0x40},
{REG_MTX9, 0x40},
{REG_MTXS, 0x0d},
/* NULL reg */
{0x00, 0x00}
@ -536,33 +535,33 @@ int ov9650_init(struct ov9650_handle *ov9650)
bzero(ov9650, sizeof(struct ov9650_handle));
/* read sensor id */
ov9650->id.MIDH = SCCB_Read(OV9650_MIDH);
ov9650->id.MIDL = SCCB_Read(OV9650_MIDL);
ov9650->id.PID = SCCB_Read(OV9650_PID);
ov9650->id.VER = SCCB_Read(OV9650_VER);
ov9650->id.MIDH = SCCB_Read(REG_MIDH);
ov9650->id.MIDL = SCCB_Read(REG_MIDL);
ov9650->id.PID = SCCB_Read(REG_PID);
ov9650->id.VER = SCCB_Read(REG_VER);
return 0;
}
void ov9650_reset(struct ov9650_handle *ov9650)
{
SCCB_Write(OV9650_COM7, 0x80);
SCCB_Write(REG_COM7, 0x80);
systick_sleep(500);
}
int ov9650_set_pixfmt(struct ov9650_handle *ov9650, enum ov9650_pixfmt pixfmt)
int ov9650_set_pixformat(struct ov9650_handle *ov9650, enum ov9650_pixformat pixformat)
{
int i=0;
uint8_t (*regs)[2];
struct frame_buffer *fb = &ov9650->frame_buffer;
ov9650->pixfmt = pixfmt;
switch (pixfmt) {
case PIXFMT_RGB565:
ov9650->pixformat = pixformat;
switch (pixformat) {
case PIXFORMAT_RGB565:
fb->bpp = 2;
regs = ov9650_rgb565_regs;
break;
case PIXFMT_YUV422:
case PIXFORMAT_YUV422:
fb->bpp = 2;
regs = ov9650_yuv422_regs;
break;
@ -587,15 +586,38 @@ int ov9650_set_framesize(struct ov9650_handle *ov9650, enum ov9650_framesize fra
ov9650->framesize = framesize;
struct frame_buffer *fb = &ov9650->frame_buffer;
uint8_t com7=0x00;
uint8_t com1=0x04; /* Skip option */
switch (framesize) {
case FRAMESIZE_QQCIF:
fb->width = 88;
fb->height = 72;
com7 |= REG_COM7_QCIF;
com1 |= REG_COM1_QQCIF;
break;
case FRAMESIZE_QQVGA:
fb->width = 160;
fb->height = 120;
com7 |= REG_COM7_QVGA;
com1 |= REG_COM1_QQVGA;
break;
case FRAMESIZE_QCIF:
fb->width = 176;
fb->height = 144;
com7 |= REG_COM7_QCIF;
break;
default:
return -1;
}
if (ov9650->pixformat == PIXFORMAT_RGB565) {
com7 |= REG_COM7_RGB;
}
SCCB_Write(REG_COM1, com1);
SCCB_Write(REG_COM7, com7);
/* realloc frame buffer */
fb->pixels = realloc(fb->pixels,
fb->width * fb->height * fb->bpp);
@ -606,14 +628,6 @@ int ov9650_set_framesize(struct ov9650_handle *ov9650, enum ov9650_framesize fra
/* Reconfigure the DMA stream */
dma_config(fb->pixels, fb->width * fb->height * fb->bpp);
#include "rgb_led.h"
/* The sensor needs time to stablize especially
when using the automatic functions of the camera */
rgb_led_set_color(LED_GREEN);
systick_sleep(5000);
rgb_led_set_color(LED_BLUE);
return 0;
}
@ -621,9 +635,9 @@ int ov9650_set_framerate(struct ov9650_handle *ov9650, enum ov9650_framerate fra
{
ov9650->framerate=framerate;
/* Write framerate register */
SCCB_Write(OV9650_CLKRC, framerate);
while (SCCB_Read(OV9650_CLKRC) != framerate) {
SCCB_Write(OV9650_CLKRC, framerate);
SCCB_Write(REG_CLKRC, framerate);
while (SCCB_Read(REG_CLKRC) != framerate) {
SCCB_Write(REG_CLKRC, framerate);
}
return 0;
}
@ -632,7 +646,7 @@ int ov9650_set_brightness(struct ov9650_handle *ov9650, int level)
{
int i;
static uint8_t regs[NUM_BR_LEVELS + 1][3] = {
{ OV9650_AEW, OV9650_AEB, OV9650_VPT },
{ REG_AEW, REG_AEB, REG_VPT },
{ 0x1c, 0x12, 0x50 }, /* -3 */
{ 0x3d, 0x30, 0x71 }, /* -2 */
{ 0x50, 0x44, 0x92 }, /* -1 */
@ -657,16 +671,16 @@ int ov9650_set_brightness(struct ov9650_handle *ov9650, int level)
int ov9650_set_exposure(struct ov9650_handle *ov9650, uint16_t exposure)
{
uint8_t val;
val = SCCB_Read(OV9650_COM1);
val = SCCB_Read(REG_COM1);
/* exposure [1:0] */
SCCB_Write(OV9650_COM1, val | (exposure&0x03));
SCCB_Write(REG_COM1, val | (exposure&0x03));
/* exposure [9:2] */
SCCB_Write(OV9650_AECH, ((exposure>>2)&0xFF));
SCCB_Write(REG_AECH, ((exposure>>2)&0xFF));
/* exposure [15:10] */
SCCB_Write(OV9650_AECHM, ((exposure>>10)&0x3F));
SCCB_Write(REG_AECHM, ((exposure>>10)&0x3F));
return 0;
}

View File

@ -2,114 +2,9 @@
#define __OV9650_H__
#include <stdint.h>
#include "imlib.h"
/* OV9650 Registers definition */
#define OV9650_GAIN 0x00
#define OV9650_BLUE 0x01
#define OV9650_RED 0x02
#define OV9650_VREF 0x03
#define OV9650_COM1 0x04
#define OV9650_BAVE 0x05
#define OV9650_GEAVE 0x06
#define OV9650_RAVE 0x08
#define OV9650_COM2 0x09
#define OV9650_PID 0x0A
#define OV9650_VER 0x0B
#define OV9650_COM3 0x0C
#define OV9650_COM4 0x0D
#define OV9650_COM5 0x0E
#define OV9650_COM6 0x0F
#define OV9650_AECH 0x10
#define OV9650_CLKRC 0x11
#define OV9650_COM7 0x12
#define OV9650_COM8 0x13
#define OV9650_COM9 0x14
#define OV9650_COM10 0x15
#define OV9650_RSVD16 0x16
#define OV9650_HSTART 0x17
#define OV9650_HSTOP 0x18
#define OV9650_VSTART 0x19
#define OV9650_VSTOP 0x1A
#define OV9650_PSHFT 0x1B
#define OV9650_MIDH 0x1C
#define OV9650_MIDL 0x1D
#define OV9650_MVFP 0x1E
#define OV9650_BOS 0x20
#define OV9650_GBOS 0x21
#define OV9650_GROS 0x22
#define OV9650_ROS 0x23
#define OV9650_AEW 0x24
#define OV9650_AEB 0x25
#define OV9650_VPT 0x26
#define OV9650_BBIAS 0x27
#define OV9650_GbBIAS 0x28
#define OV9650_GRCOM 0x29
#define OV9650_EXHCH 0x2A
#define OV9650_EXHCL 0x2B
#define OV9650_RBIAS 0x2C
#define OV9650_ADVFL 0x2D
#define OV9650_ADVFH 0x2E
#define OV9650_YAVE 0x2F
#define OV9650_HSYST 0x30
#define OV9650_HSYEN 0x31
#define OV9650_HREF 0x32
#define OV9650_CHLF 0x33
#define OV9650_ARBLM 0x34
#define OV9650_RSVD35 0x35
#define OV9650_RSVD36 0x36
#define OV9650_ADC 0x37
#define OV9650_ACOM38 0x38
#define OV9650_OFON 0x39
#define OV9650_TSLB 0x3A
#define OV9650_COM11 0x3B
#define OV9650_COM12 0x3C
#define OV9650_COM13 0x3D
#define OV9650_COM14 0x3E
#define OV9650_EDGE 0x3F
#define OV9650_COM15 0x40
#define OV9650_COM16 0x41
#define OV9650_COM17 0x42
#define OV9650_MTX1 0x4F
#define OV9650_MTX2 0x50
#define OV9650_MTX3 0x51
#define OV9650_MTX4 0x52
#define OV9650_MTX5 0x53
#define OV9650_MTX6 0x54
#define OV9650_MTX7 0x55
#define OV9650_MTX8 0x56
#define OV9650_MTX9 0x57
#define OV9650_MTXS 0x58
#define OV9650_LCC1 0x62
#define OV9650_LCC2 0x63
#define OV9650_LCC3 0x64
#define OV9650_LCC4 0x65
#define OV9650_LCC5 0x66
#define OV9650_MANU 0x67
#define OV9650_MANV 0x68
#define OV9650_HV 0x69
#define OV9650_MBD 0x6A
#define OV9650_DBLV 0x6B
#define OV9650_COM21 0x8B
#define OV9650_COM22 0x8C
#define OV9650_COM23 0x8D
#define OV9650_COM24 0x8E
#define OV9650_DBLC1 0x8F
#define OV9650_DBLC_B 0x90
#define OV9650_DBLC_R 0x91
#define OV9650_DMLNL 0x92
#define OV9650_DMLNH 0x93
#define OV9650_LCCFB 0x9D
#define OV9650_LCCFR 0x9E
#define OV9650_DBLC_GB 0x9F
#define OV9650_DBLC_GR 0xA0
#define OV9650_AECHM 0xA1
#define OV9650_COM25 0xA4
#define OV9650_COM26 0xA5
#define OV9650_GGAIN 0xA6
#define OV9650_VGAST 0xA7
enum ov9650_pixfmt {
PIXFMT_RGB565, /* 2BPP/RGB565*/
PIXFMT_YUV422, /* 2BPP/YUV422*/
enum ov9650_pixformat {
PIXFORMAT_RGB565, /* 2BPP/RGB565*/
PIXFORMAT_YUV422, /* 2BPP/YUV422*/
};
enum ov9650_framesize {
@ -130,10 +25,13 @@ enum ov9650_framerate {
FRAMERATE_60FPS=0x80,
};
enum ov9650_commands {
OV9650_SNAPSHOT=1,
OV9650_COLOR_TRACK,
OV9650_MOTION_DETECTION,
enum ov9650_command {
CMD_SNAPSHOT=1,
CMD_COLOR_TRACK,
CMD_MOTION_DETECTION,
CMD_SET_PIXFORMAT,
CMD_SET_FRAMERATE,
CMD_SET_FRAMESIZE,
};
struct ov9650_id {
@ -145,7 +43,7 @@ struct ov9650_id {
struct ov9650_handle {
struct ov9650_id id;
enum ov9650_pixfmt pixfmt;
enum ov9650_pixformat pixformat;
enum ov9650_framesize framesize;
enum ov9650_framerate framerate;
struct frame_buffer frame_buffer;
@ -155,9 +53,9 @@ struct ov9650_handle {
int ov9650_init(struct ov9650_handle *ov9650);
/* Reset sensor */
void ov9650_reset(struct ov9650_handle *ov9650);
int ov9650_set_pixfmt(struct ov9650_handle *ov9650, enum ov9650_pixfmt pixfmt);
int ov9650_set_framerate(struct ov9650_handle *ov9650, enum ov9650_framerate framerate);
int ov9650_set_pixformat(struct ov9650_handle *ov9650, enum ov9650_pixformat pixformat);
int ov9650_set_framesize(struct ov9650_handle *ov9650, enum ov9650_framesize framesize);
int ov9650_set_framerate(struct ov9650_handle *ov9650, enum ov9650_framerate framerate);
int ov9650_set_brightness(struct ov9650_handle *ov9650, int level);
int ov9650_set_exposure(struct ov9650_handle *ov9650, uint16_t exposure);
int ov9650_snapshot(struct ov9650_handle *ov9650);

115
src/ov9650_regs.h Normal file
View File

@ -0,0 +1,115 @@
#ifndef __REG_REGS_H__
#define __REG_REGS_H__
/* OV9650 Registers definition */
#define REG_GAIN 0x00
#define REG_BLUE 0x01
#define REG_RED 0x02
#define REG_VREF 0x03
#define REG_COM1 0x04
#define REG_BAVE 0x05
#define REG_GEAVE 0x06
#define REG_RAVE 0x08
#define REG_COM2 0x09
#define REG_PID 0x0A
#define REG_VER 0x0B
#define REG_COM3 0x0C
#define REG_COM4 0x0D
#define REG_COM5 0x0E
#define REG_COM6 0x0F
#define REG_AECH 0x10
#define REG_CLKRC 0x11
#define REG_COM7 0x12
#define REG_COM8 0x13
#define REG_COM9 0x14
#define REG_COM10 0x15
#define REG_RSVD16 0x16
#define REG_HSTART 0x17
#define REG_HSTOP 0x18
#define REG_VSTART 0x19
#define REG_VSTOP 0x1A
#define REG_PSHFT 0x1B
#define REG_MIDH 0x1C
#define REG_MIDL 0x1D
#define REG_MVFP 0x1E
#define REG_BOS 0x20
#define REG_GBOS 0x21
#define REG_GROS 0x22
#define REG_ROS 0x23
#define REG_AEW 0x24
#define REG_AEB 0x25
#define REG_VPT 0x26
#define REG_BBIAS 0x27
#define REG_GbBIAS 0x28
#define REG_GRCOM 0x29
#define REG_EXHCH 0x2A
#define REG_EXHCL 0x2B
#define REG_RBIAS 0x2C
#define REG_ADVFL 0x2D
#define REG_ADVFH 0x2E
#define REG_YAVE 0x2F
#define REG_HSYST 0x30
#define REG_HSYEN 0x31
#define REG_HREF 0x32
#define REG_CHLF 0x33
#define REG_ARBLM 0x34
#define REG_RSVD35 0x35
#define REG_RSVD36 0x36
#define REG_ADC 0x37
#define REG_ACOM38 0x38
#define REG_OFON 0x39
#define REG_TSLB 0x3A
#define REG_COM11 0x3B
#define REG_COM12 0x3C
#define REG_COM13 0x3D
#define REG_COM14 0x3E
#define REG_EDGE 0x3F
#define REG_COM15 0x40
#define REG_COM16 0x41
#define REG_COM17 0x42
#define REG_MTX1 0x4F
#define REG_MTX2 0x50
#define REG_MTX3 0x51
#define REG_MTX4 0x52
#define REG_MTX5 0x53
#define REG_MTX6 0x54
#define REG_MTX7 0x55
#define REG_MTX8 0x56
#define REG_MTX9 0x57
#define REG_MTXS 0x58
#define REG_LCC1 0x62
#define REG_LCC2 0x63
#define REG_LCC3 0x64
#define REG_LCC4 0x65
#define REG_LCC5 0x66
#define REG_MANU 0x67
#define REG_MANV 0x68
#define REG_HV 0x69
#define REG_MBD 0x6A
#define REG_DBLV 0x6B
#define REG_COM21 0x8B
#define REG_COM22 0x8C
#define REG_COM23 0x8D
#define REG_COM24 0x8E
#define REG_DBLC1 0x8F
#define REG_DBLC_B 0x90
#define REG_DBLC_R 0x91
#define REG_DMLNL 0x92
#define REG_DMLNH 0x93
#define REG_LCCFB 0x9D
#define REG_LCCFR 0x9E
#define REG_DBLC_GB 0x9F
#define REG_DBLC_GR 0xA0
#define REG_AECHM 0xA1
#define REG_COM25 0xA4
#define REG_COM26 0xA5
#define REG_GGAIN 0xA6
#define REG_VGAST 0xA7
/* register bits */
#define REG_COM1_QQCIF (1<<5)
#define REG_COM1_QQVGA (1<<5)
#define REG_COM7_RGB (1<<2)
#define REG_COM7_QCIF (1<<3)
#define REG_COM7_QVGA (1<<4)
#define REG_COM7_CIF (1<<5)
#define REG_COM7_VGA (1<<6)
#endif //__REG_REGS_H__