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https://github.com/openmv/openmv.git
synced 2025-11-04 14:49:50 +08:00
drivers: Make all spi based py modules cross platform.
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@ -163,7 +163,6 @@
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#define OMV_LINE_BUF_SIZE (3 * 1024) // Image line buffer round(640 * 2BPP * 2 buffers).
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#define OMV_MSC_BUF_SIZE (2K) // USB MSC bot data
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#define OMV_VFS_BUF_SIZE (1K) // VFS struct + FATFS file buffer (624 bytes)
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#define OMV_FIR_LEPTON_BUF_SIZE (1K) // FIR Lepton Packet Double Buffer (328 bytes)
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#define OMV_JPEG_BUF_SIZE (32 * 1024) // IDE JPEG buffer (header + data).
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// Memory map.
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@ -227,8 +226,8 @@
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#define FIR_I2C_SPEED (OMV_I2C_SPEED_FULL)
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// Soft I2C bus
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#define SOFT_I2C_SIOC_PIN (&omv_pin_C10_GPIO)
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#define SOFT_I2C_SIOD_PIN (&omv_pin_C11_GPIO)
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#define SOFT_I2C_SIOC_PIN (&omv_pin_B8_GPIO)
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#define SOFT_I2C_SIOD_PIN (&omv_pin_B9_GPIO)
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#define SOFT_I2C_SPIN_DELAY 64
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// IMU SPI bus
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@ -287,7 +286,8 @@
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#define AUDIO_DFSDM_CLK_DISABLE() __HAL_RCC_DFSDM1_CLK_DISABLE()
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#define AUDIO_DFSDM_DMA_CLK_ENABLE() __HAL_RCC_DMA1_CLK_ENABLE()
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// Physical I2C buses
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// Physical I2C buses.
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// I2C bus 1
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#define I2C1_ID (1)
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#define I2C1_SCL_PIN (&omv_pin_B8_I2C1)
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@ -299,6 +299,16 @@
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#define I2C3_SDA_PIN (&omv_pin_C9_I2C3)
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// Physical SPI buses.
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// SPI bus 4
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#define SPI4_ID (4)
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#define SPI4_SCLK_PIN (&omv_pin_E12_SPI4)
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#define SPI4_MISO_PIN (&omv_pin_E13_SPI4)
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#define SPI4_MOSI_PIN (&omv_pin_E14_SPI4)
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#define SPI4_SSEL_PIN (&omv_pin_E11_SPI4)
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#define SPI4_DMA_TX_CHANNEL (DMA2_Stream4)
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#define SPI4_DMA_RX_CHANNEL (DMA2_Stream3)
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// SPI bus 5
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#define SPI5_ID (5)
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#define SPI5_SCLK_PIN (&omv_pin_F7_SPI5)
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@ -309,33 +319,20 @@
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#define SPI5_DMA_RX_CHANNEL (DMA2_Stream3)
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// SPI LCD Interface
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#define OMV_SPI_LCD_CONTROLLER (&spi_obj[3])
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#define OMV_SPI_LCD_CONTROLLER_INSTANCE (SPI4)
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#define OMV_SPI_LCD_SPI_BUS (SPI4_ID)
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#define OMV_SPI_LCD_MOSI_PIN (&omv_pin_E14_SPI4)
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#define OMV_SPI_LCD_MISO_PIN (&omv_pin_E13_SPI4)
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#define OMV_SPI_LCD_SCLK_PIN (&omv_pin_E12_SPI4)
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#define OMV_SPI_LCD_SSEL_PIN (&omv_pin_E11_GPIO)
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#define OMV_SPI_LCD_RS_PIN (&omv_pin_C11_GPIO)
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//#define OMV_SPI_LCD_BL_PIN (&omv_pin_A4_GPIO)
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#define OMV_SPI_LCD_RST_PIN (&omv_pin_C10_GPIO)
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#ifdef OMV_SPI_LCD_BL_PIN
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#define OMV_SPI_LCD_BL_DAC (DAC1)
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#define OMV_SPI_LCD_BL_DAC_CHANNEL (DAC_CHANNEL_1)
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#define OMV_SPI_LCD_BL_DAC_CLK_ENABLE() __HAL_RCC_DAC12_CLK_ENABLE()
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#define OMV_SPI_LCD_BL_DAC_CLK_DISABLE() __HAL_RCC_DAC12_CLK_DISABLE()
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#define OMV_SPI_LCD_BL_DAC_FORCE_RESET() __HAL_RCC_DAC12_FORCE_RESET()
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#define OMV_SPI_LCD_BL_DAC_RELEASE_RESET() __HAL_RCC_DAC12_RELEASE_RESET()
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#endif
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#define OMV_SPI_LCD_RS_PIN (&omv_pin_G12_GPIO)
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#define OMV_SPI_LCD_RST_PIN (&omv_pin_G1_GPIO)
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// FIR Lepton
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#define OMV_FIR_LEPTON_I2C_BUS (FIR_I2C_ID)
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#define OMV_FIR_LEPTON_I2C_BUS_SPEED (FIR_I2C_SPEED)
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#define OMV_FIR_LEPTON_CONTROLLER (&spi_obj[3])
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#define OMV_FIR_LEPTON_CONTROLLER_INSTANCE (SPI4)
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#define OMV_FIR_LEPTON_SPI_BUS (SPI4_ID)
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#define OMV_FIR_LEPTON_MOSI_PIN (&omv_pin_E14_SPI4)
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#define OMV_FIR_LEPTON_MISO_PIN (&omv_pin_E13_SPI4)
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#define OMV_FIR_LEPTON_SCLK_PIN (&omv_pin_E12_SPI4)
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@ -5,15 +5,15 @@ OMV_GPIO_DEFINE(A, 7, AF2, TIM3)
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OMV_GPIO_DEFINE(A, 8, AF4, I2C3)
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OMV_GPIO_DEFINE(A, 10, NONE, GPIO)
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OMV_GPIO_DEFINE(B, 4, NONE, GPIO)
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OMV_GPIO_DEFINE(B, 8, NONE, GPIO)
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OMV_GPIO_DEFINE(B, 8, AF4, I2C1)
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OMV_GPIO_DEFINE(B, 9, NONE, GPIO)
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OMV_GPIO_DEFINE(B, 9, AF4, I2C1)
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OMV_GPIO_DEFINE(C, 0, AF10, OTG_HS)
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OMV_GPIO_DEFINE(C, 2, AF10, OTG_HS)
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OMV_GPIO_DEFINE(C, 6, AF13, DCMI)
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OMV_GPIO_DEFINE(C, 7, AF13, DCMI)
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OMV_GPIO_DEFINE(C, 9, AF4, I2C3)
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OMV_GPIO_DEFINE(C, 10, NONE, GPIO)
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OMV_GPIO_DEFINE(C, 11, NONE, GPIO)
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OMV_GPIO_DEFINE(D, 3, AF13, DCMI)
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OMV_GPIO_DEFINE(D, 10, AF3, DFSDM1)
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OMV_GPIO_DEFINE(E, 0, AF13, DCMI)
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@ -23,6 +23,7 @@ OMV_GPIO_DEFINE(E, 5, AF13, DCMI)
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OMV_GPIO_DEFINE(E, 6, AF13, DCMI)
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OMV_GPIO_DEFINE(E, 7, AF3, DFSDM1)
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OMV_GPIO_DEFINE(E, 11, NONE, GPIO)
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OMV_GPIO_DEFINE(E, 11, AF5, SPI4)
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OMV_GPIO_DEFINE(E, 12, AF5, SPI4)
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OMV_GPIO_DEFINE(E, 13, AF5, SPI4)
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OMV_GPIO_DEFINE(E, 14, AF5, SPI4)
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@ -30,5 +31,7 @@ OMV_GPIO_DEFINE(F, 6, AF5, SPI5)
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OMV_GPIO_DEFINE(F, 7, AF5, SPI5)
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OMV_GPIO_DEFINE(F, 8, AF5, SPI5)
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OMV_GPIO_DEFINE(F, 11, AF5, SPI5)
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OMV_GPIO_DEFINE(G, 1, NONE, GPIO)
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OMV_GPIO_DEFINE(G, 3, NONE, GPIO)
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OMV_GPIO_DEFINE(G, 9, AF13, DCMI)
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OMV_GPIO_DEFINE(G, 12, NONE, GPIO)
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@ -178,7 +178,6 @@
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#define OMV_LINE_BUF_SIZE (11 * 1024) // Image line buffer round(2592 * 2BPP * 2 buffers).
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#define OMV_MSC_BUF_SIZE (2K) // USB MSC bot data
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#define OMV_VFS_BUF_SIZE (1K) // VFS struct + FATFS file buffer (624 bytes)
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#define OMV_FIR_LEPTON_BUF_SIZE (1K) // FIR Lepton Packet Double Buffer (328 bytes)
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#define OMV_JPEG_BUF_SIZE (1024 * 1024) // IDE JPEG buffer (header + data).
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// Memory map.
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@ -240,13 +239,14 @@
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#define ISC_I2C_ALT_ID (4)
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#define ISC_I2C_ALT_SPEED (OMV_I2C_SPEED_STANDARD)
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// FIR I2C
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// Thermal image sensor I2C bus
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#define FIR_I2C_ID (3)
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#define FIR_I2C_SPEED (OMV_I2C_SPEED_STANDARD)
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//#define SOFT_I2C_SIOC_PIN (&omv_pin_B10_GPIO)
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//#define SOFT_I2C_SIOD_PIN (&omv_pin_B11_GPIO)
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//#define SOFT_I2C_SPIN_DELAY 64
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// Soft I2C bus
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//#define SOFT_I2C_SIOC_PIN (&omv_pin_PH7_GPIO)
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//#define SOFT_I2C_SIOD_PIN (&omv_pin_PH8_GPIO)
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//#define SOFT_I2C_SPIN_DELAY 64
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// GPIO.0 is connected to the sensor module reset pin on the Portenta
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// breakout board and to the LDO's LDO_ENABLE pin on the Himax shield.
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@ -288,6 +288,7 @@
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#define DCMI_PXCLK_PIN (&omv_pin_A6_DCMI)
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// Physical I2C buses.
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// I2C bus 3
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#define I2C3_ID (3)
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#define I2C3_SCL_PIN (&omv_pin_H7_I2C3)
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@ -298,6 +299,17 @@
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#define I2C4_SCL_PIN (&omv_pin_H11_I2C4)
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#define I2C4_SDA_PIN (&omv_pin_H12_I2C4)
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// Physical SPI buses.
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// SPI bus 2
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#define SPI2_ID (2)
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#define SPI2_SCLK_PIN (&omv_pin_I1_SPI2)
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#define SPI2_MISO_PIN (&omv_pin_C2_SPI2)
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#define SPI2_MOSI_PIN (&omv_pin_C3_SPI2)
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#define SPI2_SSEL_PIN (&omv_pin_I0_SPI2)
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#define SPI2_DMA_TX_CHANNEL (DMA1_Stream4)
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#define SPI2_DMA_RX_CHANNEL (DMA1_Stream3)
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// SAI4
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#define AUDIO_SAI (SAI4_Block_A)
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// SCKx frequency = SAI_KER_CK / MCKDIV / 2
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@ -351,31 +363,22 @@
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#define OMV_DSI_RELEASE_RESET() __HAL_RCC_DSI_RELEASE_RESET()
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// SPI LCD Interface
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#define OMV_SPI_LCD_CONTROLLER (&spi_obj[1])
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#define OMV_SPI_LCD_CONTROLLER_INSTANCE (SPI2)
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#define OMV_SPI_LCD_SPI_BUS (SPI2_ID)
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#define OMV_SPI_LCD_MOSI_PIN (&omv_pin_C3_SPI2)
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#define OMV_SPI_LCD_MISO_PIN (&omv_pin_C2_SPI2)
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#define OMV_SPI_LCD_SCLK_PIN (&omv_pin_I1_SPI2)
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#define OMV_SPI_LCD_SSEL_PIN (&omv_pin_I0_GPIO)
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#define OMV_SPI_LCD_RS_PIN (&omv_pin_K1_GPIO)
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#define OMV_SPI_LCD_BL_PIN (&omv_pin_A4_GPIO)
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#define OMV_SPI_LCD_RST_PIN (&omv_pin_H15_GPIO)
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#define OMV_SPI_LCD_RS_PIN (&omv_pin_C6_GPIO)
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#define OMV_SPI_LCD_RST_PIN (&omv_pin_C7_GPIO)
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#define OMV_SPI_LCD_BL_DAC (DAC1)
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#define OMV_SPI_LCD_BL_DAC_CHANNEL (DAC_CHANNEL_1)
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#define OMV_SPI_LCD_BL_DAC_CLK_ENABLE() __HAL_RCC_DAC12_CLK_ENABLE()
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#define OMV_SPI_LCD_BL_DAC_CLK_DISABLE() __HAL_RCC_DAC12_CLK_DISABLE()
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#define OMV_SPI_LCD_BL_DAC_FORCE_RESET() __HAL_RCC_DAC12_FORCE_RESET()
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#define OMV_SPI_LCD_BL_DAC_RELEASE_RESET() __HAL_RCC_DAC12_RELEASE_RESET()
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#define OMV_SPI_LCD_DEF_TRIPLE_BUF (true)
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// FIR Lepton
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#define OMV_FIR_LEPTON_I2C_BUS (FIR_I2C_ID)
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#define OMV_FIR_LEPTON_I2C_BUS_SPEED (FIR_I2C_SPEED)
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#define OMV_FIR_LEPTON_CONTROLLER (&spi_obj[1])
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#define OMV_FIR_LEPTON_CONTROLLER_INSTANCE (SPI2)
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#define OMV_FIR_LEPTON_SPI_BUS (SPI2_ID)
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#define OMV_FIR_LEPTON_MOSI_PIN (&omv_pin_C3_SPI2)
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#define OMV_FIR_LEPTON_MISO_PIN (&omv_pin_C2_SPI2)
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#define OMV_FIR_LEPTON_SCLK_PIN (&omv_pin_I1_SPI2)
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@ -7,6 +7,8 @@ OMV_GPIO_DEFINE(B, 2, AF10, SAI4)
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OMV_GPIO_DEFINE(C, 0, AF10, OTG_HS)
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OMV_GPIO_DEFINE(C, 2, AF5, SPI2)
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OMV_GPIO_DEFINE(C, 3, AF5, SPI2)
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OMV_GPIO_DEFINE(C, 6, NONE, GPIO)
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OMV_GPIO_DEFINE(C, 7, NONE, GPIO)
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OMV_GPIO_DEFINE(C, 13, NONE, GPIO)
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OMV_GPIO_DEFINE(C, 15, NONE, GPIO)
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OMV_GPIO_DEFINE(D, 5, NONE, GPIO)
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@ -21,13 +23,12 @@ OMV_GPIO_DEFINE(H, 11, AF13, DCMI)
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OMV_GPIO_DEFINE(H, 12, AF4, I2C4)
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OMV_GPIO_DEFINE(H, 12, AF13, DCMI)
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OMV_GPIO_DEFINE(H, 14, AF13, DCMI)
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OMV_GPIO_DEFINE(H, 15, NONE, GPIO)
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OMV_GPIO_DEFINE(I, 0, NONE, GPIO)
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OMV_GPIO_DEFINE(I, 0, AF5, SPI2)
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OMV_GPIO_DEFINE(I, 1, AF5, SPI2)
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OMV_GPIO_DEFINE(I, 4, AF13, DCMI)
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OMV_GPIO_DEFINE(I, 5, AF13, DCMI)
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OMV_GPIO_DEFINE(I, 6, AF13, DCMI)
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OMV_GPIO_DEFINE(I, 7, AF13, DCMI)
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OMV_GPIO_DEFINE(I, 11, AF10, OTG_HS)
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OMV_GPIO_DEFINE(K, 1, NONE, GPIO)
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OMV_GPIO_DEFINE(K, 1, AF1, TIM1)
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@ -109,7 +109,6 @@
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#define OMV_LINE_BUF_SIZE (2 * 1024) // Image line buffer round(320 * 2BPP * 2 buffers).
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#define OMV_MSC_BUF_SIZE (2K) // USB MSC bot data
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#define OMV_VFS_BUF_SIZE (1K) // VFS struct + FATFS file buffer (624 bytes)
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#define OMV_FIR_LEPTON_BUF_SIZE (1K) // FIR Lepton Packet Double Buffer (328 bytes)
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#define OMV_FFS_BUF_SIZE (16K) // Flash filesystem cache
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#define OMV_JPEG_BUF_SIZE (8 * 1024) // IDE JPEG buffer size (header + data).
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@ -174,7 +173,8 @@
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#define DCMI_VSYNC_PIN (&omv_pin_B7_DCMI)
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#define DCMI_PXCLK_PIN (&omv_pin_A6_DCMI)
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// Physical I2C buses
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// Physical I2C buses.
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// I2C bus 1
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#define I2C1_ID (1)
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#define I2C1_SCL_PIN (&omv_pin_B8_I2C1)
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@ -185,7 +185,8 @@
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#define I2C2_SCL_PIN (&omv_pin_B10_I2C2)
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#define I2C2_SDA_PIN (&omv_pin_B11_I2C2)
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// Physical SPI buses
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// Physical SPI buses.
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// SPI bus 2
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#define SPI2_ID (2)
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#define SPI2_SCLK_PIN (&omv_pin_B13_SPI2)
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@ -198,9 +199,7 @@
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#define DMA_REQUEST_SPI2_RX (DMA_CHANNEL_0)
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// SPI LCD Interface
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#define OMV_SPI_LCD_CONTROLLER (&spi_obj[1])
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#define OMV_SPI_LCD_CONTROLLER_INSTANCE (SPI2)
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#define OMV_SPI_LCD_SPI_BUS (SPI2_ID)
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#define OMV_SPI_LCD_MOSI_PIN (&omv_pin_B15_SPI2)
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#define OMV_SPI_LCD_MISO_PIN (&omv_pin_B14_SPI2)
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#define OMV_SPI_LCD_SCLK_PIN (&omv_pin_B13_SPI2)
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@ -220,11 +219,11 @@
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// FIR Lepton
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#define OMV_FIR_LEPTON_I2C_BUS (FIR_I2C_ID)
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#define OMV_FIR_LEPTON_I2C_BUS_SPEED (FIR_I2C_SPEED)
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#define OMV_FIR_LEPTON_CONTROLLER (&spi_obj[1])
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#define OMV_FIR_LEPTON_CONTROLLER_INSTANCE (SPI2)
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#define OMV_FIR_LEPTON_SPI_BUS (SPI2_ID)
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#define OMV_FIR_LEPTON_MOSI_PIN (&omv_pin_B15_SPI2)
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#define OMV_FIR_LEPTON_MISO_PIN (&omv_pin_B14_SPI2)
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#define OMV_FIR_LEPTON_SCLK_PIN (&omv_pin_B13_SPI2)
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#define OMV_FIR_LEPTON_SSEL_PIN (&omv_pin_B12_GPIO)
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#endif //__OMV_BOARDCONFIG_H__
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@ -109,7 +109,6 @@
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#define OMV_LINE_BUF_SIZE (3 * 1024) // Image line buffer round(640 * 2BPP * 2 buffers).
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#define OMV_MSC_BUF_SIZE (2K) // USB MSC bot data
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#define OMV_VFS_BUF_SIZE (1K) // VFS struct + FATFS file buffer (624 bytes)
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#define OMV_FIR_LEPTON_BUF_SIZE (1K) // FIR Lepton Packet Double Buffer (328 bytes)
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#define OMV_FFS_BUF_SIZE (32K) // Flash filesystem cache
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#define OMV_JPEG_BUF_SIZE (22 * 1024) // IDE JPEG buffer (header + data).
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@ -175,6 +174,7 @@
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#define DCMI_PXCLK_PIN (&omv_pin_A6_DCMI)
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// Physical I2C buses.
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// I2C bus 1
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#define I2C1_ID (1)
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#define I2C1_SCL_PIN (&omv_pin_B8_I2C1)
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@ -185,7 +185,8 @@
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#define I2C2_SCL_PIN (&omv_pin_B10_I2C2)
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#define I2C2_SDA_PIN (&omv_pin_B11_I2C2)
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// Physical SPI buses
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// Physical SPI buses.
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// SPI bus 2
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#define SPI2_ID (2)
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#define SPI2_SCLK_PIN (&omv_pin_B13_SPI2)
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@ -198,9 +199,7 @@
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#define DMA_REQUEST_SPI2_RX (DMA_CHANNEL_0)
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// SPI LCD Interface
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#define OMV_SPI_LCD_CONTROLLER (&spi_obj[1])
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#define OMV_SPI_LCD_CONTROLLER_INSTANCE (SPI2)
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#define OMV_SPI_LCD_SPI_BUS (SPI2_ID)
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#define OMV_SPI_LCD_MOSI_PIN (&omv_pin_B15_SPI2)
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#define OMV_SPI_LCD_MISO_PIN (&omv_pin_B14_SPI2)
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#define OMV_SPI_LCD_SCLK_PIN (&omv_pin_B13_SPI2)
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@ -220,11 +219,11 @@
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// FIR Lepton
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#define OMV_FIR_LEPTON_I2C_BUS (FIR_I2C_ID)
|
||||
#define OMV_FIR_LEPTON_I2C_BUS_SPEED (FIR_I2C_SPEED)
|
||||
#define OMV_FIR_LEPTON_CONTROLLER (&spi_obj[1])
|
||||
#define OMV_FIR_LEPTON_CONTROLLER_INSTANCE (SPI2)
|
||||
|
||||
#define OMV_FIR_LEPTON_SPI_BUS (SPI2_ID)
|
||||
#define OMV_FIR_LEPTON_MOSI_PIN (&omv_pin_B15_SPI2)
|
||||
#define OMV_FIR_LEPTON_MISO_PIN (&omv_pin_B14_SPI2)
|
||||
#define OMV_FIR_LEPTON_SCLK_PIN (&omv_pin_B13_SPI2)
|
||||
#define OMV_FIR_LEPTON_SSEL_PIN (&omv_pin_B12_GPIO)
|
||||
|
||||
#endif //__OMV_BOARDCONFIG_H__
|
||||
|
||||
@ -168,7 +168,6 @@
|
||||
#define OMV_LINE_BUF_SIZE (5 * 1024) // Image line buffer.
|
||||
#define OMV_MSC_BUF_SIZE (2K) // USB MSC bot data
|
||||
#define OMV_VFS_BUF_SIZE (1K) // VFS struct + FATFS file buffer (624 bytes)
|
||||
#define OMV_FIR_LEPTON_BUF_SIZE (1K) // FIR Lepton Packet Double Buffer (328 bytes)
|
||||
#define OMV_JPEG_BUF_SIZE (32 * 1024) // IDE JPEG buffer (header + data).
|
||||
|
||||
// Memory map.
|
||||
@ -231,7 +230,6 @@
|
||||
|
||||
// Main image sensor SPI bus
|
||||
#define ISC_SPI_ID (3)
|
||||
#define ISC_SPI_BAUDRATE (20000000)
|
||||
|
||||
// WINC1500 WiFi module SPI bus
|
||||
#define WINC_SPI_ID (2)
|
||||
@ -267,16 +265,19 @@
|
||||
#define DCMI_PXCLK_PIN (&omv_pin_A6_DCMI)
|
||||
|
||||
// Physical I2C buses.
|
||||
|
||||
// I2C bus 1
|
||||
#define I2C1_ID (1)
|
||||
#define I2C1_SCL_PIN (&omv_pin_B8_I2C1)
|
||||
#define I2C1_SDA_PIN (&omv_pin_B9_I2C1)
|
||||
|
||||
// I2C bus 2
|
||||
#define I2C2_ID (2)
|
||||
#define I2C2_SCL_PIN (&omv_pin_B10_I2C2)
|
||||
#define I2C2_SDA_PIN (&omv_pin_B11_I2C2)
|
||||
|
||||
// Physical SPI buses.
|
||||
|
||||
// SPI bus 2
|
||||
#define SPI2_ID (2)
|
||||
#define SPI2_SCLK_PIN (&omv_pin_B13_SPI2)
|
||||
@ -286,6 +287,7 @@
|
||||
#define SPI2_DMA_TX_CHANNEL (DMA1_Stream4)
|
||||
#define SPI2_DMA_RX_CHANNEL (DMA1_Stream3)
|
||||
|
||||
// SPI bus 3
|
||||
#define SPI3_ID (3)
|
||||
#define SPI3_SCLK_PIN (&omv_pin_B3_SPI3)
|
||||
#define SPI3_MISO_PIN (&omv_pin_B4_SPI3)
|
||||
@ -295,9 +297,7 @@
|
||||
#define SPI3_DMA_RX_CHANNEL (DMA1_Stream2)
|
||||
|
||||
// SPI LCD Interface
|
||||
#define OMV_SPI_LCD_CONTROLLER (&spi_obj[1])
|
||||
#define OMV_SPI_LCD_CONTROLLER_INSTANCE (SPI2)
|
||||
|
||||
#define OMV_SPI_LCD_SPI_BUS (SPI2_ID)
|
||||
#define OMV_SPI_LCD_MOSI_PIN (&omv_pin_B15_SPI2)
|
||||
#define OMV_SPI_LCD_MISO_PIN (&omv_pin_B14_SPI2)
|
||||
#define OMV_SPI_LCD_SCLK_PIN (&omv_pin_B13_SPI2)
|
||||
@ -317,11 +317,11 @@
|
||||
// FIR Lepton
|
||||
#define OMV_FIR_LEPTON_I2C_BUS (FIR_I2C_ID)
|
||||
#define OMV_FIR_LEPTON_I2C_BUS_SPEED (FIR_I2C_SPEED)
|
||||
#define OMV_FIR_LEPTON_CONTROLLER (&spi_obj[1])
|
||||
#define OMV_FIR_LEPTON_CONTROLLER_INSTANCE (SPI2)
|
||||
|
||||
#define OMV_FIR_LEPTON_SPI_BUS (SPI2_ID)
|
||||
#define OMV_FIR_LEPTON_MOSI_PIN (&omv_pin_B15_SPI2)
|
||||
#define OMV_FIR_LEPTON_MISO_PIN (&omv_pin_B14_SPI2)
|
||||
#define OMV_FIR_LEPTON_SCLK_PIN (&omv_pin_B13_SPI2)
|
||||
#define OMV_FIR_LEPTON_SSEL_PIN (&omv_pin_B12_GPIO)
|
||||
|
||||
#endif //__OMV_BOARDCONFIG_H__
|
||||
|
||||
@ -170,7 +170,6 @@
|
||||
#define OMV_LINE_BUF_SIZE (11 * 1024) // Image line buffer round(2592 * 2BPP * 2 buffers).
|
||||
#define OMV_MSC_BUF_SIZE (2K) // USB MSC bot data
|
||||
#define OMV_VFS_BUF_SIZE (1K) // VFS struct + FATFS file buffer (624 bytes)
|
||||
#define OMV_FIR_LEPTON_BUF_SIZE (1K) // FIR Lepton Packet Double Buffer (328 bytes)
|
||||
#define OMV_JPEG_BUF_SIZE (1024 * 1024) // IDE JPEG buffer (header + data).
|
||||
|
||||
// Memory map.
|
||||
@ -234,7 +233,6 @@
|
||||
|
||||
// Main image sensor SPI bus
|
||||
#define ISC_SPI_ID (3)
|
||||
#define ISC_SPI_BAUDRATE (20000000)
|
||||
|
||||
// WINC1500 WiFi module SPI bus
|
||||
#define WINC_SPI_ID (2)
|
||||
@ -270,16 +268,19 @@
|
||||
#define DCMI_PXCLK_PIN (&omv_pin_A6_DCMI)
|
||||
|
||||
// Physical I2C buses.
|
||||
|
||||
// I2C bus 1
|
||||
#define I2C1_ID (1)
|
||||
#define I2C1_SCL_PIN (&omv_pin_B8_I2C1)
|
||||
#define I2C1_SDA_PIN (&omv_pin_B9_I2C1)
|
||||
|
||||
// I2C bus 2
|
||||
#define I2C2_ID (2)
|
||||
#define I2C2_SCL_PIN (&omv_pin_B10_I2C2)
|
||||
#define I2C2_SDA_PIN (&omv_pin_B11_I2C2)
|
||||
|
||||
// Physical SPI buses.
|
||||
|
||||
// SPI bus 2
|
||||
#define SPI2_ID (2)
|
||||
#define SPI2_SCLK_PIN (&omv_pin_B13_SPI2)
|
||||
@ -289,6 +290,7 @@
|
||||
#define SPI2_DMA_TX_CHANNEL (DMA1_Stream4)
|
||||
#define SPI2_DMA_RX_CHANNEL (DMA1_Stream3)
|
||||
|
||||
// SPI bus 3
|
||||
#define SPI3_ID (3)
|
||||
#define SPI3_SCLK_PIN (&omv_pin_B3_SPI3)
|
||||
#define SPI3_MISO_PIN (&omv_pin_B4_SPI3)
|
||||
@ -298,9 +300,7 @@
|
||||
#define SPI3_DMA_RX_CHANNEL (DMA1_Stream2)
|
||||
|
||||
// SPI LCD Interface
|
||||
#define OMV_SPI_LCD_CONTROLLER (&spi_obj[1])
|
||||
#define OMV_SPI_LCD_CONTROLLER_INSTANCE (SPI2)
|
||||
|
||||
#define OMV_SPI_LCD_SPI_BUS (SPI2_ID)
|
||||
#define OMV_SPI_LCD_MOSI_PIN (&omv_pin_B15_SPI2)
|
||||
#define OMV_SPI_LCD_MISO_PIN (&omv_pin_B14_SPI2)
|
||||
#define OMV_SPI_LCD_SCLK_PIN (&omv_pin_B13_SPI2)
|
||||
@ -317,12 +317,13 @@
|
||||
#define OMV_SPI_LCD_BL_DAC_FORCE_RESET() __HAL_RCC_DAC12_FORCE_RESET()
|
||||
#define OMV_SPI_LCD_BL_DAC_RELEASE_RESET() __HAL_RCC_DAC12_RELEASE_RESET()
|
||||
|
||||
#define OMV_SPI_LCD_DEF_TRIPLE_BUF (true)
|
||||
|
||||
// FIR Lepton
|
||||
#define OMV_FIR_LEPTON_I2C_BUS (FIR_I2C_ID)
|
||||
#define OMV_FIR_LEPTON_I2C_BUS_SPEED (FIR_I2C_SPEED)
|
||||
#define OMV_FIR_LEPTON_CONTROLLER (&spi_obj[1])
|
||||
#define OMV_FIR_LEPTON_CONTROLLER_INSTANCE (SPI2)
|
||||
|
||||
#define OMV_FIR_LEPTON_SPI_BUS (SPI2_ID)
|
||||
#define OMV_FIR_LEPTON_MOSI_PIN (&omv_pin_B15_SPI2)
|
||||
#define OMV_FIR_LEPTON_MISO_PIN (&omv_pin_B14_SPI2)
|
||||
#define OMV_FIR_LEPTON_SCLK_PIN (&omv_pin_B13_SPI2)
|
||||
|
||||
@ -175,7 +175,6 @@
|
||||
#define OMV_LINE_BUF_SIZE (11 * 1024) // Image line buffer round(2592 * 2BPP * 2 buffers).
|
||||
#define OMV_MSC_BUF_SIZE (2K) // USB MSC bot data
|
||||
#define OMV_VFS_BUF_SIZE (1K) // VFS struct + FATFS file buffer (624 bytes)
|
||||
#define OMV_FIR_LEPTON_BUF_SIZE (1K) // FIR Lepton Packet Double Buffer (328 bytes)
|
||||
#define OMV_JPEG_BUF_SIZE (1024 * 1024) // IDE JPEG buffer (header + data).
|
||||
|
||||
// Memory map.
|
||||
@ -272,16 +271,37 @@
|
||||
#define DCMI_PXCLK_PIN (&omv_pin_A6_DCMI)
|
||||
|
||||
// Physical I2C buses.
|
||||
|
||||
// I2C bus 1
|
||||
#define I2C1_ID (1)
|
||||
#define I2C1_SCL_PIN (&omv_pin_B8_I2C1)
|
||||
#define I2C1_SDA_PIN (&omv_pin_B9_I2C1)
|
||||
|
||||
// I2C bus 2
|
||||
#define I2C2_ID (2)
|
||||
#define I2C2_SCL_PIN (&omv_pin_B10_I2C2)
|
||||
#define I2C2_SDA_PIN (&omv_pin_B11_I2C2)
|
||||
|
||||
// Physical SPI buses.
|
||||
|
||||
// SPI bus 2
|
||||
#define SPI2_ID (2)
|
||||
#define SPI2_SCLK_PIN (&omv_pin_B13_SPI2)
|
||||
#define SPI2_MISO_PIN (&omv_pin_B14_SPI2)
|
||||
#define SPI2_MOSI_PIN (&omv_pin_B15_SPI2)
|
||||
#define SPI2_SSEL_PIN (&omv_pin_B12_GPIO)
|
||||
#define SPI2_DMA_TX_CHANNEL (DMA1_Stream4)
|
||||
#define SPI2_DMA_RX_CHANNEL (DMA1_Stream3)
|
||||
|
||||
// SPI bus 3
|
||||
#define SPI3_ID (3)
|
||||
#define SPI3_SCLK_PIN (&omv_pin_B3_SPI3)
|
||||
#define SPI3_MISO_PIN (&omv_pin_B4_SPI3)
|
||||
#define SPI3_MOSI_PIN (&omv_pin_B5_SPI3)
|
||||
#define SPI3_SSEL_PIN (&omv_pin_A15_GPIO)
|
||||
#define SPI3_DMA_TX_CHANNEL (DMA1_Stream7)
|
||||
#define SPI3_DMA_RX_CHANNEL (DMA1_Stream2)
|
||||
|
||||
// SPI bus 5
|
||||
#define SPI5_ID (5)
|
||||
#define SPI5_SCLK_PIN (&omv_pin_H6_SPI5)
|
||||
@ -342,17 +362,15 @@
|
||||
#define OMV_LCD_BL_TIM_PCLK_FREQ() HAL_RCC_GetPCLK1Freq()
|
||||
|
||||
// SPI LCD Interface
|
||||
#define OMV_SPI_LCD_CONTROLLER (&spi_obj[1])
|
||||
#define OMV_SPI_LCD_CONTROLLER_INSTANCE (SPI2)
|
||||
|
||||
#define OMV_SPI_LCD_SPI_BUS (SPI2_ID)
|
||||
#define OMV_SPI_LCD_MOSI_PIN (&omv_pin_B15_SPI2)
|
||||
#define OMV_SPI_LCD_MISO_PIN (&omv_pin_B14_SPI2)
|
||||
#define OMV_SPI_LCD_SCLK_PIN (&omv_pin_B13_SPI2)
|
||||
|
||||
#define OMV_SPI_LCD_RST_PIN (&omv_pin_D12_GPIO)
|
||||
#define OMV_SPI_LCD_RS_PIN (&omv_pin_D13_GPIO)
|
||||
#define OMV_SPI_LCD_SSEL_PIN (&omv_pin_B12_GPIO)
|
||||
|
||||
#define OMV_SPI_LCD_RS_PIN (&omv_pin_D13_GPIO)
|
||||
#define OMV_SPI_LCD_BL_PIN (&omv_pin_A5_GPIO)
|
||||
#define OMV_SPI_LCD_RST_PIN (&omv_pin_D12_GPIO)
|
||||
|
||||
#define OMV_SPI_LCD_BL_DAC (DAC1)
|
||||
#define OMV_SPI_LCD_BL_DAC_CHANNEL (DAC_CHANNEL_2)
|
||||
@ -361,6 +379,8 @@
|
||||
#define OMV_SPI_LCD_BL_DAC_FORCE_RESET() __HAL_RCC_DAC12_FORCE_RESET()
|
||||
#define OMV_SPI_LCD_BL_DAC_RELEASE_RESET() __HAL_RCC_DAC12_RELEASE_RESET()
|
||||
|
||||
#define OMV_SPI_LCD_DEF_TRIPLE_BUF (true)
|
||||
|
||||
// DVI TFP410PAP I/O
|
||||
#define OMV_DVI_PRESENT
|
||||
#define OMV_DVI_RESET_PIN (&omv_pin_D11_GPIO)
|
||||
@ -387,9 +407,8 @@
|
||||
// FIR Lepton
|
||||
#define OMV_FIR_LEPTON_I2C_BUS (ISC_I2C_ID)
|
||||
#define OMV_FIR_LEPTON_I2C_BUS_SPEED (ISC_I2C_SPEED)
|
||||
#define OMV_FIR_LEPTON_CONTROLLER (&spi_obj[2])
|
||||
#define OMV_FIR_LEPTON_CONTROLLER_INSTANCE (SPI3)
|
||||
|
||||
#define OMV_FIR_LEPTON_SPI_BUS (SPI3_ID)
|
||||
#define OMV_FIR_LEPTON_MOSI_PIN (&omv_pin_B5_SPI3)
|
||||
#define OMV_FIR_LEPTON_MISO_PIN (&omv_pin_B4_SPI3)
|
||||
#define OMV_FIR_LEPTON_SCLK_PIN (&omv_pin_B3_SPI3)
|
||||
|
||||
@ -10,12 +10,10 @@
|
||||
*/
|
||||
#include "omv_boardconfig.h"
|
||||
#if (OMV_ENABLE_FIR_LEPTON == 1)
|
||||
#include STM32_HAL_H
|
||||
#include "py/nlr.h"
|
||||
#include "py/runtime.h"
|
||||
#include "py/obj.h"
|
||||
#include "py/mphal.h"
|
||||
#include "spi.h"
|
||||
#include "softtimer.h"
|
||||
|
||||
#include "crc16.h"
|
||||
@ -28,7 +26,9 @@
|
||||
#include "LEPTON_I2C_Reg.h"
|
||||
|
||||
#include "py_helper.h"
|
||||
#include "omv_common.h"
|
||||
#include "omv_gpio.h"
|
||||
#include "omv_spi.h"
|
||||
|
||||
#define FRAMEBUFFER_COUNT 3
|
||||
static volatile int framebuffer_tail = 0;
|
||||
@ -43,7 +43,7 @@ static TIM_HandleTypeDef fir_lepton_mclk_tim_handle = {};
|
||||
#endif
|
||||
|
||||
static LEP_CAMERA_PORT_DESC_T fir_lepton_handle = {};
|
||||
static DMA_HandleTypeDef fir_lepton_spi_rx_dma = {};
|
||||
static omv_spi_t spi_bus = {};
|
||||
|
||||
#define VOSPI_HEADER_WORDS (2) // 16-bits
|
||||
#define VOSPI_PID_SIZE_PIXELS (80) // w, 16-bits per pixel
|
||||
@ -60,7 +60,8 @@ static soft_timer_entry_t flir_lepton_spi_rx_timer = {};
|
||||
static int fir_lepton_spi_rx_cb_tail = 0;
|
||||
static int fir_lepton_spi_rx_cb_expected_pid = 0;
|
||||
static int fir_lepton_spi_rx_cb_expected_seg = 0;
|
||||
extern int _fir_lepton_buf[];
|
||||
static uint16_t OMV_ATTR_SECTION(OMV_ATTR_ALIGNED_DMA(fir_lepton_buf[VOSPI_BUFFER_SIZE]), ".dma_buffer");
|
||||
static void fir_lepton_spi_callback(omv_spi_t *spi, void *userdata, void *buf);
|
||||
|
||||
STATIC mp_obj_t fir_lepton_spi_resync_callback(mp_obj_t unused) {
|
||||
// For triple buffering we are never drawing where tail or head
|
||||
@ -70,9 +71,15 @@ STATIC mp_obj_t fir_lepton_spi_resync_callback(mp_obj_t unused) {
|
||||
fir_lepton_spi_rx_cb_tail = (fir_lepton_spi_rx_cb_tail + 1) % FRAMEBUFFER_COUNT;
|
||||
}
|
||||
|
||||
omv_gpio_write(OMV_FIR_LEPTON_SSEL_PIN, 0);
|
||||
HAL_SPI_Receive_DMA(OMV_FIR_LEPTON_CONTROLLER->spi, (uint8_t *) &_fir_lepton_buf, VOSPI_BUFFER_SIZE);
|
||||
omv_spi_transfer_t spi_xfer = {
|
||||
.rxbuf = fir_lepton_buf,
|
||||
.size = VOSPI_BUFFER_SIZE,
|
||||
.flags = OMV_SPI_XFER_DMA | OMV_SPI_XFER_16_BIT,
|
||||
.callback = fir_lepton_spi_callback,
|
||||
};
|
||||
|
||||
omv_gpio_write(OMV_FIR_LEPTON_SSEL_PIN, 0);
|
||||
omv_spi_transfer_start(&spi_bus, &spi_xfer);
|
||||
return mp_const_none;
|
||||
}
|
||||
STATIC MP_DEFINE_CONST_FUN_OBJ_1(fir_lepton_spi_resync_callback_obj, fir_lepton_spi_resync_callback);
|
||||
@ -106,7 +113,9 @@ static bool fir_lepton_spi_check_crc(const uint16_t *base) {
|
||||
|
||||
static mp_obj_t fir_lepton_frame_cb = mp_const_none;
|
||||
|
||||
void fir_lepton_spi_callback(const uint16_t *base) {
|
||||
void fir_lepton_spi_callback(omv_spi_t *spi, void *userdata, void *buf) {
|
||||
const uint16_t *base = (uint16_t *) buf;
|
||||
|
||||
int id = base[0];
|
||||
|
||||
// Ignore don't care packets.
|
||||
@ -136,7 +145,7 @@ void fir_lepton_spi_callback(const uint16_t *base) {
|
||||
|| (fir_lepton_3 && (pid == 20) && (seg != fir_lepton_spi_rx_cb_expected_seg))) {
|
||||
fir_lepton_spi_rx_cb_expected_pid = 0;
|
||||
fir_lepton_spi_rx_cb_expected_seg = 0;
|
||||
HAL_SPI_Abort_IT(OMV_FIR_LEPTON_CONTROLLER->spi);
|
||||
omv_spi_transfer_abort(&spi_bus);
|
||||
omv_gpio_write(OMV_FIR_LEPTON_SSEL_PIN, 1);
|
||||
fir_lepton_spi_resync();
|
||||
return;
|
||||
@ -184,14 +193,6 @@ void fir_lepton_spi_callback(const uint16_t *base) {
|
||||
}
|
||||
}
|
||||
|
||||
static void fir_lepton_spi_callback_half(SPI_HandleTypeDef *hspi) {
|
||||
fir_lepton_spi_callback((uint16_t *) &_fir_lepton_buf);
|
||||
}
|
||||
|
||||
static void fir_lepton_spi_callback_full(SPI_HandleTypeDef *hspi) {
|
||||
fir_lepton_spi_callback(((uint16_t *) &_fir_lepton_buf) + VOSPI_PACKET_SIZE);
|
||||
}
|
||||
|
||||
#if defined(OMV_FIR_LEPTON_VSYNC_PIN)
|
||||
static mp_obj_t fir_lepton_vsync_cb = NULL;
|
||||
|
||||
@ -203,7 +204,7 @@ static void fir_lepton_extint_callback(void *data) {
|
||||
#endif
|
||||
|
||||
void fir_lepton_deinit() {
|
||||
HAL_SPI_Abort(OMV_FIR_LEPTON_CONTROLLER->spi);
|
||||
omv_spi_transfer_abort(&spi_bus);
|
||||
fir_lepton_spi_rx_cb_expected_pid = 0;
|
||||
fir_lepton_spi_rx_cb_expected_seg = 0;
|
||||
fb_alloc_free_till_mark_past_mark_permanent();
|
||||
@ -217,48 +218,38 @@ void fir_lepton_deinit() {
|
||||
omv_gpio_deinit(OMV_FIR_LEPTON_MCLK_PIN);
|
||||
#endif
|
||||
|
||||
spi_deinit(OMV_FIR_LEPTON_CONTROLLER);
|
||||
omv_spi_deinit(&spi_bus);
|
||||
|
||||
// Do not put in HAL_SPI_MspDeinit as other modules may share the SPI bus.
|
||||
omv_gpio_deinit(OMV_FIR_LEPTON_MOSI_PIN);
|
||||
omv_gpio_deinit(OMV_FIR_LEPTON_MISO_PIN);
|
||||
omv_gpio_deinit(OMV_FIR_LEPTON_SCLK_PIN);
|
||||
omv_gpio_deinit(OMV_FIR_LEPTON_SSEL_PIN);
|
||||
#if defined(OMV_FIR_LEPTON_RESET_PIN)
|
||||
omv_gpio_deinit(OMV_FIR_LEPTON_RESET_PIN);
|
||||
#endif
|
||||
|
||||
#if defined(OMV_FIR_LEPTON_POWER_PIN)
|
||||
omv_gpio_deinit(OMV_FIR_LEPTON_POWER_PIN);
|
||||
#endif
|
||||
}
|
||||
|
||||
int fir_lepton_init(omv_i2c_t *bus, int *w, int *h, int *refresh, int *resolution) {
|
||||
SPI_HandleTypeDef *hspi = OMV_FIR_LEPTON_CONTROLLER->spi;
|
||||
omv_spi_config_t spi_config;
|
||||
omv_spi_default_config(&spi_config, OMV_FIR_LEPTON_SPI_BUS);
|
||||
|
||||
hspi->Init.Mode = SPI_MODE_MASTER;
|
||||
hspi->Init.Direction = SPI_DIRECTION_2LINES_RXONLY;
|
||||
hspi->Init.NSS = SPI_NSS_SOFT;
|
||||
hspi->Init.TIMode = SPI_TIMODE_DISABLE;
|
||||
hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
|
||||
#if defined(MCU_SERIES_H7)
|
||||
hspi->Init.FifoThreshold = SPI_FIFO_THRESHOLD_02DATA;
|
||||
hspi->Init.MasterKeepIOState = SPI_MASTER_KEEP_IO_STATE_ENABLE;
|
||||
#if OMV_FIR_LEPTON_RX_CLK_DIV
|
||||
spi_config.baudrate = VOSPI_CLOCK_SPEED / OMV_FIR_LEPTON_RX_CLK_DIV;
|
||||
#else
|
||||
spi_config.baudrate = VOSPI_CLOCK_SPEED;
|
||||
#endif
|
||||
spi_set_params(OMV_FIR_LEPTON_CONTROLLER, 0xffffffff, VOSPI_CLOCK_SPEED, 1, 1, 16, 0);
|
||||
spi_init(OMV_FIR_LEPTON_CONTROLLER, true);
|
||||
HAL_SPI_RegisterCallback(hspi, HAL_SPI_RX_COMPLETE_CB_ID, fir_lepton_spi_callback_full);
|
||||
HAL_SPI_RegisterCallback(hspi, HAL_SPI_RX_HALF_COMPLETE_CB_ID, fir_lepton_spi_callback_half);
|
||||
spi_config.bus_mode = OMV_SPI_BUS_RX;
|
||||
spi_config.nss_enable = false;
|
||||
spi_config.dma_flags = OMV_SPI_DMA_CIRCULAR | OMV_SPI_DMA_DOUBLE;
|
||||
omv_spi_init(&spi_bus, &spi_config);
|
||||
|
||||
// Do not put in HAL_SPI_MspInit as other modules share the SPI2/3 bus.
|
||||
omv_gpio_config(OMV_FIR_LEPTON_MOSI_PIN, OMV_GPIO_MODE_ALT, OMV_GPIO_PULL_UP, OMV_GPIO_SPEED_MED, -1);
|
||||
omv_gpio_config(OMV_FIR_LEPTON_MISO_PIN, OMV_GPIO_MODE_ALT, OMV_GPIO_PULL_UP, OMV_GPIO_SPEED_MED, -1);
|
||||
omv_gpio_config(OMV_FIR_LEPTON_SCLK_PIN, OMV_GPIO_MODE_ALT, OMV_GPIO_PULL_UP, OMV_GPIO_SPEED_MED, -1);
|
||||
omv_gpio_config(OMV_FIR_LEPTON_SSEL_PIN, OMV_GPIO_MODE_OUTPUT, OMV_GPIO_PULL_UP, OMV_GPIO_SPEED_LOW, -1);
|
||||
omv_gpio_write(OMV_FIR_LEPTON_SSEL_PIN, 1);
|
||||
|
||||
#if defined(OMV_FIR_LEPTON_RESET_PIN)
|
||||
omv_gpio_config(OMV_FIR_LEPTON_RESET_PIN, OMV_GPIO_MODE_OUTPUT, OMV_GPIO_PULL_UP, OMV_GPIO_SPEED_LOW, -1);
|
||||
omv_gpio_write(OMV_FIR_LEPTON_RESET_PIN, 1);
|
||||
#endif
|
||||
|
||||
#if defined(OMV_FIR_LEPTON_POWER_PIN)
|
||||
omv_gpio_config(OMV_FIR_LEPTON_POWER_PIN, OMV_GPIO_MODE_OUTPUT, OMV_GPIO_PULL_UP, OMV_GPIO_SPEED_LOW, -1);
|
||||
omv_gpio_write(OMV_FIR_LEPTON_POWER_PIN, 1);
|
||||
@ -400,38 +391,6 @@ int fir_lepton_init(omv_i2c_t *bus, int *w, int *h, int *refresh, int *resolutio
|
||||
framebuffers[i] = (uint16_t *) fb_alloc0(flir_w * flir_h * sizeof(uint16_t), FB_ALLOC_NO_HINT);
|
||||
}
|
||||
|
||||
dma_init(&fir_lepton_spi_rx_dma, OMV_FIR_LEPTON_CONTROLLER->rx_dma_descr, DMA_PERIPH_TO_MEMORY, hspi);
|
||||
|
||||
hspi->hdmatx = NULL;
|
||||
hspi->hdmarx = &fir_lepton_spi_rx_dma;
|
||||
|
||||
#if defined(MCU_SERIES_H7)
|
||||
fir_lepton_spi_rx_dma.Init.PeriphDataAlignment = DMA_PDATAALIGN_WORD;
|
||||
#else
|
||||
fir_lepton_spi_rx_dma.Init.PeriphDataAlignment = DMA_PDATAALIGN_HALFWORD;
|
||||
#endif
|
||||
fir_lepton_spi_rx_dma.Init.MemDataAlignment = DMA_MDATAALIGN_WORD;
|
||||
fir_lepton_spi_rx_dma.Init.Mode = DMA_CIRCULAR;
|
||||
fir_lepton_spi_rx_dma.Init.FIFOMode = DMA_FIFOMODE_ENABLE;
|
||||
fir_lepton_spi_rx_dma.Init.FIFOThreshold = DMA_FIFO_THRESHOLD_1QUARTERFULL;
|
||||
fir_lepton_spi_rx_dma.Init.MemBurst = DMA_MBURST_SINGLE;
|
||||
fir_lepton_spi_rx_dma.Init.PeriphBurst = DMA_PBURST_SINGLE;
|
||||
|
||||
DMA_Stream_TypeDef *dma_chan = (DMA_Stream_TypeDef *) fir_lepton_spi_rx_dma.Instance;
|
||||
dma_chan->CR =
|
||||
(dma_chan->CR & ~DMA_SxCR_PSIZE_Msk) |
|
||||
#if defined(MCU_SERIES_H7)
|
||||
DMA_PDATAALIGN_WORD;
|
||||
#else
|
||||
DMA_PDATAALIGN_HALFWORD;
|
||||
#endif
|
||||
dma_chan->CR = (dma_chan->CR & ~DMA_SxCR_MSIZE_Msk) | DMA_MDATAALIGN_WORD;
|
||||
dma_chan->CR = (dma_chan->CR & ~DMA_SxCR_CIRC_Msk) | DMA_CIRCULAR;
|
||||
dma_chan->FCR = (dma_chan->FCR & ~DMA_SxFCR_DMDIS_Msk) | DMA_FIFOMODE_ENABLE;
|
||||
dma_chan->FCR = (dma_chan->FCR & ~DMA_SxFCR_FTH_Msk) | DMA_FIFO_THRESHOLD_1QUARTERFULL;
|
||||
dma_chan->CR = (dma_chan->CR & ~DMA_SxCR_MBURST_Msk) | DMA_MBURST_SINGLE;
|
||||
dma_chan->CR = (dma_chan->CR & ~DMA_SxCR_PBURST_Msk) | DMA_PBURST_SINGLE;
|
||||
|
||||
fb_alloc_mark_permanent();
|
||||
fir_lepton_spi_resync();
|
||||
return 0;
|
||||
@ -476,7 +435,7 @@ static const uint16_t *fir_lepton_get_frame(int timeout) {
|
||||
mp_raise_msg(&mp_type_OSError, MP_ERROR_TEXT("Timeout!"));
|
||||
}
|
||||
|
||||
__WFI();
|
||||
MICROPY_EVENT_POLL_HOOK
|
||||
}
|
||||
}
|
||||
|
||||
@ -11,12 +11,11 @@
|
||||
#include "omv_boardconfig.h"
|
||||
|
||||
#if MICROPY_PY_LCD
|
||||
#include STM32_HAL_H
|
||||
|
||||
#include "py/obj.h"
|
||||
#include "py/nlr.h"
|
||||
#include "py/runtime.h"
|
||||
#include "pendsv.h"
|
||||
#include "spi.h"
|
||||
|
||||
#include "py_lcd_cec.h"
|
||||
#include "py_lcd_touch.h"
|
||||
@ -24,6 +23,7 @@
|
||||
#include "py_image.h"
|
||||
#include "extmod/machine_i2c.h"
|
||||
#include "omv_gpio.h"
|
||||
#include "omv_spi.h"
|
||||
|
||||
#define FRAMEBUFFER_COUNT 3
|
||||
static int framebuffer_tail = 0;
|
||||
@ -72,8 +72,8 @@ lcd_resolution = LCD_DISPLAY_QVGA;
|
||||
static int lcd_refresh = 0;
|
||||
static int lcd_intensity = 0;
|
||||
|
||||
#ifdef OMV_SPI_LCD_CONTROLLER
|
||||
static DMA_HandleTypeDef spi_tx_dma = {};
|
||||
#ifdef OMV_SPI_LCD_SPI_BUS
|
||||
static omv_spi_t spi_bus = {};
|
||||
|
||||
static volatile enum {
|
||||
SPI_TX_CB_IDLE,
|
||||
@ -84,46 +84,63 @@ static volatile enum {
|
||||
}
|
||||
spi_tx_cb_state = SPI_TX_CB_IDLE;
|
||||
|
||||
static void spi_transmit(uint8_t *txdata, uint16_t size, bool end) {
|
||||
omv_spi_transfer_t spi_xfer = {
|
||||
.txbuf = txdata,
|
||||
.size = size,
|
||||
.timeout = OMV_SPI_MAX_TIMEOUT,
|
||||
.flags = OMV_SPI_XFER_BLOCKING
|
||||
};
|
||||
|
||||
omv_gpio_write(OMV_SPI_LCD_SSEL_PIN, 0);
|
||||
omv_spi_transfer_start(&spi_bus, &spi_xfer);
|
||||
|
||||
if (end) {
|
||||
omv_gpio_write(OMV_SPI_LCD_SSEL_PIN, 1);
|
||||
}
|
||||
}
|
||||
|
||||
static void spi_transmit_16(uint8_t *txdata, uint16_t size) {
|
||||
omv_spi_transfer_t spi_xfer = {
|
||||
.txbuf = txdata,
|
||||
.size = (!lcd_byte_reverse) ? size : (size * 2),
|
||||
.timeout = OMV_SPI_MAX_TIMEOUT,
|
||||
.flags = OMV_SPI_XFER_BLOCKING | ((!lcd_byte_reverse) ? OMV_SPI_XFER_16_BIT : 0)
|
||||
};
|
||||
|
||||
omv_spi_transfer_start(&spi_bus, &spi_xfer);
|
||||
}
|
||||
|
||||
static void spi_config_deinit() {
|
||||
if (lcd_triple_buffer) {
|
||||
HAL_SPI_Abort(OMV_SPI_LCD_CONTROLLER->spi);
|
||||
omv_spi_transfer_abort(&spi_bus);
|
||||
spi_tx_cb_state = SPI_TX_CB_IDLE;
|
||||
fb_alloc_free_till_mark_past_mark_permanent();
|
||||
}
|
||||
|
||||
spi_deinit(OMV_SPI_LCD_CONTROLLER);
|
||||
omv_spi_deinit(&spi_bus);
|
||||
|
||||
// Do not put in HAL_SPI_MspDeinit as other modules share the SPI2 bus.
|
||||
omv_gpio_deinit(OMV_SPI_LCD_MOSI_PIN);
|
||||
omv_gpio_deinit(OMV_SPI_LCD_SCLK_PIN);
|
||||
omv_gpio_deinit(OMV_SPI_LCD_RST_PIN);
|
||||
omv_gpio_deinit(OMV_SPI_LCD_RS_PIN);
|
||||
omv_gpio_deinit(OMV_SPI_LCD_SSEL_PIN);
|
||||
omv_gpio_deinit(OMV_SPI_LCD_RST_PIN);
|
||||
}
|
||||
|
||||
static void spi_lcd_callback(SPI_HandleTypeDef *hspi);
|
||||
static void spi_config_init(int w, int h, int refresh_rate, bool triple_buffer, bool bgr, bool byte_reverse) {
|
||||
omv_spi_config_t spi_config;
|
||||
omv_spi_default_config(&spi_config, OMV_SPI_LCD_SPI_BUS);
|
||||
|
||||
static void spi_config_init(int w, int h, int refresh_rate, bool triple_buffer, bool bgr) {
|
||||
SPI_HandleTypeDef *hspi = OMV_SPI_LCD_CONTROLLER->spi;
|
||||
spi_config.baudrate = w * h * refresh_rate * 16;
|
||||
spi_config.bus_mode = OMV_SPI_BUS_TX;
|
||||
spi_config.nss_enable = false;
|
||||
spi_config.dma_flags = triple_buffer ? OMV_SPI_DMA_NORMAL : 0;
|
||||
omv_spi_init(&spi_bus, &spi_config);
|
||||
|
||||
hspi->Init.Mode = SPI_MODE_MASTER;
|
||||
hspi->Init.Direction = SPI_DIRECTION_1LINE;
|
||||
hspi->Init.NSS = SPI_NSS_SOFT;
|
||||
hspi->Init.TIMode = SPI_TIMODE_DISABLE;
|
||||
hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
|
||||
spi_set_params(OMV_SPI_LCD_CONTROLLER, 0xffffffff, w * h * refresh_rate * 16, 0, 0, 8, 0);
|
||||
spi_init(OMV_SPI_LCD_CONTROLLER, true);
|
||||
HAL_SPI_RegisterCallback(hspi, HAL_SPI_TX_COMPLETE_CB_ID, spi_lcd_callback);
|
||||
omv_gpio_write(OMV_SPI_LCD_SSEL_PIN, 1);
|
||||
|
||||
// Do not put in HAL_SPI_MspInit as other modules share the SPI2 bus.
|
||||
omv_gpio_config(OMV_SPI_LCD_MOSI_PIN, OMV_GPIO_MODE_ALT, OMV_GPIO_PULL_NONE, OMV_GPIO_SPEED_MED, -1);
|
||||
omv_gpio_config(OMV_SPI_LCD_SCLK_PIN, OMV_GPIO_MODE_ALT, OMV_GPIO_PULL_NONE, OMV_GPIO_SPEED_MED, -1);
|
||||
omv_gpio_config(OMV_SPI_LCD_RST_PIN, OMV_GPIO_MODE_OUTPUT, OMV_GPIO_PULL_NONE, OMV_GPIO_SPEED_LOW, -1);
|
||||
omv_gpio_write(OMV_SPI_LCD_RST_PIN, 1);
|
||||
|
||||
omv_gpio_config(OMV_SPI_LCD_RS_PIN, OMV_GPIO_MODE_OUTPUT, OMV_GPIO_PULL_NONE, OMV_GPIO_SPEED_LOW, -1);
|
||||
omv_gpio_write(OMV_SPI_LCD_RS_PIN, 1);
|
||||
omv_gpio_config(OMV_SPI_LCD_SSEL_PIN, OMV_GPIO_MODE_OUTPUT, OMV_GPIO_PULL_NONE, OMV_GPIO_SPEED_LOW, -1);
|
||||
omv_gpio_write(OMV_SPI_LCD_SSEL_PIN, 1);
|
||||
|
||||
omv_gpio_write(OMV_SPI_LCD_RST_PIN, 0);
|
||||
mp_hal_delay_ms(100);
|
||||
@ -131,29 +148,19 @@ static void spi_config_init(int w, int h, int refresh_rate, bool triple_buffer,
|
||||
mp_hal_delay_ms(100);
|
||||
|
||||
omv_gpio_write(OMV_SPI_LCD_RS_PIN, 0);
|
||||
omv_gpio_write(OMV_SPI_LCD_SSEL_PIN, 0);
|
||||
HAL_SPI_Transmit(hspi, (uint8_t []) {0x11}, 1, HAL_MAX_DELAY); // sleep out
|
||||
omv_gpio_write(OMV_SPI_LCD_SSEL_PIN, 1);
|
||||
spi_transmit((uint8_t []) {0x11}, 1, true); // sleep out
|
||||
omv_gpio_write(OMV_SPI_LCD_RS_PIN, 1);
|
||||
mp_hal_delay_ms(120);
|
||||
|
||||
omv_gpio_write(OMV_SPI_LCD_RS_PIN, 0);
|
||||
omv_gpio_write(OMV_SPI_LCD_SSEL_PIN, 0);
|
||||
HAL_SPI_Transmit(hspi, (uint8_t []) {0x36}, 1, HAL_MAX_DELAY); // memory data access control
|
||||
omv_gpio_write(OMV_SPI_LCD_SSEL_PIN, 1);
|
||||
spi_transmit((uint8_t []) {0x36}, 1, true); // memory data access control
|
||||
omv_gpio_write(OMV_SPI_LCD_RS_PIN, 1);
|
||||
omv_gpio_write(OMV_SPI_LCD_SSEL_PIN, 0);
|
||||
HAL_SPI_Transmit(hspi, (uint8_t []) {bgr ? 0xC8 : 0xC0}, 1, HAL_MAX_DELAY); // argument
|
||||
omv_gpio_write(OMV_SPI_LCD_SSEL_PIN, 1);
|
||||
spi_transmit((uint8_t []) {bgr ? 0xC8 : 0xC0}, 1, true); // argument
|
||||
|
||||
omv_gpio_write(OMV_SPI_LCD_RS_PIN, 0);
|
||||
omv_gpio_write(OMV_SPI_LCD_SSEL_PIN, 0);
|
||||
HAL_SPI_Transmit(hspi, (uint8_t []) {0x3A}, 1, HAL_MAX_DELAY); // interface pixel format
|
||||
omv_gpio_write(OMV_SPI_LCD_SSEL_PIN, 1);
|
||||
spi_transmit((uint8_t []) {0x3A}, 1, true); // interface pixel format
|
||||
omv_gpio_write(OMV_SPI_LCD_RS_PIN, 1);
|
||||
omv_gpio_write(OMV_SPI_LCD_SSEL_PIN, 0);
|
||||
HAL_SPI_Transmit(hspi, (uint8_t []) {0x05}, 1, HAL_MAX_DELAY); // argument
|
||||
omv_gpio_write(OMV_SPI_LCD_SSEL_PIN, 1);
|
||||
spi_transmit((uint8_t []) {0x05}, 1, true); // argument
|
||||
|
||||
if (triple_buffer) {
|
||||
fb_alloc_mark();
|
||||
@ -165,38 +172,6 @@ static void spi_config_init(int w, int h, int refresh_rate, bool triple_buffer,
|
||||
framebuffers[i] = (uint16_t *) fb_alloc0(w * h * sizeof(uint16_t), FB_ALLOC_CACHE_ALIGN);
|
||||
}
|
||||
|
||||
dma_init(&spi_tx_dma, OMV_SPI_LCD_CONTROLLER->tx_dma_descr, DMA_MEMORY_TO_PERIPH, hspi);
|
||||
hspi->hdmatx = &spi_tx_dma;
|
||||
hspi->hdmarx = NULL;
|
||||
#if defined(MCU_SERIES_H7)
|
||||
spi_tx_dma.Init.PeriphDataAlignment = DMA_PDATAALIGN_WORD;
|
||||
#else
|
||||
spi_tx_dma.Init.PeriphDataAlignment = DMA_PDATAALIGN_HALFWORD;
|
||||
#endif
|
||||
spi_tx_dma.Init.MemDataAlignment = DMA_MDATAALIGN_WORD;
|
||||
spi_tx_dma.Init.FIFOMode = DMA_FIFOMODE_ENABLE;
|
||||
spi_tx_dma.Init.FIFOThreshold = DMA_FIFO_THRESHOLD_FULL;
|
||||
spi_tx_dma.Init.MemBurst = DMA_MBURST_INC4;
|
||||
#if defined(MCU_SERIES_H7)
|
||||
spi_tx_dma.Init.PeriphBurst = DMA_PBURST_INC4;
|
||||
#else
|
||||
spi_tx_dma.Init.PeriphBurst = DMA_PBURST_SINGLE;
|
||||
#endif
|
||||
DMA_Stream_TypeDef *dma_chan = spi_tx_dma.Instance;
|
||||
#if defined(MCU_SERIES_H7)
|
||||
dma_chan->CR = (dma_chan->CR & ~DMA_SxCR_PSIZE_Msk) | DMA_PDATAALIGN_WORD;
|
||||
#else
|
||||
dma_chan->CR = (dma_chan->CR & ~DMA_SxCR_PSIZE_Msk) | DMA_PDATAALIGN_HALFWORD;
|
||||
#endif
|
||||
dma_chan->CR = (dma_chan->CR & ~DMA_SxCR_MSIZE_Msk) | DMA_MDATAALIGN_WORD;
|
||||
dma_chan->FCR = (dma_chan->FCR & ~DMA_SxFCR_DMDIS_Msk) | DMA_FIFOMODE_ENABLE;
|
||||
dma_chan->FCR = (dma_chan->FCR & ~DMA_SxFCR_FTH_Msk) | DMA_FIFO_THRESHOLD_FULL;
|
||||
dma_chan->CR = (dma_chan->CR & ~DMA_SxCR_MBURST_Msk) | DMA_MBURST_INC4;
|
||||
#if defined(MCU_SERIES_H7)
|
||||
dma_chan->CR = (dma_chan->CR & ~DMA_SxCR_PBURST_Msk) | DMA_PBURST_INC4;
|
||||
#else
|
||||
dma_chan->CR = (dma_chan->CR & ~DMA_SxCR_PBURST_Msk) | DMA_PBURST_SINGLE;
|
||||
#endif
|
||||
fb_alloc_mark_permanent();
|
||||
}
|
||||
}
|
||||
@ -207,82 +182,89 @@ static const uint8_t display_off[] = {0x28};
|
||||
static const uint8_t display_on[] = {0x29};
|
||||
static const uint8_t memory_write[] = {0x2C};
|
||||
|
||||
static void spi_lcd_callback(SPI_HandleTypeDef *hspi) {
|
||||
static void spi_lcd_callback(omv_spi_t *spi, void *userdata, void *buf) {
|
||||
if (lcd_type == LCD_SHIELD) {
|
||||
static uint16_t *spi_tx_cb_state_memory_write_addr = NULL;
|
||||
static uint8_t *spi_tx_cb_state_memory_write_addr = NULL;
|
||||
static size_t spi_tx_cb_state_memory_write_count = 0;
|
||||
static bool spi_tx_cb_state_memory_write_first = false;
|
||||
|
||||
switch (spi_tx_cb_state) {
|
||||
case SPI_TX_CB_MEMORY_WRITE_CMD: {
|
||||
omv_gpio_write(OMV_SPI_LCD_SSEL_PIN, 1);
|
||||
omv_gpio_write(OMV_SPI_LCD_RS_PIN, 0);
|
||||
if (!spi_tx_cb_state_on[framebuffer_tail]) {
|
||||
omv_gpio_write(OMV_SPI_LCD_SSEL_PIN, 1);
|
||||
omv_gpio_write(OMV_SPI_LCD_RS_PIN, 0);
|
||||
spi_tx_cb_state = SPI_TX_CB_DISPLAY_OFF;
|
||||
framebuffer_head = framebuffer_tail;
|
||||
omv_gpio_write(OMV_SPI_LCD_SSEL_PIN, 0);
|
||||
HAL_SPI_Transmit_IT(hspi, (uint8_t *) display_off, sizeof(display_off));
|
||||
omv_spi_transfer_t spi_xfer = {
|
||||
.txbuf = (uint8_t *) display_off,
|
||||
.size = sizeof(display_off),
|
||||
.flags = OMV_SPI_XFER_NONBLOCK,
|
||||
.callback = spi_lcd_callback,
|
||||
};
|
||||
omv_spi_transfer_start(&spi_bus, &spi_xfer);
|
||||
} else {
|
||||
omv_gpio_write(OMV_SPI_LCD_SSEL_PIN, 1);
|
||||
omv_gpio_write(OMV_SPI_LCD_RS_PIN, 0);
|
||||
spi_tx_cb_state = SPI_TX_CB_MEMORY_WRITE;
|
||||
spi_tx_cb_state_memory_write_addr = framebuffers[framebuffer_tail];
|
||||
spi_tx_cb_state_memory_write_addr = (uint8_t *) framebuffers[framebuffer_tail];
|
||||
spi_tx_cb_state_memory_write_count = lcd_width * lcd_height;
|
||||
if (lcd_byte_reverse) {
|
||||
spi_tx_cb_state_memory_write_count *= 2;
|
||||
}
|
||||
spi_tx_cb_state_memory_write_first = true;
|
||||
framebuffer_head = framebuffer_tail;
|
||||
omv_gpio_write(OMV_SPI_LCD_SSEL_PIN, 0);
|
||||
// When starting the interrupt chain the first HAL_SPI_Transmit_IT is not executed
|
||||
// in interrupt context. So, disable interrupts for the first HAL_SPI_Transmit_IT so
|
||||
// When starting the interrupt chain the first transfer is not executed
|
||||
// in interrupt context. So, disable interrupts for the first transfer so
|
||||
// that it completes first and unlocks the SPI bus before allowing the interrupt
|
||||
// it causes to trigger starting the interrupt chain.
|
||||
omv_spi_transfer_t spi_xfer = {
|
||||
.txbuf = (uint8_t *) memory_write,
|
||||
.size = sizeof(memory_write),
|
||||
.flags = OMV_SPI_XFER_NONBLOCK,
|
||||
.callback = spi_lcd_callback,
|
||||
};
|
||||
uint32_t irq_state = disable_irq();
|
||||
HAL_SPI_Transmit_IT(hspi, (uint8_t *) memory_write, sizeof(memory_write));
|
||||
omv_spi_transfer_start(&spi_bus, &spi_xfer);
|
||||
enable_irq(irq_state);
|
||||
}
|
||||
break;
|
||||
}
|
||||
case SPI_TX_CB_MEMORY_WRITE: {
|
||||
uint16_t *addr = spi_tx_cb_state_memory_write_addr;
|
||||
size_t count = IM_MIN(spi_tx_cb_state_memory_write_count, (65536 - 8u));
|
||||
spi_tx_cb_state =
|
||||
(spi_tx_cb_state_memory_write_count > (65536 - 8u)) ? SPI_TX_CB_MEMORY_WRITE : SPI_TX_CB_DISPLAY_ON;
|
||||
spi_tx_cb_state_memory_write_addr += count;
|
||||
size_t spi_tx_cb_state_memory_write_limit = (!lcd_byte_reverse)
|
||||
? OMV_SPI_MAX_16BIT_XFER : OMV_SPI_MAX_8BIT_XFER;
|
||||
uint8_t *addr = spi_tx_cb_state_memory_write_addr;
|
||||
size_t count = IM_MIN(spi_tx_cb_state_memory_write_count, spi_tx_cb_state_memory_write_limit);
|
||||
spi_tx_cb_state = (spi_tx_cb_state_memory_write_count > spi_tx_cb_state_memory_write_limit)
|
||||
? SPI_TX_CB_MEMORY_WRITE : SPI_TX_CB_DISPLAY_ON;
|
||||
spi_tx_cb_state_memory_write_addr += (!lcd_byte_reverse) ? (count * 2) : count;
|
||||
spi_tx_cb_state_memory_write_count -= count;
|
||||
if (spi_tx_cb_state_memory_write_first) {
|
||||
omv_gpio_write(OMV_SPI_LCD_SSEL_PIN, 1);
|
||||
omv_gpio_write(OMV_SPI_LCD_RS_PIN, 1);
|
||||
spi_tx_cb_state_memory_write_first = false;
|
||||
if (!lcd_byte_reverse) {
|
||||
hspi->Init.DataSize = SPI_DATASIZE_16BIT;
|
||||
#if defined(MCU_SERIES_H7)
|
||||
hspi->Instance->CFG1 = (hspi->Instance->CFG1 & ~SPI_CFG1_DSIZE_Msk) | SPI_DATASIZE_16BIT;
|
||||
hspi->Instance->CFG1 = (hspi->Instance->CFG1 & ~SPI_CFG1_FTHLV_Msk) | SPI_FIFO_THRESHOLD_08DATA;
|
||||
#elif defined(MCU_SERIES_F7)
|
||||
hspi->Instance->CR2 = (hspi->Instance->CR2 & ~SPI_CR2_DS_Msk) | SPI_DATASIZE_16BIT;
|
||||
#elif defined(MCU_SERIES_F4)
|
||||
hspi->Instance->CR1 = (hspi->Instance->CR1 & ~SPI_CR1_DFF_Msk) | SPI_DATASIZE_16BIT;
|
||||
#endif
|
||||
}
|
||||
omv_gpio_write(OMV_SPI_LCD_SSEL_PIN, 0);
|
||||
}
|
||||
HAL_SPI_Transmit_DMA(hspi, (uint8_t *) addr, count);
|
||||
omv_spi_transfer_t spi_xfer = {
|
||||
.txbuf = addr,
|
||||
.size = count,
|
||||
.flags = OMV_SPI_XFER_DMA | ((!lcd_byte_reverse) ? OMV_SPI_XFER_16_BIT : 0),
|
||||
.callback = spi_lcd_callback,
|
||||
};
|
||||
omv_spi_transfer_start(&spi_bus, &spi_xfer);
|
||||
break;
|
||||
}
|
||||
case SPI_TX_CB_DISPLAY_ON: {
|
||||
omv_gpio_write(OMV_SPI_LCD_SSEL_PIN, 1);
|
||||
omv_gpio_write(OMV_SPI_LCD_RS_PIN, 0);
|
||||
spi_tx_cb_state = SPI_TX_CB_MEMORY_WRITE_CMD;
|
||||
hspi->Init.DataSize = SPI_DATASIZE_8BIT;
|
||||
#if defined(MCU_SERIES_H7)
|
||||
hspi->Instance->CFG1 = (hspi->Instance->CFG1 & ~SPI_CFG1_DSIZE_Msk) | SPI_DATASIZE_8BIT;
|
||||
hspi->Instance->CFG1 = (hspi->Instance->CFG1 & ~SPI_CFG1_FTHLV_Msk) | SPI_FIFO_THRESHOLD_01DATA;
|
||||
#elif defined(MCU_SERIES_F7)
|
||||
hspi->Instance->CR2 = (hspi->Instance->CR2 & ~SPI_CR2_DS_Msk) | SPI_DATASIZE_8BIT;
|
||||
#elif defined(MCU_SERIES_F4)
|
||||
hspi->Instance->CR1 = (hspi->Instance->CR1 & ~SPI_CR1_DFF_Msk) | SPI_DATASIZE_8BIT;
|
||||
#endif
|
||||
omv_gpio_write(OMV_SPI_LCD_SSEL_PIN, 0);
|
||||
HAL_SPI_Transmit_IT(hspi, (uint8_t *) display_on, sizeof(display_on));
|
||||
omv_spi_transfer_t spi_xfer = {
|
||||
.txbuf = (uint8_t *) display_on,
|
||||
.size = sizeof(display_on),
|
||||
.flags = OMV_SPI_XFER_NONBLOCK,
|
||||
.callback = spi_lcd_callback,
|
||||
};
|
||||
omv_spi_transfer_start(&spi_bus, &spi_xfer);
|
||||
break;
|
||||
}
|
||||
case SPI_TX_CB_DISPLAY_OFF: {
|
||||
@ -314,12 +296,12 @@ static void spi_lcd_kick() {
|
||||
}
|
||||
|
||||
spi_tx_cb_state = SPI_TX_CB_MEMORY_WRITE_CMD;
|
||||
spi_lcd_callback(OMV_SPI_LCD_CONTROLLER->spi);
|
||||
spi_lcd_callback(&spi_bus, NULL, NULL);
|
||||
}
|
||||
}
|
||||
|
||||
static void spi_lcd_draw_image_cb(int x_start, int x_end, int y_row, imlib_draw_row_data_t *data) {
|
||||
HAL_SPI_Transmit(OMV_SPI_LCD_CONTROLLER->spi, data->dst_row_override, lcd_width, HAL_MAX_DELAY);
|
||||
spi_transmit_16(data->dst_row_override, lcd_width);
|
||||
}
|
||||
|
||||
static void spi_lcd_display(image_t *src_img, int dst_x_start, int dst_y_start,
|
||||
@ -335,35 +317,23 @@ static void spi_lcd_display(image_t *src_img, int dst_x_start, int dst_y_start,
|
||||
x_scale, y_scale, roi, alpha, alpha_palette, hint, &x0, &x1, &y0, &y1);
|
||||
|
||||
if (!lcd_triple_buffer) {
|
||||
SPI_HandleTypeDef *hspi = OMV_SPI_LCD_CONTROLLER->spi;
|
||||
dst_img.data = fb_alloc0(lcd_width * sizeof(uint16_t), FB_ALLOC_NO_HINT);
|
||||
|
||||
omv_gpio_write(OMV_SPI_LCD_RS_PIN, 0);
|
||||
omv_gpio_write(OMV_SPI_LCD_SSEL_PIN, 0);
|
||||
// memory write
|
||||
HAL_SPI_Transmit(hspi, (uint8_t *) memory_write, sizeof(memory_write), HAL_MAX_DELAY);
|
||||
omv_gpio_write(OMV_SPI_LCD_SSEL_PIN, 1);
|
||||
spi_transmit((uint8_t *) memory_write, sizeof(memory_write), true);
|
||||
omv_gpio_write(OMV_SPI_LCD_RS_PIN, 1);
|
||||
|
||||
omv_gpio_write(OMV_SPI_LCD_SSEL_PIN, 0);
|
||||
hspi->Init.DataSize = SPI_DATASIZE_16BIT;
|
||||
#if defined(MCU_SERIES_H7)
|
||||
hspi->Instance->CFG1 = (hspi->Instance->CFG1 & ~SPI_CFG1_DSIZE_Msk) | SPI_DATASIZE_16BIT;
|
||||
#elif defined(MCU_SERIES_F7)
|
||||
hspi->Instance->CR2 = (hspi->Instance->CR2 & ~SPI_CR2_DS_Msk) | SPI_DATASIZE_16BIT;
|
||||
#elif defined(MCU_SERIES_F4)
|
||||
hspi->Instance->CR1 = (hspi->Instance->CR1 & ~SPI_CR1_DFF_Msk) | SPI_DATASIZE_16BIT;
|
||||
#endif
|
||||
|
||||
if (black) {
|
||||
// zero the whole image
|
||||
for (int i = 0; i < lcd_height; i++) {
|
||||
HAL_SPI_Transmit(hspi, dst_img.data, lcd_width, HAL_MAX_DELAY);
|
||||
spi_transmit_16(dst_img.data, lcd_width);
|
||||
}
|
||||
} else {
|
||||
// Zero the top rows
|
||||
for (int i = 0; i < y0; i++) {
|
||||
HAL_SPI_Transmit(hspi, dst_img.data, lcd_width, HAL_MAX_DELAY);
|
||||
spi_transmit_16(dst_img.data, lcd_width);
|
||||
}
|
||||
|
||||
// Transmits left/right parts already zeroed...
|
||||
@ -375,25 +345,16 @@ static void spi_lcd_display(image_t *src_img, int dst_x_start, int dst_y_start,
|
||||
if (y1 < lcd_height) {
|
||||
memset(dst_img.data, 0, lcd_width * sizeof(uint16_t));
|
||||
}
|
||||
|
||||
for (int i = y1; i < lcd_height; i++) {
|
||||
HAL_SPI_Transmit(hspi, dst_img.data, lcd_width, HAL_MAX_DELAY);
|
||||
spi_transmit_16(dst_img.data, lcd_width);
|
||||
}
|
||||
}
|
||||
|
||||
hspi->Init.DataSize = SPI_DATASIZE_8BIT;
|
||||
#if defined(MCU_SERIES_H7)
|
||||
hspi->Instance->CFG1 = (hspi->Instance->CFG1 & ~SPI_CFG1_DSIZE_Msk) | SPI_DATASIZE_8BIT;
|
||||
#elif defined(MCU_SERIES_F7)
|
||||
hspi->Instance->CR2 = (hspi->Instance->CR2 & ~SPI_CR2_DS_Msk) | SPI_DATASIZE_8BIT;
|
||||
#elif defined(MCU_SERIES_F4)
|
||||
hspi->Instance->CR1 = (hspi->Instance->CR1 & ~SPI_CR1_DFF_Msk) | SPI_DATASIZE_8BIT;
|
||||
#endif
|
||||
omv_gpio_write(OMV_SPI_LCD_SSEL_PIN, 1);
|
||||
|
||||
omv_gpio_write(OMV_SPI_LCD_RS_PIN, 0);
|
||||
omv_gpio_write(OMV_SPI_LCD_SSEL_PIN, 0);
|
||||
HAL_SPI_Transmit(hspi, (uint8_t *) display_on, sizeof(display_on), HAL_MAX_DELAY);
|
||||
omv_gpio_write(OMV_SPI_LCD_SSEL_PIN, 1);
|
||||
spi_transmit((uint8_t *) display_on, sizeof(display_on), true);
|
||||
omv_gpio_write(OMV_SPI_LCD_RS_PIN, 1);
|
||||
|
||||
fb_free();
|
||||
@ -459,9 +420,7 @@ static void spi_lcd_display(image_t *src_img, int dst_x_start, int dst_y_start,
|
||||
static void spi_lcd_clear() {
|
||||
if (!lcd_triple_buffer) {
|
||||
omv_gpio_write(OMV_SPI_LCD_RS_PIN, 0);
|
||||
omv_gpio_write(OMV_SPI_LCD_SSEL_PIN, 0);
|
||||
HAL_SPI_Transmit(OMV_SPI_LCD_CONTROLLER->spi, (uint8_t *) display_off, sizeof(display_off), HAL_MAX_DELAY);
|
||||
omv_gpio_write(OMV_SPI_LCD_SSEL_PIN, 1);
|
||||
spi_transmit((uint8_t *) display_off, sizeof(display_off), true);
|
||||
omv_gpio_write(OMV_SPI_LCD_RS_PIN, 1);
|
||||
} else {
|
||||
// For triple buffering we are never drawing where tail or head (which may instantly update to
|
||||
@ -529,7 +488,7 @@ static void spi_lcd_set_backlight(int intensity) {
|
||||
lcd_intensity = intensity;
|
||||
}
|
||||
#endif // OMV_SPI_LCD_BL_PIN
|
||||
#endif // OMV_SPI_LCD_CONTROLLER
|
||||
#endif // OMV_SPI_LCD_SPI_BUS
|
||||
|
||||
#ifdef OMV_LCD_CONTROLLER
|
||||
static const uint32_t resolution_clock[] = {
|
||||
@ -1303,7 +1262,7 @@ static void ltdc_dvi_register_hotplug_cb(mp_obj_t cb) {
|
||||
|
||||
STATIC mp_obj_t py_lcd_deinit() {
|
||||
switch (lcd_type) {
|
||||
#ifdef OMV_SPI_LCD_CONTROLLER
|
||||
#ifdef OMV_SPI_LCD_SPI_BUS
|
||||
case LCD_SHIELD: {
|
||||
spi_config_deinit();
|
||||
#ifdef OMV_SPI_LCD_BL_PIN
|
||||
@ -1361,7 +1320,7 @@ STATIC mp_obj_t py_lcd_init(uint n_args, const mp_obj_t *args, mp_map_t *kw_args
|
||||
int type = py_helper_keyword_int(n_args, args, 0, kw_args, MP_OBJ_NEW_QSTR(MP_QSTR_type), LCD_SHIELD);
|
||||
|
||||
switch (type) {
|
||||
#ifdef OMV_SPI_LCD_CONTROLLER
|
||||
#ifdef OMV_SPI_LCD_SPI_BUS
|
||||
case LCD_SHIELD: {
|
||||
int w = py_helper_keyword_int(n_args, args, 1, kw_args, MP_OBJ_NEW_QSTR(MP_QSTR_width), 128);
|
||||
if ((w <= 0) || (32767 < w)) {
|
||||
@ -1375,10 +1334,16 @@ STATIC mp_obj_t py_lcd_init(uint n_args, const mp_obj_t *args, mp_map_t *kw_args
|
||||
if ((refresh_rate < 30) || (120 < refresh_rate)) {
|
||||
mp_raise_msg(&mp_type_ValueError, MP_ERROR_TEXT("Invalid Refresh Rate!"));
|
||||
}
|
||||
bool triple_buffer = py_helper_keyword_int(n_args, args, 4, kw_args, MP_OBJ_NEW_QSTR(MP_QSTR_triple_buffer), false);
|
||||
bool triple_buffer_def = false;
|
||||
#ifdef OMV_SPI_LCD_DEF_TRIPLE_BUF
|
||||
triple_buffer_def = OMV_SPI_LCD_DEF_TRIPLE_BUF;
|
||||
#endif
|
||||
bool triple_buffer = py_helper_keyword_int(n_args, args, 4, kw_args,
|
||||
MP_OBJ_NEW_QSTR(MP_QSTR_triple_buffer), triple_buffer_def);
|
||||
bool bgr = py_helper_keyword_int(n_args, args, 5, kw_args, MP_OBJ_NEW_QSTR(MP_QSTR_bgr), false);
|
||||
bool byte_reverse = py_helper_keyword_int(n_args, args, 6, kw_args, MP_OBJ_NEW_QSTR(MP_QSTR_byte_reverse), false);
|
||||
spi_config_init(w, h, refresh_rate, triple_buffer, bgr);
|
||||
bool byte_reverse = py_helper_keyword_int(n_args, args, 6, kw_args,
|
||||
MP_OBJ_NEW_QSTR(MP_QSTR_byte_reverse), false);
|
||||
spi_config_init(w, h, refresh_rate, triple_buffer, bgr, byte_reverse);
|
||||
#ifdef OMV_SPI_LCD_BL_PIN
|
||||
spi_lcd_set_backlight(255); // to on state
|
||||
#endif
|
||||
@ -1517,7 +1482,7 @@ STATIC mp_obj_t py_lcd_set_backlight(mp_obj_t intensity_obj) {
|
||||
}
|
||||
|
||||
switch (lcd_type) {
|
||||
#if defined(OMV_SPI_LCD_CONTROLLER) && defined(OMV_SPI_LCD_BL_PIN)
|
||||
#if defined(OMV_SPI_LCD_SPI_BUS) && defined(OMV_SPI_LCD_BL_PIN)
|
||||
case LCD_SHIELD: {
|
||||
spi_lcd_set_backlight(intensity);
|
||||
break;
|
||||
@ -1736,7 +1701,7 @@ STATIC mp_obj_t py_lcd_display(uint n_args, const mp_obj_t *args, mp_map_t *kw_a
|
||||
}
|
||||
|
||||
switch (lcd_type) {
|
||||
#ifdef OMV_SPI_LCD_CONTROLLER
|
||||
#ifdef OMV_SPI_LCD_SPI_BUS
|
||||
case LCD_SHIELD: {
|
||||
fb_alloc_mark();
|
||||
spi_lcd_display(arg_img, arg_x_off, arg_y_off, arg_x_scale, arg_y_scale, &arg_roi,
|
||||
@ -1765,7 +1730,7 @@ STATIC MP_DEFINE_CONST_FUN_OBJ_KW(py_lcd_display_obj, 1, py_lcd_display);
|
||||
|
||||
STATIC mp_obj_t py_lcd_clear(uint n_args, const mp_obj_t *args) {
|
||||
switch (lcd_type) {
|
||||
#ifdef OMV_SPI_LCD_CONTROLLER
|
||||
#ifdef OMV_SPI_LCD_SPI_BUS
|
||||
case LCD_SHIELD: {
|
||||
if (n_args && mp_obj_get_int(*args)) {
|
||||
// turns the display off (may not be black)
|
||||
@ -1916,4 +1881,5 @@ void py_lcd_init0() {
|
||||
}
|
||||
|
||||
MP_REGISTER_MODULE(MP_QSTR_lcd, lcd_module);
|
||||
|
||||
#endif // MICROPY_PY_LCD
|
||||
@ -11,8 +11,6 @@
|
||||
#include "omv_boardconfig.h"
|
||||
|
||||
#if MICROPY_PY_LCD
|
||||
#include STM32_HAL_H
|
||||
|
||||
#include "py/obj.h"
|
||||
#include "py/nlr.h"
|
||||
#include "py/runtime.h"
|
||||
@ -1,9 +1,9 @@
|
||||
/*
|
||||
* This file is part of the OpenMV project.
|
||||
*
|
||||
* Copyright (c) 2013-2020 Ibrahim Abdelkader <iabdalkader@openmv.io>
|
||||
* Copyright (c) 2013-2020 Kwabena W. Agyeman <kwagyeman@openmv.io>
|
||||
* Copyright (c) 2013-2020 Kaizhi Wong <kidswong999@gmail.com>
|
||||
* Copyright (c) 2013-2023 Ibrahim Abdelkader <iabdalkader@openmv.io>
|
||||
* Copyright (c) 2013-2023 Kwabena W. Agyeman <kwagyeman@openmv.io>
|
||||
* Copyright (c) 2013-2023 Kaizhi Wong <kidswong999@gmail.com>
|
||||
*
|
||||
* This work is licensed under the MIT license, see the file LICENSE for details.
|
||||
*
|
||||
@ -12,16 +12,15 @@
|
||||
#include "omv_boardconfig.h"
|
||||
|
||||
#if MICROPY_PY_TV
|
||||
#include STM32_HAL_H
|
||||
|
||||
#include "py/obj.h"
|
||||
#include "py/nlr.h"
|
||||
#include "py/runtime.h"
|
||||
#include "spi.h"
|
||||
|
||||
#include "py_helper.h"
|
||||
#include "py_image.h"
|
||||
#include "omv_gpio.h"
|
||||
#include "omv_spi.h"
|
||||
|
||||
#define TV_WIDTH 352
|
||||
#define TV_HEIGHT 240
|
||||
@ -35,7 +34,7 @@
|
||||
#error "TV_HEIGHT not even"
|
||||
#endif
|
||||
|
||||
#ifdef OMV_SPI_LCD_CONTROLLER
|
||||
#ifdef OMV_SPI_LCD_SPI_BUS
|
||||
/////////////////////////////////////////////////////////////
|
||||
// http://www.vsdsp-forum.com/phpbb/viewtopic.php?f=14&t=1801
|
||||
/////////////////////////////////////////////////////////////
|
||||
@ -207,70 +206,67 @@
|
||||
#error "TV_WIDTH * TV_HEIGHT is too big!"
|
||||
#endif
|
||||
|
||||
static void SpiRamWriteByteRegister(int opcode, int data) {
|
||||
uint8_t packet[2] = {opcode, data};
|
||||
#define TV_BAUDRATE (TV_WIDTH * TV_HEIGHT * TV_REFRESH * PICBITS)
|
||||
|
||||
static omv_spi_t spi_bus = {};
|
||||
|
||||
static void SpiTransmitReceivePacket(uint8_t *txdata, uint8_t *rxdata, uint16_t size, bool end) {
|
||||
omv_spi_transfer_t spi_xfer = {
|
||||
.txbuf = txdata,
|
||||
.rxbuf = rxdata,
|
||||
.size = size,
|
||||
.timeout = OMV_SPI_MAX_TIMEOUT,
|
||||
.flags = OMV_SPI_XFER_BLOCKING
|
||||
};
|
||||
|
||||
omv_gpio_write(OMV_SPI_LCD_SSEL_PIN, 0);
|
||||
HAL_SPI_Transmit(OMV_SPI_LCD_CONTROLLER->spi, packet, sizeof(packet), HAL_MAX_DELAY);
|
||||
omv_gpio_write(OMV_SPI_LCD_SSEL_PIN, 1);
|
||||
omv_spi_transfer_start(&spi_bus, &spi_xfer);
|
||||
|
||||
if (end) {
|
||||
omv_gpio_write(OMV_SPI_LCD_SSEL_PIN, 1);
|
||||
}
|
||||
}
|
||||
|
||||
static void SpiRamWriteByteRegister(int opcode, int data) {
|
||||
uint8_t packet[2] = {opcode, data};
|
||||
SpiTransmitReceivePacket(packet, NULL, sizeof(packet), true);
|
||||
}
|
||||
|
||||
static int SpiRamReadByteRegister(int opcode) {
|
||||
uint8_t packet[2] = {opcode, 0};
|
||||
|
||||
omv_gpio_write(OMV_SPI_LCD_SSEL_PIN, 0);
|
||||
HAL_SPI_TransmitReceive(OMV_SPI_LCD_CONTROLLER->spi, packet, packet, sizeof(packet), HAL_MAX_DELAY);
|
||||
omv_gpio_write(OMV_SPI_LCD_SSEL_PIN, 1);
|
||||
|
||||
SpiTransmitReceivePacket(packet, packet, sizeof(packet), true);
|
||||
return packet[1];
|
||||
}
|
||||
|
||||
static void SpiRamWriteWordRegister(int opcode, int data) {
|
||||
uint8_t packet[3] = {opcode, data >> 8, data};
|
||||
|
||||
omv_gpio_write(OMV_SPI_LCD_SSEL_PIN, 0);
|
||||
HAL_SPI_Transmit(OMV_SPI_LCD_CONTROLLER->spi, packet, sizeof(packet), HAL_MAX_DELAY);
|
||||
omv_gpio_write(OMV_SPI_LCD_SSEL_PIN, 1);
|
||||
SpiTransmitReceivePacket(packet, NULL, sizeof(packet), true);
|
||||
}
|
||||
|
||||
static void SpiClearRam() {
|
||||
uint8_t packet[4] = {WRITE_SRAM, 0, 0, 0};
|
||||
|
||||
omv_gpio_write(OMV_SPI_LCD_SSEL_PIN, 0);
|
||||
HAL_SPI_Transmit(OMV_SPI_LCD_CONTROLLER->spi, packet, sizeof(packet), HAL_MAX_DELAY);
|
||||
|
||||
SpiTransmitReceivePacket(packet, NULL, sizeof(packet), false);
|
||||
packet[0] = 0;
|
||||
|
||||
for (int i = 0; i < (SPI_RAM_SIZE / sizeof(packet)); i++) {
|
||||
HAL_SPI_Transmit(OMV_SPI_LCD_CONTROLLER->spi, packet, sizeof(packet), HAL_MAX_DELAY);
|
||||
SpiTransmitReceivePacket(packet, NULL, sizeof(packet), (i + 1) == (SPI_RAM_SIZE / sizeof(packet)));
|
||||
}
|
||||
|
||||
omv_gpio_write(OMV_SPI_LCD_SSEL_PIN, 1);
|
||||
}
|
||||
|
||||
static void SpiRamWriteProgram(int data0, int data1, int data2, int data3) {
|
||||
uint8_t packet[5] = {PROGRAM, data3, data2, data1, data0};
|
||||
|
||||
omv_gpio_write(OMV_SPI_LCD_SSEL_PIN, 0);
|
||||
HAL_SPI_Transmit(OMV_SPI_LCD_CONTROLLER->spi, packet, sizeof(packet), HAL_MAX_DELAY);
|
||||
omv_gpio_write(OMV_SPI_LCD_SSEL_PIN, 1);
|
||||
SpiTransmitReceivePacket(packet, NULL, sizeof(packet), true);
|
||||
}
|
||||
|
||||
static void SpiRamWriteLowPassFilter(int data) {
|
||||
uint8_t packet[6] = {WRITE_BLOCKMVC1, 0, 0, 0, 0, data};
|
||||
|
||||
omv_gpio_write(OMV_SPI_LCD_SSEL_PIN, 0);
|
||||
HAL_SPI_Transmit(OMV_SPI_LCD_CONTROLLER->spi, packet, sizeof(packet), HAL_MAX_DELAY);
|
||||
omv_gpio_write(OMV_SPI_LCD_SSEL_PIN, 1);
|
||||
SpiTransmitReceivePacket(packet, NULL, sizeof(packet), true);
|
||||
}
|
||||
|
||||
static void SpiRamWriteWord(int w_address, int data) {
|
||||
int address = w_address * sizeof(uint16_t);
|
||||
uint8_t packet[6] = {WRITE_SRAM, address >> 16, address >> 8, address, data >> 8, data};
|
||||
|
||||
omv_gpio_write(OMV_SPI_LCD_SSEL_PIN, 0);
|
||||
HAL_SPI_Transmit(OMV_SPI_LCD_CONTROLLER->spi, packet, sizeof(packet), HAL_MAX_DELAY);
|
||||
omv_gpio_write(OMV_SPI_LCD_SSEL_PIN, 1);
|
||||
SpiTransmitReceivePacket(packet, NULL, sizeof(packet), true);
|
||||
}
|
||||
|
||||
static void SpiRamWriteVSyncProtoLine(int line, int length_1, int length_2) {
|
||||
@ -294,10 +290,7 @@ static void SpiRamWriteLine(int line, int index) {
|
||||
int address = INDEX_START_BYTES + (line * LINE_INDEX_BYTE_SIZE);
|
||||
int data = index << 7;
|
||||
uint8_t packet[7] = {WRITE_SRAM, address >> 16, address >> 8, address, data, data >> 8, data >> 16};
|
||||
|
||||
omv_gpio_write(OMV_SPI_LCD_SSEL_PIN, 0);
|
||||
HAL_SPI_Transmit(OMV_SPI_LCD_CONTROLLER->spi, packet, sizeof(packet), HAL_MAX_DELAY);
|
||||
omv_gpio_write(OMV_SPI_LCD_SSEL_PIN, 1);
|
||||
SpiTransmitReceivePacket(packet, NULL, sizeof(packet), true);
|
||||
}
|
||||
|
||||
static void SpiRamVideoInit() {
|
||||
@ -402,9 +395,7 @@ tv_type = TV_NONE;
|
||||
|
||||
static bool tv_triple_buffer = false;
|
||||
|
||||
#ifdef OMV_SPI_LCD_CONTROLLER
|
||||
static DMA_HandleTypeDef spi_tx_dma = {};
|
||||
|
||||
#ifdef OMV_SPI_LCD_SPI_BUS
|
||||
static volatile enum {
|
||||
SPI_TX_CB_IDLE,
|
||||
SPI_TX_CB_MEMORY_WRITE_CMD,
|
||||
@ -414,39 +405,23 @@ spi_tx_cb_state = SPI_TX_CB_IDLE;
|
||||
|
||||
static void spi_config_deinit() {
|
||||
if (tv_triple_buffer) {
|
||||
HAL_SPI_Abort(OMV_SPI_LCD_CONTROLLER->spi);
|
||||
omv_spi_transfer_abort(&spi_bus);
|
||||
spi_tx_cb_state = SPI_TX_CB_IDLE;
|
||||
fb_alloc_free_till_mark_past_mark_permanent();
|
||||
}
|
||||
|
||||
spi_deinit(OMV_SPI_LCD_CONTROLLER);
|
||||
|
||||
// Do not put in HAL_SPI_MspDeinit as other modules share the SPI2 bus.
|
||||
omv_gpio_deinit(OMV_SPI_LCD_MOSI_PIN);
|
||||
omv_gpio_deinit(OMV_SPI_LCD_MISO_PIN);
|
||||
omv_gpio_deinit(OMV_SPI_LCD_SCLK_PIN);
|
||||
omv_gpio_deinit(OMV_SPI_LCD_SSEL_PIN);
|
||||
omv_spi_deinit(&spi_bus);
|
||||
}
|
||||
|
||||
static void spi_tv_callback(SPI_HandleTypeDef *hspi);
|
||||
|
||||
static void spi_config_init(bool triple_buffer) {
|
||||
OMV_SPI_LCD_CONTROLLER->spi->Init.Mode = SPI_MODE_MASTER;
|
||||
OMV_SPI_LCD_CONTROLLER->spi->Init.Direction = SPI_DIRECTION_2LINES;
|
||||
OMV_SPI_LCD_CONTROLLER->spi->Init.NSS = SPI_NSS_SOFT;
|
||||
OMV_SPI_LCD_CONTROLLER->spi->Init.TIMode = SPI_TIMODE_DISABLE;
|
||||
OMV_SPI_LCD_CONTROLLER->spi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
|
||||
spi_set_params(OMV_SPI_LCD_CONTROLLER, 0xffffffff,
|
||||
TV_WIDTH * TV_HEIGHT * TV_REFRESH * PICBITS,
|
||||
0, 0, 8, 0);
|
||||
spi_init(OMV_SPI_LCD_CONTROLLER, true);
|
||||
HAL_SPI_RegisterCallback(OMV_SPI_LCD_CONTROLLER->spi, HAL_SPI_TX_COMPLETE_CB_ID, spi_tv_callback);
|
||||
omv_spi_config_t spi_config;
|
||||
omv_spi_default_config(&spi_config, OMV_SPI_LCD_SPI_BUS);
|
||||
|
||||
spi_config.baudrate = TV_BAUDRATE;
|
||||
spi_config.nss_enable = false;
|
||||
spi_config.dma_flags = triple_buffer ? OMV_SPI_DMA_NORMAL : 0;
|
||||
omv_spi_init(&spi_bus, &spi_config);
|
||||
|
||||
// Do not put in HAL_SPI_MspInit as other modules share the SPI2 bus.
|
||||
omv_gpio_config(OMV_SPI_LCD_MOSI_PIN, OMV_GPIO_MODE_ALT, OMV_GPIO_PULL_NONE, OMV_GPIO_SPEED_MED, -1);
|
||||
omv_gpio_config(OMV_SPI_LCD_MISO_PIN, OMV_GPIO_MODE_ALT, OMV_GPIO_PULL_NONE, OMV_GPIO_SPEED_MED, -1);
|
||||
omv_gpio_config(OMV_SPI_LCD_SCLK_PIN, OMV_GPIO_MODE_ALT, OMV_GPIO_PULL_NONE, OMV_GPIO_SPEED_MED, -1);
|
||||
omv_gpio_config(OMV_SPI_LCD_SSEL_PIN, OMV_GPIO_MODE_OUTPUT, OMV_GPIO_PULL_NONE, OMV_GPIO_SPEED_LOW, -1);
|
||||
omv_gpio_write(OMV_SPI_LCD_SSEL_PIN, 1);
|
||||
|
||||
SpiRamVideoInit();
|
||||
@ -464,51 +439,19 @@ static void spi_config_init(bool triple_buffer) {
|
||||
framebuffers[i] = (uint16_t *) fb_alloc0(TV_WIDTH_RGB565 * TV_HEIGHT, FB_ALLOC_CACHE_ALIGN);
|
||||
}
|
||||
|
||||
dma_init(&spi_tx_dma, OMV_SPI_LCD_CONTROLLER->tx_dma_descr, DMA_MEMORY_TO_PERIPH, OMV_SPI_LCD_CONTROLLER->spi);
|
||||
OMV_SPI_LCD_CONTROLLER->spi->hdmatx = &spi_tx_dma;
|
||||
OMV_SPI_LCD_CONTROLLER->spi->hdmarx = NULL;
|
||||
#if defined(MCU_SERIES_H7)
|
||||
spi_tx_dma.Init.PeriphDataAlignment = DMA_PDATAALIGN_WORD;
|
||||
#else
|
||||
spi_tx_dma.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;
|
||||
#endif
|
||||
spi_tx_dma.Init.MemDataAlignment = DMA_MDATAALIGN_WORD;
|
||||
spi_tx_dma.Init.FIFOMode = DMA_FIFOMODE_ENABLE;
|
||||
spi_tx_dma.Init.FIFOThreshold = DMA_FIFO_THRESHOLD_FULL;
|
||||
spi_tx_dma.Init.MemBurst = DMA_MBURST_INC4;
|
||||
#if defined(MCU_SERIES_H7)
|
||||
spi_tx_dma.Init.PeriphBurst = DMA_PBURST_INC4;
|
||||
#else
|
||||
spi_tx_dma.Init.PeriphBurst = DMA_PBURST_SINGLE;
|
||||
#endif
|
||||
DMA_Stream_TypeDef *dma_chan = spi_tx_dma.Instance;
|
||||
#if defined(MCU_SERIES_H7)
|
||||
dma_chan->CR = (dma_chan->CR & ~DMA_SxCR_PSIZE_Msk) | DMA_PDATAALIGN_WORD;
|
||||
#else
|
||||
dma_chan->CR = (dma_chan->CR & ~DMA_SxCR_PSIZE_Msk) | DMA_PDATAALIGN_BYTE;
|
||||
#endif
|
||||
dma_chan->CR = (dma_chan->CR & ~DMA_SxCR_MSIZE_Msk) | DMA_MDATAALIGN_WORD;
|
||||
dma_chan->FCR = (dma_chan->FCR & ~DMA_SxFCR_DMDIS_Msk) | DMA_FIFOMODE_ENABLE;
|
||||
dma_chan->FCR = (dma_chan->FCR & ~DMA_SxFCR_FTH_Msk) | DMA_FIFO_THRESHOLD_FULL;
|
||||
dma_chan->CR = (dma_chan->CR & ~DMA_SxCR_MBURST_Msk) | DMA_MBURST_INC4;
|
||||
#if defined(MCU_SERIES_H7)
|
||||
dma_chan->CR = (dma_chan->CR & ~DMA_SxCR_PBURST_Msk) | DMA_PBURST_INC4;
|
||||
#else
|
||||
dma_chan->CR = (dma_chan->CR & ~DMA_SxCR_PBURST_Msk) | DMA_PBURST_SINGLE;
|
||||
#endif
|
||||
fb_alloc_mark_permanent();
|
||||
}
|
||||
}
|
||||
|
||||
static const uint8_t write_sram[] = {
|
||||
// Cannot be allocated on the stack for HAL_SPI_Transmit_IT().
|
||||
// Cannot be allocated on the stack.
|
||||
WRITE_SRAM,
|
||||
(uint8_t) (PICLINE_BYTE_ADDRESS(0) >> 16),
|
||||
(uint8_t) (PICLINE_BYTE_ADDRESS(0) >> 8),
|
||||
(uint8_t) (PICLINE_BYTE_ADDRESS(0) >> 0)
|
||||
};
|
||||
|
||||
static void spi_tv_callback(SPI_HandleTypeDef *hspi) {
|
||||
static void spi_tv_callback(omv_spi_t *spi, void *userdata, void *buf) {
|
||||
if (tv_type == TV_SHIELD) {
|
||||
static uint8_t *spi_tx_cb_state_memory_write_addr = NULL;
|
||||
static size_t spi_tx_cb_state_memory_write_count = 0;
|
||||
@ -520,33 +463,37 @@ static void spi_tv_callback(SPI_HandleTypeDef *hspi) {
|
||||
spi_tx_cb_state_memory_write_addr = (uint8_t *) framebuffers[framebuffer_head];
|
||||
spi_tx_cb_state_memory_write_count = PICLINE_LENGTH_BYTES * TV_HEIGHT;
|
||||
framebuffer_tail = framebuffer_head;
|
||||
#if defined(MCU_SERIES_H7)
|
||||
OMV_SPI_LCD_CONTROLLER->spi->Instance->CFG1 =
|
||||
(OMV_SPI_LCD_CONTROLLER->spi->Instance->CFG1 & ~SPI_CFG1_FTHLV_Msk) | SPI_FIFO_THRESHOLD_01DATA;
|
||||
#endif
|
||||
omv_gpio_write(OMV_SPI_LCD_SSEL_PIN, 0);
|
||||
// When starting the interrupt chain the first HAL_SPI_Transmit_IT is not executed
|
||||
// in interrupt context. So, disable interrupts for the first HAL_SPI_Transmit_IT so
|
||||
// When starting the interrupt chain the first transfer is not executed
|
||||
// in interrupt context. So, disable interrupts for the first transfer so
|
||||
// that it completes first and unlocks the SPI bus before allowing the interrupt
|
||||
// it causes to trigger starting the interrupt chain.
|
||||
omv_spi_transfer_t spi_xfer = {
|
||||
.txbuf = (uint8_t *) write_sram,
|
||||
.size = sizeof(write_sram),
|
||||
.flags = OMV_SPI_XFER_NONBLOCK,
|
||||
.callback = spi_tv_callback,
|
||||
};
|
||||
uint32_t irq_state = disable_irq();
|
||||
HAL_SPI_Transmit_IT(OMV_SPI_LCD_CONTROLLER->spi, (uint8_t *) write_sram, sizeof(write_sram));
|
||||
omv_spi_transfer_start(&spi_bus, &spi_xfer);
|
||||
enable_irq(irq_state);
|
||||
break;
|
||||
}
|
||||
case SPI_TX_CB_MEMORY_WRITE: {
|
||||
uint8_t *addr = spi_tx_cb_state_memory_write_addr;
|
||||
size_t count = IM_MIN(spi_tx_cb_state_memory_write_count, (65536 - 16u));
|
||||
spi_tx_cb_state = (spi_tx_cb_state_memory_write_count > (65536 - 16))
|
||||
size_t count = IM_MIN(spi_tx_cb_state_memory_write_count, OMV_SPI_MAX_8BIT_XFER);
|
||||
spi_tx_cb_state = (spi_tx_cb_state_memory_write_count > OMV_SPI_MAX_8BIT_XFER)
|
||||
? SPI_TX_CB_MEMORY_WRITE
|
||||
: SPI_TX_CB_MEMORY_WRITE_CMD;
|
||||
spi_tx_cb_state_memory_write_addr += count;
|
||||
spi_tx_cb_state_memory_write_count -= count;
|
||||
#if defined(MCU_SERIES_H7)
|
||||
OMV_SPI_LCD_CONTROLLER->spi->Instance->CFG1 =
|
||||
(OMV_SPI_LCD_CONTROLLER->spi->Instance->CFG1 & ~SPI_CFG1_FTHLV_Msk) | SPI_FIFO_THRESHOLD_16DATA;
|
||||
#endif
|
||||
HAL_SPI_Transmit_DMA(OMV_SPI_LCD_CONTROLLER->spi, addr, count);
|
||||
omv_spi_transfer_t spi_xfer = {
|
||||
.txbuf = addr,
|
||||
.size = count,
|
||||
.flags = OMV_SPI_XFER_DMA,
|
||||
.callback = spi_tv_callback,
|
||||
};
|
||||
omv_spi_transfer_start(&spi_bus, &spi_xfer);
|
||||
break;
|
||||
}
|
||||
default: {
|
||||
@ -619,12 +566,12 @@ static void spi_tv_draw_image_cb_convert_rgb565(uint16_t *row_pointer_i, uint8_t
|
||||
|
||||
static void spi_tv_draw_image_cb_grayscale(int x_start, int x_end, int y_row, imlib_draw_row_data_t *data) {
|
||||
spi_tv_draw_image_cb_convert_grayscale((uint8_t *) data->dst_row_override, (uint8_t *) data->dst_row_override);
|
||||
HAL_SPI_Transmit(OMV_SPI_LCD_CONTROLLER->spi, data->dst_row_override, PICLINE_LENGTH_BYTES, HAL_MAX_DELAY);
|
||||
SpiTransmitReceivePacket(data->dst_row_override, NULL, PICLINE_LENGTH_BYTES, false);
|
||||
}
|
||||
|
||||
static void spi_tv_draw_image_cb_rgb565(int x_start, int x_end, int y_row, imlib_draw_row_data_t *data) {
|
||||
spi_tv_draw_image_cb_convert_rgb565((uint16_t *) data->dst_row_override, (uint8_t *) data->dst_row_override);
|
||||
HAL_SPI_Transmit(OMV_SPI_LCD_CONTROLLER->spi, data->dst_row_override, PICLINE_LENGTH_BYTES, HAL_MAX_DELAY);
|
||||
SpiTransmitReceivePacket(data->dst_row_override, NULL, PICLINE_LENGTH_BYTES, false);
|
||||
}
|
||||
|
||||
static void spi_tv_display(image_t *src_img, int dst_x_start, int dst_y_start, float x_scale, float y_scale,
|
||||
@ -645,19 +592,18 @@ static void spi_tv_display(image_t *src_img, int dst_x_start, int dst_y_start, f
|
||||
|
||||
if (!tv_triple_buffer) {
|
||||
dst_img.data = fb_alloc0(TV_WIDTH_RGB565, FB_ALLOC_NO_HINT);
|
||||
omv_gpio_write(OMV_SPI_LCD_SSEL_PIN, 0);
|
||||
|
||||
HAL_SPI_Transmit(OMV_SPI_LCD_CONTROLLER->spi, (uint8_t *) write_sram, sizeof(write_sram), HAL_MAX_DELAY);
|
||||
SpiTransmitReceivePacket((uint8_t *) write_sram, NULL, sizeof(write_sram), false);
|
||||
|
||||
if (black) {
|
||||
// zero the whole image
|
||||
for (int i = 0; i < TV_HEIGHT; i++) {
|
||||
HAL_SPI_Transmit(OMV_SPI_LCD_CONTROLLER->spi, dst_img.data, PICLINE_LENGTH_BYTES, HAL_MAX_DELAY);
|
||||
SpiTransmitReceivePacket(dst_img.data, NULL, PICLINE_LENGTH_BYTES, false);
|
||||
}
|
||||
} else {
|
||||
// Zero the top rows
|
||||
for (int i = 0; i < y0; i++) {
|
||||
HAL_SPI_Transmit(OMV_SPI_LCD_CONTROLLER->spi, dst_img.data, PICLINE_LENGTH_BYTES, HAL_MAX_DELAY);
|
||||
SpiTransmitReceivePacket(dst_img.data, NULL, PICLINE_LENGTH_BYTES, false);
|
||||
}
|
||||
|
||||
// Transmits left/right parts already zeroed...
|
||||
@ -671,7 +617,7 @@ static void spi_tv_display(image_t *src_img, int dst_x_start, int dst_y_start, f
|
||||
}
|
||||
|
||||
for (int i = y1; i < TV_HEIGHT; i++) {
|
||||
HAL_SPI_Transmit(OMV_SPI_LCD_CONTROLLER->spi, dst_img.data, PICLINE_LENGTH_BYTES, HAL_MAX_DELAY);
|
||||
SpiTransmitReceivePacket(dst_img.data, NULL, PICLINE_LENGTH_BYTES, false);
|
||||
}
|
||||
}
|
||||
|
||||
@ -782,7 +728,7 @@ static void spi_tv_display(image_t *src_img, int dst_x_start, int dst_y_start, f
|
||||
// Kick off an update of the display.
|
||||
if (spi_tx_cb_state == SPI_TX_CB_IDLE) {
|
||||
spi_tx_cb_state = SPI_TX_CB_MEMORY_WRITE_CMD;
|
||||
spi_tv_callback(OMV_SPI_LCD_CONTROLLER->spi);
|
||||
spi_tv_callback(&spi_bus, NULL, NULL);
|
||||
}
|
||||
}
|
||||
}
|
||||
@ -790,7 +736,7 @@ static void spi_tv_display(image_t *src_img, int dst_x_start, int dst_y_start, f
|
||||
|
||||
STATIC mp_obj_t py_tv_deinit() {
|
||||
switch (tv_type) {
|
||||
#ifdef OMV_SPI_LCD_CONTROLLER
|
||||
#ifdef OMV_SPI_LCD_SPI_BUS
|
||||
case TV_SHIELD: {
|
||||
spi_config_deinit();
|
||||
break;
|
||||
@ -814,10 +760,14 @@ STATIC mp_obj_t py_tv_init(uint n_args, const mp_obj_t *args, mp_map_t *kw_args)
|
||||
MP_OBJ_NEW_QSTR(MP_QSTR_type), TV_SHIELD);
|
||||
|
||||
switch (type) {
|
||||
#ifdef OMV_SPI_LCD_CONTROLLER
|
||||
#ifdef OMV_SPI_LCD_SPI_BUS
|
||||
case TV_SHIELD: {
|
||||
bool triple_buffer_def = false;
|
||||
#ifdef OMV_SPI_LCD_DEF_TRIPLE_BUF
|
||||
triple_buffer_def = OMV_SPI_LCD_DEF_TRIPLE_BUF;
|
||||
#endif
|
||||
bool triple_buffer = py_helper_keyword_int(n_args, args, 1, kw_args,
|
||||
MP_OBJ_NEW_QSTR(MP_QSTR_triple_buffer), false);
|
||||
MP_OBJ_NEW_QSTR(MP_QSTR_triple_buffer), triple_buffer_def);
|
||||
spi_config_init(triple_buffer);
|
||||
tv_type = TV_SHIELD;
|
||||
tv_triple_buffer = triple_buffer;
|
||||
@ -883,9 +833,9 @@ STATIC mp_obj_t py_tv_channel(uint n_args, const mp_obj_t *args) {
|
||||
return mp_const_none;
|
||||
}
|
||||
|
||||
#ifdef OMV_SPI_LCD_CONTROLLER
|
||||
#ifdef OMV_SPI_LCD_SPI_BUS
|
||||
if (tv_triple_buffer) {
|
||||
HAL_SPI_Abort(OMV_SPI_LCD_CONTROLLER->spi);
|
||||
omv_spi_transfer_abort(&spi_bus);
|
||||
spi_tx_cb_state = SPI_TX_CB_IDLE;
|
||||
omv_gpio_write(OMV_SPI_LCD_SSEL_PIN, 1);
|
||||
}
|
||||
@ -899,7 +849,13 @@ STATIC mp_obj_t py_tv_channel(uint n_args, const mp_obj_t *args) {
|
||||
|
||||
SpiRamWriteByteRegister(WRITE_GPIO, 0x70 | (channel - 1));
|
||||
} else {
|
||||
#ifdef OMV_SPI_LCD_RX_CLK_DIV
|
||||
omv_spi_set_baudrate(&spi_bus, TV_BAUDRATE / OMV_SPI_LCD_RX_CLK_DIV);
|
||||
#endif
|
||||
int channel = SpiRamReadByteRegister(READ_GPIO);
|
||||
#ifdef OMV_SPI_LCD_RX_CLK_DIV
|
||||
omv_spi_set_baudrate(&spi_bus, TV_BAUDRATE);
|
||||
#endif
|
||||
return mp_obj_new_int((channel & 0x7) + 1);
|
||||
}
|
||||
#endif
|
||||
@ -993,7 +949,7 @@ STATIC mp_obj_t py_tv_display(uint n_args, const mp_obj_t *args, mp_map_t *kw_ar
|
||||
}
|
||||
|
||||
switch (tv_type) {
|
||||
#ifdef OMV_SPI_LCD_CONTROLLER
|
||||
#ifdef OMV_SPI_LCD_SPI_BUS
|
||||
case TV_SHIELD: {
|
||||
fb_alloc_mark();
|
||||
spi_tv_display(arg_img, arg_x_off, arg_y_off, arg_x_scale, arg_y_scale, &arg_roi,
|
||||
@ -1013,7 +969,7 @@ STATIC MP_DEFINE_CONST_FUN_OBJ_KW(py_tv_display_obj, 1, py_tv_display);
|
||||
|
||||
STATIC mp_obj_t py_tv_clear() {
|
||||
switch (tv_type) {
|
||||
#ifdef OMV_SPI_LCD_CONTROLLER
|
||||
#ifdef OMV_SPI_LCD_SPI_BUS
|
||||
case TV_SHIELD: {
|
||||
fb_alloc_mark();
|
||||
spi_tv_display(NULL, 0, 0, 1.f, 1.f, NULL,
|
||||
@ -1059,4 +1015,5 @@ void py_tv_init0() {
|
||||
}
|
||||
|
||||
MP_REGISTER_MODULE(MP_QSTR_tv, tv_module);
|
||||
|
||||
#endif // MICROPY_PY_TV
|
||||
@ -151,10 +151,6 @@ SECTIONS
|
||||
_vfs_buf = .; // VFS struct + FATFS file buffer (around 624 bytes)
|
||||
. = . + OMV_VFS_BUF_SIZE;
|
||||
|
||||
. = ALIGN(16);
|
||||
_fir_lepton_buf = .; // FIR Lepton Packet Double Buffer (328 bytes)
|
||||
. = . + OMV_FIR_LEPTON_BUF_SIZE;
|
||||
|
||||
#if defined(OMV_FFS_BUF_SIZE)
|
||||
. = ALIGN(16);
|
||||
_micropy_hw_internal_flash_storage_ram_cache_start = .;
|
||||
|
||||
@ -128,10 +128,6 @@ SECTIONS
|
||||
_vfs_buf = .; // VFS struct + FATFS file buffer (around 624 bytes)
|
||||
. = . + OMV_VFS_BUF_SIZE;
|
||||
|
||||
. = ALIGN(16);
|
||||
_fir_lepton_buf = .; // FIR Lepton Packet Double Buffer (328 bytes)
|
||||
. = . + OMV_FIR_LEPTON_BUF_SIZE;
|
||||
|
||||
#if defined(OMV_FFS_BUF_SIZE)
|
||||
. = ALIGN(16);
|
||||
_ffs_cache = .; // Flash filesystem cache
|
||||
|
||||
Loading…
Reference in New Issue
Block a user