Merge pull request #930 from openmv/pll_fixes

PLL Fixes
This commit is contained in:
Ibrahim Abd Elkader 2020-10-22 00:44:54 +02:00 committed by GitHub
commit 4dcc74cd25
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5 changed files with 22 additions and 3 deletions

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@ -229,12 +229,24 @@ void SystemClock_Config(void)
RCC_OscInitStruct.HSI48State = OMV_OSC_HSI48_STATE; RCC_OscInitStruct.HSI48State = OMV_OSC_HSI48_STATE;
RCC_OscInitStruct.OscillatorType |= RCC_OSCILLATORTYPE_HSI48; RCC_OscInitStruct.OscillatorType |= RCC_OSCILLATORTYPE_HSI48;
#endif #endif
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
RCC_OscInitStruct.PLL.PLLM = OMV_OSC_PLL1M; RCC_OscInitStruct.PLL.PLLM = OMV_OSC_PLL1M;
RCC_OscInitStruct.PLL.PLLN = OMV_OSC_PLL1N; RCC_OscInitStruct.PLL.PLLN = OMV_OSC_PLL1N;
RCC_OscInitStruct.PLL.PLLQ = OMV_OSC_PLL1Q; RCC_OscInitStruct.PLL.PLLQ = OMV_OSC_PLL1Q;
RCC_OscInitStruct.PLL.PLLP = OMV_OSC_PLL1P; RCC_OscInitStruct.PLL.PLLP = OMV_OSC_PLL1P;
#if defined(MCU_SERIES_H7)
// Override PLL1 frequency for revision Y devices,
// with maximum frequency of 400MHz CPU 200MHz Bus.
if (HAL_GetREVID() < 0x2003) {
// 400MHz/200MHz
RCC_OscInitStruct.PLL.PLLN = 200;
RCC_OscInitStruct.PLL.PLLQ = 16;
}
#endif
#if defined(OMV_OSC_PLL1R) #if defined(OMV_OSC_PLL1R)
RCC_OscInitStruct.PLL.PLLR = OMV_OSC_PLL1R; RCC_OscInitStruct.PLL.PLLR = OMV_OSC_PLL1R;
#endif #endif
@ -275,7 +287,7 @@ void SystemClock_Config(void)
PeriphClkInitStruct.PLL3.PLL3FRACN = OMV_OSC_PLL3FRAC; PeriphClkInitStruct.PLL3.PLL3FRACN = OMV_OSC_PLL3FRAC;
#endif #endif
#if defined(STM32H743xx) || defined(STM32H747xx) #if defined(MCU_SERIES_H7)
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_RTC|RCC_PERIPHCLK_FDCAN PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_RTC|RCC_PERIPHCLK_FDCAN
|RCC_PERIPHCLK_SPI3|RCC_PERIPHCLK_SPI2 |RCC_PERIPHCLK_SPI3|RCC_PERIPHCLK_SPI2
|RCC_PERIPHCLK_SDMMC|RCC_PERIPHCLK_I2C2 |RCC_PERIPHCLK_SDMMC|RCC_PERIPHCLK_I2C2
@ -292,7 +304,7 @@ void SystemClock_Config(void)
PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_LSI; PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_LSI;
PeriphClkInitStruct.I2c123ClockSelection = RCC_I2C123CLKSOURCE_D2PCLK1; PeriphClkInitStruct.I2c123ClockSelection = RCC_I2C123CLKSOURCE_D2PCLK1;
PeriphClkInitStruct.Spi45ClockSelection = RCC_SPI45CLKSOURCE_PLL2; PeriphClkInitStruct.Spi45ClockSelection = RCC_SPI45CLKSOURCE_PLL2;
PeriphClkInitStruct.RngClockSelection = RCC_RNGCLKSOURCE_HSI48; PeriphClkInitStruct.RngClockSelection = OMV_OSC_RNG_CLKSOURCE;
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) { if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) {
// Initialization Error // Initialization Error

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@ -109,12 +109,14 @@
#define OMV_OSC_PLL3FRAC (0) #define OMV_OSC_PLL3FRAC (0)
// Clock Sources // Clock Sources
#define OMV_OSC_USB_CLKSOURCE RCC_USBCLKSOURCE_PLL #define OMV_OSC_USB_CLKSOURCE RCC_USBCLKSOURCE_HSI48
#define OMV_OSC_RNG_CLKSOURCE RCC_RNGCLKSOURCE_HSI48
#define OMV_OSC_ADC_CLKSOURCE RCC_ADCCLKSOURCE_PLL3 #define OMV_OSC_ADC_CLKSOURCE RCC_ADCCLKSOURCE_PLL3
#define OMV_OSC_SPI123_CLKSOURCE RCC_SPI123CLKSOURCE_PLL3 #define OMV_OSC_SPI123_CLKSOURCE RCC_SPI123CLKSOURCE_PLL3
// HSE/HSI/CSI State // HSE/HSI/CSI State
#define OMV_OSC_HSE_STATE (RCC_HSE_ON) #define OMV_OSC_HSE_STATE (RCC_HSE_ON)
#define OMV_OSC_HSI48_STATE (RCC_HSI48_ON)
// Flash Latency // Flash Latency
#define OMV_FLASH_LATENCY (FLASH_LATENCY_2) #define OMV_FLASH_LATENCY (FLASH_LATENCY_2)

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@ -114,11 +114,13 @@
// Clock Sources // Clock Sources
#define OMV_OSC_USB_CLKSOURCE RCC_USBCLKSOURCE_PLL #define OMV_OSC_USB_CLKSOURCE RCC_USBCLKSOURCE_PLL
#define OMV_OSC_RNG_CLKSOURCE RCC_RNGCLKSOURCE_HSI48
#define OMV_OSC_ADC_CLKSOURCE RCC_ADCCLKSOURCE_PLL3 #define OMV_OSC_ADC_CLKSOURCE RCC_ADCCLKSOURCE_PLL3
#define OMV_OSC_SPI123_CLKSOURCE RCC_SPI123CLKSOURCE_PLL3 #define OMV_OSC_SPI123_CLKSOURCE RCC_SPI123CLKSOURCE_PLL3
// HSE/HSI/CSI State // HSE/HSI/CSI State
#define OMV_OSC_HSE_STATE (RCC_HSE_ON) #define OMV_OSC_HSE_STATE (RCC_HSE_ON)
#define OMV_OSC_HSI48_STATE (RCC_HSI48_ON)
// Flash Latency // Flash Latency
#define OMV_FLASH_LATENCY (FLASH_LATENCY_2) #define OMV_FLASH_LATENCY (FLASH_LATENCY_2)

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@ -81,6 +81,7 @@
// Clock Sources // Clock Sources
#define OMV_OSC_USB_CLKSOURCE RCC_USBCLKSOURCE_PLL #define OMV_OSC_USB_CLKSOURCE RCC_USBCLKSOURCE_PLL
#define OMV_OSC_RNG_CLKSOURCE RCC_RNGCLKSOURCE_HSI48
#define OMV_OSC_ADC_CLKSOURCE RCC_ADCCLKSOURCE_PLL2 #define OMV_OSC_ADC_CLKSOURCE RCC_ADCCLKSOURCE_PLL2
#define OMV_OSC_SPI123_CLKSOURCE RCC_SPI123CLKSOURCE_PLL2 #define OMV_OSC_SPI123_CLKSOURCE RCC_SPI123CLKSOURCE_PLL2
@ -116,6 +117,7 @@
// HSE/HSI/CSI State // HSE/HSI/CSI State
#define OMV_OSC_HSE_STATE (RCC_HSE_ON) #define OMV_OSC_HSE_STATE (RCC_HSE_ON)
#define OMV_OSC_HSI48_STATE (RCC_HSI48_ON)
// Flash Latency // Flash Latency
#define OMV_FLASH_LATENCY (FLASH_LATENCY_2) #define OMV_FLASH_LATENCY (FLASH_LATENCY_2)

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@ -109,6 +109,7 @@
// Clock Sources // Clock Sources
#define OMV_OSC_USB_CLKSOURCE RCC_USBCLKSOURCE_HSI48 #define OMV_OSC_USB_CLKSOURCE RCC_USBCLKSOURCE_HSI48
#define OMV_OSC_RNG_CLKSOURCE RCC_RNGCLKSOURCE_HSI48
#define OMV_OSC_ADC_CLKSOURCE RCC_ADCCLKSOURCE_PLL3 #define OMV_OSC_ADC_CLKSOURCE RCC_ADCCLKSOURCE_PLL3
#define OMV_OSC_SPI123_CLKSOURCE RCC_SPI123CLKSOURCE_PLL3 #define OMV_OSC_SPI123_CLKSOURCE RCC_SPI123CLKSOURCE_PLL3