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https://github.com/openmv/openmv.git
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commit
4dcc74cd25
@ -229,12 +229,24 @@ void SystemClock_Config(void)
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RCC_OscInitStruct.HSI48State = OMV_OSC_HSI48_STATE;
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RCC_OscInitStruct.OscillatorType |= RCC_OSCILLATORTYPE_HSI48;
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#endif
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RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
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RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
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RCC_OscInitStruct.PLL.PLLM = OMV_OSC_PLL1M;
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RCC_OscInitStruct.PLL.PLLN = OMV_OSC_PLL1N;
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RCC_OscInitStruct.PLL.PLLQ = OMV_OSC_PLL1Q;
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RCC_OscInitStruct.PLL.PLLP = OMV_OSC_PLL1P;
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#if defined(MCU_SERIES_H7)
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// Override PLL1 frequency for revision Y devices,
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// with maximum frequency of 400MHz CPU 200MHz Bus.
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if (HAL_GetREVID() < 0x2003) {
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// 400MHz/200MHz
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RCC_OscInitStruct.PLL.PLLN = 200;
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RCC_OscInitStruct.PLL.PLLQ = 16;
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}
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#endif
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#if defined(OMV_OSC_PLL1R)
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RCC_OscInitStruct.PLL.PLLR = OMV_OSC_PLL1R;
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#endif
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@ -275,7 +287,7 @@ void SystemClock_Config(void)
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PeriphClkInitStruct.PLL3.PLL3FRACN = OMV_OSC_PLL3FRAC;
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#endif
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#if defined(STM32H743xx) || defined(STM32H747xx)
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#if defined(MCU_SERIES_H7)
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PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_RTC|RCC_PERIPHCLK_FDCAN
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|RCC_PERIPHCLK_SPI3|RCC_PERIPHCLK_SPI2
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|RCC_PERIPHCLK_SDMMC|RCC_PERIPHCLK_I2C2
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@ -292,7 +304,7 @@ void SystemClock_Config(void)
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PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_LSI;
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PeriphClkInitStruct.I2c123ClockSelection = RCC_I2C123CLKSOURCE_D2PCLK1;
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PeriphClkInitStruct.Spi45ClockSelection = RCC_SPI45CLKSOURCE_PLL2;
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PeriphClkInitStruct.RngClockSelection = RCC_RNGCLKSOURCE_HSI48;
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PeriphClkInitStruct.RngClockSelection = OMV_OSC_RNG_CLKSOURCE;
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if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) {
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// Initialization Error
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@ -109,12 +109,14 @@
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#define OMV_OSC_PLL3FRAC (0)
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// Clock Sources
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#define OMV_OSC_USB_CLKSOURCE RCC_USBCLKSOURCE_PLL
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#define OMV_OSC_USB_CLKSOURCE RCC_USBCLKSOURCE_HSI48
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#define OMV_OSC_RNG_CLKSOURCE RCC_RNGCLKSOURCE_HSI48
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#define OMV_OSC_ADC_CLKSOURCE RCC_ADCCLKSOURCE_PLL3
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#define OMV_OSC_SPI123_CLKSOURCE RCC_SPI123CLKSOURCE_PLL3
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// HSE/HSI/CSI State
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#define OMV_OSC_HSE_STATE (RCC_HSE_ON)
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#define OMV_OSC_HSI48_STATE (RCC_HSI48_ON)
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// Flash Latency
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#define OMV_FLASH_LATENCY (FLASH_LATENCY_2)
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@ -114,11 +114,13 @@
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// Clock Sources
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#define OMV_OSC_USB_CLKSOURCE RCC_USBCLKSOURCE_PLL
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#define OMV_OSC_RNG_CLKSOURCE RCC_RNGCLKSOURCE_HSI48
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#define OMV_OSC_ADC_CLKSOURCE RCC_ADCCLKSOURCE_PLL3
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#define OMV_OSC_SPI123_CLKSOURCE RCC_SPI123CLKSOURCE_PLL3
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// HSE/HSI/CSI State
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#define OMV_OSC_HSE_STATE (RCC_HSE_ON)
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#define OMV_OSC_HSI48_STATE (RCC_HSI48_ON)
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// Flash Latency
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#define OMV_FLASH_LATENCY (FLASH_LATENCY_2)
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@ -81,6 +81,7 @@
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// Clock Sources
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#define OMV_OSC_USB_CLKSOURCE RCC_USBCLKSOURCE_PLL
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#define OMV_OSC_RNG_CLKSOURCE RCC_RNGCLKSOURCE_HSI48
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#define OMV_OSC_ADC_CLKSOURCE RCC_ADCCLKSOURCE_PLL2
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#define OMV_OSC_SPI123_CLKSOURCE RCC_SPI123CLKSOURCE_PLL2
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@ -116,6 +117,7 @@
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// HSE/HSI/CSI State
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#define OMV_OSC_HSE_STATE (RCC_HSE_ON)
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#define OMV_OSC_HSI48_STATE (RCC_HSI48_ON)
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// Flash Latency
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#define OMV_FLASH_LATENCY (FLASH_LATENCY_2)
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@ -109,6 +109,7 @@
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// Clock Sources
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#define OMV_OSC_USB_CLKSOURCE RCC_USBCLKSOURCE_HSI48
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#define OMV_OSC_RNG_CLKSOURCE RCC_RNGCLKSOURCE_HSI48
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#define OMV_OSC_ADC_CLKSOURCE RCC_ADCCLKSOURCE_PLL3
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#define OMV_OSC_SPI123_CLKSOURCE RCC_SPI123CLKSOURCE_PLL3
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