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https://github.com/openmv/openmv.git
synced 2025-11-04 14:49:50 +08:00
Update bormio/nicla pinout.
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@ -1 +1 @@
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Subproject commit 4503313ffe14e1eae06cfe0f762e941a3074c92f
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Subproject commit 34d5776f7195cb52345041d199843e22bd2da868
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@ -80,21 +80,25 @@
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#define OMV_CORE_VBAT "3.0"
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// USB IRQn.
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#define OMV_USB_IRQN (OTG_FS_IRQn)
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#define OMV_USB_IRQN (OTG_HS_IRQn)
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// PLL1 48MHz for SDMMC and FDCAN
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#define OMV_OSC_PLL1M (16)
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#define OMV_OSC_PLL1N (240)
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// Defined for cpu frequency scaling to override the revid.
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#define OMV_MAX_CPU_FREQ (400)
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// PLL1 400MHz/40MHz for SDMMC and FDCAN
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// USB and RNG are clocked from the HSI48
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#define OMV_OSC_PLL1M (5)
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#define OMV_OSC_PLL1N (160)
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#define OMV_OSC_PLL1P (2)
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#define OMV_OSC_PLL1Q (20)
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#define OMV_OSC_PLL1Q (16)
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#define OMV_OSC_PLL1R (2)
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#define OMV_OSC_PLL1VCI (RCC_PLL1VCIRANGE_2)
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#define OMV_OSC_PLL1VCO (RCC_PLL1VCOWIDE)
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#define OMV_OSC_PLL1FRAC (0)
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// PLL2 200MHz for FMC and QSPI.
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#define OMV_OSC_PLL2M (16)
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#define OMV_OSC_PLL2N (100)
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#define OMV_OSC_PLL2M (5)
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#define OMV_OSC_PLL2N (80)
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#define OMV_OSC_PLL2P (2)
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#define OMV_OSC_PLL2Q (2)
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#define OMV_OSC_PLL2R (2)
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@ -103,31 +107,32 @@
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#define OMV_OSC_PLL2FRAC (0)
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// PLL3 160MHz for ADC and SPI123
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#define OMV_OSC_PLL3M (16)
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#define OMV_OSC_PLL3N (80)
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#define OMV_OSC_PLL3M (5)
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#define OMV_OSC_PLL3N (160)
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#define OMV_OSC_PLL3P (2)
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#define OMV_OSC_PLL3Q (2)
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#define OMV_OSC_PLL3Q (5)
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#define OMV_OSC_PLL3R (2)
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#define OMV_OSC_PLL3VCI (RCC_PLL3VCIRANGE_2)
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#define OMV_OSC_PLL3VCO (RCC_PLL3VCOWIDE)
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#define OMV_OSC_PLL3FRAC (0)
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// Clock Sources
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#define OMV_OSC_PLL_CLKSOURCE RCC_PLLSOURCE_HSI
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#define OMV_OSC_PLL_CLKSOURCE RCC_PLLSOURCE_HSE
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#define OMV_OSC_USB_CLKSOURCE RCC_USBCLKSOURCE_HSI48
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#define OMV_OSC_RNG_CLKSOURCE RCC_RNGCLKSOURCE_HSI48
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#define OMV_OSC_ADC_CLKSOURCE RCC_ADCCLKSOURCE_PLL3
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#define OMV_OSC_SPI45_CLKSOURCE RCC_SPI45CLKSOURCE_PLL3
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#define OMV_OSC_SPI123_CLKSOURCE RCC_SPI123CLKSOURCE_PLL3
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// HSE/HSI/CSI State
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#define OMV_OSC_HSI_STATE (RCC_HSI_DIV1)
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#define OMV_OSC_HSE_STATE (RCC_HSE_BYPASS)
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#define OMV_OSC_HSI48_STATE (RCC_HSI48_ON)
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// Flash Latency
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#define OMV_FLASH_LATENCY (FLASH_LATENCY_2)
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// Power supply configuration
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#define OMV_PWR_SUPPLY (PWR_LDO_SUPPLY)
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#define OMV_PWR_SUPPLY (PWR_SMPS_1V8_SUPPLIES_LDO)
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// Linker script constants (see the linker script template stm32fxxx.ld.S).
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// Note: fb_alloc is a stack-based, dynamically allocated memory on FB.
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@ -200,9 +205,10 @@
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#define ISC_I2C_AF (GPIO_AF4_I2C3)
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#define ISC_I2C_CLK_ENABLE() __I2C3_CLK_ENABLE()
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#define ISC_I2C_CLK_DISABLE() __I2C3_CLK_DISABLE()
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#define ISC_I2C_PORT (GPIOH)
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#define ISC_I2C_SCL_PIN (GPIO_PIN_7)
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#define ISC_I2C_SDA_PIN (GPIO_PIN_8)
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#define ISC_I2C_SCL_PORT (GPIOA)
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#define ISC_I2C_SCL_PIN (GPIO_PIN_8)
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#define ISC_I2C_SDA_PORT (GPIOC)
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#define ISC_I2C_SDA_PIN (GPIO_PIN_9)
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#define ISC_I2C_SPEED (CAMBUS_SPEED_STANDARD)
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#define ISC_I2C_FORCE_RESET() __HAL_RCC_I2C3_FORCE_RESET()
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#define ISC_I2C_RELEASE_RESET() __HAL_RCC_I2C3_RELEASE_RESET()
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@ -213,57 +219,65 @@
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#define FIR_I2C_AF (GPIO_AF4_I2C1)
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#define FIR_I2C_CLK_ENABLE() __I2C1_CLK_ENABLE()
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#define FIR_I2C_CLK_DISABLE() __I2C1_CLK_DISABLE()
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#define FIR_I2C_PORT (GPIOB)
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#define FIR_I2C_SCL_PIN (GPIO_PIN_6)
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#define FIR_I2C_SDA_PIN (GPIO_PIN_7)
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#define FIR_I2C_SCL_PORT (GPIOB)
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#define FIR_I2C_SCL_PIN (GPIO_PIN_8)
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#define FIR_I2C_SDA_PORT (GPIOB)
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#define FIR_I2C_SDA_PIN (GPIO_PIN_9)
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#define FIR_I2C_SPEED (CAMBUS_SPEED_FULL)
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#define FIR_I2C_FORCE_RESET() __HAL_RCC_I2C1_FORCE_RESET()
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#define FIR_I2C_RELEASE_RESET() __HAL_RCC_I2C1_RELEASE_RESET()
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/* DCMI */
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#define DCMI_TIM (TIM1)
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#define DCMI_TIM_PIN (GPIO_PIN_1)
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#define DCMI_TIM_PORT (GPIOK)
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#define DCMI_TIM_AF (GPIO_AF1_TIM1)
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#define DCMI_TIM_CHANNEL (TIM_CHANNEL_1)
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#define DCMI_TIM_CLK_ENABLE() __TIM1_CLK_ENABLE()
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#define DCMI_TIM_CLK_DISABLE() __TIM1_CLK_DISABLE()
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#define DCMI_TIM_PCLK_FREQ() HAL_RCC_GetPCLK2Freq()
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#define DCMI_TIM (TIM3)
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#define DCMI_TIM_PORT (GPIOA)
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#define DCMI_TIM_PIN (GPIO_PIN_7)
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#define DCMI_TIM_AF (GPIO_AF2_TIM3)
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#define DCMI_TIM_CHANNEL (TIM_CHANNEL_2)
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#define DCMI_TIM_CLK_ENABLE() __TIM3_CLK_ENABLE()
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#define DCMI_TIM_CLK_DISABLE() __TIM3_CLK_DISABLE()
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#define DCMI_TIM_PCLK_FREQ() HAL_RCC_GetPCLK1Freq()
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//#define DCMI_RESET_PIN (GPIO_PIN_10)
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//#define DCMI_RESET_PORT (GPIOA)
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//#define DCMI_RESET_PIN (GPIO_PIN_10)
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#define DCMI_PWDN_PIN (GPIO_PIN_3)
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#define DCMI_PWDN_PORT (GPIOG)
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//#define DCMI_PWDN_PORT (GPIOG)
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//#define DCMI_PWDN_PIN (GPIO_PIN_3)
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//#define DCMI_FSYNC_PIN (GPIO_PIN_4)
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//#define DCMI_FSYNC_PORT (GPIOB)
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//#define DCMI_FSYNC_PIN (GPIO_PIN_4)
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#define DCMI_D0_PIN (GPIO_PIN_9)
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#define DCMI_D1_PIN (GPIO_PIN_10)
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#define DCMI_D2_PIN (GPIO_PIN_11)
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#define DCMI_D3_PIN (GPIO_PIN_12)
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#define DCMI_D4_PIN (GPIO_PIN_14)
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#define DCMI_D5_PIN (GPIO_PIN_4)
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#define DCMI_D6_PIN (GPIO_PIN_6)
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#define DCMI_D7_PIN (GPIO_PIN_7)
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#define DCMI_D0_PORT (GPIOC)
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#define DCMI_D0_PIN (GPIO_PIN_6)
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#define DCMI_D0_PORT (GPIOH)
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#define DCMI_D1_PORT (GPIOH)
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#define DCMI_D2_PORT (GPIOH)
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#define DCMI_D3_PORT (GPIOH)
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#define DCMI_D4_PORT (GPIOH)
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#define DCMI_D5_PORT (GPIOI)
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#define DCMI_D6_PORT (GPIOI)
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#define DCMI_D7_PORT (GPIOI)
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#define DCMI_D1_PORT (GPIOC)
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#define DCMI_D1_PIN (GPIO_PIN_7)
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#define DCMI_HSYNC_PIN (GPIO_PIN_4)
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#define DCMI_VSYNC_PIN (GPIO_PIN_5)
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#define DCMI_PXCLK_PIN (GPIO_PIN_6)
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#define DCMI_D2_PORT (GPIOE)
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#define DCMI_D2_PIN (GPIO_PIN_0)
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#define DCMI_D3_PORT (GPIOE)
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#define DCMI_D3_PIN (GPIO_PIN_1)
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#define DCMI_D4_PORT (GPIOE)
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#define DCMI_D4_PIN (GPIO_PIN_4)
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#define DCMI_D5_PORT (GPIOD)
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#define DCMI_D5_PIN (GPIO_PIN_3)
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#define DCMI_D6_PORT (GPIOE)
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#define DCMI_D6_PIN (GPIO_PIN_5)
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#define DCMI_D7_PORT (GPIOE)
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#define DCMI_D7_PIN (GPIO_PIN_6)
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#define DCMI_HSYNC_PORT (GPIOA)
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#define DCMI_VSYNC_PORT (GPIOI)
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#define DCMI_HSYNC_PIN (GPIO_PIN_4)
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#define DCMI_VSYNC_PORT (GPIOG)
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#define DCMI_VSYNC_PIN (GPIO_PIN_9)
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#define DCMI_PXCLK_PORT (GPIOA)
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#define DCMI_PXCLK_PIN (GPIO_PIN_6)
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#if defined(DCMI_RESET_PIN)
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#define DCMI_RESET_LOW() HAL_GPIO_WritePin(DCMI_RESET_PORT, DCMI_RESET_PIN, GPIO_PIN_RESET)
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@ -282,7 +296,7 @@
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#endif
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#define DCMI_VSYNC_IRQN EXTI9_5_IRQn
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#define DCMI_VSYNC_IRQ_LINE (7)
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#define DCMI_VSYNC_IRQ_LINE (9)
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#define SOFT_I2C_PORT GPIOC
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#define SOFT_I2C_SIOC_PIN GPIO_PIN_10
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@ -299,26 +313,28 @@
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#define SOFT_I2C_SPIN_DELAY 64
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#define IMU_SPI (SPI2)
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#define IMU_SPI_AF (GPIO_AF5_SPI2)
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// SPI1/2/3 clock source is PLL2 (160MHz/16 == 10MHz).
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#define IMU_SPI (SPI5)
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#define IMU_SPI_AF (GPIO_AF5_SPI5)
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// SPI4/5 clock source is PLL3 (160MHz/16 == 10MHz).
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#define IMU_SPI_PRESCALER (SPI_BAUDRATEPRESCALER_16)
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#define IMU_SPI_RESET() __HAL_RCC_SPI2_FORCE_RESET()
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#define IMU_SPI_RELEASE() __HAL_RCC_SPI2_RELEASE_RESET()
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#define IMU_SPI_RESET() __HAL_RCC_SPI5_FORCE_RESET()
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#define IMU_SPI_RELEASE() __HAL_RCC_SPI5_RELEASE_RESET()
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#define IMU_SPI_CLK_ENABLE() __HAL_RCC_SPI2_CLK_ENABLE()
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#define IMU_SPI_CLK_DISABLE() __HAL_RCC_SPI2_CLK_DISABLE()
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#define IMU_SPI_CLK_ENABLE() __HAL_RCC_SPI5_CLK_ENABLE()
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#define IMU_SPI_CLK_DISABLE() __HAL_RCC_SPI5_CLK_DISABLE()
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#define IMU_SPI_SCLK_PIN (GPIO_PIN_1)
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#define IMU_SPI_MISO_PIN (GPIO_PIN_2)
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#define IMU_SPI_MOSI_PIN (GPIO_PIN_3)
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#define IMU_SPI_SSEL_PIN (GPIO_PIN_0)
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#define IMU_SPI_SSEL_PORT (GPIOF)
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#define IMU_SPI_SSEL_PIN (GPIO_PIN_6)
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#define IMU_SPI_SCLK_PORT (GPIOI)
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#define IMU_SPI_MISO_PORT (GPIOC)
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#define IMU_SPI_MOSI_PORT (GPIOC)
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#define IMU_SPI_SSEL_PORT (GPIOI)
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#define IMU_SPI_SCLK_PORT (GPIOF)
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#define IMU_SPI_SCLK_PIN (GPIO_PIN_7)
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#define IMU_SPI_MISO_PORT (GPIOF)
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#define IMU_SPI_MISO_PIN (GPIO_PIN_8)
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#define IMU_SPI_MOSI_PORT (GPIOF)
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#define IMU_SPI_MOSI_PIN (GPIO_PIN_11)
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// SPI LCD Interface
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#define OMV_SPI_LCD_CONTROLLER (&spi_obj[3])
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