Add JPEG regs

* Some fixes to old registers
This commit is contained in:
iabdalkader 2014-06-23 18:53:57 +02:00
parent 18e62155b0
commit 561c97cb41
2 changed files with 322 additions and 229 deletions

View File

@ -7,259 +7,337 @@
#include "systick.h"
#include "ov2640_regs.h"
#define DSP_FRAME_W (800)
#define DSP_FRAME_H (600)
#define SVGA_HSIZE (800)
#define SVGA_VSIZE (600)
#define UXGA_HSIZE (1600)
#define UXGA_VSIZE (1200)
static const uint8_t default_regs[][2] = {
{ BANK_SEL, BANK_SEL_DSP},
{ 0x2c, 0xff },
{ 0x2e, 0xdf },
{ BANK_SEL, BANK_SEL_DSP },
{ 0x2c, 0xff },
{ 0x2e, 0xdf },
{ BANK_SEL, BANK_SEL_SENSOR },
{ 0x3c, 0x32 },
{ CLKRC, 0x00 }, /* Set PCLK divider */
{ COM2, COM2_OUT_DRIVE_3x }, /* Output drive x2 */
{ REG04, REG04_SET(0x00)}, /* Mirror/VFLIP/AEC[1:0] */
{ COM8, COM8_SET(COM8_BNDF_EN | COM8_AGC_EN | COM8_AEC_EN) },
{ COM9, COM9_AGC_SET(COM9_AGC_GAIN_8x)},
/* DSP input image resoultion and window size control */
{ COM7, COM7_RES_SVGA},
{ COM1, 0x0A }, /* UXGA=0x0F, SVGA=0x0A, CIF=0x06 */
{ REG32, 0x09 }, /* UXGA=0x36, SVGA/CIF=0x09 */
{ HSTART, 0x11 }, /* UXGA=0x11, SVGA/CIS=0x11 */
{ HSTOP, 0x43 }, /* UXGA=0x75, SVGA/CIF=0x43 */
{ VSTART, 0x00 }, /* UXGA=0x01, SVGA/CIF=0x00 */
{ VSTOP, 0x4b }, /* UXGA=0x97, SVGA/CIS=0x4b */
{ 0x3d, 0x38 }, /* UXGA=0x34, SVGA/CIF=0x38 */
{ 0x2c, 0x0c },
{ 0x33, 0x78 },
{ 0x3a, 0x33 },
{ 0x3b, 0xfb },
{ 0x3e, 0x00 },
{ 0x43, 0x11 },
{ 0x16, 0x10 },
{ 0x39, 0x02 },
#if 1
{ 0x35, 0xda },
{ 0x22, 0x1a },
{ 0x37, 0xc3 },
{ 0x34, 0xc0 },
{ 0x06, 0x88 },
{ 0x0d, 0x87 },
{ 0x0e, 0x41 },
{ 0x42, 0x10 },
#else
//UXGA
{ 0x35, 0x88 },
{ 0x22, 0x0a },
{ 0x37, 0x40 },
{ 0x34, 0xa0 },
{ 0x06, 0x02 },
{ 0x0d, 0xb7 },
{ 0x0e, 0x01 },
{ 0x42, 0x20 },
#endif
{ 0x23, 0x00 },
{ 0x07, 0xc0 },
{ 0x4c, 0x00 },
{ COM19, 0x00 }, /* Zoom control 2 MSBs */
{ ZOOMS, 0x00 }, /* Zoom control 8 MSBs */
{ 0x5B, 0x00 },
{ 0x4a, 0x81 },
{ 0x21, 0x99 },
/* AGC/AEC operating region */
{ AEW, 0x40 },
{ AEB, 0x38 },
{ 0x3c, 0x32 },
{ CLKRC, 0x80 }, /* Set PCLK divider */
{ COM2, COM2_OUT_DRIVE_3x }, /* Output drive x2 */
{ REG04, REG04_SET(REG04_HREF_EN)}, /* Mirror/VFLIP/AEC[1:0] */
{ COM8, COM8_SET(COM8_BNDF_EN | COM8_AGC_EN | COM8_AEC_EN) },
{ COM9, COM9_AGC_SET(COM9_AGC_GAIN_8x)},
{ 0x2c, 0x0c },
{ 0x33, 0x78 },
{ 0x3a, 0x33 },
{ 0x3b, 0xfb },
{ 0x3e, 0x00 },
{ 0x43, 0x11 },
{ 0x16, 0x10 },
{ 0x39, 0x02 },
{ 0x35, 0x88 },
{ 0x22, 0x0a },
{ 0x37, 0x40 },
{ 0x23, 0x00 },
{ ARCOM2, 0xa0 },
{ 0x06, 0x02 },
{ 0x06, 0x88 },
{ 0x07, 0xc0 },
{ 0x0d, 0xb7 },
{ 0x0e, 0x01 },
{ 0x4c, 0x00 },
{ 0x4a, 0x81 },
{ 0x21, 0x99 },
{ AEW, 0x40 },
{ AEB, 0x38 },
/* AGC/AEC fast mode operating region */
{ VV, VV_AGC_TH_SET(0x08, 0x02) },
{ 0x5c, 0x00 },
{ 0x63, 0x00 },
{ FLL, 0x00 },
{ FLH, 0x00 },
{ VV, VV_AGC_TH_SET(0x08, 0x02) },
{ COM19, 0x00 }, /* Zoom control 2 MSBs */
{ ZOOMS, 0x00 }, /* Zoom control 8 MSBs */
{ 0x5c, 0x00 },
{ 0x63, 0x00 },
{ FLL, 0x00 },
{ FLH, 0x00 },
/* Set banding filter */
{ COM3, COM3_BAND_SET(COM3_BAND_AUTO) },
{ REG5D, 0x55 },
{ REG5E, 0x7d },
{ REG5F, 0x7d },
{ REG60, 0x55 },
{ COM3, COM3_BAND_SET(COM3_BAND_AUTO) },
{ REG5D, 0x55 },
{ REG5E, 0x7d },
{ REG5F, 0x7d },
{ REG60, 0x55 },
{ HISTO_LOW, 0x70 },
{ HISTO_HIGH, 0x80 },
{ 0x7c, 0x05 },
{ 0x20, 0x80 },
{ 0x28, 0x30 },
{ 0x6c, 0x00 },
{ 0x6d, 0x80 },
{ 0x6e, 0x00 },
{ 0x70, 0x02 },
{ 0x71, 0x94 },
{ 0x73, 0xc1 },
{ 0x5a, 0x57 },
{ BD50, 0xbb },
{ BD60, 0x9c },
{ 0x7c, 0x05 },
{ 0x20, 0x80 },
{ 0x28, 0x30 },
{ 0x6c, 0x00 },
{ 0x6d, 0x80 },
{ 0x6e, 0x00 },
{ 0x70, 0x02 },
{ 0x71, 0x94 },
{ 0x73, 0xc1 },
{ 0x3d, 0x34 },
//{ COM7, COM7_RES_UXGA | COM7_ZOOM_EN },
{ 0x5a, 0x57 },
{ BD50, 0xbb },
{ BD60, 0x9c },
{ BANK_SEL, BANK_SEL_DSP },
{ 0xe5, 0x7f },
{ MC_BIST, MC_BIST_RESET | MC_BIST_BOOT_ROM_SEL },
{ 0x41, 0x24 },
{ RESET, RESET_JPEG | RESET_DVP | RESET_CIF },
{ 0x76, 0xff },
{ 0x33, 0xa0 },
{ 0x43, 0x18 },
{ 0x4c, 0x00 },
{ CTRL3, CTRL3_BPC_EN | CTRL3_WPC_EN | 0x10 },
{ 0x88, 0x3f },
{ 0xd7, 0x03 },
{ 0xd9, 0x10 },
{ R_DVP_SP, R_DVP_SP_AUTO_MODE | 0x00},
{ 0xc8, 0x08 },
{ 0xc9, 0x80 },
{ BPADDR, 0x00 },
{ BPDATA, 0x00 },
{ BPADDR, 0x03 },
{ BPDATA, 0x48 },
{ BPDATA, 0x48 },
{ BPADDR, 0x08 },
{ BPDATA, 0x20 },
{ BPDATA, 0x10 },
{ BPDATA, 0x0e },
{ 0x90, 0x00 },
{ 0x91, 0x0e },
{ 0x91, 0x1a },
{ 0x91, 0x31 },
{ 0x91, 0x5a },
{ 0x91, 0x69 },
{ 0x91, 0x75 },
{ 0x91, 0x7e },
{ 0x91, 0x88 },
{ 0x91, 0x8f },
{ 0x91, 0x96 },
{ 0x91, 0xa3 },
{ 0x91, 0xaf },
{ 0x91, 0xc4 },
{ 0x91, 0xd7 },
{ 0x91, 0xe8 },
{ 0x91, 0x20 },
{ 0x92, 0x00 },
{ 0x93, 0x06 },
{ 0x93, 0xe3 },
{ 0x93, 0x03 },
{ 0x93, 0x03 },
{ 0x93, 0x00 },
{ 0x93, 0x02 },
{ 0x93, 0x00 },
{ 0x93, 0x00 },
{ 0x93, 0x00 },
{ 0x93, 0x00 },
{ 0x93, 0x00 },
{ 0x93, 0x00 },
{ 0x93, 0x00 },
{ 0x96, 0x00 },
{ 0x97, 0x08 },
{ 0x97, 0x19 },
{ 0x97, 0x02 },
{ 0x97, 0x0c },
{ 0x97, 0x24 },
{ 0x97, 0x30 },
{ 0x97, 0x28 },
{ 0x97, 0x26 },
{ 0x97, 0x02 },
{ 0x97, 0x98 },
{ 0x97, 0x80 },
{ 0x97, 0x00 },
{ 0x97, 0x00 },
{ 0xa4, 0x00 },
{ 0xa8, 0x00 },
{ 0xc5, 0x11 },
{ 0xc6, 0x51 },
{ 0xbf, 0x80 },
{ 0xc7, 0x10 },
{ 0xb6, 0x66 },
{ 0xb8, 0xA5 },
{ 0xb7, 0x64 },
{ 0xb9, 0x7C },
{ 0xb3, 0xaf },
{ 0xb4, 0x97 },
{ 0xb5, 0xFF },
{ 0xb0, 0xC5 },
{ 0xb1, 0x94 },
{ 0xb2, 0x0f },
{ 0xc4, 0x5c },
{ 0xa6, 0x00 },
{ 0xa7, 0x20 },
{ 0xa7, 0xd8 },
{ 0xa7, 0x1b },
{ 0xa7, 0x31 },
{ 0xa7, 0x00 },
{ 0xa7, 0x18 },
{ 0xa7, 0x20 },
{ 0xa7, 0xd8 },
{ 0xa7, 0x19 },
{ 0xa7, 0x31 },
{ 0xa7, 0x00 },
{ 0xa7, 0x18 },
{ 0xa7, 0x20 },
{ 0xa7, 0xd8 },
{ 0xa7, 0x19 },
{ 0xa7, 0x31 },
{ 0xa7, 0x00 },
{ 0xa7, 0x18 },
{ 0x7f, 0x00 },
{ 0xe5, 0x1f },
{ 0xe1, 0x77 },
{ 0xdd, 0x7f },
/* Enable AEC/AEC_SEL/YUV/YUV422/RGB */
{ CTRL0, CTRL0_YUV422 | CTRL0_YUV_EN | CTRL0_RGB_EN },
{ 0xe5, 0x7f },
{ MC_BIST, MC_BIST_RESET | MC_BIST_BOOT_ROM_SEL },
{ 0x41, 0x24 },
{ RESET, RESET_JPEG | RESET_DVP },
{ 0x76, 0xff },
{ 0x33, 0xa0 },
{ 0x42, 0x20 },
{ 0x43, 0x18 },
{ 0x4c, 0x00 },
{ CTRL3, CTRL3_BPC_EN | CTRL3_WPC_EN | 0x10 },
{ 0x88, 0x3f },
{ 0xd7, 0x03 },
{ 0xd9, 0x10 },
{ R_DVP_SP , R_DVP_SP_AUTO_MODE | 0x2 },
{ 0xc8, 0x08 },
{ 0xc9, 0x80 },
{ BPADDR, 0x00 },
{ BPDATA, 0x00 },
{ BPADDR, 0x03 },
{ BPDATA, 0x48 },
{ BPDATA, 0x48 },
{ BPADDR, 0x08 },
{ BPDATA, 0x20 },
{ BPDATA, 0x10 },
{ BPDATA, 0x0e },
{ 0x90, 0x00 },
{ 0x91, 0x0e },
{ 0x91, 0x1a },
{ 0x91, 0x31 },
{ 0x91, 0x5a },
{ 0x91, 0x69 },
{ 0x91, 0x75 },
{ 0x91, 0x7e },
{ 0x91, 0x88 },
{ 0x91, 0x8f },
{ 0x91, 0x96 },
{ 0x91, 0xa3 },
{ 0x91, 0xaf },
{ 0x91, 0xc4 },
{ 0x91, 0xd7 },
{ 0x91, 0xe8 },
{ 0x91, 0x20 },
{ 0x92, 0x00 },
{ 0x93, 0x06 },
{ 0x93, 0xe3 },
{ 0x93, 0x03 },
{ 0x93, 0x03 },
{ 0x93, 0x00 },
{ 0x93, 0x02 },
{ 0x93, 0x00 },
{ 0x93, 0x00 },
{ 0x93, 0x00 },
{ 0x93, 0x00 },
{ 0x93, 0x00 },
{ 0x93, 0x00 },
{ 0x93, 0x00 },
{ 0x96, 0x00 },
{ 0x97, 0x08 },
{ 0x97, 0x19 },
{ 0x97, 0x02 },
{ 0x97, 0x0c },
{ 0x97, 0x24 },
{ 0x97, 0x30 },
{ 0x97, 0x28 },
{ 0x97, 0x26 },
{ 0x97, 0x02 },
{ 0x97, 0x98 },
{ 0x97, 0x80 },
{ 0x97, 0x00 },
{ 0x97, 0x00 },
{ 0xa4, 0x00 },
{ 0xa8, 0x00 },
{ 0xc5, 0x11 },
{ 0xc6, 0x51 },
{ 0xbf, 0x80 },
{ 0xc7, 0x10 },
{ 0xb6, 0x66 },
{ 0xb8, 0xA5 },
{ 0xb7, 0x64 },
{ 0xb9, 0x7C },
{ 0xb3, 0xaf },
{ 0xb4, 0x97 },
{ 0xb5, 0xFF },
{ 0xb0, 0xC5 },
{ 0xb1, 0x94 },
{ 0xb2, 0x0f },
{ 0xc4, 0x5c },
{ 0xa6, 0x00 },
{ 0xa7, 0x20 },
{ 0xa7, 0xd8 },
{ 0xa7, 0x1b },
{ 0xa7, 0x31 },
{ 0xa7, 0x00 },
{ 0xa7, 0x18 },
{ 0xa7, 0x20 },
{ 0xa7, 0xd8 },
{ 0xa7, 0x19 },
{ 0xa7, 0x31 },
{ 0xa7, 0x00 },
{ 0xa7, 0x18 },
{ 0xa7, 0x20 },
{ 0xa7, 0xd8 },
{ 0xa7, 0x19 },
{ 0xa7, 0x31 },
{ 0xa7, 0x00 },
{ 0xa7, 0x18 },
{ 0x7f, 0x00 },
{ 0xe5, 0x1f },
{ 0xe1, 0x77 },
{ 0xdd, 0x7f },
{ CTRL0, CTRL0_YUV422 | CTRL0_YUV_EN | CTRL0_RGB_EN },
{ 0x00, 0x00 }
};
/* Set DSP input image size and offset.
The sensor output image can be scaled with OUTW/OUTH */
{ BANK_SEL, BANK_SEL_DSP },
{ RESET, RESET_DVP },
{ HSIZE8, (DSP_FRAME_W>>3)}, /* Image Horizontal Size HSIZE[10:3] */
{ VSIZE8, (DSP_FRAME_H>>3)}, /* Image Vertiacl Size VSIZE[10:3] */
static const uint8_t cif_regs[][2] = {
};
/* {HSIZE[11], HSIZE[2:0], VSIZE[2:0]} */
{ SIZEL, ((DSP_FRAME_W&0x7)<<3) | (DSP_FRAME_H&0x7)},
static const uint8_t svga_regs[][2] = {
{ BANK_SEL, BANK_SEL_SENSOR },
/* DSP input image resoultion and window size control */
{ COM7, COM7_RES_SVGA},
{ COM1, 0x0A }, /* UXGA=0x0F, SVGA=0x0A, CIF=0x06 */
{ REG32, 0x09 }, /* UXGA=0x36, SVGA/CIF=0x09 */
{ XOFFL, 0x00 }, /* OFFSET_X[7:0] */
{ YOFFL, 0x00 }, /* OFFSET_Y[7:0] */
{ HSIZE, ((DSP_FRAME_W>>2)&0xFF) }, /* H_SIZE[7:0] real/4 */
{ VSIZE, ((DSP_FRAME_H>>2)&0xFF) }, /* V_SIZE[7:0] real/4 */
{ HSTART, 0x11 }, /* UXGA=0x11, SVGA/CIS=0x11 */
{ HSTOP, 0x43 }, /* UXGA=0x75, SVGA/CIF=0x43 */
/* V_SIZE[8]/OFFSET_Y[10:8]/H_SIZE[8]/OFFSET_X[10:8] */
{ VHYX, ((DSP_FRAME_H>>3)&0x80) | ((DSP_FRAME_W>>7)&0x08) },
{ TEST, 0x00 }, /* H_SIZE[9] */
{ VSTART, 0x00 }, /* UXGA=0x01, SVGA/CIF=0x00 */
{ VSTOP, 0x4b }, /* UXGA=0x97, SVGA/CIS=0x4b */
{ 0x3d, 0x38 }, /* UXGA=0x34, SVGA/CIF=0x38 */
{ CTRL2, CTRL2_DCW_EN | CTRL2_SDE_EN |
CTRL2_UV_AVG_EN | CTRL2_CMX_EN | CTRL2_UV_ADJ_EN },
/* UXGA H_DIVIDER/V_DIVIDER */
/* UXGA=0x1B SVGA=0x09 QCIF=0x00 */
{ CTRLI, CTRLI_LP_DP | 0x09 },
{ 0x35, 0xda },
{ 0x22, 0x1a },
{ 0x37, 0xc3 },
{ 0x34, 0xc0 },
{ 0x06, 0x88 },
{ 0x0d, 0x87 },
{ 0x0e, 0x41 },
{ 0x42, 0x03 },
{ R_BYPASS, R_BYPASS_USE_DSP },
{0x00, 0x00}
/* Set DSP input image size and offset.
The sensor output image can be scaled with OUTW/OUTH */
{ BANK_SEL, BANK_SEL_DSP },
{ R_BYPASS, R_BYPASS_DSP_BYPAS },
{ RESET, RESET_DVP },
{ HSIZE8, (SVGA_HSIZE>>3)}, /* Image Horizontal Size HSIZE[10:3] */
{ VSIZE8, (SVGA_VSIZE>>3)}, /* Image Vertiacl Size VSIZE[10:3] */
/* {HSIZE[11], HSIZE[2:0], VSIZE[2:0]} */
{ SIZEL, ((SVGA_HSIZE>>6)&0x40) | ((SVGA_HSIZE&0x7)<<3) | (SVGA_VSIZE&0x7)},
{ XOFFL, 0x00 }, /* OFFSET_X[7:0] */
{ YOFFL, 0x00 }, /* OFFSET_Y[7:0] */
{ HSIZE, ((SVGA_HSIZE>>2)&0xFF) }, /* H_SIZE[7:0]= HSIZE/4 */
{ VSIZE, ((SVGA_VSIZE>>2)&0xFF) }, /* V_SIZE[7:0]= VSIZE/4 */
/* V_SIZE[8]/OFFSET_Y[10:8]/H_SIZE[8]/OFFSET_X[10:8] */
{ VHYX, ((SVGA_VSIZE>>3)&0x80) | ((SVGA_HSIZE>>7)&0x08) },
{ TEST, (SVGA_HSIZE>>4)&0x80}, /* H_SIZE[9] */
{ CTRL2, CTRL2_DCW_EN | CTRL2_SDE_EN |
CTRL2_UV_AVG_EN | CTRL2_CMX_EN | CTRL2_UV_ADJ_EN },
/* H_DIVIDER/V_DIVIDER */
{ CTRLI, CTRLI_LP_DP | 0x00},
/* DVP prescalar */
{ R_DVP_SP, R_DVP_SP_AUTO_MODE},
{ R_BYPASS, R_BYPASS_DSP_EN },
{ RESET, 0x00 },
{0, 0},
};
static const uint8_t uxga_regs[][2] = {
{ BANK_SEL, BANK_SEL_SENSOR },
/* DSP input image resoultion and window size control */
{ COM7, COM7_RES_UXGA},
{ COM1, 0x0F }, /* UXGA=0x0F, SVGA=0x0A, CIF=0x06 */
{ REG32, 0x36 }, /* UXGA=0x36, SVGA/CIF=0x09 */
{ HSTART, 0x11 }, /* UXGA=0x11, SVGA/CIS=0x11 */
{ HSTOP, 0x75 }, /* UXGA=0x75, SVGA/CIF=0x43 */
{ VSTART, 0x01 }, /* UXGA=0x01, SVGA/CIF=0x00 */
{ VSTOP, 0x97 }, /* UXGA=0x97, SVGA/CIS=0x4b */
{ 0x3d, 0x34 }, /* UXGA=0x34, SVGA/CIF=0x38 */
{ 0x35, 0x88 },
{ 0x22, 0x0a },
{ 0x37, 0x40 },
{ 0x34, 0xa0 },
{ 0x06, 0x02 },
{ 0x0d, 0xb7 },
{ 0x0e, 0x01 },
{ 0x42, 0x83 },
/* Set DSP input image size and offset.
The sensor output image can be scaled with OUTW/OUTH */
{ BANK_SEL, BANK_SEL_DSP },
{ R_BYPASS, R_BYPASS_DSP_BYPAS },
{ RESET, RESET_DVP },
{ HSIZE8, (UXGA_HSIZE>>3)}, /* Image Horizontal Size HSIZE[10:3] */
{ VSIZE8, (UXGA_VSIZE>>3)}, /* Image Vertiacl Size VSIZE[10:3] */
/* {HSIZE[11], HSIZE[2:0], VSIZE[2:0]} */
{ SIZEL, ((SVGA_HSIZE>>6)&0x40) | ((UXGA_HSIZE&0x7)<<3) | (UXGA_VSIZE&0x7)},
{ XOFFL, 0x00 }, /* OFFSET_X[7:0] */
{ YOFFL, 0x00 }, /* OFFSET_Y[7:0] */
{ HSIZE, ((UXGA_HSIZE>>2)&0xFF) }, /* H_SIZE[7:0] real/4 */
{ VSIZE, ((UXGA_VSIZE>>2)&0xFF) }, /* V_SIZE[7:0] real/4 */
/* V_SIZE[8]/OFFSET_Y[10:8]/H_SIZE[8]/OFFSET_X[10:8] */
{ VHYX, ((UXGA_VSIZE>>3)&0x80) | ((UXGA_HSIZE>>7)&0x08) },
{ TEST, (UXGA_HSIZE>>4)&0x80}, /* H_SIZE[9] */
{ CTRL2, CTRL2_DCW_EN | CTRL2_SDE_EN |
CTRL2_UV_AVG_EN | CTRL2_CMX_EN | CTRL2_UV_ADJ_EN },
/* H_DIVIDER/V_DIVIDER */
{ CTRLI, CTRLI_LP_DP | 0x00},
/* DVP prescalar */
{ R_DVP_SP, R_DVP_SP_AUTO_MODE | 0x04},
{ R_BYPASS, R_BYPASS_DSP_EN },
{ RESET, 0x00 },
{0, 0},
};
static const uint8_t yuv422_regs[][2] = {
{ BANK_SEL, BANK_SEL_DSP },
{ RESET, RESET_DVP},
{ IMAGE_MODE, IMAGE_MODE_YUV422 },
{ 0xD7, 0x01 },
{ 0x33, 0xa0 },
{ 0xe1, 0x67 },
{ 0xE1, 0x67 },
{ RESET, 0x00 },
{0, 0},
};
static const uint8_t rgb565_regs[][2] = {
{ BANK_SEL, BANK_SEL_DSP },
{ RESET, RESET_DVP},
{ IMAGE_MODE, IMAGE_MODE_RGB565 },
{ 0xd7, 0x03 },
{ 0xD7, 0x03 },
{ 0xE1, 0x77 },
{ RESET, 0x00 },
{0, 0},
};
static const uint8_t jpeg_regs[][2] = {
{ BANK_SEL, BANK_SEL_DSP },
{ RESET, RESET_DVP},
{ IMAGE_MODE, IMAGE_MODE_JPEG_EN|IMAGE_MODE_RGB565 },
{ 0xD7, 0x03 },
{ 0xE1, 0x77 },
{ QS, 0x05 },
{ RESET, 0x00 },
{0, 0},
};
@ -314,6 +392,14 @@ static int reset()
i++;
}
i = 0;
regs = svga_regs;
/* Write DSP input regsiters */
while (regs[i][0]) {
SCCB_Write(regs[i][0], regs[i][1]);
i++;
}
return 0;
}
@ -332,7 +418,7 @@ static int set_pixformat(enum sensor_pixformat pixformat)
regs = yuv422_regs;
break;
case PIXFORMAT_JPEG:
return -1;
regs = jpeg_regs;
break;
default:
return -1;
@ -349,9 +435,14 @@ static int set_pixformat(enum sensor_pixformat pixformat)
static int set_framesize(enum sensor_framesize framesize)
{
int ret=0;
uint8_t clkrc = 0x80;
uint16_t w=res_width[framesize];
uint16_t h=res_height[framesize];
if (framesize > FRAMESIZE_QVGA) {
clkrc =0x81;
}
/* Disable DSP */
ret |= SCCB_Write(BANK_SEL, BANK_SEL_DSP);
ret |= SCCB_Write(R_BYPASS, R_BYPASS_DSP_BYPAS);
@ -361,9 +452,13 @@ static int set_framesize(enum sensor_framesize framesize)
ret |= SCCB_Write(ZMOH, (h>>2)&0xFF); /* OUTH[7:0] (real/4) */
ret |= SCCB_Write(ZMHH, ((h>>8)&0x04)|((w>>10)&0x03)); /* OUTH[8]/OUTW[9:8] */
/* Set CLKRC */
ret |= SCCB_Write(BANK_SEL, BANK_SEL_SENSOR);
ret |= SCCB_Write(CLKRC, clkrc);
/* Enable DSP */
ret |= SCCB_Write(BANK_SEL, BANK_SEL_DSP);
ret |= SCCB_Write(R_BYPASS, R_BYPASS_USE_DSP);
ret |= SCCB_Write(R_BYPASS, R_BYPASS_DSP_EN);
return ret;
}

View File

@ -2,7 +2,7 @@
#define __REG_REGS_H__
/* OV2640 Registers definition */
/* DSP register bank FF=0x00*/
#define Q 0x44
#define QS 0x44
#define HSIZE 0x51
#define VSIZE 0x52
#define XOFFL 0x53
@ -58,7 +58,6 @@
#define R_BYPASS 0x05
#define R_BYPASS_DSP_EN 0x00
#define R_BYPASS_DSP_BYPAS 0x01
#define R_BYPASS_USE_DSP 0x00
#define IMAGE_MODE 0xDA
#define IMAGE_MODE_Y8_DVP_EN 0x40
@ -101,7 +100,6 @@
#define AEC 0x10
#define CLKRC 0x11
#define COM10 0x15
#define ARCOM2 0x34
#define HSTART 0x17
#define HSTOP 0x18
#define VSTART 0x19