mirror of
https://github.com/openmv/openmv.git
synced 2025-11-04 14:49:50 +08:00
Add support for OpenMV2
This commit is contained in:
parent
26425fa66e
commit
57cccca3f3
@ -25,7 +25,7 @@ MICROPY_DIR=micropython
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OMV_DIR=omv
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# Target
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TARGET ?= OPENMV1
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TARGET ?= OPENMV2
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# Debugging/Optimization
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ifeq ($(DEBUG), 1)
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@ -48,7 +48,7 @@ CFLAGS += -DARM_MATH_CM4 -D__FPU_PRESENT=1 -D__FPU_USED=1 -DUSE_USB_FS -DUSE_DEV
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ifeq ($(TARGET), OPENMV1)
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CFLAGS += -DSTM32F407xx
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else
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CFLAGS += -DSTM32F429xx
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CFLAGS += -DSTM32F427xx
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endif
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CFLAGS += -I. -Iinclude
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@ -111,7 +111,6 @@ OBJ += $(addprefix $(BUILD)/$(OMV_DIR)/, \
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)
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else
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OBJ += $(addprefix $(BUILD)/$(OMV_DIR)/, \
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sdram.o \
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sdcard_sdio.o \
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)
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endif
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@ -154,7 +153,7 @@ OBJ += $(addprefix $(BUILD)/$(CMSIS_DIR)/src/st/,\
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else
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OBJ += $(addprefix $(BUILD)/$(CMSIS_DIR)/src/st/,\
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system_stm32f4xx.o \
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startup_stm32f429xx.o \
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startup_stm32f427xx.o \
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)
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endif
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@ -189,6 +188,7 @@ OBJ += $(addprefix $(BUILD)/$(MICROPY_DIR)/,\
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rtc.o \
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irq.o \
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adc.o \
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dac.o \
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uart.o \
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systick.o \
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i2c.o \
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@ -2,7 +2,7 @@
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ifeq ($(TARGET), OPENMV1)
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SRC_S = src/st/startup_stm32f407xx.s
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else
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SRC_S = src/st/startup_stm32f429xx.s
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SRC_S = src/st/startup_stm32f427xx.s
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endif
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SRC_C = src/st/system_stm32f4xx.c
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@ -76,8 +76,35 @@ defined in linker script */
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.section .text.Reset_Handler
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.weak Reset_Handler
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.type Reset_Handler, %function
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Reset_Handler:
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ldr sp, =_estack /* set stack pointer */
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Reset_Handler:
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ldr r0,=0x20002000 /* load magic number location */
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ldr r2,[r0, #0]
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str r0,[r0, #0] /* invalidate */
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ldr r1,=0xDEADBEEF /* if magic number found */
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cmp r2,r1
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bne EnableCCM /* run the bootloader, else... */
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Reboot_Loader:
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ldr r0, =0x40023844 /* RCC_APB2ENR */
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ldr r1, =0x00004000 /* enable SYSCFG clock */
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str r1, [r0, #0]
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ldr r0, =0x40013800 /* SYSCFG_MEMRMP */
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ldr r1, =0x00000001 /* remap ROM at zero */
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str r1, [r0, #0]
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ldr r0,=0x1FFF0000
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ldr sp,[r0, #0] /* 0x20002d40 */
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ldr r0,[r0, #4]
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bx r0
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EnableCCM:
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/* enable ccm clock */
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ldr r0,=0x40023830
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ldr r3,[r0]
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orr r3, r3, #1048576 /* 0x100000 */
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str r3,[r0]
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ldr sp, =_estack /* set stack pointer */
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/* Copy the data segment initializers from flash to SRAM */
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movs r1, #0
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@ -110,7 +137,7 @@ LoopFillZerobss:
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/* Call the clock system intitialization function.*/
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bl SystemInit
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/* Call static constructors */
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bl __libc_init_array
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/* bl __libc_init_array */
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/* Call the application's entry point.*/
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bl main
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bx lr
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@ -556,7 +556,7 @@ void SystemClock_Config(void)
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Error_Handler();
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}
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#ifdef STM32F429xx
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#if defined(STM32F427xx) || defined(STM32F429xx)
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if(HAL_PWREx_ActivateOverDrive() != HAL_OK) {
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/* Initialization Error */
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Error_Handler();
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@ -1 +1 @@
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Subproject commit a80252b42837ddda74333a7683a6ab79440b5199
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Subproject commit ce13e9a9b19259ec9c76201785ea5b0fc6daab0c
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@ -19,7 +19,6 @@ SRCS += $(addprefix , \
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)
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else
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SRCS += $(addprefix , \
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sdram.c \
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sdcard_sdio.c \
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)
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endif
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108
src/omv/pincfg.h
108
src/omv/pincfg.h
@ -140,35 +140,6 @@ typedef enum {
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#define SD_SELECT() HAL_GPIO_WritePin(SD_CS_PORT, SD_CS_PIN, GPIO_PIN_RESET)
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#define SD_DESELECT() HAL_GPIO_WritePin(SD_CS_PORT, SD_CS_PIN, GPIO_PIN_SET)
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/* Wlan */
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#define WLAN_SPI SPI3
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#define WLAN_SPI_AF (GPIO_AF6_SPI3)
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#define WLAN_IRQn (EXTI15_10_IRQn)
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#define WLAN_IRQHandler (EXTI15_10_IRQHandler)
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#define WLAN_EXTI_LINE (1<<11)
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#define WLAN_CS_PIN (GPIO_PIN_15)
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#define WLAN_EN_PIN (GPIO_PIN_10)
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#define WLAN_IRQ_PIN (GPIO_PIN_11)
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#define WLAN_SCLK_PIN (GPIO_PIN_10)
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#define WLAN_MISO_PIN (GPIO_PIN_11)
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#define WLAN_MOSI_PIN (GPIO_PIN_12)
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#define WLAN_CS_PORT (GPIOA)
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#define WLAN_EN_PORT (GPIOB)
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#define WLAN_IRQ_PORT (GPIOB)
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#define WLAN_SCLK_PORT (GPIOC)
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#define WLAN_MISO_PORT (GPIOC)
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#define WLAN_MOSI_PORT (GPIOC)
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#define WLAN_SPI_CLK_ENABLE() __SPI3_CLK_ENABLE()
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#define WLAN_SPI_CLK_DISABLE() __SPI3_CLK_DISABLE()
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#define WLAN_SELECT() HAL_GPIO_WritePin(WLAN_CS_PORT, WLAN_CS_PIN, GPIO_PIN_RESET)
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#define WLAN_DESELECT() HAL_GPIO_WritePin(WLAN_CS_PORT, WLAN_CS_PIN, GPIO_PIN_SET)
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#define __WLAN_DISABLE() HAL_GPIO_WritePin(WLAN_EN_PORT, WLAN_EN_PIN, GPIO_PIN_RESET)
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#else //OPENMV2
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/* GPIOs */
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@ -203,13 +174,13 @@ typedef enum {
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{ MP_OBJ_NEW_QSTR(MP_QSTR_PB4), MP_OBJ_NEW_SMALL_INT(GPIO_PD13)}
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/* SCCB/I2C */
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#define SCCB_I2C (I2C2)
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#define SCCB_AF (GPIO_AF4_I2C2)
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#define SCCB_CLK_ENABLE() __I2C2_CLK_ENABLE()
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#define SCCB_CLK_DISABLE() __I2C2_CLK_DISABLE()
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#define SCCB_I2C (I2C1)
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#define SCCB_AF (GPIO_AF4_I2C1)
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#define SCCB_CLK_ENABLE() __I2C1_CLK_ENABLE()
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#define SCCB_CLK_DISABLE() __I2C1_CLK_DISABLE()
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#define SCCB_PORT (GPIOB)
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#define SCCB_SCL_PIN (GPIO_PIN_10)
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#define SCCB_SDA_PIN (GPIO_PIN_11)
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#define SCCB_SCL_PIN (GPIO_PIN_8)
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#define SCCB_SDA_PIN (GPIO_PIN_9)
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/* SPI */
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#define USR_SPI (SPI4)
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@ -246,29 +217,35 @@ typedef enum {
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#define DCMI_TIM_CLK_ENABLE() __TIM1_CLK_ENABLE()
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#define DCMI_TIM_CLK_DISABLE() __TIM1_CLK_DISABLE()
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#define DCMI_RESET_PIN (GPIO_PIN_15)
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#define DCMI_RESET_PIN (GPIO_PIN_10)
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#define DCMI_RESET_PORT (GPIOA)
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#define DCMI_PWDN_PIN (GPIO_PIN_10)
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#define DCMI_PWDN_PORT (GPIOA)
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#define DCMI_PWDN_PIN (GPIO_PIN_5)
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#define DCMI_PWDN_PORT (GPIOB)
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#define DCMI_FREX_PIN (GPIO_PIN_9)
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#define DCMI_FREX_PORT (GPIOD)
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#define DCMI_EXPST_PIN (GPIO_PIN_8)
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#define DCMI_EXPST_PORT (GPIOD)
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#define DCMI_D0_PIN (GPIO_PIN_6)
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#define DCMI_D1_PIN (GPIO_PIN_7)
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#define DCMI_D2_PIN (GPIO_PIN_10)
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#define DCMI_D3_PIN (GPIO_PIN_11)
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#define DCMI_D2_PIN (GPIO_PIN_0)
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#define DCMI_D3_PIN (GPIO_PIN_1)
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#define DCMI_D4_PIN (GPIO_PIN_4)
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#define DCMI_D5_PIN (GPIO_PIN_3)
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#define DCMI_D6_PIN (GPIO_PIN_8)
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#define DCMI_D7_PIN (GPIO_PIN_9)
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#define DCMI_D5_PIN (GPIO_PIN_6)
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#define DCMI_D6_PIN (GPIO_PIN_5)
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#define DCMI_D7_PIN (GPIO_PIN_6)
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#define DCMI_D0_PORT (GPIOC)
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#define DCMI_D1_PORT (GPIOC)
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#define DCMI_D2_PORT (GPIOG)
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#define DCMI_D3_PORT (GPIOG)
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#define DCMI_D2_PORT (GPIOE)
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#define DCMI_D3_PORT (GPIOE)
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#define DCMI_D4_PORT (GPIOE)
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#define DCMI_D5_PORT (GPIOD)
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#define DCMI_D6_PORT (GPIOB)
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#define DCMI_D7_PORT (GPIOB)
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#define DCMI_D5_PORT (GPIOB)
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#define DCMI_D6_PORT (GPIOE)
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#define DCMI_D7_PORT (GPIOE)
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#define DCMI_HSYNC_PIN (GPIO_PIN_4)
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#define DCMI_VSYNC_PIN (GPIO_PIN_7)
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@ -284,37 +261,14 @@ typedef enum {
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#define DCMI_PWDN_LOW() HAL_GPIO_WritePin(DCMI_PWDN_PORT, DCMI_PWDN_PIN, GPIO_PIN_RESET)
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#define DCMI_PWDN_HIGH() HAL_GPIO_WritePin(DCMI_PWDN_PORT, DCMI_PWDN_PIN, GPIO_PIN_SET)
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/* Wlan */
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#define WLAN_SPI SPI3
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#define WLAN_SPI_AF (GPIO_AF6_SPI3)
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#define WLAN_IRQn (EXTI15_10_IRQn)
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#define WLAN_IRQHandler (EXTI15_10_IRQHandler)
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#define WLAN_EXTI_LINE (1<<11)
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#define DCMI_FREX_LOW() HAL_GPIO_WritePin(DCMI_FREX_PORT, DCMI_FREX_PIN, GPIO_PIN_RESET)
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#define DCMI_FREX_HIGH() HAL_GPIO_WritePin(DCMI_FREX_PORT, DCMI_FREX_PIN, GPIO_PIN_SET)
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#define WLAN_CS_PIN (GPIO_PIN_15)
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#define WLAN_EN_PIN (GPIO_PIN_10)
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#define WLAN_IRQ_PIN (GPIO_PIN_11)
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#define WLAN_SCLK_PIN (GPIO_PIN_10)
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#define WLAN_MISO_PIN (GPIO_PIN_11)
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#define WLAN_MOSI_PIN (GPIO_PIN_12)
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#define DCMI_EXPST_LOW() HAL_GPIO_WritePin(DCMI_EXPST_PORT, DCMI_EXPST_PIN, GPIO_PIN_RESET)
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#define DCMI_EXPST_HIGH() HAL_GPIO_WritePin(DCMI_EXPST_PORT, DCMI_EXPST_PIN, GPIO_PIN_SET)
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#define WLAN_CS_PORT (GPIOA)
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#define WLAN_EN_PORT (GPIOB)
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#define WLAN_IRQ_PORT (GPIOB)
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#define WLAN_SCLK_PORT (GPIOC)
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#define WLAN_MISO_PORT (GPIOC)
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#define WLAN_MOSI_PORT (GPIOC)
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#define WLAN_SPI_CLK_ENABLE() __SPI3_CLK_ENABLE()
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#define WLAN_SPI_CLK_DISABLE() __SPI3_CLK_DISABLE()
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#define WLAN_SELECT() HAL_GPIO_WritePin(WLAN_CS_PORT, WLAN_CS_PIN, GPIO_PIN_RESET)
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#define WLAN_DESELECT() HAL_GPIO_WritePin(WLAN_CS_PORT, WLAN_CS_PIN, GPIO_PIN_SET)
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#define __WLAN_DISABLE() HAL_GPIO_WritePin(WLAN_EN_PORT, WLAN_EN_PIN, GPIO_PIN_RESET)
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#define SD_CD_PIN (GPIO_PIN_4)
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#define SD_CD_PORT (GPIOD)
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#define SD_CD_PIN (GPIO_PIN_15)
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#define SD_CD_PORT (GPIOA)
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#endif //OPENMV1
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#endif //__PINCFG_H__
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@ -28,9 +28,9 @@ ENTRY(Reset_Handler)
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#define CCM_LENGTH 64K
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#else
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#define HEAP_MEMORY SDRAM
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#define HEAP_MEMORY CCM
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#define FLASH_ORIGIN 0x08000000
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#define FLASH_LENGTH 2048K
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#define FLASH_LENGTH 1024K
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#define ISR_ORIGIN 0x08000000
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#define ISR_LENGTH 16K
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@ -43,9 +43,6 @@ ENTRY(Reset_Handler)
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#define CCM_ORIGIN 0x10000000
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#define CCM_LENGTH 64K
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#define SDRAM_ORIGIN 0xC0000000
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#define SDRAM_LENGTH 15M
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#endif //OPENMV1
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/* Specify the memory areas */
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@ -56,27 +53,14 @@ MEMORY
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FLASH_TEXT (rx) : ORIGIN = TEXT_ORIGIN, LENGTH = TEXT_LENGTH
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RAM (xrw) : ORIGIN = RAM_ORIGIN, LENGTH = RAM_LENGTH
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CCM (xrw) : ORIGIN = CCM_ORIGIN, LENGTH = CCM_LENGTH
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#ifdef OPENMV2
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SDRAM (xrw) : ORIGIN = SDRAM_ORIGIN, LENGTH = SDRAM_LENGTH
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#endif
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}
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_estack = 0x10010000; /* Stack is allocated on CCM block */
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_ram_end = 0x10010000; /* 64KB CCM */
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#ifdef OPENMV1
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_fb_base = 0x20000000;
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_stack_size = 0x1000; /* required amount of stack */
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_heap_size = 0XB400; /* required amount of heap */
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#else
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_fb_base = 0xC0F04000; /* sdram_start + head_end + cache */
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_stack_size = 0x4000; /* required amount of stack */
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_heap_size = 0x00F00000; /* required amount of heap */
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_cache_size = 0x4000; /* required amount of cache */
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_heap_end = ORIGIN(SDRAM) + _heap_size;
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#endif
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/* Define output sections */
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SECTIONS
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@ -145,11 +129,9 @@ SECTIONS
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{
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. = ALIGN(4);
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_heap_start = .;
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#ifdef OPENMV1
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. = . + _heap_size;
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. = ALIGN(4);
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_heap_end = .;
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#endif
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} >HEAP_MEMORY
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/* Make sure there is enough RAM the stack and FS cache */
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@ -209,9 +209,11 @@ void HAL_SD_MspInit(SD_HandleTypeDef *hsd)
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GPIO_InitStructure.Mode = GPIO_MODE_AF_PP;
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GPIO_InitStructure.Alternate = GPIO_AF12_SDIO;
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/* SDIO_D0..D3, SDIO_CLK */
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GPIO_InitStructure.Pin = GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_11|GPIO_PIN_12;
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HAL_GPIO_Init(GPIOC, &GPIO_InitStructure);
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/* SDIO_CMD */
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GPIO_InitStructure.Pin = GPIO_PIN_2;
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HAL_GPIO_Init(GPIOD, &GPIO_InitStructure);
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}
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@ -3,6 +3,8 @@
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SRCS = $(addprefix src/,\
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stm32f4xx_hal_adc.c\
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stm32f4xx_hal_adc_ex.c\
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stm32f4xx_hal_dac.c\
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stm32f4xx_hal_dac_ex.c\
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stm32f4xx_hal.c\
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stm32f4xx_hal_cortex.c\
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stm32f4xx_hal_dcmi.c\
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