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Merge pull request #1867 from openmv/winc_omv_spi
drivers/winc1500: Switch to the new SPI HAL.
This commit is contained in:
commit
5bbccf9d8f
@ -1,33 +1,30 @@
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#include STM32_HAL_H
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#include "stm32_hal_legacy.h"
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#include "conf_winc.h"
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#include "bsp/include/nm_bsp.h"
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#include "common/include/nm_common.h"
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#include "py/nlr.h"
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#include "py/runtime.h"
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#include "pin.h"
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#include "genhdr/pins.h"
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#include "extint.h"
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#include "systick.h"
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/*
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* This file is part of the OpenMV project.
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*
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* Copyright (c) 2023 Ibrahim Abdelkader <iabdalkader@openmv.io>
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* Copyright (c) 2023 Kwabena W. Agyeman <kwagyeman@openmv.io>
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*
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* This work is licensed under the MIT license, see the file LICENSE for details.
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*
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* WINC1500 BSP.
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*/
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#include <stdint.h>
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#include <string.h>
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#include "py/mphal.h"
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#include "omv_boardconfig.h"
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#include "omv_gpio.h"
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static tpfNmBspIsr gpfIsr;
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/*
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* @fn nm_bsp_init
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* @brief Initialize BSP
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* @return 0 in case of success and -1 in case of failure
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*/
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sint8 nm_bsp_init(void)
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{
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gpfIsr = NULL;
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#include "conf_winc.h"
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#include "bsp/include/nm_bsp.h"
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#include "common/include/nm_common.h"
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// Configure SPI pins
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omv_gpio_config(WINC_SPI_MISO_PIN, OMV_GPIO_MODE_ALT, OMV_GPIO_PULL_NONE, OMV_GPIO_SPEED_HIGH, -1);
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omv_gpio_config(WINC_SPI_MOSI_PIN, OMV_GPIO_MODE_ALT, OMV_GPIO_PULL_NONE, OMV_GPIO_SPEED_HIGH, -1);
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omv_gpio_config(WINC_SPI_SCLK_PIN, OMV_GPIO_MODE_ALT, OMV_GPIO_PULL_DOWN, OMV_GPIO_SPEED_HIGH, -1);
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omv_gpio_config(WINC_SPI_SSEL_PIN, OMV_GPIO_MODE_OUTPUT, OMV_GPIO_PULL_UP, OMV_GPIO_SPEED_LOW, -1);
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omv_gpio_write(WINC_SPI_SSEL_PIN, 1);
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static tpfNmBspIsr gpfIsr;
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sint8 nm_bsp_init(void) {
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gpfIsr = NULL;
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// Configure GPIO pins
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omv_gpio_config(WINC_EN_PIN, OMV_GPIO_MODE_OUTPUT, OMV_GPIO_PULL_UP, OMV_GPIO_SPEED_LOW, -1);
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@ -36,69 +33,39 @@ sint8 nm_bsp_init(void)
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omv_gpio_config(WINC_RST_PIN, OMV_GPIO_MODE_OUTPUT, OMV_GPIO_PULL_UP, OMV_GPIO_SPEED_LOW, -1);
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omv_gpio_write(WINC_RST_PIN, 1);
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// Perform chip reset.
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nm_bsp_reset();
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// Perform chip reset.
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nm_bsp_reset();
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return M2M_SUCCESS;
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return M2M_SUCCESS;
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}
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/**
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* @fn nm_bsp_reset
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* @brief Reset NMC1500 SoC by setting CHIP_EN and RESET_N signals low,
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* CHIP_EN high then RESET_N high
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*/
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void nm_bsp_reset(void)
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{
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void nm_bsp_reset(void) {
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omv_gpio_write(WINC_EN_PIN, 0);
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omv_gpio_write(WINC_RST_PIN, 0);
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nm_bsp_sleep(100);
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nm_bsp_sleep(100);
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omv_gpio_write(WINC_EN_PIN, 1);
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nm_bsp_sleep(100);
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nm_bsp_sleep(100);
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omv_gpio_write(WINC_RST_PIN, 1);
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nm_bsp_sleep(100);
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nm_bsp_sleep(100);
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}
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extern void systick_sleep(uint32_t ms);
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/*
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* @fn nm_bsp_sleep
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* @brief Sleep in units of mSec
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* @param[IN] u32TimeMsec
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* Time in milliseconds
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*/
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void nm_bsp_sleep(uint32 u32TimeMsec)
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{
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systick_sleep(u32TimeMsec);
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void nm_bsp_sleep(uint32 u32TimeMsec) {
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mp_hal_delay_ms(u32TimeMsec);
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}
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// Pin IRQ handler
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static void nm_bsp_extint_callback(omv_gpio_t pin, void *data)
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{
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static void nm_bsp_extint_callback(omv_gpio_t pin, void *data) {
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if (gpfIsr) {
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gpfIsr();
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}
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}
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/*
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* @fn nm_bsp_register_isr
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* @brief Register interrupt service routine
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* @param[IN] pfIsr
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* Pointer to ISR handler
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*/
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void nm_bsp_register_isr(tpfNmBspIsr pfIsr)
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{
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gpfIsr = pfIsr;
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void nm_bsp_register_isr(tpfNmBspIsr pfIsr) {
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gpfIsr = pfIsr;
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omv_gpio_config(WINC_IRQ_PIN, OMV_GPIO_MODE_IT_FALL, OMV_GPIO_PULL_UP, OMV_GPIO_SPEED_LOW, -1);
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omv_gpio_irq_register(WINC_IRQ_PIN, nm_bsp_extint_callback, NULL);
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omv_gpio_irq_enable(WINC_IRQ_PIN, true);
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}
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/*
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* @fn nm_bsp_interrupt_ctrl
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* @brief Enable/Disable interrupts
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* @param[IN] u8Enable
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* '0' disable interrupts. '1' enable interrupts
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*/
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void nm_bsp_interrupt_ctrl(uint8 enable)
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{
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void nm_bsp_interrupt_ctrl(uint8 enable) {
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omv_gpio_irq_enable(WINC_IRQ_PIN, enable);
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}
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@ -1,207 +1,97 @@
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/**
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/*
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* This file is part of the OpenMV project.
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*
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* \file
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* Copyright (c) 2013->2023 Ibrahim Abdelkader <iabdalkader@openmv.io>
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* Copyright (c) 2013->2023 Kwabena W. Agyeman <kwagyeman@openmv.io>
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*
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* \brief This module contains NMC1000 bus wrapper APIs implementation.
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*
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* Copyright (c) 2015 Atmel Corporation. All rights reserved.
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*
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* \asf_license_start
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*
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* \page License
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* 3. The name of Atmel may not be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
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* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
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* POSSIBILITY OF SUCH DAMAGE.
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*
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* \asf_license_stop
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* This work is licensed under the MIT license, see the file LICENSE for details.
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*
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* WINC1500 bus wrapper.
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*/
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#include <stdio.h>
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#include <stdint.h>
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#include <string.h>
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#include STM32_HAL_H
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#include "py/mphal.h"
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#include "omv_boardconfig.h"
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#include "omv_gpio.h"
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#include "omv_spi.h"
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#include "conf_winc.h"
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#include "bsp/include/nm_bsp.h"
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#include "common/include/nm_common.h"
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#include "bus_wrapper/include/nm_bus_wrapper.h"
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#include "conf_winc.h"
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#include "py/nlr.h"
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#include "py/runtime.h"
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#include "pin.h"
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#include "genhdr/pins.h"
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#include "extint.h"
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#include "omv_boardconfig.h"
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#include "omv_gpio.h"
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static SPI_HandleTypeDef SPI_HANDLE;
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#define NM_BUS_MAX_TRX_SZ (4096)
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#define NM_BUS_SPI_TIMEOUT (1000)
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#define NM_BUS_MAX_TRX_SZ 4096
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static omv_spi_t spi_bus;
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tstrNmBusCapabilities egstrNmBusCapabilities =
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{
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tstrNmBusCapabilities egstrNmBusCapabilities = {
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NM_BUS_MAX_TRX_SZ
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};
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#ifdef CONF_WINC_USE_I2C
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#define SLAVE_ADDRESS 0x60
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/** Number of times to try to send packet if failed. */
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#define I2C_TIMEOUT 100
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static sint8 nm_i2c_write(uint8 *b, uint16 sz)
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{
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sint8 result = M2M_ERR_BUS_FAIL;
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return result;
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}
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static sint8 nm_i2c_read(uint8 *rb, uint16 sz)
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{
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sint8 result = M2M_ERR_BUS_FAIL;
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return result;
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}
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static sint8 nm_i2c_write_special(uint8 *wb1, uint16 sz1, uint8 *wb2, uint16 sz2)
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{
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static uint8 tmp[NM_BUS_MAX_TRX_SZ];
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m2m_memcpy(tmp, wb1, sz1);
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m2m_memcpy(&tmp[sz1], wb2, sz2);
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return nm_i2c_write(tmp, sz1+sz2);
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}
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#endif
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#ifdef CONF_WINC_USE_SPI
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static sint8 spi_rw(uint8 *tx_buf, uint8 *rx_buf, uint16 u16Sz)
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{
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sint8 result = M2M_SUCCESS;
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omv_gpio_write(WINC_SPI_SSEL_PIN, 0);
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if (tx_buf != 0) {
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if (HAL_SPI_Transmit(&SPI_HANDLE, tx_buf, u16Sz, WINC_SPI_TIMEOUT) != HAL_OK) {
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result = M2M_ERR_BUS_FAIL;
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}
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} else {
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memset(rx_buf, 0, u16Sz);
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if (HAL_SPI_TransmitReceive(&SPI_HANDLE, rx_buf, rx_buf, u16Sz, WINC_SPI_TIMEOUT) != HAL_OK) {
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result = M2M_ERR_BUS_FAIL;
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}
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}
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omv_gpio_write(WINC_SPI_SSEL_PIN, 1);
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return result;
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}
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#endif
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/*
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* @fn nm_bus_init
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* @brief Initialize the bus wrapper
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* @return M2M_SUCCESS in case of success and M2M_ERR_BUS_FAIL in case of failure
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*/
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sint8 nm_bus_init(void *pvinit)
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{
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sint8 nm_bus_init(void *pvinit) {
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sint8 result = M2M_SUCCESS;
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omv_gpio_write(WINC_SPI_SSEL_PIN, 1);
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omv_spi_config_t spi_config;
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omv_spi_default_config(&spi_config, WINC_SPI_ID);
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// SPI configuration
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SPI_HANDLE.Instance = WINC_SPI;
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SPI_HANDLE.Init.Mode = SPI_MODE_MASTER;
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SPI_HANDLE.Init.Direction = SPI_DIRECTION_2LINES;
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SPI_HANDLE.Init.DataSize = SPI_DATASIZE_8BIT;
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SPI_HANDLE.Init.CLKPolarity = SPI_POLARITY_LOW;
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SPI_HANDLE.Init.CLKPhase = SPI_PHASE_1EDGE;
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SPI_HANDLE.Init.NSS = SPI_NSS_SOFT;
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SPI_HANDLE.Init.BaudRatePrescaler = WINC_SPI_PRESCALER;
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SPI_HANDLE.Init.FirstBit = SPI_FIRSTBIT_MSB;
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SPI_HANDLE.Init.TIMode = SPI_TIMODE_DISABLED;
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SPI_HANDLE.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLED;
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SPI_HANDLE.Init.CRCPolynomial = 7;
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spi_config.baudrate = WINC_SPI_BAUDRATE;
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spi_config.nss_enable = false; // Soft NSS
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// Enable SPI clock
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WINC_SPI_CLK_ENABLE();
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// Init SPI
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HAL_SPI_DeInit(&SPI_HANDLE);
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if (HAL_SPI_Init(&SPI_HANDLE) != HAL_OK) {
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if (omv_spi_init(&spi_bus, &spi_config) != 0) {
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result = M2M_ERR_BUS_FAIL;
|
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}
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|
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nm_bsp_reset();
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omv_gpio_write(WINC_SPI_SSEL_PIN, 1);
|
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return result;
|
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}
|
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|
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/*
|
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* @fn nm_bus_ioctl
|
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* @brief send/receive from the bus
|
||||
* @param[IN] u8Cmd
|
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* IOCTL command for the operation
|
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* @param[IN] pvParameter
|
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* Arbitrary parameter depenging on IOCTL
|
||||
* @return M2M_SUCCESS in case of success and M2M_ERR_BUS_FAIL in case of failure
|
||||
* @note For SPI only, it's important to be able to send/receive at the same time
|
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*/
|
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sint8 nm_bus_ioctl(uint8 u8Cmd, void* pvParameter)
|
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{
|
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sint8 s8Ret = 0;
|
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switch(u8Cmd)
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{
|
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#ifdef CONF_WINC_USE_I2C
|
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case NM_BUS_IOCTL_R: {
|
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tstrNmI2cDefault *pstrParam = (tstrNmI2cDefault *)pvParameter;
|
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s8Ret = nm_i2c_read(pstrParam->pu8Buf, pstrParam->u16Sz);
|
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}
|
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break;
|
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case NM_BUS_IOCTL_W: {
|
||||
tstrNmI2cDefault *pstrParam = (tstrNmI2cDefault *)pvParameter;
|
||||
s8Ret = nm_i2c_write(pstrParam->pu8Buf, pstrParam->u16Sz);
|
||||
}
|
||||
break;
|
||||
case NM_BUS_IOCTL_W_SPECIAL: {
|
||||
tstrNmI2cSpecial *pstrParam = (tstrNmI2cSpecial *)pvParameter;
|
||||
s8Ret = nm_i2c_write_special(pstrParam->pu8Buf1, pstrParam->u16Sz1, pstrParam->pu8Buf2, pstrParam->u16Sz2);
|
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}
|
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break;
|
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#elif defined CONF_WINC_USE_SPI
|
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case NM_BUS_IOCTL_RW: {
|
||||
tstrNmSpiRw *pstrParam = (tstrNmSpiRw *)pvParameter;
|
||||
s8Ret = spi_rw(pstrParam->pu8InBuf, pstrParam->pu8OutBuf, pstrParam->u16Sz);
|
||||
}
|
||||
break;
|
||||
#endif
|
||||
default:
|
||||
s8Ret = -1;
|
||||
M2M_ERR("invalide ioclt cmd\n");
|
||||
break;
|
||||
}
|
||||
|
||||
return s8Ret;
|
||||
}
|
||||
|
||||
/*
|
||||
* @fn nm_bus_deinit
|
||||
* @brief De-initialize the bus wrapper
|
||||
*/
|
||||
sint8 nm_bus_deinit(void)
|
||||
{
|
||||
sint8 nm_bus_deinit(void) {
|
||||
omv_spi_deinit(&spi_bus);
|
||||
return M2M_SUCCESS;
|
||||
}
|
||||
|
||||
static sint8 nm_bus_rw(uint8 *txbuf, uint8 *rxbuf, uint16 size) {
|
||||
sint8 result = M2M_SUCCESS;
|
||||
omv_spi_transfer_t spi_xfer = {
|
||||
.txbuf = txbuf,
|
||||
.rxbuf = rxbuf,
|
||||
.size = size,
|
||||
.timeout = NM_BUS_SPI_TIMEOUT,
|
||||
.flags = OMV_SPI_XFER_BLOCKING,
|
||||
.callback = NULL,
|
||||
.userdata = NULL,
|
||||
};
|
||||
|
||||
if (txbuf == NULL) {
|
||||
memset(rxbuf, 0, size);
|
||||
spi_xfer.txbuf = rxbuf;
|
||||
spi_xfer.rxbuf = rxbuf;
|
||||
}
|
||||
|
||||
omv_gpio_write(spi_bus.cs, 0);
|
||||
omv_spi_transfer_start(&spi_bus, &spi_xfer);
|
||||
omv_gpio_write(spi_bus.cs, 1);
|
||||
|
||||
return result;
|
||||
}
|
||||
|
||||
sint8 nm_bus_ioctl(uint8 cmd, void *arg) {
|
||||
sint8 ret = 0;
|
||||
switch (cmd) {
|
||||
case NM_BUS_IOCTL_RW: {
|
||||
tstrNmSpiRw *spi_rw = (tstrNmSpiRw *) arg;
|
||||
ret = nm_bus_rw(spi_rw->pu8InBuf, spi_rw->pu8OutBuf, spi_rw->u16Sz);
|
||||
}
|
||||
break;
|
||||
default:
|
||||
ret = -1;
|
||||
M2M_ERR("Invalid IOCTL\n");
|
||||
break;
|
||||
}
|
||||
return ret;
|
||||
}
|
||||
|
||||
@ -129,7 +129,7 @@
|
||||
#define OMV_FLASH_TXT_ORIGIN 0x08010000
|
||||
#define OMV_FLASH_TXT_LENGTH 960K
|
||||
|
||||
// Image sensor I2C
|
||||
// Main image sensor I2C bus
|
||||
#define ISC_I2C (I2C1)
|
||||
#define ISC_I2C_ID (1)
|
||||
#define ISC_I2C_SPEED (OMV_I2C_SPEED_STANDARD)
|
||||
@ -140,7 +140,7 @@
|
||||
#define ISC_I2C_FORCE_RESET() __HAL_RCC_I2C1_FORCE_RESET()
|
||||
#define ISC_I2C_RELEASE_RESET() __HAL_RCC_I2C1_RELEASE_RESET()
|
||||
|
||||
// FIR I2C configuration.
|
||||
// Thermal image sensor I2C bus
|
||||
#define FIR_I2C (I2C2)
|
||||
#define FIR_I2C_ID (2)
|
||||
#define FIR_I2C_SPEED (OMV_I2C_SPEED_FULL)
|
||||
@ -151,11 +151,18 @@
|
||||
#define FIR_I2C_FORCE_RESET() __HAL_RCC_I2C2_FORCE_RESET()
|
||||
#define FIR_I2C_RELEASE_RESET() __HAL_RCC_I2C2_RELEASE_RESET()
|
||||
|
||||
// Soft I2C bus.
|
||||
// Soft I2C bus
|
||||
#define SOFT_I2C_SIOC_PIN (&omv_pin_B10_GPIO)
|
||||
#define SOFT_I2C_SIOD_PIN (&omv_pin_B11_GPIO)
|
||||
#define SOFT_I2C_SPIN_DELAY 16
|
||||
|
||||
// WINC SPI bus
|
||||
#define WINC_SPI_ID (2)
|
||||
#define WINC_SPI_BAUDRATE (27000000)
|
||||
#define WINC_EN_PIN (&omv_pin_A5_GPIO)
|
||||
#define WINC_RST_PIN (&omv_pin_D12_GPIO)
|
||||
#define WINC_IRQ_PIN (&omv_pin_D13_GPIO)
|
||||
|
||||
// DCMI pins.
|
||||
#define DCMI_TIM (TIM1)
|
||||
#define DCMI_TIM_PIN (&omv_pin_A8_TIM1)
|
||||
@ -181,18 +188,16 @@
|
||||
#define DCMI_VSYNC_PIN (&omv_pin_B7_DCMI)
|
||||
#define DCMI_PXCLK_PIN (&omv_pin_A6_DCMI)
|
||||
|
||||
#define WINC_SPI (SPI2)
|
||||
#define WINC_SPI_TIMEOUT (1000)
|
||||
#define WINC_SPI_PRESCALER (SPI_BAUDRATEPRESCALER_2)
|
||||
#define WINC_SPI_CLK_ENABLE() __HAL_RCC_SPI2_CLK_ENABLE()
|
||||
#define WINC_SPI_SCLK_PIN (&omv_pin_B13_SPI2)
|
||||
#define WINC_SPI_MISO_PIN (&omv_pin_B14_SPI2)
|
||||
#define WINC_SPI_MOSI_PIN (&omv_pin_B15_SPI2)
|
||||
#define WINC_SPI_SSEL_PIN (&omv_pin_B12_GPIO)
|
||||
|
||||
#define WINC_EN_PIN (&omv_pin_A5_GPIO)
|
||||
#define WINC_RST_PIN (&omv_pin_D12_GPIO)
|
||||
#define WINC_IRQ_PIN (&omv_pin_D13_GPIO)
|
||||
// Physical SPI buses
|
||||
#define SPI2_ID (2)
|
||||
#define SPI2_SCLK_PIN (&omv_pin_B13_SPI2)
|
||||
#define SPI2_MISO_PIN (&omv_pin_B14_SPI2)
|
||||
#define SPI2_MOSI_PIN (&omv_pin_B15_SPI2)
|
||||
#define SPI2_SSEL_PIN (&omv_pin_B12_SPI2)
|
||||
#define SPI2_DMA_TX_CHANNEL (DMA1_Stream4)
|
||||
#define SPI2_DMA_RX_CHANNEL (DMA1_Stream3)
|
||||
#define DMA_REQUEST_SPI2_TX (DMA_CHANNEL_0)
|
||||
#define DMA_REQUEST_SPI2_RX (DMA_CHANNEL_0)
|
||||
|
||||
// SPI LCD Interface
|
||||
#define OMV_SPI_LCD_CONTROLLER (&spi_obj[1])
|
||||
|
||||
@ -13,6 +13,7 @@ OMV_GPIO_DEFINE(B, 10, AF4, I2C2)
|
||||
OMV_GPIO_DEFINE(B, 11, NONE, GPIO)
|
||||
OMV_GPIO_DEFINE(B, 11, AF4, I2C2)
|
||||
OMV_GPIO_DEFINE(B, 12, NONE, GPIO)
|
||||
OMV_GPIO_DEFINE(B, 12, AF5, SPI2)
|
||||
OMV_GPIO_DEFINE(B, 13, AF5, SPI2)
|
||||
OMV_GPIO_DEFINE(B, 14, AF5, SPI2)
|
||||
OMV_GPIO_DEFINE(B, 15, AF5, SPI2)
|
||||
|
||||
@ -129,7 +129,7 @@
|
||||
#define OMV_FLASH_TXT_ORIGIN 0x08020000
|
||||
#define OMV_FLASH_TXT_LENGTH 1920K
|
||||
|
||||
// Image sensor I2C
|
||||
// Main image sensor I2C bus
|
||||
#define ISC_I2C (I2C1)
|
||||
#define ISC_I2C_ID (1)
|
||||
#define ISC_I2C_SPEED (OMV_I2C_SPEED_STANDARD)
|
||||
@ -140,23 +140,30 @@
|
||||
#define ISC_I2C_FORCE_RESET() __HAL_RCC_I2C1_FORCE_RESET()
|
||||
#define ISC_I2C_RELEASE_RESET() __HAL_RCC_I2C1_RELEASE_RESET()
|
||||
|
||||
// FIR I2C configuration.
|
||||
// FIR I2C bus
|
||||
#define FIR_I2C (I2C2)
|
||||
#define FIR_I2C_ID (2)
|
||||
#define FIR_I2C_SPEED (OMV_I2C_SPEED_FULL)
|
||||
#define FIR_I2C_SCL_PIN (&omv_pin_B10_I2C2)
|
||||
#define FIR_I2C_SDA_PIN (&omv_pin_B11_I2C2)
|
||||
#define FIR_I2C_CLK_ENABLE() __I2C2_CLK_ENABLE()
|
||||
#define FIR_I2C_CLK_DISABLE() __I2C2_CLK_DISABLE()
|
||||
#define FIR_I2C_SPEED (OMV_I2C_SPEED_FULL)
|
||||
#define FIR_I2C_FORCE_RESET() __HAL_RCC_I2C2_FORCE_RESET()
|
||||
#define FIR_I2C_RELEASE_RESET() __HAL_RCC_I2C2_RELEASE_RESET()
|
||||
|
||||
// Soft I2C bus.
|
||||
// Soft I2C bus
|
||||
#define SOFT_I2C_SIOC_PIN (&omv_pin_B10_GPIO)
|
||||
#define SOFT_I2C_SIOD_PIN (&omv_pin_B11_GPIO)
|
||||
#define SOFT_I2C_SPIN_DELAY 24
|
||||
|
||||
/* DCMI */
|
||||
// WINC SPI bus
|
||||
#define WINC_SPI_ID (2)
|
||||
#define WINC_SPI_BAUDRATE (27000000)
|
||||
#define WINC_EN_PIN (&omv_pin_A5_GPIO)
|
||||
#define WINC_RST_PIN (&omv_pin_D12_GPIO)
|
||||
#define WINC_IRQ_PIN (&omv_pin_D13_GPIO)
|
||||
|
||||
// DCMI timer
|
||||
#define DCMI_TIM (TIM1)
|
||||
#define DCMI_TIM_PIN (&omv_pin_A8_TIM1)
|
||||
#define DCMI_TIM_CHANNEL (TIM_CHANNEL_1)
|
||||
@ -164,6 +171,7 @@
|
||||
#define DCMI_TIM_CLK_DISABLE() __TIM1_CLK_DISABLE()
|
||||
#define DCMI_TIM_PCLK_FREQ() HAL_RCC_GetPCLK2Freq()
|
||||
|
||||
// DCMI pins
|
||||
#define DCMI_RESET_PIN (&omv_pin_A10_GPIO)
|
||||
#define DCMI_POWER_PIN (&omv_pin_B5_GPIO)
|
||||
|
||||
@ -180,20 +188,16 @@
|
||||
#define DCMI_VSYNC_PIN (&omv_pin_B7_DCMI)
|
||||
#define DCMI_PXCLK_PIN (&omv_pin_A6_DCMI)
|
||||
|
||||
#define WINC_SPI (SPI2)
|
||||
#define WINC_SPI_TIMEOUT (1000)
|
||||
// SPI1/2/3 clock source is PCLK1 (54MHz/2 == 27MHz).
|
||||
#define WINC_SPI_PRESCALER (SPI_BAUDRATEPRESCALER_2)
|
||||
#define WINC_SPI_CLK_ENABLE() __HAL_RCC_SPI2_CLK_ENABLE()
|
||||
|
||||
#define WINC_SPI_SCLK_PIN (&omv_pin_B13_SPI2)
|
||||
#define WINC_SPI_MISO_PIN (&omv_pin_B14_SPI2)
|
||||
#define WINC_SPI_MOSI_PIN (&omv_pin_B15_SPI2)
|
||||
#define WINC_SPI_SSEL_PIN (&omv_pin_B12_GPIO)
|
||||
|
||||
#define WINC_EN_PIN (&omv_pin_A5_GPIO)
|
||||
#define WINC_RST_PIN (&omv_pin_D12_GPIO)
|
||||
#define WINC_IRQ_PIN (&omv_pin_D13_GPIO)
|
||||
// Physical SPI buses
|
||||
#define SPI2_ID (2)
|
||||
#define SPI2_SCLK_PIN (&omv_pin_B13_SPI2)
|
||||
#define SPI2_MISO_PIN (&omv_pin_B14_SPI2)
|
||||
#define SPI2_MOSI_PIN (&omv_pin_B15_SPI2)
|
||||
#define SPI2_SSEL_PIN (&omv_pin_B12_SPI2)
|
||||
#define SPI2_DMA_TX_CHANNEL (DMA1_Stream4)
|
||||
#define SPI2_DMA_RX_CHANNEL (DMA1_Stream3)
|
||||
#define DMA_REQUEST_SPI2_TX (DMA_CHANNEL_0)
|
||||
#define DMA_REQUEST_SPI2_RX (DMA_CHANNEL_0)
|
||||
|
||||
// SPI LCD Interface
|
||||
#define OMV_SPI_LCD_CONTROLLER (&spi_obj[1])
|
||||
|
||||
@ -13,6 +13,7 @@ OMV_GPIO_DEFINE(B, 10, AF4, I2C2)
|
||||
OMV_GPIO_DEFINE(B, 11, NONE, GPIO)
|
||||
OMV_GPIO_DEFINE(B, 11, AF4, I2C2)
|
||||
OMV_GPIO_DEFINE(B, 12, NONE, GPIO)
|
||||
OMV_GPIO_DEFINE(B, 12, AF5, SPI2)
|
||||
OMV_GPIO_DEFINE(B, 13, AF5, SPI2)
|
||||
OMV_GPIO_DEFINE(B, 14, AF5, SPI2)
|
||||
OMV_GPIO_DEFINE(B, 15, AF5, SPI2)
|
||||
|
||||
@ -247,6 +247,13 @@
|
||||
#define ISC_SPI_ID (3)
|
||||
#define ISC_SPI_BAUDRATE (20000000)
|
||||
|
||||
// WINC1500 WiFi module SPI bus
|
||||
#define WINC_SPI_ID (2)
|
||||
#define WINC_SPI_BAUDRATE (40000000)
|
||||
#define WINC_EN_PIN (&omv_pin_A5_GPIO)
|
||||
#define WINC_RST_PIN (&omv_pin_D12_GPIO)
|
||||
#define WINC_IRQ_PIN (&omv_pin_D13_GPIO)
|
||||
|
||||
// DCMI timer.
|
||||
#define DCMI_TIM (TIM1)
|
||||
#define DCMI_TIM_PIN (&omv_pin_A8_TIM1)
|
||||
@ -274,6 +281,14 @@
|
||||
#define DCMI_PXCLK_PIN (&omv_pin_A6_DCMI)
|
||||
|
||||
// Physical SPI buses.
|
||||
#define SPI2_ID (2)
|
||||
#define SPI2_SCLK_PIN (&omv_pin_B13_SPI2)
|
||||
#define SPI2_MISO_PIN (&omv_pin_B14_SPI2)
|
||||
#define SPI2_MOSI_PIN (&omv_pin_B15_SPI2)
|
||||
#define SPI2_SSEL_PIN (&omv_pin_B12_SPI2)
|
||||
#define SPI2_DMA_TX_CHANNEL (DMA1_Stream4)
|
||||
#define SPI2_DMA_RX_CHANNEL (DMA1_Stream3)
|
||||
|
||||
#define SPI3_ID (3)
|
||||
#define SPI3_SCLK_PIN (&omv_pin_B3_SPI3)
|
||||
#define SPI3_MISO_PIN (&omv_pin_B4_SPI3)
|
||||
@ -282,21 +297,6 @@
|
||||
#define SPI3_DMA_TX_CHANNEL (DMA1_Stream7)
|
||||
#define SPI3_DMA_RX_CHANNEL (DMA1_Stream2)
|
||||
|
||||
#define WINC_SPI (SPI2)
|
||||
#define WINC_SPI_TIMEOUT (1000)
|
||||
// SPI1/2/3 clock source is PLL2 (160MHz/4 == 40MHz).
|
||||
#define WINC_SPI_PRESCALER (SPI_BAUDRATEPRESCALER_4)
|
||||
#define WINC_SPI_CLK_ENABLE() __HAL_RCC_SPI2_CLK_ENABLE()
|
||||
|
||||
#define WINC_SPI_SCLK_PIN (&omv_pin_B13_SPI2)
|
||||
#define WINC_SPI_MISO_PIN (&omv_pin_B14_SPI2)
|
||||
#define WINC_SPI_MOSI_PIN (&omv_pin_B15_SPI2)
|
||||
#define WINC_SPI_SSEL_PIN (&omv_pin_B12_GPIO)
|
||||
|
||||
#define WINC_EN_PIN (&omv_pin_A5_GPIO)
|
||||
#define WINC_RST_PIN (&omv_pin_D12_GPIO)
|
||||
#define WINC_IRQ_PIN (&omv_pin_D13_GPIO)
|
||||
|
||||
// SPI LCD Interface
|
||||
#define OMV_SPI_LCD_CONTROLLER (&spi_obj[1])
|
||||
#define OMV_SPI_LCD_CONTROLLER_INSTANCE (SPI2)
|
||||
|
||||
@ -17,6 +17,7 @@ OMV_GPIO_DEFINE(B, 10, AF4, I2C2)
|
||||
OMV_GPIO_DEFINE(B, 11, NONE, GPIO)
|
||||
OMV_GPIO_DEFINE(B, 11, AF4, I2C2)
|
||||
OMV_GPIO_DEFINE(B, 12, NONE, GPIO)
|
||||
OMV_GPIO_DEFINE(B, 12, AF5, SPI2)
|
||||
OMV_GPIO_DEFINE(B, 13, AF5, SPI2)
|
||||
OMV_GPIO_DEFINE(B, 14, AF5, SPI2)
|
||||
OMV_GPIO_DEFINE(B, 15, AF5, SPI2)
|
||||
|
||||
@ -250,6 +250,13 @@
|
||||
#define ISC_SPI_ID (3)
|
||||
#define ISC_SPI_BAUDRATE (20000000)
|
||||
|
||||
// WINC1500 WiFi module SPI bus
|
||||
#define WINC_SPI_ID (2)
|
||||
#define WINC_SPI_BAUDRATE (40000000)
|
||||
#define WINC_EN_PIN (&omv_pin_A5_GPIO)
|
||||
#define WINC_RST_PIN (&omv_pin_D12_GPIO)
|
||||
#define WINC_IRQ_PIN (&omv_pin_D13_GPIO)
|
||||
|
||||
// DCMI timer.
|
||||
#define DCMI_TIM (TIM1)
|
||||
#define DCMI_TIM_PIN (&omv_pin_A8_TIM1)
|
||||
@ -277,6 +284,14 @@
|
||||
#define DCMI_PXCLK_PIN (&omv_pin_A6_DCMI)
|
||||
|
||||
// Physical SPI buses.
|
||||
#define SPI2_ID (2)
|
||||
#define SPI2_SCLK_PIN (&omv_pin_B13_SPI2)
|
||||
#define SPI2_MISO_PIN (&omv_pin_B14_SPI2)
|
||||
#define SPI2_MOSI_PIN (&omv_pin_B15_SPI2)
|
||||
#define SPI2_SSEL_PIN (&omv_pin_B12_SPI2)
|
||||
#define SPI2_DMA_TX_CHANNEL (DMA1_Stream4)
|
||||
#define SPI2_DMA_RX_CHANNEL (DMA1_Stream3)
|
||||
|
||||
#define SPI3_ID (3)
|
||||
#define SPI3_SCLK_PIN (&omv_pin_B3_SPI3)
|
||||
#define SPI3_MISO_PIN (&omv_pin_B4_SPI3)
|
||||
@ -285,20 +300,6 @@
|
||||
#define SPI3_DMA_TX_CHANNEL (DMA1_Stream7)
|
||||
#define SPI3_DMA_RX_CHANNEL (DMA1_Stream2)
|
||||
|
||||
#define WINC_SPI (SPI2)
|
||||
#define WINC_SPI_TIMEOUT (1000)
|
||||
// SPI1/2/3 clock source is PLL2 (160MHz/4 == 40MHz).
|
||||
#define WINC_SPI_PRESCALER (SPI_BAUDRATEPRESCALER_4)
|
||||
#define WINC_SPI_CLK_ENABLE() __HAL_RCC_SPI2_CLK_ENABLE()
|
||||
#define WINC_SPI_SCLK_PIN (&omv_pin_B13_SPI2)
|
||||
#define WINC_SPI_MISO_PIN (&omv_pin_B14_SPI2)
|
||||
#define WINC_SPI_MOSI_PIN (&omv_pin_B15_SPI2)
|
||||
#define WINC_SPI_SSEL_PIN (&omv_pin_B12_GPIO)
|
||||
|
||||
#define WINC_EN_PIN (&omv_pin_A5_GPIO)
|
||||
#define WINC_RST_PIN (&omv_pin_D12_GPIO)
|
||||
#define WINC_IRQ_PIN (&omv_pin_D13_GPIO)
|
||||
|
||||
// SPI LCD Interface
|
||||
#define OMV_SPI_LCD_CONTROLLER (&spi_obj[1])
|
||||
#define OMV_SPI_LCD_CONTROLLER_INSTANCE (SPI2)
|
||||
|
||||
@ -17,6 +17,7 @@ OMV_GPIO_DEFINE(B, 10, AF4, I2C2)
|
||||
OMV_GPIO_DEFINE(B, 11, NONE, GPIO)
|
||||
OMV_GPIO_DEFINE(B, 11, AF4, I2C2)
|
||||
OMV_GPIO_DEFINE(B, 12, NONE, GPIO)
|
||||
OMV_GPIO_DEFINE(B, 12, AF5, SPI2)
|
||||
OMV_GPIO_DEFINE(B, 13, AF5, SPI2)
|
||||
OMV_GPIO_DEFINE(B, 14, AF5, SPI2)
|
||||
OMV_GPIO_DEFINE(B, 15, AF5, SPI2)
|
||||
|
||||
@ -225,7 +225,7 @@
|
||||
#define OMV_AXI_QOS_MDMA_W_PRI 15 // Max pri to move data.
|
||||
#define OMV_AXI_QOS_LTDC_R_PRI 15 // Max pri to read out the frame buffer.
|
||||
|
||||
// Image sensor I2C
|
||||
// Main image sensor I2C bus
|
||||
#define ISC_I2C (I2C1)
|
||||
#define ISC_I2C_ID (1)
|
||||
#define ISC_I2C_SPEED (OMV_I2C_SPEED_STANDARD)
|
||||
@ -236,7 +236,7 @@
|
||||
#define ISC_I2C_FORCE_RESET() __HAL_RCC_I2C1_FORCE_RESET()
|
||||
#define ISC_I2C_RELEASE_RESET() __HAL_RCC_I2C1_RELEASE_RESET()
|
||||
|
||||
// FIR I2C configuration.
|
||||
// Thermal image sensor I2C bus
|
||||
#define FIR_I2C (I2C2)
|
||||
#define FIR_I2C_ID (2)
|
||||
#define FIR_I2C_SPEED (OMV_I2C_SPEED_FULL)
|
||||
@ -252,6 +252,14 @@
|
||||
#define SOFT_I2C_SIOD_PIN (&omv_pin_B11_GPIO)
|
||||
#define SOFT_I2C_SPIN_DELAY 64
|
||||
|
||||
// WINC1500 WiFi module SPI bus
|
||||
#define WINC_SPI_ID (5)
|
||||
#define WINC_SPI_BAUDRATE (50000000)
|
||||
#define WINC_EN_PIN (&omv_pin_A0_GPIO)
|
||||
#define WINC_RST_PIN (&omv_pin_C3_GPIO)
|
||||
#define WINC_WAKE_PIN (&omv_pin_A1_GPIO)
|
||||
#define WINC_CFG_PIN (&omv_pin_I15_GPIO)
|
||||
#define WINC_IRQ_PIN (&omv_pin_H5_GPIO)
|
||||
|
||||
/* DCMI */
|
||||
#define DCMI_TIM (TIM1)
|
||||
@ -277,22 +285,13 @@
|
||||
#define DCMI_VSYNC_PIN (&omv_pin_B7_DCMI)
|
||||
#define DCMI_PXCLK_PIN (&omv_pin_A6_DCMI)
|
||||
|
||||
#define WINC_SPI (SPI5)
|
||||
#define WINC_SPI_TIMEOUT (1000)
|
||||
// SPI5 clock source is PLL2 (200MHz/4 == 50MHz) - Slightly over the maximum of 48 MHz.
|
||||
#define WINC_SPI_PRESCALER (SPI_BAUDRATEPRESCALER_4)
|
||||
#define WINC_SPI_CLK_ENABLE() __HAL_RCC_SPI5_CLK_ENABLE()
|
||||
// Physical SPI buses.
|
||||
|
||||
#define WINC_SPI_SCLK_PIN (&omv_pin_H6_SPI5)
|
||||
#define WINC_SPI_MISO_PIN (&omv_pin_H7_SPI5)
|
||||
#define WINC_SPI_MOSI_PIN (&omv_pin_J10_SPI5)
|
||||
#define WINC_SPI_SSEL_PIN (&omv_pin_K1_GPIO)
|
||||
|
||||
#define WINC_EN_PIN (&omv_pin_A0_GPIO)
|
||||
#define WINC_RST_PIN (&omv_pin_C3_GPIO)
|
||||
#define WINC_WAKE_PIN (&omv_pin_A1_GPIO)
|
||||
#define WINC_CFG_PIN (&omv_pin_I15_GPIO)
|
||||
#define WINC_IRQ_PIN (&omv_pin_H5_GPIO)
|
||||
#define SPI_ID (5)
|
||||
#define SPI5_SCLK_PIN (&omv_pin_H6_SPI5)
|
||||
#define SPI5_MISO_PIN (&omv_pin_H7_SPI5)
|
||||
#define SPI5_MOSI_PIN (&omv_pin_J10_SPI5)
|
||||
#define SPI5_SSEL_PIN (&omv_pin_K1_GPIO)
|
||||
|
||||
// LCD Interface
|
||||
#define OMV_LCD_CONTROLLER (LTDC)
|
||||
|
||||
Loading…
Reference in New Issue
Block a user