Merge pull request #2719 from openmv/fix_n6_port
Some checks failed
🔥 Firmware Build / build-firmware (ARDUINO_GIGA) (push) Has been cancelled
🔥 Firmware Build / build-firmware (ARDUINO_NANO_33_BLE_SENSE) (push) Has been cancelled
🔥 Firmware Build / build-firmware (ARDUINO_NANO_RP2040_CONNECT) (push) Has been cancelled
🔥 Firmware Build / build-firmware (ARDUINO_NICLA_VISION) (push) Has been cancelled
🔥 Firmware Build / build-firmware (ARDUINO_PORTENTA_H7) (push) Has been cancelled
🔥 Firmware Build / build-firmware (DOCKER) (push) Has been cancelled
🔥 Firmware Build / build-firmware (OPENMV2) (push) Has been cancelled
🔥 Firmware Build / build-firmware (OPENMV3) (push) Has been cancelled
🔥 Firmware Build / build-firmware (OPENMV4) (push) Has been cancelled
🔥 Firmware Build / build-firmware (OPENMV4P) (push) Has been cancelled
🔥 Firmware Build / build-firmware (OPENMVPT) (push) Has been cancelled
🔥 Firmware Build / build-firmware (OPENMV_AE3) (push) Has been cancelled
🔥 Firmware Build / build-firmware (OPENMV_N6) (push) Has been cancelled
🔥 Firmware Build / build-firmware (OPENMV_RT1060) (push) Has been cancelled
🔥 Firmware Build / code-size-report (push) Has been cancelled
🔥 Firmware Build / stable-release (push) Has been cancelled
🔥 Firmware Build / development-release (push) Has been cancelled

ports/stm32: Fix N6 support.
This commit is contained in:
Ibrahim Abdelkader 2025-06-20 15:31:01 +03:00 committed by GitHub
commit 696c68c9af
No known key found for this signature in database
GPG Key ID: B5690EEEBB952194
15 changed files with 82 additions and 30 deletions

View File

@ -111,6 +111,7 @@ ifeq ($(PROFILE), 1)
CFLAGS += -DOMV_PROFILE_ENABLE=1
endif
# Include OpenMV board config first to set the port.
include $(OMV_BOARD_CONFIG_DIR)/omv_boardconfig.mk
@ -125,6 +126,12 @@ MPY_MKARGS = PORT=$(PORT) BOARD=$(TARGET) DEBUG=$(DEBUG) MICROPY_MANIFEST_OMV_LI
FROZEN_MANIFEST=$(FROZEN_MANIFEST) OMV_SRC_QSTR="$(OMV_SRC_QSTR)"\
MICROPY_ROM_TEXT_COMPRESSION=$(ROM_TEXT_COMPRESSION) USER_C_MODULES=$(TOP_DIR)
# Disable broken optimization for CM55.
ifeq ($(CPU),cortex-m55)
CFLAGS += -fdisable-rtl-loop2_doloop
endif
# Configure additional built-in modules. Note must define both the CFLAGS and the Make command line args.
ifeq ($(MICROPY_PY_CSI), 1)
MPY_CFLAGS += -DMICROPY_PY_CSI=1

View File

@ -222,6 +222,7 @@
#define OMV_CSI_TIM_CLK_ENABLE() __TIM1_CLK_ENABLE()
#define OMV_CSI_TIM_CLK_DISABLE() __TIM1_CLK_DISABLE()
#define OMV_CSI_TIM_CLK_SLEEP_ENABLE() __TIM1_CLK_SLEEP_ENABLE()
#define OMV_CSI_TIM_CLK_SLEEP_DISABLE() __TIM1_CLK_SLEEP_DISABLE()
#define OMV_CSI_TIM_PCLK_FREQ() HAL_RCC_GetPCLK2Freq()
#define OMV_CSI_DMA_MEMCPY_ENABLE (1)
#define OMV_CSI_HW_CROP_ENABLE (1)

View File

@ -215,6 +215,7 @@
#define OMV_CSI_TIM_CLK_ENABLE() __TIM3_CLK_ENABLE()
#define OMV_CSI_TIM_CLK_DISABLE() __TIM3_CLK_DISABLE()
#define OMV_CSI_TIM_CLK_SLEEP_ENABLE() __TIM3_CLK_SLEEP_ENABLE()
#define OMV_CSI_TIM_CLK_SLEEP_DISABLE() __TIM3_CLK_SLEEP_DISABLE()
#define OMV_CSI_TIM_PCLK_FREQ() HAL_RCC_GetPCLK1Freq()
#define OMV_CSI_DMA_MEMCPY_ENABLE (1)
#define OMV_CSI_HW_CROP_ENABLE (1)

View File

@ -227,6 +227,7 @@
#define OMV_CSI_TIM_CLK_ENABLE() __TIM1_CLK_ENABLE()
#define OMV_CSI_TIM_CLK_DISABLE() __TIM1_CLK_DISABLE()
#define OMV_CSI_TIM_CLK_SLEEP_ENABLE() __TIM1_CLK_SLEEP_ENABLE()
#define OMV_CSI_TIM_CLK_SLEEP_DISABLE() __TIM1_CLK_SLEEP_DISABLE()
#define OMV_CSI_TIM_PCLK_FREQ() HAL_RCC_GetPCLK2Freq()
#define OMV_CSI_DMA_MEMCPY_ENABLE (1)
#define OMV_CSI_HW_CROP_ENABLE (1)

View File

@ -87,6 +87,7 @@
#define OMV_CSI_TIM_CLK_ENABLE() __TIM1_CLK_ENABLE()
#define OMV_CSI_TIM_CLK_DISABLE() __TIM1_CLK_DISABLE()
#define OMV_CSI_TIM_CLK_SLEEP_ENABLE() __TIM1_CLK_SLEEP_ENABLE()
#define OMV_CSI_TIM_CLK_SLEEP_DISABLE() __TIM1_CLK_SLEEP_DISABLE()
#define OMV_CSI_HW_CROP_ENABLE (1)
#define OMV_CSI_RESET_PIN (GPIO_PIN_10)

View File

@ -145,6 +145,7 @@
#define OMV_CSI_TIM_CLK_ENABLE() __TIM1_CLK_ENABLE()
#define OMV_CSI_TIM_CLK_DISABLE() __TIM1_CLK_DISABLE()
#define OMV_CSI_TIM_CLK_SLEEP_ENABLE() __TIM1_CLK_SLEEP_ENABLE()
#define OMV_CSI_TIM_CLK_SLEEP_DISABLE() __TIM1_CLK_SLEEP_DISABLE()
#define OMV_CSI_TIM_PCLK_FREQ() HAL_RCC_GetPCLK2Freq()
#define OMV_CSI_HW_CROP_ENABLE (1)

View File

@ -144,6 +144,7 @@
#define OMV_CSI_TIM_CLK_ENABLE() __TIM1_CLK_ENABLE()
#define OMV_CSI_TIM_CLK_DISABLE() __TIM1_CLK_DISABLE()
#define OMV_CSI_TIM_CLK_SLEEP_ENABLE() __TIM1_CLK_SLEEP_ENABLE()
#define OMV_CSI_TIM_CLK_SLEEP_DISABLE() __TIM1_CLK_SLEEP_DISABLE()
#define OMV_CSI_TIM_PCLK_FREQ() HAL_RCC_GetPCLK2Freq()
#define OMV_CSI_HW_CROP_ENABLE (1)

View File

@ -218,6 +218,7 @@
#define OMV_CSI_TIM_CLK_ENABLE() __TIM1_CLK_ENABLE()
#define OMV_CSI_TIM_CLK_DISABLE() __TIM1_CLK_DISABLE()
#define OMV_CSI_TIM_CLK_SLEEP_ENABLE() __TIM1_CLK_SLEEP_ENABLE()
#define OMV_CSI_TIM_CLK_SLEEP_DISABLE() __TIM1_CLK_SLEEP_DISABLE()
#define OMV_CSI_TIM_PCLK_FREQ() HAL_RCC_GetPCLK2Freq()
#define OMV_CSI_DMA_MEMCPY_ENABLE (1)
#define OMV_CSI_HW_CROP_ENABLE (1)

View File

@ -218,6 +218,7 @@
#define OMV_CSI_TIM_CLK_ENABLE() __TIM1_CLK_ENABLE()
#define OMV_CSI_TIM_CLK_DISABLE() __TIM1_CLK_DISABLE()
#define OMV_CSI_TIM_CLK_SLEEP_ENABLE() __TIM1_CLK_SLEEP_ENABLE()
#define OMV_CSI_TIM_CLK_SLEEP_DISABLE() __TIM1_CLK_SLEEP_DISABLE()
#define OMV_CSI_TIM_PCLK_FREQ() HAL_RCC_GetPCLK2Freq()
#define OMV_CSI_DMA_MEMCPY_ENABLE (1)
#define OMV_CSI_HW_CROP_ENABLE (1)

View File

@ -211,6 +211,7 @@
#define OMV_CSI_TIM_CLK_ENABLE() __TIM1_CLK_ENABLE()
#define OMV_CSI_TIM_CLK_DISABLE() __TIM1_CLK_DISABLE()
#define OMV_CSI_TIM_CLK_SLEEP_ENABLE() __TIM1_CLK_SLEEP_ENABLE()
#define OMV_CSI_TIM_CLK_SLEEP_DISABLE() __TIM1_CLK_SLEEP_DISABLE()
#define OMV_CSI_TIM_PCLK_FREQ() HAL_RCC_GetPCLK2Freq()
#define OMV_CSI_DMA_MEMCPY_ENABLE (1)
#define OMV_CSI_HW_CROP_ENABLE (1)

View File

@ -159,27 +159,27 @@
#define OMV_GC_BLOCK0_MEMORY SRAM2 // Main GC block
#define OMV_GC_BLOCK0_SIZE (1M)
#define OMV_GC_BLOCK1_MEMORY DRAM // Main GC block
#define OMV_GC_BLOCK1_SIZE (32M)
#define OMV_MSC_BUF_SIZE (2K) // USB MSC bot data
#define OMV_GC_BLOCK1_SIZE (24M)
#define OMV_MSC_BUF_SIZE (4K) // USB MSC bot data
// Memory map.
#define OMV_DTCM_ORIGIN 0x20000000
#define OMV_DTCM_ORIGIN 0x30000000
#define OMV_DTCM_LENGTH 128K
#define OMV_ITCM_ORIGIN 0x00000000
#define OMV_ITCM_ORIGIN 0x10000000
#define OMV_ITCM_LENGTH 64K
#define OMV_SRAM1_ORIGIN 0x24000000 // AXISRAM1
#define OMV_SRAM1_ORIGIN 0x34000000 // AXISRAM1
#define OMV_SRAM1_LENGTH 1M // 1MB
#define OMV_SRAM2_ORIGIN 0x24100000 // AXISRAM2
#define OMV_SRAM2_ORIGIN 0x34100000 // AXISRAM2
#define OMV_SRAM2_LENGTH 1M // 1MB
#define OMV_SRAM3_ORIGIN 0x24200000 // AXISRAM3
#define OMV_SRAM3_ORIGIN 0x34200000 // AXISRAM3
#define OMV_SRAM3_LENGTH 448K // 448KB
#define OMV_SRAM4_ORIGIN 0x24270000 // AXISRAM4
#define OMV_SRAM4_ORIGIN 0x34270000 // AXISRAM4
#define OMV_SRAM4_LENGTH 448K // 448KB
#define OMV_SRAM5_ORIGIN 0x242E0000 // AXISRAM5
#define OMV_SRAM5_ORIGIN 0x342E0000 // AXISRAM5
#define OMV_SRAM5_LENGTH 448K // 448KB
#define OMV_SRAM6_ORIGIN 0x24350000 // AXISRAM6
#define OMV_SRAM6_ORIGIN 0x34350000 // AXISRAM6
#define OMV_SRAM6_LENGTH 448K // 448KB
#define OMV_SRAM7_ORIGIN 0x28000000 // AHBSRAM1 + AHBSRAM2 combined
#define OMV_SRAM7_ORIGIN 0x38000000 // AHBSRAM1 + AHBSRAM2 combined
#define OMV_SRAM7_LENGTH 32K // 16KB + 16KB = 32KB
#define OMV_DRAM_ORIGIN 0x90000000 // XSPI1
#define OMV_DRAM_LENGTH 64M // 512 Mbits (64 MBytes)
@ -226,9 +226,9 @@
#define OMV_SPI5_MISO_PIN (&omv_pin_D4_SPI5)
#define OMV_SPI5_MOSI_PIN (&omv_pin_A4_SPI5)
#define OMV_SPI5_SSEL_PIN (&omv_pin_A3_SPI5)
#define OMV_SPI5_DMA_TX_CHANNEL (GPDMA1_Channel0)
#define OMV_SPI5_DMA_TX_CHANNEL (GPDMA1_Channel8)
#define OMV_SPI5_DMA_TX_REQUEST (GPDMA1_REQUEST_SPI5_TX)
#define OMV_SPI5_DMA_RX_CHANNEL (GPDMA1_Channel1)
#define OMV_SPI5_DMA_RX_CHANNEL (GPDMA1_Channel9)
#define OMV_SPI5_DMA_RX_REQUEST (GPDMA1_REQUEST_SPI5_RX)
// CSI SPI bus
@ -260,9 +260,9 @@
#define OMV_MDF_FLT0_IRQ ADF1_FLT0_IRQn
#define OMV_MDF_FLT0_IRQHandler ADF1_FLT0_IRQHandler
#define OMV_MDF_FLT0_DMA_STREAM GPDMA1_Channel6
#define OMV_MDF_FLT0_DMA_STREAM GPDMA1_Channel10
#define OMV_MDF_FLT0_DMA_REQUEST GPDMA1_REQUEST_ADF1_FLT0
#define OMV_MDF_FLT0_DMA_IRQ GPDMA1_Channel6_IRQn
#define OMV_MDF_FLT0_DMA_IRQ GPDMA1_Channel10_IRQn
// Camera Interface
#define OMV_CSI_CLK_SOURCE (OMV_CSI_CLK_SOURCE_TIM)
@ -273,6 +273,7 @@
#define OMV_CSI_TIM_CLK_ENABLE() __TIM1_CLK_ENABLE()
#define OMV_CSI_TIM_CLK_DISABLE() __TIM1_CLK_DISABLE()
#define OMV_CSI_TIM_CLK_SLEEP_ENABLE() __TIM1_CLK_SLEEP_ENABLE()
#define OMV_CSI_TIM_CLK_SLEEP_DISABLE() __TIM1_CLK_SLEEP_DISABLE()
#define OMV_CSI_TIM_PCLK_FREQ() HAL_RCC_GetPCLK2Freq()
#define OMV_CSI_DMA_CHANNEL (HPDMA1_Channel12)
#define OMV_CSI_DMA_REQUEST (HPDMA1_REQUEST_DCMI_PSSI)

View File

@ -48,3 +48,9 @@ endif
# Include the port Makefile.
include $(PORT_DIR)/$(PORT_LOWER)_port.mk
# Disable broken optimization for CM55.
ifeq ($(CPU),cortex-m55)
CFLAGS += -fdisable-rtl-loop2_doloop
endif

@ -1 +1 @@
Subproject commit 54a07f038d32899b2a1d3a4dead8363a2b90c90d
Subproject commit 06311ef05438b0a6ab266c59c54ec388fd2c513b

View File

@ -90,7 +90,7 @@ CLANG_FLAGS = -fshort-enums \
-Wno-unused-command-line-argument \
-D__ARMCC_VERSION=6100100 \
-DALIF_CMSIS_H=$(CMSIS_MCU_H) \
$(filter-out -march%,$(CFLAGS))
$(filter-out -march% -fdisable-rtl%,$(CFLAGS))
OMV_CFLAGS += -I$(TOP_DIR)/$(OMV_DIR)/$(COMMON_DIR)
OMV_CFLAGS += -I$(TOP_DIR)/$(OMV_DIR)/modules/

View File

@ -153,52 +153,54 @@ void HAL_MspInit(void) {
// Enable GPIO clocks.
__HAL_RCC_GPIOA_CLK_ENABLE();
__HAL_RCC_GPIOA_CLK_SLEEP_ENABLE();
__HAL_RCC_GPIOB_CLK_ENABLE();
__HAL_RCC_GPIOB_CLK_SLEEP_ENABLE();
__HAL_RCC_GPIOC_CLK_ENABLE();
__HAL_RCC_GPIOC_CLK_SLEEP_ENABLE();
__HAL_RCC_GPIOD_CLK_ENABLE();
__HAL_RCC_GPIOD_CLK_SLEEP_ENABLE();
__HAL_RCC_GPIOE_CLK_ENABLE();
__HAL_RCC_GPIOE_CLK_SLEEP_ENABLE();
#if OMV_GPIO_PORT_F_ENABLE
__HAL_RCC_GPIOF_CLK_ENABLE();
__HAL_RCC_GPIOF_CLK_SLEEP_ENABLE();
#endif
#if OMV_GPIO_PORT_G_ENABLE
__HAL_RCC_GPIOG_CLK_ENABLE();
__HAL_RCC_GPIOG_CLK_SLEEP_ENABLE();
#endif
#if OMV_GPIO_PORT_H_ENABLE
__HAL_RCC_GPIOH_CLK_ENABLE();
__HAL_RCC_GPIOH_CLK_SLEEP_ENABLE();
#endif
#if OMV_GPIO_PORT_I_ENABLE
__HAL_RCC_GPIOI_CLK_ENABLE();
__HAL_RCC_GPIOI_CLK_SLEEP_ENABLE();
#endif
#if OMV_GPIO_PORT_J_ENABLE
__HAL_RCC_GPIOJ_CLK_ENABLE();
__HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE();
#endif
#if OMV_GPIO_PORT_K_ENABLE
__HAL_RCC_GPIOK_CLK_ENABLE();
__HAL_RCC_GPIOK_CLK_SLEEP_ENABLE();
#endif
#if OMV_GPIO_PORT_N_ENABLE
__HAL_RCC_GPION_CLK_ENABLE();
__HAL_RCC_GPION_CLK_SLEEP_ENABLE();
#endif
#if OMV_GPIO_PORT_O_ENABLE
__HAL_RCC_GPIOO_CLK_ENABLE();
__HAL_RCC_GPIOO_CLK_SLEEP_ENABLE();
#endif
#if OMV_GPIO_PORT_P_ENABLE
__HAL_RCC_GPIOP_CLK_ENABLE();
__HAL_RCC_GPIOP_CLK_SLEEP_ENABLE();
#endif
#if OMV_GPIO_PORT_Q_ENABLE
__HAL_RCC_GPIOQ_CLK_ENABLE();
#endif
// Enable low-power GPIO clocks.
#if defined(STM32N6)
__HAL_RCC_GPIOA_CLK_SLEEP_ENABLE();
__HAL_RCC_GPIOB_CLK_SLEEP_ENABLE();
__HAL_RCC_GPIOC_CLK_SLEEP_ENABLE();
__HAL_RCC_GPIOD_CLK_SLEEP_ENABLE();
__HAL_RCC_GPIOE_CLK_SLEEP_ENABLE();
__HAL_RCC_GPIOF_CLK_SLEEP_ENABLE();
__HAL_RCC_GPIOG_CLK_SLEEP_ENABLE();
__HAL_RCC_GPIOO_CLK_SLEEP_ENABLE();
__HAL_RCC_GPIOP_CLK_SLEEP_ENABLE();
__HAL_RCC_GPIOQ_CLK_SLEEP_ENABLE();
#endif
// Enable DMA clocks.
@ -378,24 +380,28 @@ void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c) {
__HAL_RCC_I2C1_FORCE_RESET();
__HAL_RCC_I2C1_RELEASE_RESET();
__HAL_RCC_I2C1_CLK_DISABLE();
__HAL_RCC_I2C1_CLK_SLEEP_DISABLE();
#endif
#if defined(OMV_I2C2_ID)
} else if (hi2c->Instance == I2C2) {
__HAL_RCC_I2C2_FORCE_RESET();
__HAL_RCC_I2C2_RELEASE_RESET();
__HAL_RCC_I2C2_CLK_DISABLE();
__HAL_RCC_I2C2_CLK_SLEEP_DISABLE();
#endif
#if defined(OMV_I2C3_ID)
} else if (hi2c->Instance == I2C3) {
__HAL_RCC_I2C3_FORCE_RESET();
__HAL_RCC_I2C3_RELEASE_RESET();
__HAL_RCC_I2C3_CLK_DISABLE();
__HAL_RCC_I2C3_CLK_SLEEP_DISABLE();
#endif
#if defined(OMV_I2C4_ID)
} else if (hi2c->Instance == I2C4) {
__HAL_RCC_I2C4_FORCE_RESET();
__HAL_RCC_I2C4_RELEASE_RESET();
__HAL_RCC_I2C4_CLK_DISABLE();
__HAL_RCC_I2C4_CLK_SLEEP_DISABLE();
#endif
}
}
@ -422,6 +428,19 @@ void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim) {
}
void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim) {
#if defined(OMV_CSI_TIM)
if (htim->Instance == OMV_CSI_TIM) {
// Disable DCMI timer clock.
OMV_CSI_TIM_CLK_DISABLE();
OMV_CSI_TIM_CLK_SLEEP_DISABLE();
// Deinit timer GPIO.
omv_gpio_deinit(OMV_CSI_TIM_PIN);
#if defined(OMV_CSI_TIM_EXT_PIN)
omv_gpio_deinit(OMV_CSI_TIM_EXT_PIN);
#endif
}
#endif // (OMV_CSI_TIM)
#if defined(OMV_BUZZER_TIM)
if (htim->Instance == OMV_BUZZER_TIM) {
OMV_BUZZER_TIM_FORCE_RESET();
@ -702,6 +721,7 @@ void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi) {
__HAL_RCC_SPI1_FORCE_RESET();
__HAL_RCC_SPI1_RELEASE_RESET();
__HAL_RCC_SPI1_CLK_DISABLE();
__HAL_RCC_SPI1_CLK_SLEEP_DISABLE();
spi_pins = (spi_pins_t) {
OMV_SPI1_SCLK_PIN, OMV_SPI1_MISO_PIN, OMV_SPI1_MOSI_PIN, OMV_SPI1_SSEL_PIN
};
@ -711,6 +731,7 @@ void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi) {
__HAL_RCC_SPI2_FORCE_RESET();
__HAL_RCC_SPI2_RELEASE_RESET();
__HAL_RCC_SPI2_CLK_DISABLE();
__HAL_RCC_SPI2_CLK_SLEEP_DISABLE();
spi_pins = (spi_pins_t) {
OMV_SPI2_SCLK_PIN, OMV_SPI2_MISO_PIN, OMV_SPI2_MOSI_PIN, OMV_SPI2_SSEL_PIN
};
@ -720,6 +741,7 @@ void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi) {
__HAL_RCC_SPI3_FORCE_RESET();
__HAL_RCC_SPI3_RELEASE_RESET();
__HAL_RCC_SPI3_CLK_DISABLE();
__HAL_RCC_SPI3_CLK_SLEEP_DISABLE();
spi_pins = (spi_pins_t) {
OMV_SPI3_SCLK_PIN, OMV_SPI3_MISO_PIN, OMV_SPI3_MOSI_PIN, OMV_SPI3_SSEL_PIN
};
@ -729,6 +751,7 @@ void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi) {
__HAL_RCC_SPI4_FORCE_RESET();
__HAL_RCC_SPI4_RELEASE_RESET();
__HAL_RCC_SPI4_CLK_DISABLE();
__HAL_RCC_SPI4_CLK_SLEEP_DISABLE();
spi_pins = (spi_pins_t) {
OMV_SPI4_SCLK_PIN, OMV_SPI4_MISO_PIN, OMV_SPI4_MOSI_PIN, OMV_SPI4_SSEL_PIN
};
@ -738,6 +761,7 @@ void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi) {
__HAL_RCC_SPI5_FORCE_RESET();
__HAL_RCC_SPI5_RELEASE_RESET();
__HAL_RCC_SPI5_CLK_DISABLE();
__HAL_RCC_SPI5_CLK_SLEEP_DISABLE();
spi_pins = (spi_pins_t) {
OMV_SPI5_SCLK_PIN, OMV_SPI5_MISO_PIN, OMV_SPI5_MOSI_PIN, OMV_SPI5_SSEL_PIN
};
@ -747,6 +771,7 @@ void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi) {
__HAL_RCC_SPI6_FORCE_RESET();
__HAL_RCC_SPI6_RELEASE_RESET();
__HAL_RCC_SPI6_CLK_DISABLE();
__HAL_RCC_SPI6_CLK_SLEEP_DISABLE();
spi_pins = (spi_pins_t) {
SPI6_SCLK_PIN, SPI6_MISO_PIN, SPI6_MOSI_PIN, SPI6_SSEL_PIN
};
@ -895,6 +920,7 @@ void HAL_JPEG_MspDeInit(JPEG_HandleTypeDef *hjpeg) {
__HAL_RCC_JPEG_FORCE_RESET();
__HAL_RCC_JPEG_RELEASE_RESET();
__HAL_RCC_JPEG_CLK_DISABLE();
__HAL_RCC_JPEG_CLK_SLEEP_DISABLE();
}
#endif
@ -1086,14 +1112,17 @@ void HAL_XSPI_MspDeInit(XSPI_HandleTypeDef *hxspi) {
__HAL_RCC_XSPI1_FORCE_RESET();
__HAL_RCC_XSPI1_RELEASE_RESET();
__HAL_RCC_XSPI1_CLK_DISABLE();
__HAL_RCC_XSPI1_CLK_SLEEP_DISABLE();
} else if (hxspi->Instance == XSPI2) {
__HAL_RCC_XSPI2_FORCE_RESET();
__HAL_RCC_XSPI2_RELEASE_RESET();
__HAL_RCC_XSPI2_CLK_DISABLE();
__HAL_RCC_XSPI2_CLK_SLEEP_DISABLE();
} else if (hxspi->Instance == XSPI3) {
__HAL_RCC_XSPI3_FORCE_RESET();
__HAL_RCC_XSPI3_RELEASE_RESET();
__HAL_RCC_XSPI3_CLK_DISABLE();
__HAL_RCC_XSPI3_CLK_SLEEP_DISABLE();
}
for (int i = 0; i < OMV_ARRAY_SIZE(xspi_pins); i++) {