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Merge pull request #2719 from openmv/fix_n6_port
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ports/stm32: Fix N6 support.
This commit is contained in:
commit
696c68c9af
7
Makefile
7
Makefile
@ -111,6 +111,7 @@ ifeq ($(PROFILE), 1)
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CFLAGS += -DOMV_PROFILE_ENABLE=1
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endif
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# Include OpenMV board config first to set the port.
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include $(OMV_BOARD_CONFIG_DIR)/omv_boardconfig.mk
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@ -125,6 +126,12 @@ MPY_MKARGS = PORT=$(PORT) BOARD=$(TARGET) DEBUG=$(DEBUG) MICROPY_MANIFEST_OMV_LI
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FROZEN_MANIFEST=$(FROZEN_MANIFEST) OMV_SRC_QSTR="$(OMV_SRC_QSTR)"\
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MICROPY_ROM_TEXT_COMPRESSION=$(ROM_TEXT_COMPRESSION) USER_C_MODULES=$(TOP_DIR)
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# Disable broken optimization for CM55.
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ifeq ($(CPU),cortex-m55)
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CFLAGS += -fdisable-rtl-loop2_doloop
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endif
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# Configure additional built-in modules. Note must define both the CFLAGS and the Make command line args.
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ifeq ($(MICROPY_PY_CSI), 1)
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MPY_CFLAGS += -DMICROPY_PY_CSI=1
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@ -222,6 +222,7 @@
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#define OMV_CSI_TIM_CLK_ENABLE() __TIM1_CLK_ENABLE()
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#define OMV_CSI_TIM_CLK_DISABLE() __TIM1_CLK_DISABLE()
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#define OMV_CSI_TIM_CLK_SLEEP_ENABLE() __TIM1_CLK_SLEEP_ENABLE()
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#define OMV_CSI_TIM_CLK_SLEEP_DISABLE() __TIM1_CLK_SLEEP_DISABLE()
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#define OMV_CSI_TIM_PCLK_FREQ() HAL_RCC_GetPCLK2Freq()
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#define OMV_CSI_DMA_MEMCPY_ENABLE (1)
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#define OMV_CSI_HW_CROP_ENABLE (1)
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@ -215,6 +215,7 @@
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#define OMV_CSI_TIM_CLK_ENABLE() __TIM3_CLK_ENABLE()
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#define OMV_CSI_TIM_CLK_DISABLE() __TIM3_CLK_DISABLE()
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#define OMV_CSI_TIM_CLK_SLEEP_ENABLE() __TIM3_CLK_SLEEP_ENABLE()
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#define OMV_CSI_TIM_CLK_SLEEP_DISABLE() __TIM3_CLK_SLEEP_DISABLE()
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#define OMV_CSI_TIM_PCLK_FREQ() HAL_RCC_GetPCLK1Freq()
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#define OMV_CSI_DMA_MEMCPY_ENABLE (1)
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#define OMV_CSI_HW_CROP_ENABLE (1)
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@ -227,6 +227,7 @@
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#define OMV_CSI_TIM_CLK_ENABLE() __TIM1_CLK_ENABLE()
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#define OMV_CSI_TIM_CLK_DISABLE() __TIM1_CLK_DISABLE()
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#define OMV_CSI_TIM_CLK_SLEEP_ENABLE() __TIM1_CLK_SLEEP_ENABLE()
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#define OMV_CSI_TIM_CLK_SLEEP_DISABLE() __TIM1_CLK_SLEEP_DISABLE()
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#define OMV_CSI_TIM_PCLK_FREQ() HAL_RCC_GetPCLK2Freq()
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#define OMV_CSI_DMA_MEMCPY_ENABLE (1)
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#define OMV_CSI_HW_CROP_ENABLE (1)
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@ -87,6 +87,7 @@
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#define OMV_CSI_TIM_CLK_ENABLE() __TIM1_CLK_ENABLE()
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#define OMV_CSI_TIM_CLK_DISABLE() __TIM1_CLK_DISABLE()
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#define OMV_CSI_TIM_CLK_SLEEP_ENABLE() __TIM1_CLK_SLEEP_ENABLE()
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#define OMV_CSI_TIM_CLK_SLEEP_DISABLE() __TIM1_CLK_SLEEP_DISABLE()
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#define OMV_CSI_HW_CROP_ENABLE (1)
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#define OMV_CSI_RESET_PIN (GPIO_PIN_10)
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@ -145,6 +145,7 @@
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#define OMV_CSI_TIM_CLK_ENABLE() __TIM1_CLK_ENABLE()
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#define OMV_CSI_TIM_CLK_DISABLE() __TIM1_CLK_DISABLE()
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#define OMV_CSI_TIM_CLK_SLEEP_ENABLE() __TIM1_CLK_SLEEP_ENABLE()
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#define OMV_CSI_TIM_CLK_SLEEP_DISABLE() __TIM1_CLK_SLEEP_DISABLE()
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#define OMV_CSI_TIM_PCLK_FREQ() HAL_RCC_GetPCLK2Freq()
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#define OMV_CSI_HW_CROP_ENABLE (1)
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@ -144,6 +144,7 @@
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#define OMV_CSI_TIM_CLK_ENABLE() __TIM1_CLK_ENABLE()
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#define OMV_CSI_TIM_CLK_DISABLE() __TIM1_CLK_DISABLE()
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#define OMV_CSI_TIM_CLK_SLEEP_ENABLE() __TIM1_CLK_SLEEP_ENABLE()
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#define OMV_CSI_TIM_CLK_SLEEP_DISABLE() __TIM1_CLK_SLEEP_DISABLE()
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#define OMV_CSI_TIM_PCLK_FREQ() HAL_RCC_GetPCLK2Freq()
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#define OMV_CSI_HW_CROP_ENABLE (1)
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|
@ -218,6 +218,7 @@
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#define OMV_CSI_TIM_CLK_ENABLE() __TIM1_CLK_ENABLE()
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#define OMV_CSI_TIM_CLK_DISABLE() __TIM1_CLK_DISABLE()
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#define OMV_CSI_TIM_CLK_SLEEP_ENABLE() __TIM1_CLK_SLEEP_ENABLE()
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#define OMV_CSI_TIM_CLK_SLEEP_DISABLE() __TIM1_CLK_SLEEP_DISABLE()
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#define OMV_CSI_TIM_PCLK_FREQ() HAL_RCC_GetPCLK2Freq()
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#define OMV_CSI_DMA_MEMCPY_ENABLE (1)
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#define OMV_CSI_HW_CROP_ENABLE (1)
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|
@ -218,6 +218,7 @@
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#define OMV_CSI_TIM_CLK_ENABLE() __TIM1_CLK_ENABLE()
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#define OMV_CSI_TIM_CLK_DISABLE() __TIM1_CLK_DISABLE()
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#define OMV_CSI_TIM_CLK_SLEEP_ENABLE() __TIM1_CLK_SLEEP_ENABLE()
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#define OMV_CSI_TIM_CLK_SLEEP_DISABLE() __TIM1_CLK_SLEEP_DISABLE()
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#define OMV_CSI_TIM_PCLK_FREQ() HAL_RCC_GetPCLK2Freq()
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#define OMV_CSI_DMA_MEMCPY_ENABLE (1)
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#define OMV_CSI_HW_CROP_ENABLE (1)
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|
@ -211,6 +211,7 @@
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#define OMV_CSI_TIM_CLK_ENABLE() __TIM1_CLK_ENABLE()
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#define OMV_CSI_TIM_CLK_DISABLE() __TIM1_CLK_DISABLE()
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#define OMV_CSI_TIM_CLK_SLEEP_ENABLE() __TIM1_CLK_SLEEP_ENABLE()
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#define OMV_CSI_TIM_CLK_SLEEP_DISABLE() __TIM1_CLK_SLEEP_DISABLE()
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#define OMV_CSI_TIM_PCLK_FREQ() HAL_RCC_GetPCLK2Freq()
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#define OMV_CSI_DMA_MEMCPY_ENABLE (1)
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#define OMV_CSI_HW_CROP_ENABLE (1)
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@ -159,27 +159,27 @@
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#define OMV_GC_BLOCK0_MEMORY SRAM2 // Main GC block
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#define OMV_GC_BLOCK0_SIZE (1M)
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#define OMV_GC_BLOCK1_MEMORY DRAM // Main GC block
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#define OMV_GC_BLOCK1_SIZE (32M)
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#define OMV_MSC_BUF_SIZE (2K) // USB MSC bot data
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#define OMV_GC_BLOCK1_SIZE (24M)
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#define OMV_MSC_BUF_SIZE (4K) // USB MSC bot data
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// Memory map.
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#define OMV_DTCM_ORIGIN 0x20000000
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#define OMV_DTCM_ORIGIN 0x30000000
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#define OMV_DTCM_LENGTH 128K
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#define OMV_ITCM_ORIGIN 0x00000000
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#define OMV_ITCM_ORIGIN 0x10000000
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#define OMV_ITCM_LENGTH 64K
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#define OMV_SRAM1_ORIGIN 0x24000000 // AXISRAM1
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#define OMV_SRAM1_ORIGIN 0x34000000 // AXISRAM1
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#define OMV_SRAM1_LENGTH 1M // 1MB
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#define OMV_SRAM2_ORIGIN 0x24100000 // AXISRAM2
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#define OMV_SRAM2_ORIGIN 0x34100000 // AXISRAM2
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#define OMV_SRAM2_LENGTH 1M // 1MB
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#define OMV_SRAM3_ORIGIN 0x24200000 // AXISRAM3
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#define OMV_SRAM3_ORIGIN 0x34200000 // AXISRAM3
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#define OMV_SRAM3_LENGTH 448K // 448KB
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#define OMV_SRAM4_ORIGIN 0x24270000 // AXISRAM4
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#define OMV_SRAM4_ORIGIN 0x34270000 // AXISRAM4
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#define OMV_SRAM4_LENGTH 448K // 448KB
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#define OMV_SRAM5_ORIGIN 0x242E0000 // AXISRAM5
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#define OMV_SRAM5_ORIGIN 0x342E0000 // AXISRAM5
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#define OMV_SRAM5_LENGTH 448K // 448KB
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#define OMV_SRAM6_ORIGIN 0x24350000 // AXISRAM6
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#define OMV_SRAM6_ORIGIN 0x34350000 // AXISRAM6
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#define OMV_SRAM6_LENGTH 448K // 448KB
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#define OMV_SRAM7_ORIGIN 0x28000000 // AHBSRAM1 + AHBSRAM2 combined
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#define OMV_SRAM7_ORIGIN 0x38000000 // AHBSRAM1 + AHBSRAM2 combined
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#define OMV_SRAM7_LENGTH 32K // 16KB + 16KB = 32KB
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#define OMV_DRAM_ORIGIN 0x90000000 // XSPI1
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#define OMV_DRAM_LENGTH 64M // 512 Mbits (64 MBytes)
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@ -226,9 +226,9 @@
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#define OMV_SPI5_MISO_PIN (&omv_pin_D4_SPI5)
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#define OMV_SPI5_MOSI_PIN (&omv_pin_A4_SPI5)
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#define OMV_SPI5_SSEL_PIN (&omv_pin_A3_SPI5)
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#define OMV_SPI5_DMA_TX_CHANNEL (GPDMA1_Channel0)
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#define OMV_SPI5_DMA_TX_CHANNEL (GPDMA1_Channel8)
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#define OMV_SPI5_DMA_TX_REQUEST (GPDMA1_REQUEST_SPI5_TX)
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#define OMV_SPI5_DMA_RX_CHANNEL (GPDMA1_Channel1)
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#define OMV_SPI5_DMA_RX_CHANNEL (GPDMA1_Channel9)
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#define OMV_SPI5_DMA_RX_REQUEST (GPDMA1_REQUEST_SPI5_RX)
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// CSI SPI bus
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@ -260,9 +260,9 @@
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#define OMV_MDF_FLT0_IRQ ADF1_FLT0_IRQn
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#define OMV_MDF_FLT0_IRQHandler ADF1_FLT0_IRQHandler
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#define OMV_MDF_FLT0_DMA_STREAM GPDMA1_Channel6
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#define OMV_MDF_FLT0_DMA_STREAM GPDMA1_Channel10
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#define OMV_MDF_FLT0_DMA_REQUEST GPDMA1_REQUEST_ADF1_FLT0
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#define OMV_MDF_FLT0_DMA_IRQ GPDMA1_Channel6_IRQn
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#define OMV_MDF_FLT0_DMA_IRQ GPDMA1_Channel10_IRQn
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// Camera Interface
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#define OMV_CSI_CLK_SOURCE (OMV_CSI_CLK_SOURCE_TIM)
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@ -273,6 +273,7 @@
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#define OMV_CSI_TIM_CLK_ENABLE() __TIM1_CLK_ENABLE()
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#define OMV_CSI_TIM_CLK_DISABLE() __TIM1_CLK_DISABLE()
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#define OMV_CSI_TIM_CLK_SLEEP_ENABLE() __TIM1_CLK_SLEEP_ENABLE()
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#define OMV_CSI_TIM_CLK_SLEEP_DISABLE() __TIM1_CLK_SLEEP_DISABLE()
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#define OMV_CSI_TIM_PCLK_FREQ() HAL_RCC_GetPCLK2Freq()
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#define OMV_CSI_DMA_CHANNEL (HPDMA1_Channel12)
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#define OMV_CSI_DMA_REQUEST (HPDMA1_REQUEST_DCMI_PSSI)
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@ -48,3 +48,9 @@ endif
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# Include the port Makefile.
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include $(PORT_DIR)/$(PORT_LOWER)_port.mk
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# Disable broken optimization for CM55.
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ifeq ($(CPU),cortex-m55)
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CFLAGS += -fdisable-rtl-loop2_doloop
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endif
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@ -1 +1 @@
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Subproject commit 54a07f038d32899b2a1d3a4dead8363a2b90c90d
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Subproject commit 06311ef05438b0a6ab266c59c54ec388fd2c513b
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@ -90,7 +90,7 @@ CLANG_FLAGS = -fshort-enums \
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-Wno-unused-command-line-argument \
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-D__ARMCC_VERSION=6100100 \
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-DALIF_CMSIS_H=$(CMSIS_MCU_H) \
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$(filter-out -march%,$(CFLAGS))
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$(filter-out -march% -fdisable-rtl%,$(CFLAGS))
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OMV_CFLAGS += -I$(TOP_DIR)/$(OMV_DIR)/$(COMMON_DIR)
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OMV_CFLAGS += -I$(TOP_DIR)/$(OMV_DIR)/modules/
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|
@ -153,52 +153,54 @@ void HAL_MspInit(void) {
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// Enable GPIO clocks.
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__HAL_RCC_GPIOA_CLK_ENABLE();
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__HAL_RCC_GPIOA_CLK_SLEEP_ENABLE();
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__HAL_RCC_GPIOB_CLK_ENABLE();
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__HAL_RCC_GPIOB_CLK_SLEEP_ENABLE();
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__HAL_RCC_GPIOC_CLK_ENABLE();
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__HAL_RCC_GPIOC_CLK_SLEEP_ENABLE();
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__HAL_RCC_GPIOD_CLK_ENABLE();
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__HAL_RCC_GPIOD_CLK_SLEEP_ENABLE();
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__HAL_RCC_GPIOE_CLK_ENABLE();
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__HAL_RCC_GPIOE_CLK_SLEEP_ENABLE();
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#if OMV_GPIO_PORT_F_ENABLE
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__HAL_RCC_GPIOF_CLK_ENABLE();
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__HAL_RCC_GPIOF_CLK_SLEEP_ENABLE();
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#endif
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#if OMV_GPIO_PORT_G_ENABLE
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__HAL_RCC_GPIOG_CLK_ENABLE();
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__HAL_RCC_GPIOG_CLK_SLEEP_ENABLE();
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#endif
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#if OMV_GPIO_PORT_H_ENABLE
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__HAL_RCC_GPIOH_CLK_ENABLE();
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__HAL_RCC_GPIOH_CLK_SLEEP_ENABLE();
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#endif
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#if OMV_GPIO_PORT_I_ENABLE
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__HAL_RCC_GPIOI_CLK_ENABLE();
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__HAL_RCC_GPIOI_CLK_SLEEP_ENABLE();
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#endif
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#if OMV_GPIO_PORT_J_ENABLE
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__HAL_RCC_GPIOJ_CLK_ENABLE();
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__HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE();
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#endif
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#if OMV_GPIO_PORT_K_ENABLE
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__HAL_RCC_GPIOK_CLK_ENABLE();
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__HAL_RCC_GPIOK_CLK_SLEEP_ENABLE();
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#endif
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#if OMV_GPIO_PORT_N_ENABLE
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__HAL_RCC_GPION_CLK_ENABLE();
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__HAL_RCC_GPION_CLK_SLEEP_ENABLE();
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#endif
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#if OMV_GPIO_PORT_O_ENABLE
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__HAL_RCC_GPIOO_CLK_ENABLE();
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__HAL_RCC_GPIOO_CLK_SLEEP_ENABLE();
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#endif
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#if OMV_GPIO_PORT_P_ENABLE
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__HAL_RCC_GPIOP_CLK_ENABLE();
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__HAL_RCC_GPIOP_CLK_SLEEP_ENABLE();
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#endif
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#if OMV_GPIO_PORT_Q_ENABLE
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__HAL_RCC_GPIOQ_CLK_ENABLE();
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#endif
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// Enable low-power GPIO clocks.
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#if defined(STM32N6)
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__HAL_RCC_GPIOA_CLK_SLEEP_ENABLE();
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__HAL_RCC_GPIOB_CLK_SLEEP_ENABLE();
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__HAL_RCC_GPIOC_CLK_SLEEP_ENABLE();
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__HAL_RCC_GPIOD_CLK_SLEEP_ENABLE();
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__HAL_RCC_GPIOE_CLK_SLEEP_ENABLE();
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__HAL_RCC_GPIOF_CLK_SLEEP_ENABLE();
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__HAL_RCC_GPIOG_CLK_SLEEP_ENABLE();
|
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__HAL_RCC_GPIOO_CLK_SLEEP_ENABLE();
|
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__HAL_RCC_GPIOP_CLK_SLEEP_ENABLE();
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__HAL_RCC_GPIOQ_CLK_SLEEP_ENABLE();
|
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#endif
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|
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// Enable DMA clocks.
|
||||
@ -378,24 +380,28 @@ void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c) {
|
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__HAL_RCC_I2C1_FORCE_RESET();
|
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__HAL_RCC_I2C1_RELEASE_RESET();
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__HAL_RCC_I2C1_CLK_DISABLE();
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__HAL_RCC_I2C1_CLK_SLEEP_DISABLE();
|
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#endif
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#if defined(OMV_I2C2_ID)
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} else if (hi2c->Instance == I2C2) {
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__HAL_RCC_I2C2_FORCE_RESET();
|
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__HAL_RCC_I2C2_RELEASE_RESET();
|
||||
__HAL_RCC_I2C2_CLK_DISABLE();
|
||||
__HAL_RCC_I2C2_CLK_SLEEP_DISABLE();
|
||||
#endif
|
||||
#if defined(OMV_I2C3_ID)
|
||||
} else if (hi2c->Instance == I2C3) {
|
||||
__HAL_RCC_I2C3_FORCE_RESET();
|
||||
__HAL_RCC_I2C3_RELEASE_RESET();
|
||||
__HAL_RCC_I2C3_CLK_DISABLE();
|
||||
__HAL_RCC_I2C3_CLK_SLEEP_DISABLE();
|
||||
#endif
|
||||
#if defined(OMV_I2C4_ID)
|
||||
} else if (hi2c->Instance == I2C4) {
|
||||
__HAL_RCC_I2C4_FORCE_RESET();
|
||||
__HAL_RCC_I2C4_RELEASE_RESET();
|
||||
__HAL_RCC_I2C4_CLK_DISABLE();
|
||||
__HAL_RCC_I2C4_CLK_SLEEP_DISABLE();
|
||||
#endif
|
||||
}
|
||||
}
|
||||
@ -422,6 +428,19 @@ void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim) {
|
||||
}
|
||||
|
||||
void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim) {
|
||||
#if defined(OMV_CSI_TIM)
|
||||
if (htim->Instance == OMV_CSI_TIM) {
|
||||
// Disable DCMI timer clock.
|
||||
OMV_CSI_TIM_CLK_DISABLE();
|
||||
OMV_CSI_TIM_CLK_SLEEP_DISABLE();
|
||||
// Deinit timer GPIO.
|
||||
omv_gpio_deinit(OMV_CSI_TIM_PIN);
|
||||
#if defined(OMV_CSI_TIM_EXT_PIN)
|
||||
omv_gpio_deinit(OMV_CSI_TIM_EXT_PIN);
|
||||
#endif
|
||||
}
|
||||
#endif // (OMV_CSI_TIM)
|
||||
|
||||
#if defined(OMV_BUZZER_TIM)
|
||||
if (htim->Instance == OMV_BUZZER_TIM) {
|
||||
OMV_BUZZER_TIM_FORCE_RESET();
|
||||
@ -702,6 +721,7 @@ void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi) {
|
||||
__HAL_RCC_SPI1_FORCE_RESET();
|
||||
__HAL_RCC_SPI1_RELEASE_RESET();
|
||||
__HAL_RCC_SPI1_CLK_DISABLE();
|
||||
__HAL_RCC_SPI1_CLK_SLEEP_DISABLE();
|
||||
spi_pins = (spi_pins_t) {
|
||||
OMV_SPI1_SCLK_PIN, OMV_SPI1_MISO_PIN, OMV_SPI1_MOSI_PIN, OMV_SPI1_SSEL_PIN
|
||||
};
|
||||
@ -711,6 +731,7 @@ void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi) {
|
||||
__HAL_RCC_SPI2_FORCE_RESET();
|
||||
__HAL_RCC_SPI2_RELEASE_RESET();
|
||||
__HAL_RCC_SPI2_CLK_DISABLE();
|
||||
__HAL_RCC_SPI2_CLK_SLEEP_DISABLE();
|
||||
spi_pins = (spi_pins_t) {
|
||||
OMV_SPI2_SCLK_PIN, OMV_SPI2_MISO_PIN, OMV_SPI2_MOSI_PIN, OMV_SPI2_SSEL_PIN
|
||||
};
|
||||
@ -720,6 +741,7 @@ void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi) {
|
||||
__HAL_RCC_SPI3_FORCE_RESET();
|
||||
__HAL_RCC_SPI3_RELEASE_RESET();
|
||||
__HAL_RCC_SPI3_CLK_DISABLE();
|
||||
__HAL_RCC_SPI3_CLK_SLEEP_DISABLE();
|
||||
spi_pins = (spi_pins_t) {
|
||||
OMV_SPI3_SCLK_PIN, OMV_SPI3_MISO_PIN, OMV_SPI3_MOSI_PIN, OMV_SPI3_SSEL_PIN
|
||||
};
|
||||
@ -729,6 +751,7 @@ void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi) {
|
||||
__HAL_RCC_SPI4_FORCE_RESET();
|
||||
__HAL_RCC_SPI4_RELEASE_RESET();
|
||||
__HAL_RCC_SPI4_CLK_DISABLE();
|
||||
__HAL_RCC_SPI4_CLK_SLEEP_DISABLE();
|
||||
spi_pins = (spi_pins_t) {
|
||||
OMV_SPI4_SCLK_PIN, OMV_SPI4_MISO_PIN, OMV_SPI4_MOSI_PIN, OMV_SPI4_SSEL_PIN
|
||||
};
|
||||
@ -738,6 +761,7 @@ void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi) {
|
||||
__HAL_RCC_SPI5_FORCE_RESET();
|
||||
__HAL_RCC_SPI5_RELEASE_RESET();
|
||||
__HAL_RCC_SPI5_CLK_DISABLE();
|
||||
__HAL_RCC_SPI5_CLK_SLEEP_DISABLE();
|
||||
spi_pins = (spi_pins_t) {
|
||||
OMV_SPI5_SCLK_PIN, OMV_SPI5_MISO_PIN, OMV_SPI5_MOSI_PIN, OMV_SPI5_SSEL_PIN
|
||||
};
|
||||
@ -747,6 +771,7 @@ void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi) {
|
||||
__HAL_RCC_SPI6_FORCE_RESET();
|
||||
__HAL_RCC_SPI6_RELEASE_RESET();
|
||||
__HAL_RCC_SPI6_CLK_DISABLE();
|
||||
__HAL_RCC_SPI6_CLK_SLEEP_DISABLE();
|
||||
spi_pins = (spi_pins_t) {
|
||||
SPI6_SCLK_PIN, SPI6_MISO_PIN, SPI6_MOSI_PIN, SPI6_SSEL_PIN
|
||||
};
|
||||
@ -895,6 +920,7 @@ void HAL_JPEG_MspDeInit(JPEG_HandleTypeDef *hjpeg) {
|
||||
__HAL_RCC_JPEG_FORCE_RESET();
|
||||
__HAL_RCC_JPEG_RELEASE_RESET();
|
||||
__HAL_RCC_JPEG_CLK_DISABLE();
|
||||
__HAL_RCC_JPEG_CLK_SLEEP_DISABLE();
|
||||
}
|
||||
#endif
|
||||
|
||||
@ -1086,14 +1112,17 @@ void HAL_XSPI_MspDeInit(XSPI_HandleTypeDef *hxspi) {
|
||||
__HAL_RCC_XSPI1_FORCE_RESET();
|
||||
__HAL_RCC_XSPI1_RELEASE_RESET();
|
||||
__HAL_RCC_XSPI1_CLK_DISABLE();
|
||||
__HAL_RCC_XSPI1_CLK_SLEEP_DISABLE();
|
||||
} else if (hxspi->Instance == XSPI2) {
|
||||
__HAL_RCC_XSPI2_FORCE_RESET();
|
||||
__HAL_RCC_XSPI2_RELEASE_RESET();
|
||||
__HAL_RCC_XSPI2_CLK_DISABLE();
|
||||
__HAL_RCC_XSPI2_CLK_SLEEP_DISABLE();
|
||||
} else if (hxspi->Instance == XSPI3) {
|
||||
__HAL_RCC_XSPI3_FORCE_RESET();
|
||||
__HAL_RCC_XSPI3_RELEASE_RESET();
|
||||
__HAL_RCC_XSPI3_CLK_DISABLE();
|
||||
__HAL_RCC_XSPI3_CLK_SLEEP_DISABLE();
|
||||
}
|
||||
|
||||
for (int i = 0; i < OMV_ARRAY_SIZE(xspi_pins); i++) {
|
||||
|
Loading…
Reference in New Issue
Block a user