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https://github.com/openmv/openmv.git
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boards/All: Update board display configuration.
This commit is contained in:
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227824aaca
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@ -6,6 +6,6 @@ set(MICROPY_PY_BLUETOOTH 0)
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set(MICROPY_BLUETOOTH_NIMBLE 0)
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set(MICROPY_PY_AUDIO 1)
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set(MICROPY_PY_MICRO_SPEECH 0)
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set(MICROPY_PY_LCD 0)
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set(MICROPY_PY_DISPLAY 0)
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set(MICROPY_PY_TV 0)
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set(MICROPY_PY_BUZZER 0)
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@ -246,9 +246,9 @@
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#define DCMI_TIM_PCLK_FREQ() HAL_RCC_GetPCLK1Freq()
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// DCMI pins
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//#define DCMI_RESET_PIN (&omv_pin_A10_GPIO)
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//#define DCMI_POWER_PIN (&omv_pin_G3_GPIO)
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//#define DCMI_FSYNC_PIN (&omv_pin_B4_GPIO)
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//#define DCMI_RESET_PIN (&omv_pin_A10_GPIO)
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//#define DCMI_POWER_PIN (&omv_pin_G3_GPIO)
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//#define DCMI_FSYNC_PIN (&omv_pin_B4_GPIO)
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#define DCMI_D0_PIN (&omv_pin_C6_DCMI)
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#define DCMI_D1_PIN (&omv_pin_C7_DCMI)
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@ -319,14 +319,14 @@
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#define SPI5_DMA_RX_CHANNEL (DMA2_Stream3)
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// SPI LCD Interface
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#define OMV_SPI_LCD_SPI_BUS (SPI4_ID)
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#define OMV_SPI_LCD_MOSI_PIN (&omv_pin_E14_SPI4)
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#define OMV_SPI_LCD_MISO_PIN (&omv_pin_E13_SPI4)
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#define OMV_SPI_LCD_SCLK_PIN (&omv_pin_E12_SPI4)
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#define OMV_SPI_LCD_SSEL_PIN (&omv_pin_E11_GPIO)
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#define OMV_SPI_DISPLAY_CONTROLLER (SPI4_ID)
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#define OMV_SPI_DISPLAY_MOSI_PIN (&omv_pin_E14_SPI4)
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#define OMV_SPI_DISPLAY_MISO_PIN (&omv_pin_E13_SPI4)
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#define OMV_SPI_DISPLAY_SCLK_PIN (&omv_pin_E12_SPI4)
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#define OMV_SPI_DISPLAY_SSEL_PIN (&omv_pin_E11_GPIO)
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#define OMV_SPI_LCD_RS_PIN (&omv_pin_G12_GPIO)
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#define OMV_SPI_LCD_RST_PIN (&omv_pin_G1_GPIO)
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#define OMV_SPI_DISPLAY_RS_PIN (&omv_pin_G12_GPIO)
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#define OMV_SPI_DISPLAY_RST_PIN (&omv_pin_G1_GPIO)
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// FIR Lepton
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#define OMV_FIR_LEPTON_I2C_BUS (FIR_I2C_ID)
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@ -28,6 +28,6 @@ MICROPY_PY_BLUETOOTH = 1
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MICROPY_BLUETOOTH_NIMBLE = 1
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MICROPY_PY_AUDIO = 1
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MICROPY_PY_MICRO_SPEECH = 1
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MICROPY_PY_LCD = 0
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MICROPY_PY_DISPLAY = 0
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MICROPY_PY_TV = 0
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MICROPY_PY_BUZZER = 0
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@ -12,376 +12,375 @@
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#define __OMV_BOARDCONFIG_H__
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// Architecture info
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#define OMV_ARCH_STR "PORTENTA H7 8192 SDRAM" // 33 chars max
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#define OMV_BOARD_TYPE "H7"
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#define OMV_UNIQUE_ID_ADDR 0x1FF1E800 // Unique ID address.
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#define OMV_UNIQUE_ID_SIZE 3 // Unique ID size in words.
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#define OMV_UNIQUE_ID_OFFSET 4 // Bytes offset for multi-word UIDs.
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#define OMV_ARCH_STR "PORTENTA H7 8192 SDRAM" // 33 chars max
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#define OMV_BOARD_TYPE "H7"
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#define OMV_UNIQUE_ID_ADDR 0x1FF1E800 // Unique ID address.
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#define OMV_UNIQUE_ID_SIZE 3 // Unique ID size in words.
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#define OMV_UNIQUE_ID_OFFSET 4 // Bytes offset for multi-word UIDs.
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#define OMV_XCLK_MCO (0U)
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#define OMV_XCLK_TIM (1U)
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#define OMV_XCLK_OSC (2U)
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#define OMV_XCLK_MCO (0U)
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#define OMV_XCLK_TIM (1U)
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#define OMV_XCLK_OSC (2U)
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// Sensor external clock source.
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#define OMV_XCLK_SOURCE (OMV_XCLK_TIM)
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#define OMV_XCLK_SOURCE (OMV_XCLK_TIM)
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// Sensor external clock timer frequency.
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#define OMV_XCLK_FREQUENCY (12000000)
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#define OMV_XCLK_FREQUENCY (12000000)
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// Enable hardware JPEG
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#define OMV_HARDWARE_JPEG (1)
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#define OMV_HARDWARE_JPEG (1)
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// Enable MDMA sensor offload.
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#define OMV_ENABLE_SENSOR_MDMA (1)
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#define OMV_ENABLE_SENSOR_MDMA (1)
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// Enable additional GPIO banks.
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#define OMV_ENABLE_GPIO_BANK_F (1)
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#define OMV_ENABLE_GPIO_BANK_G (1)
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#define OMV_ENABLE_GPIO_BANK_H (1)
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#define OMV_ENABLE_GPIO_BANK_I (1)
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#define OMV_ENABLE_GPIO_BANK_J (1)
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#define OMV_ENABLE_GPIO_BANK_K (1)
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#define OMV_ENABLE_GPIO_BANK_F (1)
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#define OMV_ENABLE_GPIO_BANK_G (1)
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#define OMV_ENABLE_GPIO_BANK_H (1)
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#define OMV_ENABLE_GPIO_BANK_I (1)
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#define OMV_ENABLE_GPIO_BANK_J (1)
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#define OMV_ENABLE_GPIO_BANK_K (1)
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// Enable sensor drivers
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#define OMV_ENABLE_OV2640 (0)
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#define OMV_ENABLE_OV5640 (1)
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#define OMV_ENABLE_OV7690 (0)
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#define OMV_ENABLE_OV7725 (1)
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#define OMV_ENABLE_OV9650 (0)
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#define OMV_ENABLE_MT9M114 (0)
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#define OMV_ENABLE_MT9V0XX (1)
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#define OMV_ENABLE_LEPTON (0)
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#define OMV_ENABLE_HM01B0 (1)
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#define OMV_ENABLE_HM0360 (1)
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#define OMV_ENABLE_GC2145 (0)
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#define OMV_ENABLE_OV2640 (0)
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#define OMV_ENABLE_OV5640 (1)
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#define OMV_ENABLE_OV7690 (0)
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#define OMV_ENABLE_OV7725 (1)
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#define OMV_ENABLE_OV9650 (0)
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#define OMV_ENABLE_MT9M114 (0)
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#define OMV_ENABLE_MT9V0XX (1)
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#define OMV_ENABLE_LEPTON (0)
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#define OMV_ENABLE_HM01B0 (1)
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#define OMV_ENABLE_HM0360 (1)
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#define OMV_ENABLE_GC2145 (0)
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// OV7725 sensor settings
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#define OMV_OV7725_PLL_CONFIG (0x41) // x4
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#define OMV_OV7725_BANDING (0x7F)
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#define OMV_OV7725_PLL_CONFIG (0x41) // x4
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#define OMV_OV7725_BANDING (0x7F)
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// MT9V0XX sensor settings
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#define MT9V0XX_XCLK_FREQ (25000000)
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#define MT9V0XX_XCLK_FREQ (25000000)
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// OV5640 sensor settings
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#define OMV_ENABLE_OV5640_AF (1)
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#define OMV_OV5640_XCLK_FREQ (12500000)
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#define OMV_OV5640_PLL_CTRL2 (0x7E)
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#define OMV_OV5640_PLL_CTRL3 (0x13)
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#define OMV_OV5640_REV_Y_CHECK (0)
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#define OMV_OV5640_REV_Y_FREQ (12500000)
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#define OMV_OV5640_REV_Y_CTRL2 (0x7E)
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#define OMV_OV5640_REV_Y_CTRL3 (0x13)
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#define OMV_ENABLE_OV5640_AF (1)
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#define OMV_OV5640_XCLK_FREQ (12500000)
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#define OMV_OV5640_PLL_CTRL2 (0x7E)
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#define OMV_OV5640_PLL_CTRL3 (0x13)
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#define OMV_OV5640_REV_Y_CHECK (0)
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#define OMV_OV5640_REV_Y_FREQ (12500000)
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#define OMV_OV5640_REV_Y_CTRL2 (0x7E)
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#define OMV_OV5640_REV_Y_CTRL3 (0x13)
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// FIR Module
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#define OMV_ENABLE_FIR_MLX90621 (1)
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#define OMV_ENABLE_FIR_MLX90640 (1)
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#define OMV_ENABLE_FIR_MLX90641 (1)
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#define OMV_ENABLE_FIR_AMG8833 (1)
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#define OMV_ENABLE_FIR_LEPTON (1)
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#define OMV_ENABLE_FIR_MLX90621 (1)
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#define OMV_ENABLE_FIR_MLX90640 (1)
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#define OMV_ENABLE_FIR_MLX90641 (1)
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#define OMV_ENABLE_FIR_AMG8833 (1)
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#define OMV_ENABLE_FIR_LEPTON (1)
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// Enable WiFi debug
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#define OMV_ENABLE_WIFIDBG (0)
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#define OMV_ENABLE_WIFIDBG (0)
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// Enable self-tests on first boot
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#define OMV_ENABLE_SELFTEST (0)
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#define OMV_ENABLE_SELFTEST (0)
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// If buffer size is bigger than this threshold, the quality is reduced.
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// This is only used for JPEG images sent to the IDE not normal compression.
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#define JPEG_QUALITY_THRESH (320 * 240 * 2)
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#define JPEG_QUALITY_THRESH (320 * 240 * 2)
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// Low and high JPEG QS.
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#define JPEG_QUALITY_LOW 50
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#define JPEG_QUALITY_HIGH 90
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#define JPEG_QUALITY_LOW 50
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#define JPEG_QUALITY_HIGH 90
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// FB Heap Block Size
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#define OMV_UMM_BLOCK_SIZE 256
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#define OMV_UMM_BLOCK_SIZE 256
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// Core VBAT for selftests
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#define OMV_CORE_VBAT "3.0"
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#define OMV_CORE_VBAT "3.0"
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// USB IRQn.
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#define OMV_USB_IRQN (OTG_HS_IRQn)
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#define OMV_USB_ULPI (1)
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#define OMV_USB_ULPI_STP_PIN (&omv_pin_C0_OTG_HS)
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#define OMV_USB_ULPI_DIR_PIN (&omv_pin_I11_OTG_HS)
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#define OMV_USB_IRQN (OTG_HS_IRQn)
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#define OMV_USB_ULPI (1)
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#define OMV_USB_ULPI_STP_PIN (&omv_pin_C0_OTG_HS)
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#define OMV_USB_ULPI_DIR_PIN (&omv_pin_I11_OTG_HS)
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// Defined for cpu frequency scaling to override the revid.
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#define OMV_MAX_CPU_FREQ (400)
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#define OMV_MAX_CPU_FREQ (400)
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// PLL1 400MHz/40MHz for SDMMC and FDCAN
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// USB and RNG are clocked from the HSI48
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#define OMV_OSC_PLL1M (5)
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#define OMV_OSC_PLL1N (160)
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#define OMV_OSC_PLL1P (2)
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#define OMV_OSC_PLL1Q (16)
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#define OMV_OSC_PLL1R (2)
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#define OMV_OSC_PLL1VCI (RCC_PLL1VCIRANGE_2)
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#define OMV_OSC_PLL1VCO (RCC_PLL1VCOWIDE)
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#define OMV_OSC_PLL1FRAC (0)
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#define OMV_OSC_PLL1M (5)
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#define OMV_OSC_PLL1N (160)
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#define OMV_OSC_PLL1P (2)
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#define OMV_OSC_PLL1Q (16)
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#define OMV_OSC_PLL1R (2)
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#define OMV_OSC_PLL1VCI (RCC_PLL1VCIRANGE_2)
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#define OMV_OSC_PLL1VCO (RCC_PLL1VCOWIDE)
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#define OMV_OSC_PLL1FRAC (0)
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// PLL2 200MHz for FMC and QSPI.
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#define OMV_OSC_PLL2M (5)
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#define OMV_OSC_PLL2N (80)
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#define OMV_OSC_PLL2P (2)
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#define OMV_OSC_PLL2Q (2)
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#define OMV_OSC_PLL2R (2)
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#define OMV_OSC_PLL2VCI (RCC_PLL2VCIRANGE_2)
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#define OMV_OSC_PLL2VCO (RCC_PLL2VCOWIDE)
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#define OMV_OSC_PLL2FRAC (0)
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#define OMV_OSC_PLL2M (5)
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#define OMV_OSC_PLL2N (80)
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#define OMV_OSC_PLL2P (2)
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#define OMV_OSC_PLL2Q (2)
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#define OMV_OSC_PLL2R (2)
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#define OMV_OSC_PLL2VCI (RCC_PLL2VCIRANGE_2)
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#define OMV_OSC_PLL2VCO (RCC_PLL2VCOWIDE)
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#define OMV_OSC_PLL2FRAC (0)
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// PLL3 160MHz for ADC and SPI123
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#define OMV_OSC_PLL3M (5)
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#define OMV_OSC_PLL3N (160)
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#define OMV_OSC_PLL3P (2)
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#define OMV_OSC_PLL3Q (5)
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#define OMV_OSC_PLL3R (2)
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#define OMV_OSC_PLL3VCI (RCC_PLL3VCIRANGE_2)
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#define OMV_OSC_PLL3VCO (RCC_PLL3VCOWIDE)
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#define OMV_OSC_PLL3FRAC (0)
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#define OMV_OSC_PLL3M (5)
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#define OMV_OSC_PLL3N (160)
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#define OMV_OSC_PLL3P (2)
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#define OMV_OSC_PLL3Q (5)
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#define OMV_OSC_PLL3R (2)
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#define OMV_OSC_PLL3VCI (RCC_PLL3VCIRANGE_2)
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#define OMV_OSC_PLL3VCO (RCC_PLL3VCOWIDE)
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#define OMV_OSC_PLL3FRAC (0)
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// Clock Sources
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#define OMV_OSC_PLL_CLKSOURCE RCC_PLLSOURCE_HSE
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#define OMV_OSC_USB_CLKSOURCE RCC_USBCLKSOURCE_HSI48
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#define OMV_OSC_RNG_CLKSOURCE RCC_RNGCLKSOURCE_HSI48
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#define OMV_OSC_ADC_CLKSOURCE RCC_ADCCLKSOURCE_PLL3
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#define OMV_OSC_SPI123_CLKSOURCE RCC_SPI123CLKSOURCE_PLL3
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#define OMV_OSC_PLL_CLKSOURCE RCC_PLLSOURCE_HSE
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#define OMV_OSC_USB_CLKSOURCE RCC_USBCLKSOURCE_HSI48
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#define OMV_OSC_RNG_CLKSOURCE RCC_RNGCLKSOURCE_HSI48
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#define OMV_OSC_ADC_CLKSOURCE RCC_ADCCLKSOURCE_PLL3
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#define OMV_OSC_SPI123_CLKSOURCE RCC_SPI123CLKSOURCE_PLL3
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// HSE/HSI/CSI State
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#define OMV_OSC_HSE_STATE (RCC_HSE_BYPASS)
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#define OMV_OSC_HSI48_STATE (RCC_HSI48_ON)
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#define OMV_OSC_HSE_STATE (RCC_HSE_BYPASS)
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#define OMV_OSC_HSI48_STATE (RCC_HSI48_ON)
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// Flash Latency
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#define OMV_FLASH_LATENCY (FLASH_LATENCY_2)
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#define OMV_FLASH_LATENCY (FLASH_LATENCY_2)
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// Power supply configuration
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#define OMV_PWR_SUPPLY (PWR_SMPS_1V8_SUPPLIES_LDO)
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#define OMV_PWR_SUPPLY (PWR_SMPS_1V8_SUPPLIES_LDO)
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// Linker script constants (see the linker script template stm32fxxx.ld.S).
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// Note: fb_alloc is a stack-based, dynamically allocated memory on FB.
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// The maximum available fb_alloc memory = FB_ALLOC_SIZE + FB_SIZE - (w*h*bpp).
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#define OMV_MAIN_MEMORY SRAM1 // data, bss and heap
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#define OMV_STACK_MEMORY DTCM // stack memory
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#define OMV_DMA_MEMORY SRAM3 // DMA buffers memory.
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#define OMV_FB_MEMORY DRAM // Framebuffer, fb_alloc
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#define OMV_JPEG_MEMORY DRAM // JPEG buffer memory buffer.
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#define OMV_JPEG_MEMORY_OFFSET (7M) // JPEG buffer is placed after FB/fballoc memory.
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#define OMV_VOSPI_MEMORY SRAM4 // VoSPI buffer memory.
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#define OMV_FB_OVERLAY_MEMORY AXI_SRAM // Fast fb_alloc memory.
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#define OMV_MAIN_MEMORY SRAM1 // data, bss and heap
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#define OMV_STACK_MEMORY DTCM // stack memory
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#define OMV_DMA_MEMORY SRAM3 // DMA buffers memory.
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#define OMV_FB_MEMORY DRAM // Framebuffer, fb_alloc
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#define OMV_JPEG_MEMORY DRAM // JPEG buffer memory buffer.
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#define OMV_JPEG_MEMORY_OFFSET (7M) // JPEG buffer is placed after FB/fballoc memory.
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#define OMV_VOSPI_MEMORY SRAM4 // VoSPI buffer memory.
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#define OMV_FB_OVERLAY_MEMORY AXI_SRAM // Fast fb_alloc memory.
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#define OMV_FB_SIZE (4M) // FB memory: header + VGA/GS image
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#define OMV_FB_ALLOC_SIZE (3M) // minimum fb alloc size
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#define OMV_FB_OVERLAY_SIZE (480 * 1024) // Fast fb_alloc memory size.
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#define OMV_STACK_SIZE (64K)
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#define OMV_HEAP_SIZE (160K)
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#define OMV_SDRAM_SIZE (8 * 1024 * 1024) // This needs to be here for UVC firmware.
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#define OMV_FB_SIZE (4M) // FB memory: header + VGA/GS image
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#define OMV_FB_ALLOC_SIZE (3M) // minimum fb alloc size
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#define OMV_FB_OVERLAY_SIZE (480 * 1024) // Fast fb_alloc memory size.
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#define OMV_STACK_SIZE (64K)
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#define OMV_HEAP_SIZE (160K)
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#define OMV_SDRAM_SIZE (8 * 1024 * 1024) // This needs to be here for UVC firmware.
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#define OMV_LINE_BUF_SIZE (11 * 1024) // Image line buffer round(2592 * 2BPP * 2 buffers).
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#define OMV_MSC_BUF_SIZE (2K) // USB MSC bot data
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#define OMV_VFS_BUF_SIZE (1K) // VFS struct + FATFS file buffer (624 bytes)
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#define OMV_JPEG_BUF_SIZE (1024 * 1024) // IDE JPEG buffer (header + data).
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#define OMV_LINE_BUF_SIZE (11 * 1024) // Image line buffer round(2592 * 2BPP * 2 buffers).
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#define OMV_MSC_BUF_SIZE (2K) // USB MSC bot data
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#define OMV_VFS_BUF_SIZE (1K) // VFS struct + FATFS file buffer (624 bytes)
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#define OMV_JPEG_BUF_SIZE (1024 * 1024) // IDE JPEG buffer (header + data).
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// Memory map.
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#define OMV_FLASH_ORIGIN 0x08000000
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#define OMV_FLASH_LENGTH 2048K
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#define OMV_DTCM_ORIGIN 0x20000000 // Note accessible by CPU and MDMA only.
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#define OMV_DTCM_LENGTH 128K
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#define OMV_SRAM1_ORIGIN 0x30000000
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#define OMV_SRAM1_LENGTH 256K // SRAM1 + SRAM2
|
||||
#define OMV_SRAM3_ORIGIN 0x30040000 // Second half of SRAM3 reserved for M4.
|
||||
#define OMV_SRAM3_LENGTH 16K
|
||||
#define OMV_SRAM4_ORIGIN 0x38000000
|
||||
#define OMV_SRAM4_LENGTH 64K
|
||||
#define OMV_AXI_SRAM_ORIGIN 0x24000000
|
||||
#define OMV_AXI_SRAM_LENGTH 512K
|
||||
#define OMV_DRAM_ORIGIN 0xC0000000
|
||||
#define OMV_DRAM_LENGTH 8M
|
||||
#define OMV_CM4_RAM_ORIGIN 0x30044000 // Cortex-M4 memory.
|
||||
#define OMV_CM4_RAM_LENGTH 16K
|
||||
#define OMV_CM4_FLASH_ORIGIN 0x08020000
|
||||
#define OMV_CM4_FLASH_LENGTH 128K
|
||||
#define OMV_FLASH_ORIGIN 0x08000000
|
||||
#define OMV_FLASH_LENGTH 2048K
|
||||
#define OMV_DTCM_ORIGIN 0x20000000 // Note accessible by CPU and MDMA only.
|
||||
#define OMV_DTCM_LENGTH 128K
|
||||
#define OMV_SRAM1_ORIGIN 0x30000000
|
||||
#define OMV_SRAM1_LENGTH 256K // SRAM1 + SRAM2
|
||||
#define OMV_SRAM3_ORIGIN 0x30040000 // Second half of SRAM3 reserved for M4.
|
||||
#define OMV_SRAM3_LENGTH 16K
|
||||
#define OMV_SRAM4_ORIGIN 0x38000000
|
||||
#define OMV_SRAM4_LENGTH 64K
|
||||
#define OMV_AXI_SRAM_ORIGIN 0x24000000
|
||||
#define OMV_AXI_SRAM_LENGTH 512K
|
||||
#define OMV_DRAM_ORIGIN 0xC0000000
|
||||
#define OMV_DRAM_LENGTH 8M
|
||||
#define OMV_CM4_RAM_ORIGIN 0x30044000 // Cortex-M4 memory.
|
||||
#define OMV_CM4_RAM_LENGTH 16K
|
||||
#define OMV_CM4_FLASH_ORIGIN 0x08020000
|
||||
#define OMV_CM4_FLASH_LENGTH 128K
|
||||
|
||||
// Flash configuration.
|
||||
#define OMV_FLASH_FFS_ORIGIN 0x08020000
|
||||
#define OMV_FLASH_FFS_LENGTH 128K
|
||||
#define OMV_FLASH_TXT_ORIGIN 0x08040000
|
||||
#define OMV_FLASH_TXT_LENGTH 1792K
|
||||
#define OMV_FLASH_EXT_ORIGIN 0x90000000
|
||||
#define OMV_FLASH_EXT_LENGTH 16M
|
||||
#define OMV_FLASH_FFS_ORIGIN 0x08020000
|
||||
#define OMV_FLASH_FFS_LENGTH 128K
|
||||
#define OMV_FLASH_TXT_ORIGIN 0x08040000
|
||||
#define OMV_FLASH_TXT_LENGTH 1792K
|
||||
#define OMV_FLASH_EXT_ORIGIN 0x90000000
|
||||
#define OMV_FLASH_EXT_LENGTH 16M
|
||||
|
||||
// Domain 1 DMA buffers region.
|
||||
#define OMV_DMA_MEMORY_D1 AXI_SRAM
|
||||
#define OMV_DMA_MEMORY_D1_SIZE (16 * 1024) // Reserved memory for DMA buffers
|
||||
#define OMV_DMA_REGION_D1_BASE (OMV_AXI_SRAM_ORIGIN + OMV_FB_OVERLAY_SIZE)
|
||||
#define OMV_DMA_REGION_D1_SIZE MPU_REGION_SIZE_32KB
|
||||
#define OMV_DMA_MEMORY_D1 AXI_SRAM
|
||||
#define OMV_DMA_MEMORY_D1_SIZE (16 * 1024) // Reserved memory for DMA buffers
|
||||
#define OMV_DMA_REGION_D1_BASE (OMV_AXI_SRAM_ORIGIN + OMV_FB_OVERLAY_SIZE)
|
||||
#define OMV_DMA_REGION_D1_SIZE MPU_REGION_SIZE_32KB
|
||||
|
||||
// Domain 2 DMA buffers region.
|
||||
#define OMV_DMA_MEMORY_D2 SRAM3
|
||||
#define OMV_DMA_MEMORY_D2_SIZE (1 * 1024) // Reserved memory for DMA buffers
|
||||
#define OMV_DMA_REGION_D2_BASE (OMV_SRAM3_ORIGIN + (0 * 1024))
|
||||
#define OMV_DMA_REGION_D2_SIZE MPU_REGION_SIZE_16KB
|
||||
#define OMV_DMA_MEMORY_D2 SRAM3
|
||||
#define OMV_DMA_MEMORY_D2_SIZE (1 * 1024) // Reserved memory for DMA buffers
|
||||
#define OMV_DMA_REGION_D2_BASE (OMV_SRAM3_ORIGIN + (0 * 1024))
|
||||
#define OMV_DMA_REGION_D2_SIZE MPU_REGION_SIZE_16KB
|
||||
|
||||
// Domain 3 DMA buffers region.
|
||||
#define OMV_DMA_MEMORY_D3 SRAM4
|
||||
#define OMV_DMA_MEMORY_D3_SIZE (32 * 1024) // Reserved memory for DMA buffers
|
||||
#define OMV_DMA_REGION_D3_BASE (OMV_SRAM4_ORIGIN + (0 * 1024))
|
||||
#define OMV_DMA_REGION_D3_SIZE MPU_REGION_SIZE_64KB
|
||||
#define OMV_DMA_MEMORY_D3 SRAM4
|
||||
#define OMV_DMA_MEMORY_D3_SIZE (32 * 1024) // Reserved memory for DMA buffers
|
||||
#define OMV_DMA_REGION_D3_BASE (OMV_SRAM4_ORIGIN + (0 * 1024))
|
||||
#define OMV_DMA_REGION_D3_SIZE MPU_REGION_SIZE_64KB
|
||||
|
||||
// AXI QoS - Low-High (0:15) - default 0
|
||||
#define OMV_AXI_QOS_MDMA_R_PRI 14 // Max pri to move data.
|
||||
#define OMV_AXI_QOS_MDMA_W_PRI 15 // Max pri to move data.
|
||||
#define OMV_AXI_QOS_LTDC_R_PRI 15 // Max pri to read out the frame buffer.
|
||||
#define OMV_AXI_QOS_MDMA_R_PRI 14 // Max pri to move data.
|
||||
#define OMV_AXI_QOS_MDMA_W_PRI 15 // Max pri to move data.
|
||||
#define OMV_AXI_QOS_LTDC_R_PRI 15 // Max pri to read out the frame buffer.
|
||||
|
||||
// Image sensor I2C
|
||||
#define ISC_I2C_ID (3)
|
||||
#define ISC_I2C_SPEED (OMV_I2C_SPEED_STANDARD)
|
||||
#define ISC_I2C_ID (3)
|
||||
#define ISC_I2C_SPEED (OMV_I2C_SPEED_STANDARD)
|
||||
|
||||
// Alternate I2C bus for the Portenta breakout
|
||||
#define ISC_I2C_ALT_ID (4)
|
||||
#define ISC_I2C_ALT_SPEED (OMV_I2C_SPEED_STANDARD)
|
||||
#define ISC_I2C_ALT_ID (4)
|
||||
#define ISC_I2C_ALT_SPEED (OMV_I2C_SPEED_STANDARD)
|
||||
|
||||
// Thermal image sensor I2C bus
|
||||
#define FIR_I2C_ID (3)
|
||||
#define FIR_I2C_SPEED (OMV_I2C_SPEED_STANDARD)
|
||||
#define FIR_I2C_ID (3)
|
||||
#define FIR_I2C_SPEED (OMV_I2C_SPEED_STANDARD)
|
||||
|
||||
// Soft I2C bus
|
||||
//#define SOFT_I2C_SIOC_PIN (&omv_pin_PH7_GPIO)
|
||||
//#define SOFT_I2C_SIOD_PIN (&omv_pin_PH8_GPIO)
|
||||
//#define SOFT_I2C_SPIN_DELAY 64
|
||||
//#define SOFT_I2C_SIOC_PIN (&omv_pin_PH7_GPIO)
|
||||
//#define SOFT_I2C_SIOD_PIN (&omv_pin_PH8_GPIO)
|
||||
//#define SOFT_I2C_SPIN_DELAY 64
|
||||
|
||||
// GPIO.0 is connected to the sensor module reset pin on the Portenta
|
||||
// breakout board and to the LDO's LDO_ENABLE pin on the Himax shield.
|
||||
// The sensor probing process will detect the right reset or powerdown
|
||||
// polarity, so it should be fine to enable it for both boards.
|
||||
#define DCMI_RESET_PIN (&omv_pin_C13_GPIO)
|
||||
#define DCMI_RESET_PIN (&omv_pin_C13_GPIO)
|
||||
|
||||
// GPIO.1 is connected to the sensor module frame sync pin (OUTPUT) on
|
||||
// the Portenta breakout board and to the INT pin (OUTPUT) on the Himax
|
||||
// shield, so it can't be enabled for the two boards at the same time.
|
||||
//#define DCMI_FSYNC_PIN (&omv_pin_C15_GPIO)
|
||||
//#define DCMI_FSYNC_PIN (&omv_pin_C15_GPIO)
|
||||
|
||||
// GPIO.3 is connected to the powerdown pin on the Portenta breakout board,
|
||||
// and to the STROBE pin on the Himax shield, however it's not actually
|
||||
// used on the Himax shield and can be safely enable for the two boards.
|
||||
#define DCMI_POWER_PIN (&omv_pin_D5_GPIO)
|
||||
#define DCMI_POWER_PIN (&omv_pin_D5_GPIO)
|
||||
|
||||
/* DCMI */
|
||||
#define DCMI_TIM (TIM1)
|
||||
#define DCMI_TIM_PIN (&omv_pin_K1_TIM1)
|
||||
#define DCMI_TIM (TIM1)
|
||||
#define DCMI_TIM_PIN (&omv_pin_K1_TIM1)
|
||||
// Enable TIM1-CH1 on PA8 too for Portenta breakout.
|
||||
#define DCMI_TIM_EXT_PIN (&omv_pin_A8_TIM1)
|
||||
#define DCMI_TIM_CHANNEL (TIM_CHANNEL_1)
|
||||
#define DCMI_TIM_CLK_ENABLE() __TIM1_CLK_ENABLE()
|
||||
#define DCMI_TIM_CLK_DISABLE() __TIM1_CLK_DISABLE()
|
||||
#define DCMI_TIM_PCLK_FREQ() HAL_RCC_GetPCLK2Freq()
|
||||
#define DCMI_TIM_EXT_PIN (&omv_pin_A8_TIM1)
|
||||
#define DCMI_TIM_CHANNEL (TIM_CHANNEL_1)
|
||||
#define DCMI_TIM_CLK_ENABLE() __TIM1_CLK_ENABLE()
|
||||
#define DCMI_TIM_CLK_DISABLE() __TIM1_CLK_DISABLE()
|
||||
#define DCMI_TIM_PCLK_FREQ() HAL_RCC_GetPCLK2Freq()
|
||||
|
||||
#define DCMI_D0_PIN (&omv_pin_H9_DCMI)
|
||||
#define DCMI_D1_PIN (&omv_pin_H10_DCMI)
|
||||
#define DCMI_D2_PIN (&omv_pin_H11_DCMI)
|
||||
#define DCMI_D3_PIN (&omv_pin_H12_DCMI)
|
||||
#define DCMI_D4_PIN (&omv_pin_H14_DCMI)
|
||||
#define DCMI_D5_PIN (&omv_pin_I4_DCMI)
|
||||
#define DCMI_D6_PIN (&omv_pin_I6_DCMI)
|
||||
#define DCMI_D7_PIN (&omv_pin_I7_DCMI)
|
||||
#define DCMI_D0_PIN (&omv_pin_H9_DCMI)
|
||||
#define DCMI_D1_PIN (&omv_pin_H10_DCMI)
|
||||
#define DCMI_D2_PIN (&omv_pin_H11_DCMI)
|
||||
#define DCMI_D3_PIN (&omv_pin_H12_DCMI)
|
||||
#define DCMI_D4_PIN (&omv_pin_H14_DCMI)
|
||||
#define DCMI_D5_PIN (&omv_pin_I4_DCMI)
|
||||
#define DCMI_D6_PIN (&omv_pin_I6_DCMI)
|
||||
#define DCMI_D7_PIN (&omv_pin_I7_DCMI)
|
||||
|
||||
#define DCMI_HSYNC_PIN (&omv_pin_A4_DCMI)
|
||||
#define DCMI_VSYNC_PIN (&omv_pin_I5_DCMI)
|
||||
#define DCMI_PXCLK_PIN (&omv_pin_A6_DCMI)
|
||||
#define DCMI_HSYNC_PIN (&omv_pin_A4_DCMI)
|
||||
#define DCMI_VSYNC_PIN (&omv_pin_I5_DCMI)
|
||||
#define DCMI_PXCLK_PIN (&omv_pin_A6_DCMI)
|
||||
|
||||
// Physical I2C buses.
|
||||
|
||||
// I2C bus 3
|
||||
#define I2C3_ID (3)
|
||||
#define I2C3_SCL_PIN (&omv_pin_H7_I2C3)
|
||||
#define I2C3_SDA_PIN (&omv_pin_H8_I2C3)
|
||||
#define I2C3_ID (3)
|
||||
#define I2C3_SCL_PIN (&omv_pin_H7_I2C3)
|
||||
#define I2C3_SDA_PIN (&omv_pin_H8_I2C3)
|
||||
|
||||
// I2C bus 4
|
||||
#define I2C4_ID (4)
|
||||
#define I2C4_SCL_PIN (&omv_pin_H11_I2C4)
|
||||
#define I2C4_SDA_PIN (&omv_pin_H12_I2C4)
|
||||
#define I2C4_ID (4)
|
||||
#define I2C4_SCL_PIN (&omv_pin_H11_I2C4)
|
||||
#define I2C4_SDA_PIN (&omv_pin_H12_I2C4)
|
||||
|
||||
// Physical SPI buses.
|
||||
|
||||
// SPI bus 2
|
||||
#define SPI2_ID (2)
|
||||
#define SPI2_SCLK_PIN (&omv_pin_I1_SPI2)
|
||||
#define SPI2_MISO_PIN (&omv_pin_C2_SPI2)
|
||||
#define SPI2_MOSI_PIN (&omv_pin_C3_SPI2)
|
||||
#define SPI2_SSEL_PIN (&omv_pin_I0_SPI2)
|
||||
#define SPI2_DMA_TX_CHANNEL (DMA1_Stream4)
|
||||
#define SPI2_DMA_RX_CHANNEL (DMA1_Stream3)
|
||||
#define SPI2_ID (2)
|
||||
#define SPI2_SCLK_PIN (&omv_pin_I1_SPI2)
|
||||
#define SPI2_MISO_PIN (&omv_pin_C2_SPI2)
|
||||
#define SPI2_MOSI_PIN (&omv_pin_C3_SPI2)
|
||||
#define SPI2_SSEL_PIN (&omv_pin_I0_SPI2)
|
||||
#define SPI2_DMA_TX_CHANNEL (DMA1_Stream4)
|
||||
#define SPI2_DMA_RX_CHANNEL (DMA1_Stream3)
|
||||
|
||||
// SAI4
|
||||
#define AUDIO_SAI (SAI4_Block_A)
|
||||
#define AUDIO_SAI (SAI4_Block_A)
|
||||
// SCKx frequency = SAI_KER_CK / MCKDIV / 2
|
||||
#define AUDIO_SAI_MCKDIV (12)
|
||||
#define AUDIO_SAI_FREQKHZ (2048U) // 2048KHz
|
||||
#define AUDIO_MAX_CHANNELS (2) // Maximum number of channels.
|
||||
#define AUDIO_SAI_MCKDIV (12)
|
||||
#define AUDIO_SAI_FREQKHZ (2048U) // 2048KHz
|
||||
#define AUDIO_MAX_CHANNELS (2) // Maximum number of channels.
|
||||
|
||||
#define AUDIO_SAI_CK_PIN (&omv_pin_E2_SAI4)
|
||||
#define AUDIO_SAI_D1_PIN (&omv_pin_B2_SAI4)
|
||||
#define AUDIO_SAI_CK_PIN (&omv_pin_E2_SAI4)
|
||||
#define AUDIO_SAI_D1_PIN (&omv_pin_B2_SAI4)
|
||||
|
||||
#define AUDIO_SAI_DMA_STREAM BDMA_Channel1
|
||||
#define AUDIO_SAI_DMA_REQUEST BDMA_REQUEST_SAI4_A
|
||||
#define AUDIO_SAI_DMA_IRQ BDMA_Channel1_IRQn
|
||||
#define AUDIO_SAI_DMA_IRQHandler BDMA_Channel1_IRQHandler
|
||||
#define AUDIO_SAI_DMA_STREAM BDMA_Channel1
|
||||
#define AUDIO_SAI_DMA_REQUEST BDMA_REQUEST_SAI4_A
|
||||
#define AUDIO_SAI_DMA_IRQ BDMA_Channel1_IRQn
|
||||
#define AUDIO_SAI_DMA_IRQHandler BDMA_Channel1_IRQHandler
|
||||
|
||||
#define AUDIO_SAI_CLK_ENABLE() __HAL_RCC_SAI4_CLK_ENABLE()
|
||||
#define AUDIO_SAI_CLK_DISABLE() __HAL_RCC_SAI4_CLK_DISABLE()
|
||||
#define AUDIO_SAI_DMA_CLK_ENABLE() __HAL_RCC_BDMA_CLK_ENABLE()
|
||||
#define AUDIO_SAI_CLK_ENABLE() __HAL_RCC_SAI4_CLK_ENABLE()
|
||||
#define AUDIO_SAI_CLK_DISABLE() __HAL_RCC_SAI4_CLK_DISABLE()
|
||||
#define AUDIO_SAI_DMA_CLK_ENABLE() __HAL_RCC_BDMA_CLK_ENABLE()
|
||||
|
||||
// SAI1
|
||||
// Set SAI1 clock source in system ex: Sai1ClockSelection = RCC_SAI1CLKSOURCE_PLL;
|
||||
// #define AUDIO_SAI (SAI1_Block_A)
|
||||
// #define AUDIO_SAI_MCKDIV (12)
|
||||
// #define AUDIO_SAI_FREQKHZ (2048U) // 2048KHz
|
||||
// #define AUDIO_MAX_CHANNELS (2) // Maximum number of channels.
|
||||
//#define AUDIO_SAI (SAI1_Block_A)
|
||||
//#define AUDIO_SAI_MCKDIV (12)
|
||||
//#define AUDIO_SAI_FREQKHZ (2048U) // 2048KHz
|
||||
//#define AUDIO_MAX_CHANNELS (2) // Maximum number of channels.
|
||||
//
|
||||
// #define AUDIO_SAI_CK_PIN (&omv_pin_E2_SAI1)
|
||||
// #define AUDIO_SAI_D1_PIN (&omv_pin_B2_SAI1)
|
||||
//#define AUDIO_SAI_CK_PIN (&omv_pin_E2_SAI1)
|
||||
//#define AUDIO_SAI_D1_PIN (&omv_pin_B2_SAI1)
|
||||
//
|
||||
// #define AUDIO_SAI_DMA_STREAM DMA2_Stream6
|
||||
// #define AUDIO_SAI_DMA_REQUEST DMA_REQUEST_SAI1_A
|
||||
// #define AUDIO_SAI_DMA_IRQ DMA2_Stream6_IRQn
|
||||
// #define AUDIO_SAI_DMA_IRQHandler DMA2_Stream6_IRQHandler
|
||||
//#define AUDIO_SAI_DMA_STREAM DMA2_Stream6
|
||||
//#define AUDIO_SAI_DMA_REQUEST DMA_REQUEST_SAI1_A
|
||||
//#define AUDIO_SAI_DMA_IRQ DMA2_Stream6_IRQn
|
||||
//#define AUDIO_SAI_DMA_IRQHandler DMA2_Stream6_IRQHandler
|
||||
//
|
||||
// #define AUDIO_SAI_CLK_ENABLE() __HAL_RCC_SAI1_CLK_ENABLE()
|
||||
// #define AUDIO_SAI_CLK_DISABLE() __HAL_RCC_SAI1_CLK_DISABLE()
|
||||
// #define AUDIO_SAI_DMA_CLK_ENABLE() __HAL_RCC_DMA2_CLK_ENABLE()
|
||||
//#define AUDIO_SAI_CLK_ENABLE() __HAL_RCC_SAI1_CLK_ENABLE()
|
||||
//#define AUDIO_SAI_CLK_DISABLE() __HAL_RCC_SAI1_CLK_DISABLE()
|
||||
//#define AUDIO_SAI_DMA_CLK_ENABLE() __HAL_RCC_DMA2_CLK_ENABLE()
|
||||
|
||||
// LCD Interface
|
||||
#define OMV_LCD_CONTROLLER (LTDC)
|
||||
#define OMV_LCD_CLK_ENABLE() __HAL_RCC_LTDC_CLK_ENABLE()
|
||||
#define OMV_LCD_CLK_DISABLE() __HAL_RCC_LTDC_CLK_DISABLE()
|
||||
#define OMV_LCD_FORCE_RESET() __HAL_RCC_LTDC_FORCE_RESET()
|
||||
#define OMV_LCD_RELEASE_RESET() __HAL_RCC_LTDC_RELEASE_RESET()
|
||||
#define OMV_RGB_DISPLAY_CONTROLLER (LTDC)
|
||||
#define OMV_RGB_DISPLAY_CLK_ENABLE() __HAL_RCC_LTDC_CLK_ENABLE()
|
||||
#define OMV_RGB_DISPLAY_CLK_DISABLE() __HAL_RCC_LTDC_CLK_DISABLE()
|
||||
#define OMV_RGB_DISPLAY_FORCE_RESET() __HAL_RCC_LTDC_FORCE_RESET()
|
||||
#define OMV_RGB_DISPLAY_RELEASE_RESET() __HAL_RCC_LTDC_RELEASE_RESET()
|
||||
|
||||
// DSI Interface
|
||||
#define OMV_DSI_CONTROLLER (DSI)
|
||||
#define OMV_DSI_CLK_ENABLE() __HAL_RCC_DSI_CLK_ENABLE()
|
||||
#define OMV_DSI_CLK_DISABLE() __HAL_RCC_DSI_CLK_DISABLE()
|
||||
#define OMV_DSI_FORCE_RESET() __HAL_RCC_DSI_FORCE_RESET()
|
||||
#define OMV_DSI_RELEASE_RESET() __HAL_RCC_DSI_RELEASE_RESET()
|
||||
//#define OMV_DSI_DISPLAY_CONTROLLER (DSI)
|
||||
//#define OMV_DSI_DISPLAY_CLK_ENABLE() __HAL_RCC_DSI_CLK_ENABLE()
|
||||
//#define OMV_DSI_DISPLAY_CLK_DISABLE() __HAL_RCC_DSI_CLK_DISABLE()
|
||||
//#define OMV_DSI_DISPLAY_FORCE_RESET() __HAL_RCC_DSI_FORCE_RESET()
|
||||
//#define OMV_DSI_DISPLAY_RELEASE_RESET() __HAL_RCC_DSI_RELEASE_RESET()
|
||||
|
||||
// SPI LCD Interface
|
||||
#define OMV_SPI_LCD_SPI_BUS (SPI2_ID)
|
||||
#define OMV_SPI_LCD_MOSI_PIN (&omv_pin_C3_SPI2)
|
||||
#define OMV_SPI_LCD_MISO_PIN (&omv_pin_C2_SPI2)
|
||||
#define OMV_SPI_LCD_SCLK_PIN (&omv_pin_I1_SPI2)
|
||||
#define OMV_SPI_LCD_SSEL_PIN (&omv_pin_I0_GPIO)
|
||||
#define OMV_SPI_DISPLAY_CONTROLLER (SPI2_ID)
|
||||
#define OMV_SPI_DISPLAY_MOSI_PIN (&omv_pin_C3_SPI2)
|
||||
#define OMV_SPI_DISPLAY_MISO_PIN (&omv_pin_C2_SPI2)
|
||||
#define OMV_SPI_DISPLAY_SCLK_PIN (&omv_pin_I1_SPI2)
|
||||
#define OMV_SPI_DISPLAY_SSEL_PIN (&omv_pin_I0_GPIO)
|
||||
|
||||
#define OMV_SPI_LCD_RS_PIN (&omv_pin_C6_GPIO)
|
||||
#define OMV_SPI_LCD_RST_PIN (&omv_pin_C7_GPIO)
|
||||
|
||||
#define OMV_SPI_LCD_DEF_TRIPLE_BUF (1)
|
||||
#define OMV_SPI_DISPLAY_RS_PIN (&omv_pin_C6_GPIO)
|
||||
#define OMV_SPI_DISPLAY_RST_PIN (&omv_pin_C7_GPIO)
|
||||
#define OMV_SPI_DISPLAY_TRIPLE_BUFFER (1)
|
||||
|
||||
// FIR Lepton
|
||||
#define OMV_FIR_LEPTON_I2C_BUS (FIR_I2C_ID)
|
||||
#define OMV_FIR_LEPTON_I2C_BUS_SPEED (FIR_I2C_SPEED)
|
||||
#define OMV_FIR_LEPTON_I2C_BUS (FIR_I2C_ID)
|
||||
#define OMV_FIR_LEPTON_I2C_BUS_SPEED (FIR_I2C_SPEED)
|
||||
|
||||
#define OMV_FIR_LEPTON_SPI_BUS (SPI2_ID)
|
||||
#define OMV_FIR_LEPTON_MOSI_PIN (&omv_pin_C3_SPI2)
|
||||
#define OMV_FIR_LEPTON_MISO_PIN (&omv_pin_C2_SPI2)
|
||||
#define OMV_FIR_LEPTON_SCLK_PIN (&omv_pin_I1_SPI2)
|
||||
#define OMV_FIR_LEPTON_SSEL_PIN (&omv_pin_I0_GPIO)
|
||||
#define OMV_FIR_LEPTON_SPI_BUS (SPI2_ID)
|
||||
#define OMV_FIR_LEPTON_MOSI_PIN (&omv_pin_C3_SPI2)
|
||||
#define OMV_FIR_LEPTON_MISO_PIN (&omv_pin_C2_SPI2)
|
||||
#define OMV_FIR_LEPTON_SCLK_PIN (&omv_pin_I1_SPI2)
|
||||
#define OMV_FIR_LEPTON_SSEL_PIN (&omv_pin_I0_GPIO)
|
||||
|
||||
#endif //__OMV_BOARDCONFIG_H__
|
||||
|
||||
@ -27,6 +27,6 @@ MICROPY_PY_BLUETOOTH = 1
|
||||
MICROPY_BLUETOOTH_NIMBLE = 1
|
||||
MICROPY_PY_AUDIO = 1
|
||||
MICROPY_PY_MICRO_SPEECH = 1
|
||||
MICROPY_PY_LCD = 1
|
||||
MICROPY_PY_DISPLAY = 1
|
||||
MICROPY_PY_TV = 1
|
||||
MICROPY_PY_BUZZER = 0
|
||||
|
||||
@ -199,22 +199,22 @@
|
||||
#define DMA_REQUEST_SPI2_RX (DMA_CHANNEL_0)
|
||||
|
||||
// SPI LCD Interface
|
||||
#define OMV_SPI_LCD_SPI_BUS (SPI2_ID)
|
||||
#define OMV_SPI_LCD_MOSI_PIN (&omv_pin_B15_SPI2)
|
||||
#define OMV_SPI_LCD_MISO_PIN (&omv_pin_B14_SPI2)
|
||||
#define OMV_SPI_LCD_SCLK_PIN (&omv_pin_B13_SPI2)
|
||||
#define OMV_SPI_LCD_SSEL_PIN (&omv_pin_B12_GPIO)
|
||||
#define OMV_SPI_DISPLAY_CONTROLLER (SPI2_ID)
|
||||
#define OMV_SPI_DISPLAY_MOSI_PIN (&omv_pin_B15_SPI2)
|
||||
#define OMV_SPI_DISPLAY_MISO_PIN (&omv_pin_B14_SPI2)
|
||||
#define OMV_SPI_DISPLAY_SCLK_PIN (&omv_pin_B13_SPI2)
|
||||
#define OMV_SPI_DISPLAY_SSEL_PIN (&omv_pin_B12_GPIO)
|
||||
|
||||
#define OMV_SPI_LCD_RS_PIN (&omv_pin_D13_GPIO)
|
||||
#define OMV_SPI_LCD_BL_PIN (&omv_pin_A5_GPIO)
|
||||
#define OMV_SPI_LCD_RST_PIN (&omv_pin_D12_GPIO)
|
||||
#define OMV_SPI_DISPLAY_RS_PIN (&omv_pin_D13_GPIO)
|
||||
#define OMV_SPI_DISPLAY_RST_PIN (&omv_pin_D12_GPIO)
|
||||
#define OMV_SPI_DISPLAY_BL_PIN (&omv_pin_A5_GPIO)
|
||||
|
||||
#define OMV_SPI_LCD_BL_DAC (DAC)
|
||||
#define OMV_SPI_LCD_BL_DAC_CHANNEL (DAC_CHANNEL_2)
|
||||
#define OMV_SPI_LCD_BL_DAC_CLK_ENABLE() __HAL_RCC_DAC_CLK_ENABLE()
|
||||
#define OMV_SPI_LCD_BL_DAC_CLK_DISABLE() __HAL_RCC_DAC_CLK_DISABLE()
|
||||
#define OMV_SPI_LCD_BL_DAC_FORCE_RESET() __HAL_RCC_DAC_FORCE_RESET()
|
||||
#define OMV_SPI_LCD_BL_DAC_RELEASE_RESET() __HAL_RCC_DAC_RELEASE_RESET()
|
||||
#define OMV_DISPLAY_BL_DAC (DAC)
|
||||
#define OMV_DISPLAY_BL_DAC_CHANNEL (DAC_CHANNEL_2)
|
||||
#define OMV_DISPLAY_BL_DAC_CLK_ENABLE() __HAL_RCC_DAC_CLK_ENABLE()
|
||||
#define OMV_DISPLAY_BL_DAC_CLK_DISABLE() __HAL_RCC_DAC_CLK_DISABLE()
|
||||
#define OMV_DISPLAY_BL_DAC_FORCE_RESET() __HAL_RCC_DAC_FORCE_RESET()
|
||||
#define OMV_DISPLAY_BL_DAC_RELEASE_RESET() __HAL_RCC_DAC_RELEASE_RESET()
|
||||
|
||||
// FIR Lepton
|
||||
#define OMV_FIR_LEPTON_I2C_BUS (FIR_I2C_ID)
|
||||
|
||||
@ -15,6 +15,6 @@ OMV_ENABLE_BL=1
|
||||
OMV_ENABLE_UVC=1
|
||||
MICROPY_PY_SENSOR = 1
|
||||
MICROPY_PY_WINC1500 = 1
|
||||
MICROPY_PY_LCD = 1
|
||||
MICROPY_PY_DISPLAY = 1
|
||||
MICROPY_PY_TV = 1
|
||||
MICROPY_PY_BUZZER = 0
|
||||
|
||||
@ -199,22 +199,22 @@
|
||||
#define DMA_REQUEST_SPI2_RX (DMA_CHANNEL_0)
|
||||
|
||||
// SPI LCD Interface
|
||||
#define OMV_SPI_LCD_SPI_BUS (SPI2_ID)
|
||||
#define OMV_SPI_LCD_MOSI_PIN (&omv_pin_B15_SPI2)
|
||||
#define OMV_SPI_LCD_MISO_PIN (&omv_pin_B14_SPI2)
|
||||
#define OMV_SPI_LCD_SCLK_PIN (&omv_pin_B13_SPI2)
|
||||
#define OMV_SPI_LCD_SSEL_PIN (&omv_pin_B12_GPIO)
|
||||
#define OMV_SPI_DISPLAY_CONTROLLER (SPI2_ID)
|
||||
#define OMV_SPI_DISPLAY_MOSI_PIN (&omv_pin_B15_SPI2)
|
||||
#define OMV_SPI_DISPLAY_MISO_PIN (&omv_pin_B14_SPI2)
|
||||
#define OMV_SPI_DISPLAY_SCLK_PIN (&omv_pin_B13_SPI2)
|
||||
#define OMV_SPI_DISPLAY_SSEL_PIN (&omv_pin_B12_GPIO)
|
||||
|
||||
#define OMV_SPI_LCD_RS_PIN (&omv_pin_D13_GPIO)
|
||||
#define OMV_SPI_LCD_BL_PIN (&omv_pin_A5_GPIO)
|
||||
#define OMV_SPI_LCD_RST_PIN (&omv_pin_D12_GPIO)
|
||||
#define OMV_SPI_DISPLAY_RS_PIN (&omv_pin_D13_GPIO)
|
||||
#define OMV_SPI_DISPLAY_RST_PIN (&omv_pin_D12_GPIO)
|
||||
#define OMV_SPI_DISPLAY_BL_PIN (&omv_pin_A5_GPIO)
|
||||
|
||||
#define OMV_SPI_LCD_BL_DAC (DAC)
|
||||
#define OMV_SPI_LCD_BL_DAC_CHANNEL (DAC_CHANNEL_2)
|
||||
#define OMV_SPI_LCD_BL_DAC_CLK_ENABLE() __HAL_RCC_DAC_CLK_ENABLE()
|
||||
#define OMV_SPI_LCD_BL_DAC_CLK_DISABLE() __HAL_RCC_DAC_CLK_DISABLE()
|
||||
#define OMV_SPI_LCD_BL_DAC_FORCE_RESET() __HAL_RCC_DAC_FORCE_RESET()
|
||||
#define OMV_SPI_LCD_BL_DAC_RELEASE_RESET() __HAL_RCC_DAC_RELEASE_RESET()
|
||||
#define OMV_DISPLAY_BL_DAC (DAC)
|
||||
#define OMV_DISPLAY_BL_DAC_CHANNEL (DAC_CHANNEL_2)
|
||||
#define OMV_DISPLAY_BL_DAC_CLK_ENABLE() __HAL_RCC_DAC_CLK_ENABLE()
|
||||
#define OMV_DISPLAY_BL_DAC_CLK_DISABLE() __HAL_RCC_DAC_CLK_DISABLE()
|
||||
#define OMV_DISPLAY_BL_DAC_FORCE_RESET() __HAL_RCC_DAC_FORCE_RESET()
|
||||
#define OMV_DISPLAY_BL_DAC_RELEASE_RESET() __HAL_RCC_DAC_RELEASE_RESET()
|
||||
|
||||
// FIR Lepton
|
||||
#define OMV_FIR_LEPTON_I2C_BUS (FIR_I2C_ID)
|
||||
|
||||
@ -16,6 +16,6 @@ OMV_ENABLE_UVC=1
|
||||
MICROPY_PY_SENSOR = 1
|
||||
MICROPY_PY_ULAB = 1
|
||||
MICROPY_PY_WINC1500 = 1
|
||||
MICROPY_PY_LCD = 1
|
||||
MICROPY_PY_DISPLAY = 1
|
||||
MICROPY_PY_TV = 1
|
||||
MICROPY_PY_BUZZER = 0
|
||||
|
||||
@ -297,22 +297,22 @@
|
||||
#define SPI3_DMA_RX_CHANNEL (DMA1_Stream2)
|
||||
|
||||
// SPI LCD Interface
|
||||
#define OMV_SPI_LCD_SPI_BUS (SPI2_ID)
|
||||
#define OMV_SPI_LCD_MOSI_PIN (&omv_pin_B15_SPI2)
|
||||
#define OMV_SPI_LCD_MISO_PIN (&omv_pin_B14_SPI2)
|
||||
#define OMV_SPI_LCD_SCLK_PIN (&omv_pin_B13_SPI2)
|
||||
#define OMV_SPI_LCD_SSEL_PIN (&omv_pin_B12_GPIO)
|
||||
#define OMV_SPI_DISPLAY_CONTROLLER (SPI2_ID)
|
||||
#define OMV_SPI_DISPLAY_MOSI_PIN (&omv_pin_B15_SPI2)
|
||||
#define OMV_SPI_DISPLAY_MISO_PIN (&omv_pin_B14_SPI2)
|
||||
#define OMV_SPI_DISPLAY_SCLK_PIN (&omv_pin_B13_SPI2)
|
||||
#define OMV_SPI_DISPLAY_SSEL_PIN (&omv_pin_B12_GPIO)
|
||||
|
||||
#define OMV_SPI_LCD_RS_PIN (&omv_pin_D13_GPIO)
|
||||
#define OMV_SPI_LCD_BL_PIN (&omv_pin_A5_GPIO)
|
||||
#define OMV_SPI_LCD_RST_PIN (&omv_pin_D12_GPIO)
|
||||
#define OMV_SPI_DISPLAY_RS_PIN (&omv_pin_D13_GPIO)
|
||||
#define OMV_SPI_DISPLAY_RST_PIN (&omv_pin_D12_GPIO)
|
||||
#define OMV_SPI_DISPLAY_BL_PIN (&omv_pin_A5_GPIO)
|
||||
|
||||
#define OMV_SPI_LCD_BL_DAC (DAC1)
|
||||
#define OMV_SPI_LCD_BL_DAC_CHANNEL (DAC_CHANNEL_2)
|
||||
#define OMV_SPI_LCD_BL_DAC_CLK_ENABLE() __HAL_RCC_DAC12_CLK_ENABLE()
|
||||
#define OMV_SPI_LCD_BL_DAC_CLK_DISABLE() __HAL_RCC_DAC12_CLK_DISABLE()
|
||||
#define OMV_SPI_LCD_BL_DAC_FORCE_RESET() __HAL_RCC_DAC12_FORCE_RESET()
|
||||
#define OMV_SPI_LCD_BL_DAC_RELEASE_RESET() __HAL_RCC_DAC12_RELEASE_RESET()
|
||||
#define OMV_DISPLAY_BL_DAC (DAC1)
|
||||
#define OMV_DISPLAY_BL_DAC_CHANNEL (DAC_CHANNEL_2)
|
||||
#define OMV_DISPLAY_BL_DAC_CLK_ENABLE() __HAL_RCC_DAC12_CLK_ENABLE()
|
||||
#define OMV_DISPLAY_BL_DAC_CLK_DISABLE() __HAL_RCC_DAC12_CLK_DISABLE()
|
||||
#define OMV_DISPLAY_BL_DAC_FORCE_RESET() __HAL_RCC_DAC12_FORCE_RESET()
|
||||
#define OMV_DISPLAY_BL_DAC_RELEASE_RESET() __HAL_RCC_DAC12_RELEASE_RESET()
|
||||
|
||||
// FIR Lepton
|
||||
#define OMV_FIR_LEPTON_I2C_BUS (FIR_I2C_ID)
|
||||
|
||||
@ -16,6 +16,6 @@ OMV_ENABLE_UVC=1
|
||||
MICROPY_PY_SENSOR = 1
|
||||
MICROPY_PY_ULAB = 1
|
||||
MICROPY_PY_WINC1500 = 1
|
||||
MICROPY_PY_LCD = 1
|
||||
MICROPY_PY_DISPLAY = 1
|
||||
MICROPY_PY_TV = 1
|
||||
MICROPY_PY_BUZZER = 0
|
||||
|
||||
@ -300,24 +300,23 @@
|
||||
#define SPI3_DMA_RX_CHANNEL (DMA1_Stream2)
|
||||
|
||||
// SPI LCD Interface
|
||||
#define OMV_SPI_LCD_SPI_BUS (SPI2_ID)
|
||||
#define OMV_SPI_LCD_MOSI_PIN (&omv_pin_B15_SPI2)
|
||||
#define OMV_SPI_LCD_MISO_PIN (&omv_pin_B14_SPI2)
|
||||
#define OMV_SPI_LCD_SCLK_PIN (&omv_pin_B13_SPI2)
|
||||
#define OMV_SPI_LCD_SSEL_PIN (&omv_pin_B12_GPIO)
|
||||
#define OMV_SPI_DISPLAY_CONTROLLER (SPI2_ID)
|
||||
#define OMV_SPI_DISPLAY_MOSI_PIN (&omv_pin_B15_SPI2)
|
||||
#define OMV_SPI_DISPLAY_MISO_PIN (&omv_pin_B14_SPI2)
|
||||
#define OMV_SPI_DISPLAY_SCLK_PIN (&omv_pin_B13_SPI2)
|
||||
#define OMV_SPI_DISPLAY_SSEL_PIN (&omv_pin_B12_GPIO)
|
||||
|
||||
#define OMV_SPI_LCD_RS_PIN (&omv_pin_D13_GPIO)
|
||||
#define OMV_SPI_LCD_BL_PIN (&omv_pin_A5_GPIO)
|
||||
#define OMV_SPI_LCD_RST_PIN (&omv_pin_D12_GPIO)
|
||||
#define OMV_SPI_DISPLAY_RS_PIN (&omv_pin_D13_GPIO)
|
||||
#define OMV_SPI_DISPLAY_RST_PIN (&omv_pin_D12_GPIO)
|
||||
#define OMV_SPI_DISPLAY_BL_PIN (&omv_pin_A5_GPIO)
|
||||
#define OMV_SPI_DISPLAY_TRIPLE_BUFFER (1)
|
||||
|
||||
#define OMV_SPI_LCD_BL_DAC (DAC1)
|
||||
#define OMV_SPI_LCD_BL_DAC_CHANNEL (DAC_CHANNEL_2)
|
||||
#define OMV_SPI_LCD_BL_DAC_CLK_ENABLE() __HAL_RCC_DAC12_CLK_ENABLE()
|
||||
#define OMV_SPI_LCD_BL_DAC_CLK_DISABLE() __HAL_RCC_DAC12_CLK_DISABLE()
|
||||
#define OMV_SPI_LCD_BL_DAC_FORCE_RESET() __HAL_RCC_DAC12_FORCE_RESET()
|
||||
#define OMV_SPI_LCD_BL_DAC_RELEASE_RESET() __HAL_RCC_DAC12_RELEASE_RESET()
|
||||
|
||||
#define OMV_SPI_LCD_DEF_TRIPLE_BUF (1)
|
||||
#define OMV_DISPLAY_BL_DAC (DAC1)
|
||||
#define OMV_DISPLAY_BL_DAC_CHANNEL (DAC_CHANNEL_2)
|
||||
#define OMV_DISPLAY_BL_DAC_CLK_ENABLE() __HAL_RCC_DAC12_CLK_ENABLE()
|
||||
#define OMV_DISPLAY_BL_DAC_CLK_DISABLE() __HAL_RCC_DAC12_CLK_DISABLE()
|
||||
#define OMV_DISPLAY_BL_DAC_FORCE_RESET() __HAL_RCC_DAC12_FORCE_RESET()
|
||||
#define OMV_DISPLAY_BL_DAC_RELEASE_RESET() __HAL_RCC_DAC12_RELEASE_RESET()
|
||||
|
||||
// FIR Lepton
|
||||
#define OMV_FIR_LEPTON_I2C_BUS (FIR_I2C_ID)
|
||||
|
||||
@ -16,6 +16,6 @@ OMV_ENABLE_UVC=1
|
||||
MICROPY_PY_SENSOR = 1
|
||||
MICROPY_PY_ULAB = 1
|
||||
MICROPY_PY_WINC1500 = 1
|
||||
MICROPY_PY_LCD = 1
|
||||
MICROPY_PY_DISPLAY = 1
|
||||
MICROPY_PY_TV = 1
|
||||
MICROPY_PY_BUZZER = 0
|
||||
|
||||
@ -317,20 +317,18 @@
|
||||
#define ISC_SPI_MOSI_PIN (&omv_pin_G14_SPI6)
|
||||
#define ISC_SPI_SSEL_PIN (&omv_pin_A15_SPI6)
|
||||
|
||||
// SPI LCD Interface
|
||||
#define OMV_SPI_LCD_CONTROLLER (&spi_obj[1])
|
||||
#define OMV_SPI_LCD_CONTROLLER_INSTANCE (SPI2)
|
||||
|
||||
#define OMV_SPI_LCD_MOSI_PIN (&omv_pin_C1_SPI2)
|
||||
#define OMV_SPI_LCD_MISO_PIN (&omv_pin_C2_SPI2)
|
||||
#define OMV_SPI_LCD_SCLK_PIN (&omv_pin_A12_SPI2)
|
||||
#define OMV_SPI_LCD_SSEL_PIN (&omv_pin_A11_GPIO)
|
||||
|
||||
#define OMV_SPI_LCD_RST_PIN (&omv_pin_C6_GPIO)
|
||||
#define OMV_SPI_LCD_RS_PIN (&omv_pin_C7_GPIO)
|
||||
#define OMV_SPI_LCD_BL_PIN (&omv_pin_C5_GPIO)
|
||||
|
||||
#if 0
|
||||
// SPI LCD Interface
|
||||
#define OMV_SPI_DISPLAY_CONTROLLER (&spi_obj[1])
|
||||
#define OMV_SPI_DISPLAY_MOSI_PIN (&omv_pin_C1_SPI2)
|
||||
#define OMV_SPI_DISPLAY_MISO_PIN (&omv_pin_C2_SPI2)
|
||||
#define OMV_SPI_DISPLAY_SCLK_PIN (&omv_pin_A12_SPI2)
|
||||
#define OMV_SPI_DISPLAY_SSEL_PIN (&omv_pin_A11_GPIO)
|
||||
|
||||
#define OMV_SPI_DISPLAY_RST_PIN (&omv_pin_C6_GPIO)
|
||||
#define OMV_SPI_DISPLAY_RS_PIN (&omv_pin_C7_GPIO)
|
||||
#define OMV_SPI_DISPLAY_BL_PIN (&omv_pin_C5_GPIO)
|
||||
|
||||
// FIR Lepton
|
||||
#define OMV_FIR_LEPTON_I2C_BUS (FIR_I2C_ID)
|
||||
#define OMV_FIR_LEPTON_I2C_BUS_SPEED (FIR_I2C_SPEED)
|
||||
|
||||
@ -20,7 +20,7 @@ MICROPY_PY_LWIP = 1
|
||||
MICROPY_PY_NETWORK_CYW43 = 1
|
||||
MICROPY_PY_BLUETOOTH = 1
|
||||
MICROPY_BLUETOOTH_NIMBLE = 1
|
||||
MICROPY_PY_LCD = 1
|
||||
MICROPY_PY_DISPLAY = 1
|
||||
MICROPY_PY_TV = 1
|
||||
MICROPY_PY_BUZZER = 0
|
||||
MICROPY_PY_TOF = 1
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
static const char fresh_main_py[] =
|
||||
"import sensor, image, time, lcd, fir, math, pyb\n"
|
||||
"import sensor, image, time, display, fir, math, pyb\n"
|
||||
"\n"
|
||||
"from machine import I2C\n"
|
||||
"from vl53l1x import VL53L1X\n"
|
||||
@ -21,7 +21,7 @@ static const char fresh_main_py[] =
|
||||
" fir_img = sensor.alloc_extra_fb(fir.width(), fir.height(), sensor.GRAYSCALE)\n"
|
||||
" time.sleep_ms(50)\n"
|
||||
"\n"
|
||||
" lcd.init(lcd.LCD_DISPLAY_WITH_HDMI, framesize=lcd.FWVGA, refresh=60)\n"
|
||||
" lcd = display.RGBDisplay(framesize=display.FWVGA, refresh=60)\n"
|
||||
"\n"
|
||||
" alpha_pal = image.Image(256, 1, sensor.GRAYSCALE)\n"
|
||||
" for i in range(256): alpha_pal[i] = int(math.pow((i / 255), 2) * 255)\n"
|
||||
@ -76,7 +76,7 @@ static const char fresh_main_py[] =
|
||||
" img.draw_string(4, 36, 'Max Temp: %0.2f C' % to_max, color = (255, 255, 255), mono_space = False, scale = 2)\n"
|
||||
" # img.draw_string(4, 54, 'Distance: %d mm' % distance.read(), color = (255, 255, 255), mono_space = False, scale = 2)\n"
|
||||
"\n"
|
||||
" lcd.display(img, x_size = lcd.width(), hint = image.BILINEAR)\n"
|
||||
" lcd.write(img, x_size=lcd.width(), hint=image.BILINEAR)\n"
|
||||
"\n"
|
||||
"try:\n"
|
||||
" main()\n"
|
||||
|
||||
@ -312,97 +312,94 @@
|
||||
#define SPI5_DMA_RX_CHANNEL (DMA2_Stream3)
|
||||
|
||||
// LCD Interface
|
||||
#define OMV_LCD_CONTROLLER (LTDC)
|
||||
#define OMV_LCD_CLK_ENABLE() __HAL_RCC_LTDC_CLK_ENABLE()
|
||||
#define OMV_LCD_CLK_DISABLE() __HAL_RCC_LTDC_CLK_DISABLE()
|
||||
#define OMV_LCD_FORCE_RESET() __HAL_RCC_LTDC_FORCE_RESET()
|
||||
#define OMV_LCD_RELEASE_RESET() __HAL_RCC_LTDC_RELEASE_RESET()
|
||||
#define OMV_RGB_DISPLAY_CONTROLLER (LTDC)
|
||||
#define OMV_RGB_DISPLAY_CLK_ENABLE() __HAL_RCC_LTDC_CLK_ENABLE()
|
||||
#define OMV_RGB_DISPLAY_CLK_DISABLE() __HAL_RCC_LTDC_CLK_DISABLE()
|
||||
#define OMV_RGB_DISPLAY_FORCE_RESET() __HAL_RCC_LTDC_FORCE_RESET()
|
||||
#define OMV_RGB_DISPLAY_RELEASE_RESET() __HAL_RCC_LTDC_RELEASE_RESET()
|
||||
|
||||
#define OMV_LCD_R0_PIN (&omv_pin_G13_LTDC)
|
||||
#define OMV_LCD_R1_PIN (&omv_pin_A2_LTDC)
|
||||
#define OMV_LCD_R2_PIN (&omv_pin_J1_LTDC)
|
||||
#define OMV_LCD_R3_PIN (&omv_pin_J2_LTDC)
|
||||
#define OMV_LCD_R4_PIN (&omv_pin_J3_LTDC)
|
||||
#define OMV_LCD_R5_PIN (&omv_pin_J4_LTDC)
|
||||
#define OMV_LCD_R6_PIN (&omv_pin_J5_LTDC)
|
||||
#define OMV_LCD_R7_PIN (&omv_pin_J0_LTDC)
|
||||
#define OMV_RGB_DISPLAY_R0_PIN (&omv_pin_G13_LTDC)
|
||||
#define OMV_RGB_DISPLAY_R1_PIN (&omv_pin_A2_LTDC)
|
||||
#define OMV_RGB_DISPLAY_R2_PIN (&omv_pin_J1_LTDC)
|
||||
#define OMV_RGB_DISPLAY_R3_PIN (&omv_pin_J2_LTDC)
|
||||
#define OMV_RGB_DISPLAY_R4_PIN (&omv_pin_J3_LTDC)
|
||||
#define OMV_RGB_DISPLAY_R5_PIN (&omv_pin_J4_LTDC)
|
||||
#define OMV_RGB_DISPLAY_R6_PIN (&omv_pin_J5_LTDC)
|
||||
#define OMV_RGB_DISPLAY_R7_PIN (&omv_pin_J0_LTDC)
|
||||
|
||||
#define OMV_LCD_G0_PIN (&omv_pin_J7_LTDC)
|
||||
#define OMV_LCD_G1_PIN (&omv_pin_J8_LTDC)
|
||||
#define OMV_LCD_G2_PIN (&omv_pin_J9_LTDC)
|
||||
#define OMV_LCD_G3_PIN (&omv_pin_J12_LTDC)
|
||||
#define OMV_LCD_G4_PIN (&omv_pin_J11_LTDC)
|
||||
#define OMV_LCD_G5_PIN (&omv_pin_K0_LTDC)
|
||||
#define OMV_LCD_G6_PIN (&omv_pin_I11_LTDC)
|
||||
#define OMV_LCD_G7_PIN (&omv_pin_D3_LTDC)
|
||||
#define OMV_RGB_DISPLAY_G0_PIN (&omv_pin_J7_LTDC)
|
||||
#define OMV_RGB_DISPLAY_G1_PIN (&omv_pin_J8_LTDC)
|
||||
#define OMV_RGB_DISPLAY_G2_PIN (&omv_pin_J9_LTDC)
|
||||
#define OMV_RGB_DISPLAY_G3_PIN (&omv_pin_J12_LTDC)
|
||||
#define OMV_RGB_DISPLAY_G4_PIN (&omv_pin_J11_LTDC)
|
||||
#define OMV_RGB_DISPLAY_G5_PIN (&omv_pin_K0_LTDC)
|
||||
#define OMV_RGB_DISPLAY_G6_PIN (&omv_pin_I11_LTDC)
|
||||
#define OMV_RGB_DISPLAY_G7_PIN (&omv_pin_D3_LTDC)
|
||||
|
||||
#define OMV_LCD_B0_PIN (&omv_pin_G14_LTDC)
|
||||
#define OMV_LCD_B1_PIN (&omv_pin_G12_LTDC)
|
||||
#define OMV_LCD_B2_PIN (&omv_pin_D6_LTDC)
|
||||
#define OMV_LCD_B3_PIN (&omv_pin_J15_LTDC)
|
||||
#define OMV_LCD_B4_PIN (&omv_pin_K3_LTDC)
|
||||
#define OMV_LCD_B5_PIN (&omv_pin_K4_LTDC)
|
||||
#define OMV_LCD_B6_PIN (&omv_pin_K5_LTDC)
|
||||
#define OMV_LCD_B7_PIN (&omv_pin_K6_LTDC)
|
||||
#define OMV_RGB_DISPLAY_B0_PIN (&omv_pin_G14_LTDC)
|
||||
#define OMV_RGB_DISPLAY_B1_PIN (&omv_pin_G12_LTDC)
|
||||
#define OMV_RGB_DISPLAY_B2_PIN (&omv_pin_D6_LTDC)
|
||||
#define OMV_RGB_DISPLAY_B3_PIN (&omv_pin_J15_LTDC)
|
||||
#define OMV_RGB_DISPLAY_B4_PIN (&omv_pin_K3_LTDC)
|
||||
#define OMV_RGB_DISPLAY_B5_PIN (&omv_pin_K4_LTDC)
|
||||
#define OMV_RGB_DISPLAY_B6_PIN (&omv_pin_K5_LTDC)
|
||||
#define OMV_RGB_DISPLAY_B7_PIN (&omv_pin_K6_LTDC)
|
||||
|
||||
#define OMV_LCD_CLK_PIN (&omv_pin_I14_LTDC)
|
||||
#define OMV_LCD_DE_PIN (&omv_pin_K7_LTDC)
|
||||
#define OMV_LCD_HSYNC_PIN (&omv_pin_I12_LTDC)
|
||||
#define OMV_LCD_VSYNC_PIN (&omv_pin_I13_LTDC)
|
||||
#define OMV_LCD_DISP_PIN (&omv_pin_G9_GPIO)
|
||||
#define OMV_LCD_BL_PIN (&omv_pin_B0_TIM3)
|
||||
#define OMV_RGB_DISPLAY_CLK_PIN (&omv_pin_I14_LTDC)
|
||||
#define OMV_RGB_DISPLAY_DE_PIN (&omv_pin_K7_LTDC)
|
||||
#define OMV_RGB_DISPLAY_HSYNC_PIN (&omv_pin_I12_LTDC)
|
||||
#define OMV_RGB_DISPLAY_VSYNC_PIN (&omv_pin_I13_LTDC)
|
||||
#define OMV_RGB_DISPLAY_DISP_PIN (&omv_pin_G9_GPIO)
|
||||
#define OMV_RGB_DISPLAY_BL_PIN (&omv_pin_B0_TIM3)
|
||||
|
||||
#define OMV_LCD_BL_TIM (TIM3)
|
||||
#define OMV_LCD_BL_FREQ (100000)
|
||||
#define OMV_LCD_BL_TIM_CHANNEL (TIM_CHANNEL_3)
|
||||
#define OMV_LCD_BL_TIM_CLK_ENABLE() __HAL_RCC_TIM3_CLK_ENABLE()
|
||||
#define OMV_LCD_BL_TIM_CLK_DISABLE() __HAL_RCC_TIM3_CLK_DISABLE()
|
||||
#define OMV_LCD_BL_TIM_FORCE_RESET() __HAL_RCC_TIM3_FORCE_RESET()
|
||||
#define OMV_LCD_BL_TIM_RELEASE_RESET() __HAL_RCC_TIM3_RELEASE_RESET()
|
||||
#define OMV_LCD_BL_TIM_PCLK_FREQ() HAL_RCC_GetPCLK1Freq()
|
||||
#define OMV_DISPLAY_BL_TIM (TIM3)
|
||||
#define OMV_DISPLAY_BL_TIM_FREQ (100000)
|
||||
#define OMV_DISPLAY_BL_TIM_CHANNEL (TIM_CHANNEL_3)
|
||||
#define OMV_DISPLAY_BL_TIM_CLK_ENABLE() __HAL_RCC_TIM3_CLK_ENABLE()
|
||||
#define OMV_DISPLAY_BL_TIM_CLK_DISABLE() __HAL_RCC_TIM3_CLK_DISABLE()
|
||||
#define OMV_DISPLAY_BL_TIM_FORCE_RESET() __HAL_RCC_TIM3_FORCE_RESET()
|
||||
#define OMV_DISPLAY_BL_TIM_RELEASE_RESET() __HAL_RCC_TIM3_RELEASE_RESET()
|
||||
#define OMV_DISPLAY_BL_TIM_PCLK_FREQ() HAL_RCC_GetPCLK1Freq()
|
||||
|
||||
// SPI LCD Interface
|
||||
#define OMV_SPI_LCD_SPI_BUS (SPI2_ID)
|
||||
#define OMV_SPI_LCD_MOSI_PIN (&omv_pin_B15_SPI2)
|
||||
#define OMV_SPI_LCD_MISO_PIN (&omv_pin_B14_SPI2)
|
||||
#define OMV_SPI_LCD_SCLK_PIN (&omv_pin_B13_SPI2)
|
||||
#define OMV_SPI_LCD_SSEL_PIN (&omv_pin_B12_GPIO)
|
||||
#define OMV_SPI_DISPLAY_CONTROLLER (SPI2_ID)
|
||||
#define OMV_SPI_DISPLAY_MOSI_PIN (&omv_pin_B15_SPI2)
|
||||
#define OMV_SPI_DISPLAY_MISO_PIN (&omv_pin_B14_SPI2)
|
||||
#define OMV_SPI_DISPLAY_SCLK_PIN (&omv_pin_B13_SPI2)
|
||||
#define OMV_SPI_DISPLAY_SSEL_PIN (&omv_pin_B12_GPIO)
|
||||
|
||||
#define OMV_SPI_LCD_RS_PIN (&omv_pin_D13_GPIO)
|
||||
#define OMV_SPI_LCD_BL_PIN (&omv_pin_A5_GPIO)
|
||||
#define OMV_SPI_LCD_RST_PIN (&omv_pin_D12_GPIO)
|
||||
#define OMV_SPI_DISPLAY_RS_PIN (&omv_pin_D13_GPIO)
|
||||
#define OMV_SPI_DISPLAY_RST_PIN (&omv_pin_D12_GPIO)
|
||||
#define OMV_SPI_DISPLAY_BL_PIN (&omv_pin_A5_GPIO)
|
||||
#define OMV_SPI_DISPLAY_TRIPLE_BUFFER (1)
|
||||
|
||||
#define OMV_SPI_LCD_BL_DAC (DAC1)
|
||||
#define OMV_SPI_LCD_BL_DAC_CHANNEL (DAC_CHANNEL_2)
|
||||
#define OMV_SPI_LCD_BL_DAC_CLK_ENABLE() __HAL_RCC_DAC12_CLK_ENABLE()
|
||||
#define OMV_SPI_LCD_BL_DAC_CLK_DISABLE() __HAL_RCC_DAC12_CLK_DISABLE()
|
||||
#define OMV_SPI_LCD_BL_DAC_FORCE_RESET() __HAL_RCC_DAC12_FORCE_RESET()
|
||||
#define OMV_SPI_LCD_BL_DAC_RELEASE_RESET() __HAL_RCC_DAC12_RELEASE_RESET()
|
||||
#define OMV_DISPLAY_BL_DAC (DAC1)
|
||||
#define OMV_DISPLAY_BL_DAC_CHANNEL (DAC_CHANNEL_2)
|
||||
#define OMV_DISPLAY_BL_DAC_CLK_ENABLE() __HAL_RCC_DAC12_CLK_ENABLE()
|
||||
#define OMV_DISPLAY_BL_DAC_CLK_DISABLE() __HAL_RCC_DAC12_CLK_DISABLE()
|
||||
#define OMV_DISPLAY_BL_DAC_FORCE_RESET() __HAL_RCC_DAC12_FORCE_RESET()
|
||||
#define OMV_DISPLAY_BL_DAC_RELEASE_RESET() __HAL_RCC_DAC12_RELEASE_RESET()
|
||||
|
||||
#define OMV_SPI_LCD_DEF_TRIPLE_BUF (1)
|
||||
|
||||
// DVI TFP410PAP I/O
|
||||
#define OMV_DVI_PRESENT
|
||||
#define OMV_DVI_RESET_PIN (&omv_pin_D11_GPIO)
|
||||
#define OMV_DVI_SCL_PIN (pin_B1)
|
||||
#define OMV_DVI_SDA_PIN (pin_B2)
|
||||
#define OMV_DVI_INT_PIN (&omv_pin_I8_GPIO)
|
||||
|
||||
// DDC I/O
|
||||
#define OMV_DDC_PRESENT
|
||||
// HDMI CEC/DDC I/O
|
||||
#define OMV_DISPLAY_CEC_ENABLE (1)
|
||||
#define OMV_DISPLAY_DDC_ENABLE (1)
|
||||
#define OMV_CEC_PIN (&omv_pin_H2_GPIO)
|
||||
#define OMV_DDC_SCL_PIN (pin_H3)
|
||||
#define OMV_DDC_SDA_PIN (pin_H4)
|
||||
|
||||
// Touch Screen I/O
|
||||
#define OMV_TOUCH_PRESENT
|
||||
#define OMV_TOUCH_RESET_PIN (&omv_pin_K2_GPIO)
|
||||
#define OMV_TOUCH_SCL_PIN (pin_J13)
|
||||
#define OMV_TOUCH_SDA_PIN (pin_J14)
|
||||
#define OMV_TOUCH_INT_PIN (&omv_pin_J6_GPIO)
|
||||
// TFP410 DVI serializer
|
||||
#define OMV_TFP410_ENABLE (1)
|
||||
#define OMV_TFP410_RESET_PIN (&omv_pin_D11_GPIO)
|
||||
#define OMV_TFP410_SCL_PIN (pin_B1)
|
||||
#define OMV_TFP410_SDA_PIN (pin_B2)
|
||||
#define OMV_TFP410_INT_PIN (&omv_pin_I8_GPIO)
|
||||
|
||||
// HDMI CEC I/O
|
||||
#define OMV_CEC_PRESENT
|
||||
#define OMV_CEC_PIN (&omv_pin_H2_GPIO)
|
||||
// FT5X06 Touch Screen
|
||||
#define OMV_FT5X06_ENABLE (1)
|
||||
#define OMV_FT5X06_RESET_PIN (&omv_pin_K2_GPIO)
|
||||
#define OMV_FT5X06_SCL_PIN (pin_J13)
|
||||
#define OMV_FT5X06_SDA_PIN (pin_J14)
|
||||
#define OMV_FT5X06_INT_PIN (&omv_pin_J6_GPIO)
|
||||
|
||||
// FIR Lepton
|
||||
#define OMV_FIR_LEPTON_I2C_BUS (ISC_I2C_ID)
|
||||
|
||||
@ -16,6 +16,6 @@ OMV_ENABLE_UVC=1
|
||||
MICROPY_PY_SENSOR = 1
|
||||
MICROPY_PY_ULAB = 1
|
||||
MICROPY_PY_WINC1500 = 1
|
||||
MICROPY_PY_LCD = 1
|
||||
MICROPY_PY_DISPLAY = 1
|
||||
MICROPY_PY_TV = 1
|
||||
MICROPY_PY_BUZZER = 1
|
||||
|
||||
@ -205,19 +205,17 @@
|
||||
#define LPSPI4_DMA_RX_CHANNEL (0U)
|
||||
|
||||
// SPI LCD Interface
|
||||
#define OMV_SPI_LCD_SPI_BUS (LPSPI3_ID)
|
||||
#define OMV_SPI_LCD_MOSI_PIN (&omv_pin_LPSPI3_MOSI)
|
||||
#define OMV_SPI_LCD_MISO_PIN (&omv_pin_LPSPI3_MISO)
|
||||
#define OMV_SPI_LCD_SCLK_PIN (&omv_pin_LPSPI3_SCLK)
|
||||
#define OMV_SPI_LCD_SSEL_PIN (&omv_pin_LPSPI3_GPIO)
|
||||
#define OMV_SPI_DISPLAY_CONTROLLER (LPSPI3_ID)
|
||||
#define OMV_SPI_DISPLAY_MOSI_PIN (&omv_pin_LPSPI3_MOSI)
|
||||
#define OMV_SPI_DISPLAY_MISO_PIN (&omv_pin_LPSPI3_MISO)
|
||||
#define OMV_SPI_DISPLAY_SCLK_PIN (&omv_pin_LPSPI3_SCLK)
|
||||
#define OMV_SPI_DISPLAY_SSEL_PIN (&omv_pin_LPSPI3_GPIO)
|
||||
|
||||
#define OMV_SPI_LCD_RS_PIN (&omv_pin_P8_GPIO)
|
||||
#define OMV_SPI_LCD_BL_PIN (&omv_pin_P6_GPIO)
|
||||
#define OMV_SPI_LCD_RST_PIN (&omv_pin_P7_GPIO)
|
||||
|
||||
#define OMV_SPI_LCD_DEF_TRIPLE_BUF (1)
|
||||
|
||||
#define OMV_SPI_LCD_RX_CLK_DIV (8)
|
||||
#define OMV_SPI_DISPLAY_RS_PIN (&omv_pin_P8_GPIO)
|
||||
#define OMV_SPI_DISPLAY_RST_PIN (&omv_pin_P7_GPIO)
|
||||
#define OMV_SPI_DISPLAY_BL_PIN (&omv_pin_P6_GPIO)
|
||||
#define OMV_SPI_DISPLAY_TRIPLE_BUFFER (0)
|
||||
#define OMV_SPI_DISPLAY_RX_CLK_DIV (8)
|
||||
|
||||
// FIR Lepton
|
||||
#define OMV_FIR_LEPTON_I2C_BUS (FIR_I2C_ID)
|
||||
|
||||
@ -19,6 +19,6 @@ MICROPY_PY_LWIP = 1
|
||||
MICROPY_PY_NETWORK_CYW43 = 1
|
||||
MICROPY_PY_BLUETOOTH = 1
|
||||
MICROPY_BLUETOOTH_NIMBLE = 1
|
||||
MICROPY_PY_LCD = 1
|
||||
MICROPY_PY_DISPLAY = 1
|
||||
MICROPY_PY_TV = 1
|
||||
MICROPY_PY_BUZZER = 0
|
||||
|
||||
@ -6,6 +6,6 @@ set(MICROPY_PY_BLUETOOTH 0)
|
||||
set(MICROPY_BLUETOOTH_NIMBLE 0)
|
||||
set(MICROPY_PY_AUDIO 0)
|
||||
set(MICROPY_PY_MICRO_SPEECH 0)
|
||||
set(MICROPY_PY_LCD 0)
|
||||
set(MICROPY_PY_DISPLAY 0)
|
||||
set(MICROPY_PY_TV 0)
|
||||
set(MICROPY_PY_BUZZER 0)
|
||||
|
||||
@ -14,7 +14,7 @@ OMV_HSE_VALUE=12000000
|
||||
DFU_DEVICE=0x0483:0xdf11
|
||||
MICROPY_PY_ULAB=1
|
||||
MICROPY_PY_AUDIO=1
|
||||
MICROPY_PY_LCD = 0
|
||||
MICROPY_PY_DISPLAY = 0
|
||||
MICROPY_PY_TV = 0
|
||||
MICROPY_PY_BUZZER = 0
|
||||
MICROPY_PY_SENSOR = 1
|
||||
|
||||
Loading…
Reference in New Issue
Block a user