Merge pull request #2473 from openmv/bootloader_updates

misc: Refactor Makefile variables, and misc bootloader fixes.
This commit is contained in:
Ibrahim Abdelkader 2024-10-31 19:18:25 +03:00 committed by GitHub
commit 6ee52f73c0
No known key found for this signature in database
GPG Key ID: B5690EEEBB952194
20 changed files with 138 additions and 118 deletions

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@ -94,5 +94,5 @@ int main(void) {
tud_deinit(TUD_OPT_RHPORT);
// JUMP!
((void (*) (void)) (*((uint32_t *) (OMV_BOOT_JUMP_ADDR + 4)))) ();
((void (*) (void)) (*((uint32_t *) (OMV_BOOT_JUMP + 4)))) ();
}

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@ -42,6 +42,15 @@ SECTIONS
_exit = .;
} >ROM
.gnu.sgstubs :
{
. = ALIGN(4);
_start_sg = .;
*(.gnu*)
. = ALIGN(4);
_end_sg = .;
} >ROM
/* used by the startup to initialize data */
_sidata = LOADADDR(.data);
@ -75,6 +84,7 @@ SECTIONS
.stack :
{
. = ALIGN(4);
_sstack = .;
. = . + _stack_size;
. = ALIGN(4);
_estack = .;

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@ -69,28 +69,43 @@ int port_init(void) {
HAL_NVIC_SetPriority(SysTick_IRQn, 0, 0);
// Enable GPIO clocks
__GPIOA_CLK_ENABLE();
__GPIOB_CLK_ENABLE();
__GPIOC_CLK_ENABLE();
__GPIOD_CLK_ENABLE();
__GPIOE_CLK_ENABLE();
__HAL_RCC_GPIOA_CLK_ENABLE();
__HAL_RCC_GPIOB_CLK_ENABLE();
__HAL_RCC_GPIOC_CLK_ENABLE();
__HAL_RCC_GPIOD_CLK_ENABLE();
__HAL_RCC_GPIOE_CLK_ENABLE();
#ifdef OMV_GPIO_PORT_F_ENABLE
__GPIOF_CLK_ENABLE();
__HAL_RCC_GPIOF_CLK_ENABLE();
#endif
#ifdef OMV_GPIO_PORT_G_ENABLE
__GPIOG_CLK_ENABLE();
__HAL_RCC_GPIOG_CLK_ENABLE();
#endif
#ifdef OMV_GPIO_PORT_H_ENABLE
__GPIOH_CLK_ENABLE();
__HAL_RCC_GPIOH_CLK_ENABLE();
#endif
#ifdef OMV_GPIO_PORT_I_ENABLE
__GPIOI_CLK_ENABLE();
__HAL_RCC_GPIOI_CLK_ENABLE();
#endif
#ifdef OMV_GPIO_PORT_J_ENABLE
__GPIOJ_CLK_ENABLE();
__HAL_RCC_GPIOJ_CLK_ENABLE();
#endif
#ifdef OMV_GPIO_PORT_K_ENABLE
__GPIOK_CLK_ENABLE();
__HAL_RCC_GPIOK_CLK_ENABLE();
#endif
#ifdef OMV_GPIO_PORT_H_ENABLE
__HAL_RCC_GPIOH_CLK_ENABLE();
#endif
#ifdef OMV_GPIO_PORT_N_ENABLE
__HAL_RCC_GPION_CLK_ENABLE();
#endif
#ifdef OMV_GPIO_PORT_O_ENABLE
__HAL_RCC_GPIOO_CLK_ENABLE();
#endif
#ifdef OMV_GPIO_PORT_P_ENABLE
__HAL_RCC_GPIOP_CLK_ENABLE();
#endif
#ifdef OMV_GPIO_PORT_Q_ENABLE
__HAL_RCC_GPIOQ_CLK_ENABLE();
#endif
// Configure I/O pins.
@ -114,17 +129,16 @@ int port_init(void) {
__HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE();
// Configure and enable USB IRQ.
HAL_NVIC_SetPriority(OTG_FS_IRQn, 6, 0);
NVIC_ClearPendingIRQ(OTG_FS_IRQn);
HAL_NVIC_EnableIRQ(OTG_FS_IRQn);
HAL_NVIC_SetPriority(OMV_USB_IRQN, 6, 0);
NVIC_ClearPendingIRQ(OMV_USB_IRQN);
HAL_NVIC_EnableIRQ(OMV_USB_IRQN);
return 0;
}
int port_deinit(void) {
// Disable USB IRQ.
HAL_NVIC_DisableIRQ(OTG_FS_IRQn);
NVIC_ClearPendingIRQ(OTG_FS_IRQn);
HAL_NVIC_DisableIRQ(OMV_USB_IRQN);
NVIC_ClearPendingIRQ(OMV_USB_IRQN);
// Deinitialize SPI Flash.
#if OMV_BOOT_SPI_FLASH_ENABLE
@ -142,28 +156,43 @@ int port_deinit(void) {
__HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE();
// Disable GPIO clocks.
__GPIOA_CLK_DISABLE();
__GPIOB_CLK_DISABLE();
__GPIOC_CLK_DISABLE();
__GPIOD_CLK_DISABLE();
__GPIOE_CLK_DISABLE();
__HAL_RCC_GPIOA_CLK_DISABLE();
__HAL_RCC_GPIOB_CLK_DISABLE();
__HAL_RCC_GPIOC_CLK_DISABLE();
__HAL_RCC_GPIOD_CLK_DISABLE();
__HAL_RCC_GPIOE_CLK_DISABLE();
#ifdef OMV_GPIO_PORT_F_ENABLE
__GPIOF_CLK_DISABLE();
__HAL_RCC_GPIOF_CLK_DISABLE();
#endif
#ifdef OMV_GPIO_PORT_G_ENABLE
__GPIOG_CLK_DISABLE();
__HAL_RCC_GPIOG_CLK_DISABLE();
#endif
#ifdef OMV_GPIO_PORT_H_ENABLE
__GPIOH_CLK_DISABLE();
__HAL_RCC_GPIOH_CLK_DISABLE();
#endif
#ifdef OMV_GPIO_PORT_I_ENABLE
__GPIOI_CLK_DISABLE();
__HAL_RCC_GPIOI_CLK_DISABLE();
#endif
#ifdef OMV_GPIO_PORT_J_ENABLE
__GPIOJ_CLK_DISABLE();
__HAL_RCC_GPIOJ_CLK_DISABLE();
#endif
#ifdef OMV_GPIO_PORT_K_ENABLE
__GPIOK_CLK_DISABLE();
__HAL_RCC_GPIOK_CLK_DISABLE();
#endif
#ifdef OMV_GPIO_PORT_H_ENABLE
__HAL_RCC_GPIOH_CLK_DISABLE();
#endif
#ifdef OMV_GPIO_PORT_N_ENABLE
__HAL_RCC_GPION_CLK_DISABLE();
#endif
#ifdef OMV_GPIO_PORT_O_ENABLE
__HAL_RCC_GPIOO_CLK_DISABLE();
#endif
#ifdef OMV_GPIO_PORT_P_ENABLE
__HAL_RCC_GPIOP_CLK_DISABLE();
#endif
#ifdef OMV_GPIO_PORT_Q_ENABLE
__HAL_RCC_GPIOQ_CLK_DISABLE();
#endif
return 0;
}
@ -195,7 +224,7 @@ void port_pin_mode(uint32_t pin, uint32_t mode) {
GPIO_InitTypeDef pin_config;
pin_config.Pin = p->pin;
pin_config.Pull = GPIO_PULLUP;
pin_config.Speed = GPIO_SPEED_LOW;
pin_config.Speed = GPIO_SPEED_FREQ_LOW;
if (mode == PIN_MODE_OUTPUT) {
pin_config.Mode = GPIO_MODE_OUTPUT_PP;
} else {

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@ -68,16 +68,15 @@ LDFLAGS = -mthumb \
CFLAGS += -D$(MCU) \
-D$(TARGET) \
-DARM_NN_TRUNCATE \
-D__FPU_PRESENT=1 \
-D__VFP_FP__ \
-DUSE_DEVICE_MODE \
-DHSE_VALUE=$(OMV_HSE_VALUE)\
-DVECT_TAB_OFFSET=0 \
-DOMV_BOOT_JUMP_ADDR=$(MAIN_APP_ADDR) \
-DOMV_VTOR_BASE=$(OMV_BOOT_BASE) \
-DOMV_BOOT_JUMP=$(OMV_FIRM_BASE) \
-DSTM32_HAL_H=$(HAL_INC) \
-DCMSIS_MCU_H=$(CMSIS_MCU_H) \
-DUSE_FULL_LL_DRIVER \
$(OMV_BOARD_EXTRA_CFLAGS)
$(OMV_BOARD_CFLAGS)
CFLAGS += -I$(OMV_BOARD_CONFIG_DIR) \
-I$(TOP_DIR)/$(BOOT_DIR)/include \
@ -118,19 +117,24 @@ SRC_C += $(addprefix $(CMSIS_DIR)/src/,\
SRC_C += $(addprefix $(HAL_DIR)/src/,\
$(MCU_SERIES_LOWER)_hal.c \
$(MCU_SERIES_LOWER)_hal_cortex.c \
$(MCU_SERIES_LOWER)_hal_flash.c \
$(MCU_SERIES_LOWER)_hal_flash_ex.c \
$(MCU_SERIES_LOWER)_hal_gpio.c \
$(MCU_SERIES_LOWER)_hal_pwr.c \
$(MCU_SERIES_LOWER)_hal_pwr_ex.c \
$(MCU_SERIES_LOWER)_hal_rcc.c \
$(MCU_SERIES_LOWER)_hal_rcc_ex.c \
$(MCU_SERIES_LOWER)_hal_rng.c \
$(MCU_SERIES_LOWER)_hal_qspi.c \
$(MCU_SERIES_LOWER)_ll_rcc.c \
$(MCU_SERIES_LOWER)_ll_usb.c \
)
ifeq ($(MCU_SERIES),$(filter $(MCU_SERIES),STM32F4xx STM32F7xx STM32H7xx))
SRC_C += $(addprefix $(HAL_DIR)/src/,\
$(MCU_SERIES_LOWER)_hal_qspi.c \
$(MCU_SERIES_LOWER)_hal_flash.c \
$(MCU_SERIES_LOWER)_hal_flash_ex.c \
)
endif
# Firmware objects
OBJS += $(addprefix $(BUILD)/, $(SRC_C:.c=.o))
OBJS += $(addprefix $(BUILD)/, $(SRC_S:.s=.o))

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@ -180,11 +180,7 @@ void SystemInit(void)
#endif // !defined(CORE_CM4)
/* Configure the Vector Table location add offset address ------------------*/
#ifdef VECT_TAB_SRAM
SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
#else
SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
#endif
SCB->VTOR = OMV_VTOR_BASE;
}
void SystemClock_Config(void)
@ -435,9 +431,4 @@ void SystemClock_Config(void)
// Enable the USB voltage level detector
HAL_PWREx_EnableUSBVoltageDetector();
#endif
#if defined(CORE_CM7) && defined(M4_APP_ADDR)
HAL_SYSCFG_CM4BootAddConfig(SYSCFG_BOOT_ADDR0, M4_APP_ADDR);
HAL_RCCEx_EnableBootCore(RCC_BOOT_C2);
#endif
}

@ -1 +1 @@
Subproject commit 762552586b79e7b8bc4a2b64a45498ca2768ef53
Subproject commit 12f6d620efcdde76824b6e90c269e0184809c236

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@ -6,22 +6,17 @@ HAL_DIR=hal/stm32/h7
HAL_INC='<stm32h7xx_hal.h>'
CMSIS_MCU_H='<stm32h747xx.h>'
CFLAGS_MCU=MCU_SERIES_H7
VECT_TAB_OFFSET=0x40000
MAIN_APP_ADDR=0x08040000
M4_VECT_TAB_OFFSET=0x20000
M4_APP_ADDR=0x08020000
OMV_FIRM_BASE=0x08040000
OMV_HSE_VALUE=16000000
DFU_DEVICE=0x2341:0x035b
OMV_BOARD_EXTRA_CFLAGS = -DCORE_CM7 \
OMV_BOARD_CFLAGS = -DCORE_CM7 \
-DUSE_USB_FS \
-DCYW43_FIRMWARE_ADDRESS=0x90F00000 \
-DCYW43_CHIPSET_FIRMWARE_INCLUDE_FILE="\"$(TOP_DIR)/$(CYW4343_FW_DIR)/cyw4343_7_45_98_102.h\"" \
-DCYW43_BT_FIRMWARE_ADDRESS=0x90FC0000 \
-DCYW43_BT_FIRMWARE_INCLUDE_FILE="\"$(TOP_DIR)/$(CYW4343_FW_DIR)/cyw4343_btfw.h\""
OMV_ENABLE_BL=0
OMV_ENABLE_UVC=1
OMV_ENABLE_CM4=0
MICROPY_PY_CSI = 1
MICROPY_PY_ULAB = 1
MICROPY_PY_LWIP = 1

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@ -7,10 +7,13 @@ HAL_DIR=hal/nrfx
CMSIS_MCU_H='<nrf52840.h>'
NRF_SOFTDEV=s140_nrf52_6.1.1
CFLAGS_MCU=NRF52_SERIES
OMV_BOARD_EXTRA_CFLAGS = -DCONFIG_GPIO_AS_PINRESET -DNRF52840_XXAA -DSOFTDEVICE_PRESENT -DBLUETOOTH_SD_DEBUG=1 -DBLUETOOTH_SD=140
VECT_TAB_OFFSET=0x26000
MAIN_APP_ADDR=0x00026000
OMV_FIRM_BASE=0x00026000
OMV_HSE_VALUE=12000000
OMV_BOARD_CFLAGS = -DCONFIG_GPIO_AS_PINRESET \
-DNRF52840_XXAA \
-DSOFTDEVICE_PRESENT \
-DBLUETOOTH_SD_DEBUG=1 \
-DBLUETOOTH_SD=140
DFU_DEVICE=0x0483:0xdf11
MICROPY_PY_ULAB=1
MICROPY_PY_AUDIO=1

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@ -6,14 +6,11 @@ HAL_DIR=hal/stm32/h7
HAL_INC='<stm32h7xx_hal.h>'
CMSIS_MCU_H='<stm32h747xx.h>'
CFLAGS_MCU=MCU_SERIES_H7
VECT_TAB_OFFSET=0x40000
MAIN_APP_ADDR=0x08040000
M4_VECT_TAB_OFFSET=0x20000
M4_APP_ADDR=0x08020000
OMV_FIRM_BASE=0x08040000
OMV_HSE_VALUE=25000000
DFU_DEVICE=0x2341:0x035b
USERMOD_OPT = -Os
OMV_BOARD_EXTRA_CFLAGS = -DCORE_CM7 \
OMV_BOARD_CFLAGS = -DCORE_CM7 \
-DUSE_USB_HS \
-DCYW43_FIRMWARE_ADDRESS=0x90F00000 \
-DCYW43_CHIPSET_FIRMWARE_INCLUDE_FILE="\"$(TOP_DIR)/$(CYW4343_FW_DIR)/cyw4343_7_45_98_102.h\"" \
@ -21,7 +18,6 @@ OMV_BOARD_EXTRA_CFLAGS = -DCORE_CM7 \
-DCYW43_BT_FIRMWARE_INCLUDE_FILE="\"$(TOP_DIR)/$(CYW4343_FW_DIR)/cyw4343_btfw.h\""
OMV_ENABLE_BL = 0
OMV_ENABLE_UVC = 1
OMV_ENABLE_CM4 = 0
MICROPY_PY_CSI = 1
MICROPY_PY_ULAB = 1
MICROPY_PY_WINC1500 = 0

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@ -6,22 +6,17 @@ HAL_DIR=hal/stm32/h7
HAL_INC='<stm32h7xx_hal.h>'
CMSIS_MCU_H='<stm32h747xx.h>'
CFLAGS_MCU=MCU_SERIES_H7
VECT_TAB_OFFSET=0x40000
MAIN_APP_ADDR=0x08040000
M4_VECT_TAB_OFFSET=0x20000
M4_APP_ADDR=0x08020000
OMV_FIRM_BASE=0x08040000
OMV_HSE_VALUE=25000000
DFU_DEVICE=0x2341:0x035b
OMV_BOARD_EXTRA_CFLAGS = -DCORE_CM7 \
OMV_BOARD_CFLAGS = -DCORE_CM7 \
-DUSE_USB_HS \
-DCYW43_FIRMWARE_ADDRESS=0x90F00000 \
-DCYW43_CHIPSET_FIRMWARE_INCLUDE_FILE="\"$(TOP_DIR)/$(CYW4343_FW_DIR)/cyw4343_7_45_98_102.h\"" \
-DCYW43_BT_FIRMWARE_ADDRESS=0x90FC0000 \
-DCYW43_BT_FIRMWARE_INCLUDE_FILE="\"$(TOP_DIR)/$(CYW4343_FW_DIR)/cyw4343_btfw.h\""
OMV_ENABLE_BL=0
OMV_ENABLE_UVC=1
OMV_ENABLE_CM4=0
MICROPY_PY_CSI = 1
MICROPY_PY_ULAB = 1
MICROPY_PY_WINC1500 = 0

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@ -5,9 +5,9 @@ PORT=stm32
HAL_DIR=hal/stm32/f4
HAL_INC='<stm32f4xx_hal.h>'
CFLAGS_MCU=MCU_SERIES_F4
OMV_BOARD_EXTRA_CFLAGS=-DUSE_USB_FS
VECT_TAB_OFFSET=0x10000
MAIN_APP_ADDR=0x08010000
OMV_BOARD_CFLAGS=-DUSE_USB_FS
OMV_BOOT_BASE=0x08000000
OMV_FIRM_BASE=0x08010000
OMV_HSE_VALUE=12000000
DFU_DEVICE=0x0483:0xdf11
OMV_ENABLE_BL=1

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@ -7,9 +7,9 @@ HAL_DIR=hal/stm32/f4
HAL_INC='<stm32f4xx_hal.h>'
CMSIS_MCU_H='<stm32f427xx.h>'
CFLAGS_MCU=MCU_SERIES_F4
OMV_BOARD_EXTRA_CFLAGS=-DCFG_TUSB_MCU=OPT_MCU_STM32F4
VECT_TAB_OFFSET=0x10000
MAIN_APP_ADDR=0x08010000
OMV_BOARD_CFLAGS=-DCFG_TUSB_MCU=OPT_MCU_STM32F4
OMV_BOOT_BASE=0x08000000
OMV_FIRM_BASE=0x08010000
OMV_HSE_VALUE=12000000
DFU_DEVICE=0x0483:0xdf11
OMV_ENABLE_BL=1

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@ -7,9 +7,9 @@ HAL_DIR=hal/stm32/f7
HAL_INC='<stm32f7xx_hal.h>'
CMSIS_MCU_H='<stm32f765xx.h>'
CFLAGS_MCU=MCU_SERIES_F7
OMV_BOARD_EXTRA_CFLAGS=-DCFG_TUSB_MCU=OPT_MCU_STM32F7
VECT_TAB_OFFSET=0x20000
MAIN_APP_ADDR=0x08020000
OMV_BOARD_CFLAGS=-DCFG_TUSB_MCU=OPT_MCU_STM32F7
OMV_BOOT_BASE=0x08000000
OMV_FIRM_BASE=0x08020000
OMV_HSE_VALUE=12000000
DFU_DEVICE=0x0483:0xdf11
OMV_ENABLE_BL=1

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@ -7,9 +7,9 @@ HAL_DIR=hal/stm32/h7
HAL_INC='<stm32h7xx_hal.h>'
CMSIS_MCU_H='<stm32h743xx.h>'
CFLAGS_MCU=MCU_SERIES_H7
OMV_BOARD_EXTRA_CFLAGS=-DCFG_TUSB_MCU=OPT_MCU_STM32H7
VECT_TAB_OFFSET=0x40000
MAIN_APP_ADDR=0x08040000
OMV_BOARD_CFLAGS=-DCFG_TUSB_MCU=OPT_MCU_STM32H7
OMV_BOOT_BASE=0x08000000
OMV_FIRM_BASE=0x08040000
OMV_HSE_VALUE=12000000
DFU_DEVICE=0x0483:0xdf11
OMV_ENABLE_BL=1

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@ -7,9 +7,9 @@ HAL_DIR=hal/stm32/h7
HAL_INC='<stm32h7xx_hal.h>'
CMSIS_MCU_H='<stm32h743xx.h>'
CFLAGS_MCU=MCU_SERIES_H7
OMV_BOARD_EXTRA_CFLAGS=-DCFG_TUSB_MCU=OPT_MCU_STM32H7
VECT_TAB_OFFSET=0x40000
MAIN_APP_ADDR=0x08040000
OMV_BOARD_CFLAGS=-DCFG_TUSB_MCU=OPT_MCU_STM32H7
OMV_BOOT_BASE=0x08000000
OMV_FIRM_BASE=0x08040000
OMV_HSE_VALUE=12000000
DFU_DEVICE=0x0483:0xdf11
OMV_ENABLE_BL=1

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@ -7,9 +7,9 @@ HAL_DIR=hal/stm32/h7
HAL_INC='<stm32h7xx_hal.h>'
CMSIS_MCU_H='<stm32h743xx.h>'
CFLAGS_MCU=MCU_SERIES_H7
OMV_BOARD_EXTRA_CFLAGS=-DCFG_TUSB_MCU=OPT_MCU_STM32H7
VECT_TAB_OFFSET=0x40000
MAIN_APP_ADDR=0x08040000
OMV_BOARD_CFLAGS=-DCFG_TUSB_MCU=OPT_MCU_STM32H7
OMV_BOOT_BASE=0x08000000
OMV_FIRM_BASE=0x08040000
OMV_HSE_VALUE=12000000
DFU_DEVICE=0x0483:0xdf11
OMV_ENABLE_BL=1

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@ -6,9 +6,8 @@ FABI=hard
PORT=mimxrt
HAL_DIR=hal/mimxrt/MIMXRT1062
CMSIS_MCU_H='<MIMXRT1062.h>'
OMV_BOARD_EXTRA_CFLAGS=-DBOARD_FLASH_SIZE=0x800000
VECT_TAB_OFFSET=0x0
MAIN_APP_ADDR=0x60000000
OMV_BOARD_CFLAGS=-DBOARD_FLASH_SIZE=0x800000
OMV_FIRM_BASE=0x60000000
OMV_HSE_VALUE=12000000
OMV_ENABLE_BL=0
OMV_ENABLE_UVC=0

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@ -60,7 +60,7 @@ CFLAGS += -DCPU_$(MCU_VARIANT) \
-D__START=main \
-D__STARTUP_CLEAR_BSS \
-D__STARTUP_INITIALIZE_RAMFUNCTION \
$(OMV_BOARD_EXTRA_CFLAGS)
$(OMV_BOARD_CFLAGS)
# Linker Flags
LDFLAGS = -mthumb \

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@ -31,7 +31,7 @@ CFLAGS += -std=gnu99 -Wall -Werror -Warray-bounds -mthumb -nostartfiles -fdata-s
CFLAGS += -D$(MCU) -D$(CFLAGS_MCU) -DARM_NN_TRUNCATE -D__FPU_PRESENT=1 -D__VFP_FP__ -D$(TARGET)\
-fsingle-precision-constant -Wdouble-promotion -mcpu=$(CPU) -mtune=$(CPU) -mfpu=$(FPU) -mfloat-abi=hard\
-DCMSIS_MCU_H=$(CMSIS_MCU_H) -DMP_PORT_NO_SOFTTIMER
CFLAGS += $(OMV_BOARD_EXTRA_CFLAGS)
CFLAGS += $(OMV_BOARD_CFLAGS)
# Disable LTO and set the SD
MICROPY_ARGS += LTO=0 SD=$(SD)

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@ -51,14 +51,12 @@ CFLAGS += -D$(MCU) \
-DARM_NN_TRUNCATE \
-D__FPU_PRESENT=1 \
-D__VFP_FP__ \
-DUSE_DEVICE_MODE \
-DHSE_VALUE=$(OMV_HSE_VALUE)\
-DVECT_TAB_OFFSET=$(VECT_TAB_OFFSET) \
-DMAIN_APP_ADDR=$(MAIN_APP_ADDR) \
-DOMV_VTOR_BASE=$(OMV_FIRM_BASE) \
-DSTM32_HAL_H=$(HAL_INC) \
-DCMSIS_MCU_H=$(CMSIS_MCU_H) \
-DUSE_FULL_LL_DRIVER \
$(OMV_BOARD_EXTRA_CFLAGS)
$(OMV_BOARD_CFLAGS)
# Linker Flags
LDFLAGS = -mthumb \
@ -696,7 +694,7 @@ BOOTLOADER = bootloader
$(BOOTLOADER): | $(BUILD) $(FW_DIR)
$(MAKE) -C $(TOP_DIR)/$(BOOT_DIR) BUILD=$(BUILD)/$(BOOT_DIR)
$(OBJCOPY) -Obinary $(FW_DIR)/$(BOOTLOADER).elf $(FW_DIR)/$(BOOTLOADER).bin
$(PYTHON) $(MKDFU) -D $(DFU_DEVICE) -b 0x08000000:$(FW_DIR)/$(BOOTLOADER).bin $(FW_DIR)/$(BOOTLOADER).dfu
$(PYTHON) $(MKDFU) -D $(DFU_DEVICE) -b $(OMV_BOOT_BASE):$(FW_DIR)/$(BOOTLOADER).bin $(FW_DIR)/$(BOOTLOADER).dfu
endif
# This target generates the UVC firmware.
@ -706,7 +704,7 @@ $(UVC): FIRMWARE_OBJS UVC_OBJS
$(UVC_DIR)/stm32fxxx.ld.S > $(BUILD)/$(UVC_DIR)/stm32fxxx.lds
$(CC) $(UVC_LDFLAGS) $(UVC_OBJ) -o $(FW_DIR)/$(UVC).elf -lgcc
$(OBJCOPY) -Obinary $(FW_DIR)/$(UVC).elf $(FW_DIR)/$(UVC).bin
$(PYTHON) $(MKDFU) -D $(DFU_DEVICE) -b $(MAIN_APP_ADDR):$(FW_DIR)/$(UVC).bin $(FW_DIR)/$(UVC).dfu
$(PYTHON) $(MKDFU) -D $(DFU_DEVICE) -b $(OMV_FIRM_BASE):$(FW_DIR)/$(UVC).bin $(FW_DIR)/$(UVC).dfu
endif
# This target generates the main/app firmware image located at 0x08010000
@ -715,13 +713,13 @@ $(FIRMWARE): FIRMWARE_OBJS
$(OMV_DIR)/ports/$(PORT)/$(LDSCRIPT).ld.S > $(BUILD)/$(LDSCRIPT).lds
$(CC) $(LDFLAGS) $(FIRM_OBJ) -o $(FW_DIR)/$(FIRMWARE).elf $(LIBS) -lm
$(OBJCOPY) -Obinary $(FW_DIR)/$(FIRMWARE).elf $(FW_DIR)/$(FIRMWARE).bin
$(PYTHON) $(MKDFU) -D $(DFU_DEVICE) -b $(MAIN_APP_ADDR):$(FW_DIR)/$(FIRMWARE).bin $(FW_DIR)/$(FIRMWARE).dfu
$(PYTHON) $(MKDFU) -D $(DFU_DEVICE) -b $(OMV_FIRM_BASE):$(FW_DIR)/$(FIRMWARE).bin $(FW_DIR)/$(FIRMWARE).dfu
# This target generates the uvc, bootloader and firmware images.
$(OPENMV): $(BOOTLOADER) $(UVC) $(FIRMWARE)
ifeq ($(OMV_ENABLE_BL), 1)
# Generate a contiguous firmware image for factory programming
$(OBJCOPY) -Obinary --pad-to=$(MAIN_APP_ADDR) --gap-fill=0xFF $(FW_DIR)/$(BOOTLOADER).elf $(FW_DIR)/$(BOOTLOADER)_padded.bin
$(OBJCOPY) -Obinary --pad-to=$(OMV_FIRM_BASE) --gap-fill=0xFF $(FW_DIR)/$(BOOTLOADER).elf $(FW_DIR)/$(BOOTLOADER)_padded.bin
$(CAT) $(FW_DIR)/$(BOOTLOADER)_padded.bin $(FW_DIR)/$(FIRMWARE).bin > $(FW_DIR)/$(OPENMV).bin
$(RM) $(FW_DIR)/$(BOOTLOADER)_padded.bin
$(SIZE) $(FW_DIR)/$(BOOTLOADER).elf