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https://github.com/openmv/openmv.git
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Merge pull request #1227 from openmv/cm4_firmware
Add support for generating Cortex-M4 firmware.
This commit is contained in:
commit
70a42f9e18
@ -46,6 +46,7 @@ BUILD=$(TOP_DIR)/build
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FW_DIR=$(BUILD)/bin
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FW_DIR=$(BUILD)/bin
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OMV_DIR=omv
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OMV_DIR=omv
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UVC_DIR=uvc
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UVC_DIR=uvc
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CM4_DIR=cm4
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BOOTLDR_DIR=bootloader
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BOOTLDR_DIR=bootloader
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CUBEAI_DIR=stm32cubeai
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CUBEAI_DIR=stm32cubeai
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CMSIS_DIR=hal/cmsis
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CMSIS_DIR=hal/cmsis
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59
src/cm4/Makefile
Executable file
59
src/cm4/Makefile
Executable file
@ -0,0 +1,59 @@
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# This file is part of the OpenMV project.
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#
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# Copyright (c) 2013-2021 Ibrahim Abdelkader <iabdalkader@openmv.io>
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# Copyright (c) 2013-2021 Kwabena W. Agyeman <kwagyeman@openmv.io>
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#
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# This work is licensed under the MIT license, see the file LICENSE for details.
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#
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# CM4 firmware Makefile
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SRC_C = $(wildcard src/*.c)
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SRC_C += $(addprefix $(HAL_DIR)/src/, \
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stm32h7xx_hal.c \
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stm32h7xx_hal_cortex.c \
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stm32h7xx_hal_gpio.c \
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stm32h7xx_hal_pwr.c \
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stm32h7xx_hal_pwr_ex.c \
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stm32h7xx_hal_rcc.c \
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stm32h7xx_hal_rcc_ex.c \
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stm32h7xx_hal_rtc.c \
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stm32h7xx_hal_rtc_ex.c \
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)
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#SRCS += $(addprefix $(HAL_DIR)/src/, $(notdir $(wildcard ../$(HAL_DIR)/src/*.c)))
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SRC_C += $(addprefix $(CMSIS_DIR)/src/, \
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$(SYSTEM).c \
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)
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SRC_S += $(addprefix $(CMSIS_DIR)/src/, \
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$(STARTUP).s \
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)
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OBJS = $(addprefix $(BUILD)/, $(SRC_S:.s=.o))
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OBJS += $(addprefix $(BUILD)/, $(SRC_C:.c=.o))
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OBJ_DIRS = $(sort $(dir $(OBJS)))
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all: | $(OBJ_DIRS) $(OBJS)
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$(OBJ_DIRS):
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$(MKDIR) -p $@
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$(BUILD)/$(HAL_DIR)/src/%.o : $(TOP_DIR)/$(HAL_DIR)/src/%.c
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$(ECHO) "CC $<"
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$(CC) $(CFLAGS) -c -o $@ $<
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$(BUILD)/$(CMSIS_DIR)/src/%.o : $(TOP_DIR)/$(CMSIS_DIR)/src/%.c
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$(ECHO) "CC $<"
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$(CC) $(CFLAGS) -c -o $@ $<
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$(BUILD)/$(CMSIS_DIR)/src/%.o : $(TOP_DIR)/$(CMSIS_DIR)/src/%.s
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$(ECHO) "AS $<"
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$(AS) $(AFLAGS) $< -o $@
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$(BUILD)/%.o : %.c
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$(ECHO) "CC $<"
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$(CC) $(CFLAGS) -c -o $@ $<
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$(BUILD)/%.o : %.s
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$(ECHO) "AS $<"
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$(AS) $(AFLAGS) $< -o $@
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-include $(OBJS:%.o=%.d)
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14
src/cm4/src/main.c
Normal file
14
src/cm4/src/main.c
Normal file
@ -0,0 +1,14 @@
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#include STM32_HAL_H
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int main(void)
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{
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__disable_irq();
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// Add Cortex-M4 code here.
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HAL_PWREx_ClearPendingEvent();
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HAL_PWREx_EnterSTOPMode(PWR_MAINREGULATOR_ON, PWR_STOPENTRY_WFE, PWR_D2_DOMAIN);
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while (1) {
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__WFI();
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}
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}
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139
src/cm4/src/stm32h7xx_it.c
Normal file
139
src/cm4/src/stm32h7xx_it.c
Normal file
@ -0,0 +1,139 @@
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/**
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******************************************************************************
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* @file PWR/PWR_STANDBY_RTC/CM4/Src/stm32h7xx_it.c
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* @author MCD Application Team
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* @brief Main Interrupt Service Routines.
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* This file provides template for all exceptions handler and
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* peripherals interrupt service routine.
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******************************************************************************
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* @attention
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*
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* <h2><center>© Copyright (c) 2019 STMicroelectronics.
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* All rights reserved.</center></h2>
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*
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* This software component is licensed by ST under BSD 3-Clause license,
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* the "License"; You may not use this file except in compliance with the
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* License. You may obtain a copy of the License at:
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* opensource.org/licenses/BSD-3-Clause
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*
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******************************************************************************
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*/
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#include STM32_HAL_H
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/**
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* @brief This function handles NMI exception.
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* @param None
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* @retval None
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*/
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void NMI_Handler(void)
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{
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}
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/**
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* @brief This function handles Hard Fault exception.
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* @param None
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* @retval None
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*/
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void HardFault_Handler(void)
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{
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/* Go to infinite loop when Hard Fault exception occurs */
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while (1)
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{
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}
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}
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/**
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* @brief This function handles Memory Manage exception.
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* @param None
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* @retval None
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*/
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void MemManage_Handler(void)
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{
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/* Go to infinite loop when Memory Manage exception occurs */
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while (1)
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|
{
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}
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}
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/**
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* @brief This function handles Bus Fault exception.
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* @param None
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* @retval None
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*/
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void BusFault_Handler(void)
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{
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/* Go to infinite loop when Bus Fault exception occurs */
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while (1)
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|
{
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|
}
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}
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/**
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* @brief This function handles Usage Fault exception.
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* @param None
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* @retval None
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*/
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void UsageFault_Handler(void)
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{
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/* Go to infinite loop when Usage Fault exception occurs */
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while (1)
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{
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}
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}
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/**
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* @brief This function handles SVCall exception.
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* @param None
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* @retval None
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*/
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void SVC_Handler(void)
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{
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}
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/**
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* @brief This function handles Debug Monitor exception.
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* @param None
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* @retval None
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*/
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void DebugMon_Handler(void)
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{
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}
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/**
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* @brief This function handles PendSVC exception.
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* @param None
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* @retval None
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*/
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void PendSV_Handler(void)
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{
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}
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/**
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* @brief This function handles SysTick Handler.
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* @param None
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* @retval None
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*/
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void SysTick_Handler(void)
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{
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HAL_IncTick();
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}
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/**
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* @brief This function handles HSEM2 wake-up interrupt request.
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* @param None
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* @retval None
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*/
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void HSEM2_IRQHandler(void)
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{
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}
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/**
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* @}
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*/
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/**
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* @}
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*/
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/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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102
src/cm4/stm32fxxx.ld.S
Normal file
102
src/cm4/stm32fxxx.ld.S
Normal file
@ -0,0 +1,102 @@
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/*
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* This file is part of the OpenMV project.
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*
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* Copyright (c) 2013-2021 Ibrahim Abdelkader <iabdalkader@openmv.io>
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* Copyright (c) 2013-2021 Kwabena W. Agyeman <kwagyeman@openmv.io>
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*
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* This work is licensed under the MIT license, see the file LICENSE for details.
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*
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* Linker script for STM32 Devices.
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*/
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/* Entry Point */
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ENTRY(Reset_Handler)
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#include "omv_boardconfig.h"
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/* Specify the memory areas */
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MEMORY
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{
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RAM (xrw) : ORIGIN = OMV_CM4_RAM_ORIGIN, LENGTH = OMV_CM4_RAM_LENGTH
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FLASH (rx) : ORIGIN = OMV_CM4_FLASH_ORIGIN, LENGTH = OMV_CM4_FLASH_LENGTH
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}
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_heap_size = (1 * 1024); /* heap size */
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_stack_size = (4 * 1024); /* stack size */
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/* Define output sections */
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SECTIONS
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{
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/* The program code and other data goes into FLASH */
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.text :
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|
{
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. = ALIGN(4);
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KEEP(*(.isr_vector))// ISR table
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. = ALIGN(4);
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*(.text) // .text sections (code)
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. = ALIGN(4);
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|
*(.text*) // .text* sections (code)
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|
. = ALIGN(4);
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|
*(.rodata) // .rodata sections (constants, strings, etc.)
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|
. = ALIGN(4);
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|
*(.rodata*) // .rodata* sections (constants, strings, etc.)
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|
. = ALIGN(4);
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|
_etext = .; // define a global symbols at end of code
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|
} >FLASH
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|
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/* used by the startup to initialize data */
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_sidata = LOADADDR(.data);
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|
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||||||
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/* Initialized data sections */
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.data :
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|
{
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|
. = ALIGN(4);
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||||||
|
_sdata = .; // Create a global symbol at data start
|
||||||
|
_ram_start = .;
|
||||||
|
*(.data) // .data sections
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|
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||||||
|
. = ALIGN(4);
|
||||||
|
*(.data*) // .data* sections
|
||||||
|
|
||||||
|
. = ALIGN(4);
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||||||
|
_edata = .; // define a global symbol at data end
|
||||||
|
} >RAM AT> FLASH
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||||||
|
|
||||||
|
/* Uninitialized data section */
|
||||||
|
. = ALIGN(4);
|
||||||
|
.bss (NOLOAD) :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
_sbss = .; // Used by the startup to initialize the .bss secion
|
||||||
|
. = ALIGN(4);
|
||||||
|
*(.bss*)
|
||||||
|
. = ALIGN(4);
|
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|
*(COMMON)
|
||||||
|
. = ALIGN(4);
|
||||||
|
_ebss = .; // define a global symbol at bss end
|
||||||
|
} >RAM
|
||||||
|
|
||||||
|
._heap (NOLOAD) :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
_heap_start = .;
|
||||||
|
. = . + _heap_size;
|
||||||
|
|
||||||
|
. = ALIGN(4);
|
||||||
|
_heap_end = .;
|
||||||
|
|
||||||
|
} >RAM
|
||||||
|
|
||||||
|
/* Make sure there is enough ram for the stack */
|
||||||
|
._stack (NOLOAD) :
|
||||||
|
{
|
||||||
|
. = ALIGN(8);
|
||||||
|
_sstack = .;
|
||||||
|
. = . + _stack_size;
|
||||||
|
|
||||||
|
. = ALIGN(8);
|
||||||
|
_estack = .;
|
||||||
|
} >RAM
|
||||||
|
|
||||||
|
.ARM.attributes 0 : { *(.ARM.attributes) }
|
||||||
|
}
|
||||||
@ -97,8 +97,13 @@ void SystemInit(void)
|
|||||||
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
|
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
|
||||||
SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
|
SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
|
||||||
#endif
|
#endif
|
||||||
/* Reset the RCC clock configuration to the default reset state ------------*/
|
|
||||||
|
|
||||||
|
/*SEVONPEND enabled so that an interrupt coming from the CPU(n) interrupt
|
||||||
|
signal is detectable by the CPU after a WFI/WFE instruction. */
|
||||||
|
//SCB->SCR |= SCB_SCR_SEVONPEND_Msk;
|
||||||
|
|
||||||
|
#if !defined(CORE_CM4)
|
||||||
|
/* Reset the RCC clock configuration to the default reset state ------------*/
|
||||||
/* Set HSION bit */
|
/* Set HSION bit */
|
||||||
RCC->CR |= CONFIG_RCC_CR_1ST;
|
RCC->CR |= CONFIG_RCC_CR_1ST;
|
||||||
|
|
||||||
@ -159,13 +164,6 @@ void SystemInit(void)
|
|||||||
*((__IO uint32_t*)0x51008108) = 0x00000001;
|
*((__IO uint32_t*)0x51008108) = 0x00000001;
|
||||||
#endif // defined(MCU_SERIES_H7)
|
#endif // defined(MCU_SERIES_H7)
|
||||||
|
|
||||||
/* Configure the Vector Table location add offset address ------------------*/
|
|
||||||
#ifdef VECT_TAB_SRAM
|
|
||||||
SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
|
|
||||||
#else
|
|
||||||
SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/* dpgeorge: enable 8-byte stack alignment for IRQ handlers, in accord with EABI */
|
/* dpgeorge: enable 8-byte stack alignment for IRQ handlers, in accord with EABI */
|
||||||
SCB->CCR |= SCB_CCR_STKALIGN_Msk;
|
SCB->CCR |= SCB_CCR_STKALIGN_Msk;
|
||||||
|
|
||||||
@ -178,6 +176,15 @@ void SystemInit(void)
|
|||||||
DBGMCU->CR |= DBGMCU_CR_DBG_STANDBYD1;
|
DBGMCU->CR |= DBGMCU_CR_DBG_STANDBYD1;
|
||||||
#endif
|
#endif
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
|
#endif // !defined(CORE_CM4)
|
||||||
|
|
||||||
|
/* Configure the Vector Table location add offset address ------------------*/
|
||||||
|
#ifdef VECT_TAB_SRAM
|
||||||
|
SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
|
||||||
|
#else
|
||||||
|
SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
|
||||||
|
#endif
|
||||||
}
|
}
|
||||||
|
|
||||||
void SystemClock_Config(void)
|
void SystemClock_Config(void)
|
||||||
@ -366,4 +373,9 @@ void SystemClock_Config(void)
|
|||||||
// Enable the USB voltage level detector
|
// Enable the USB voltage level detector
|
||||||
HAL_PWREx_EnableUSBVoltageDetector();
|
HAL_PWREx_EnableUSBVoltageDetector();
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
|
#if defined(CORE_CM7) && defined(M4_APP_ADDR)
|
||||||
|
HAL_SYSCFG_CM4BootAddConfig(SYSCFG_BOOT_ADDR0, M4_APP_ADDR);
|
||||||
|
HAL_RCCEx_EnableBootCore(RCC_BOOT_C2);
|
||||||
|
#endif
|
||||||
}
|
}
|
||||||
|
|||||||
@ -38,8 +38,8 @@
|
|||||||
#define OMV_OV7725_BANDING (0x7F)
|
#define OMV_OV7725_BANDING (0x7F)
|
||||||
|
|
||||||
// Bootloader LED GPIO port/pin
|
// Bootloader LED GPIO port/pin
|
||||||
#define OMV_BOOTLDR_LED_PIN (GPIO_PIN_1)
|
#define OMV_BOOTLDR_LED_PIN (GPIO_PIN_6)
|
||||||
#define OMV_BOOTLDR_LED_PORT (GPIOC)
|
#define OMV_BOOTLDR_LED_PORT (GPIOK)
|
||||||
|
|
||||||
// RAW buffer size
|
// RAW buffer size
|
||||||
#define OMV_RAW_BUF_SIZE (4*1024*1024)
|
#define OMV_RAW_BUF_SIZE (4*1024*1024)
|
||||||
@ -152,7 +152,7 @@
|
|||||||
#define OMV_FB_SIZE (4M) // FB memory: header + VGA/GS image
|
#define OMV_FB_SIZE (4M) // FB memory: header + VGA/GS image
|
||||||
#define OMV_FB_ALLOC_SIZE (3M) // minimum fb alloc size
|
#define OMV_FB_ALLOC_SIZE (3M) // minimum fb alloc size
|
||||||
#define OMV_STACK_SIZE (64K)
|
#define OMV_STACK_SIZE (64K)
|
||||||
#define OMV_HEAP_SIZE (196K)
|
#define OMV_HEAP_SIZE (180K)
|
||||||
#define OMV_SDRAM_SIZE (8 * 1024 * 1024) // This needs to be here for UVC firmware.
|
#define OMV_SDRAM_SIZE (8 * 1024 * 1024) // This needs to be here for UVC firmware.
|
||||||
|
|
||||||
#define OMV_LINE_BUF_SIZE (11 * 1024) // Image line buffer round(2592 * 2BPP * 2 buffers).
|
#define OMV_LINE_BUF_SIZE (11 * 1024) // Image line buffer round(2592 * 2BPP * 2 buffers).
|
||||||
@ -168,8 +168,8 @@
|
|||||||
#define OMV_DTCM_ORIGIN 0x20000000 // Note accessible by CPU and MDMA only.
|
#define OMV_DTCM_ORIGIN 0x20000000 // Note accessible by CPU and MDMA only.
|
||||||
#define OMV_DTCM_LENGTH 128K
|
#define OMV_DTCM_LENGTH 128K
|
||||||
#define OMV_SRAM1_ORIGIN 0x30000000
|
#define OMV_SRAM1_ORIGIN 0x30000000
|
||||||
#define OMV_SRAM1_LENGTH 272K // SRAM1 + SRAM2 + 1/2 SRAM3
|
#define OMV_SRAM1_LENGTH 256K // SRAM1 + SRAM2
|
||||||
#define OMV_SRAM3_ORIGIN 0x30044000
|
#define OMV_SRAM3_ORIGIN 0x30040000 // Second half of SRAM3 reserved for M4.
|
||||||
#define OMV_SRAM3_LENGTH 16K
|
#define OMV_SRAM3_LENGTH 16K
|
||||||
#define OMV_SRAM4_ORIGIN 0x38000000
|
#define OMV_SRAM4_ORIGIN 0x38000000
|
||||||
#define OMV_SRAM4_LENGTH 64K
|
#define OMV_SRAM4_LENGTH 64K
|
||||||
@ -179,6 +179,10 @@
|
|||||||
#define OMV_DRAM_LENGTH 8M
|
#define OMV_DRAM_LENGTH 8M
|
||||||
#define OMV_FLASH_EXT_ORIGIN 0x90000000
|
#define OMV_FLASH_EXT_ORIGIN 0x90000000
|
||||||
#define OMV_FLASH_EXT_LENGTH 16M
|
#define OMV_FLASH_EXT_LENGTH 16M
|
||||||
|
#define OMV_CM4_RAM_ORIGIN 0x30044000 // Cortex-M4 memory.
|
||||||
|
#define OMV_CM4_RAM_LENGTH 16K
|
||||||
|
#define OMV_CM4_FLASH_ORIGIN 0x08020000
|
||||||
|
#define OMV_CM4_FLASH_LENGTH 128K
|
||||||
|
|
||||||
// Domain 1 DMA buffers region.
|
// Domain 1 DMA buffers region.
|
||||||
#define OMV_DMA_MEMORY_D1 AXI_SRAM
|
#define OMV_DMA_MEMORY_D1 AXI_SRAM
|
||||||
|
|||||||
@ -8,11 +8,14 @@ HAL_INC='<stm32h7xx_hal.h>'
|
|||||||
CFLAGS_MCU=MCU_SERIES_H7
|
CFLAGS_MCU=MCU_SERIES_H7
|
||||||
VECT_TAB_OFFSET=0x40000
|
VECT_TAB_OFFSET=0x40000
|
||||||
MAIN_APP_ADDR=0x08040000
|
MAIN_APP_ADDR=0x08040000
|
||||||
|
M4_VECT_TAB_OFFSET=0x20000
|
||||||
|
M4_APP_ADDR=0x08020000
|
||||||
OMV_HSE_VALUE=25000000
|
OMV_HSE_VALUE=25000000
|
||||||
DFU_DEVICE=0x2341:0x035b
|
DFU_DEVICE=0x2341:0x035b
|
||||||
OMV_BOARD_EXTRA_CFLAGS = -DCORE_CM7
|
OMV_BOARD_EXTRA_CFLAGS = -DCORE_CM7
|
||||||
OMV_ENABLE_BL=0
|
OMV_ENABLE_BL=0
|
||||||
OMV_ENABLE_UVC=1
|
OMV_ENABLE_UVC=1
|
||||||
|
OMV_ENABLE_CM4=0
|
||||||
MICROPY_PY_SENSOR = 1
|
MICROPY_PY_SENSOR = 1
|
||||||
MICROPY_PY_ULAB = 1
|
MICROPY_PY_ULAB = 1
|
||||||
MICROPY_PY_WINC1500 = 0
|
MICROPY_PY_WINC1500 = 0
|
||||||
|
|||||||
@ -66,6 +66,21 @@ UVC_LDFLAGS = -mcpu=$(CPU) -mabi=aapcs-linux -mthumb -mfpu=$(FPU) -mfloat-abi=ha
|
|||||||
-nostdlib -Wl,--gc-sections -Wl,-T$(BUILD)/$(UVC_DIR)/stm32fxxx.lds
|
-nostdlib -Wl,--gc-sections -Wl,-T$(BUILD)/$(UVC_DIR)/stm32fxxx.lds
|
||||||
endif
|
endif
|
||||||
|
|
||||||
|
ifeq ($(OMV_ENABLE_CM4), 1)
|
||||||
|
CFLAGS += -DM4_APP_ADDR=$(M4_APP_ADDR)
|
||||||
|
CM4_CFLAGS += -std=gnu99 -Wall -Werror -Warray-bounds -mthumb -nostartfiles -fdata-sections -ffunction-sections
|
||||||
|
CM4_CFLAGS += -D$(MCU) -D$(CFLAGS_MCU) -D$(ARM_MATH) -DARM_NN_TRUNCATE -DCORE_CM4\
|
||||||
|
-fsingle-precision-constant -Wdouble-promotion -mcpu=cortex-m4 -mtune=cortex-m4 -mfpu=$(FPU) -mfloat-abi=hard
|
||||||
|
CM4_CFLAGS += -D__FPU_PRESENT=1 -D__VFP_FP__ -DHSE_VALUE=$(OMV_HSE_VALUE)\
|
||||||
|
-D$(TARGET) -DVECT_TAB_OFFSET=$(M4_VECT_TAB_OFFSET) -DMAIN_APP_ADDR=$(M4_APP_ADDR) -DSTM32_HAL_H=$(HAL_INC)
|
||||||
|
CM4_CFLAGS += $(HAL_CFLAGS)
|
||||||
|
CM4_CFLAGS += -I$(OMV_BOARD_CONFIG_DIR)
|
||||||
|
CM4_CFLAGS += -I$(TOP_DIR)/$(CM4_DIR)/include/
|
||||||
|
# Linker Flags
|
||||||
|
CM4_LDFLAGS = -mcpu=cortex-m4 -mabi=aapcs-linux -mthumb -mfpu=$(FPU) -mfloat-abi=hard\
|
||||||
|
-nostdlib -Wl,--gc-sections -Wl,-T$(BUILD)/$(CM4_DIR)/stm32fxxx.lds
|
||||||
|
endif
|
||||||
|
|
||||||
CFLAGS += $(HAL_CFLAGS) $(MPY_CFLAGS) $(OMV_CFLAGS)
|
CFLAGS += $(HAL_CFLAGS) $(MPY_CFLAGS) $(OMV_CFLAGS)
|
||||||
|
|
||||||
# Linker Flags
|
# Linker Flags
|
||||||
@ -498,6 +513,17 @@ UVC_OBJ += $(wildcard $(BUILD)/$(MLX90640_DIR)/src/*.o)
|
|||||||
UVC_OBJ += $(wildcard $(BUILD)/$(MLX90641_DIR)/src/*.o)
|
UVC_OBJ += $(wildcard $(BUILD)/$(MLX90641_DIR)/src/*.o)
|
||||||
endif
|
endif
|
||||||
|
|
||||||
|
ifeq ($(OMV_ENABLE_CM4), 1)
|
||||||
|
CM4 = cm4
|
||||||
|
# CM4 object files
|
||||||
|
CM4_OBJ += $(wildcard $(BUILD)/$(CM4_DIR)/src/*.o)
|
||||||
|
CM4_OBJ += $(wildcard $(BUILD)/$(CM4_DIR)/$(HAL_DIR)/src/*.o)
|
||||||
|
CM4_OBJ += $(addprefix $(BUILD)/$(CM4_DIR)/$(CMSIS_DIR)/src/, \
|
||||||
|
$(STARTUP).o \
|
||||||
|
$(SYSTEM).o \
|
||||||
|
)
|
||||||
|
endif
|
||||||
|
|
||||||
###################################################
|
###################################################
|
||||||
#Export Variables
|
#Export Variables
|
||||||
export Q
|
export Q
|
||||||
@ -519,6 +545,8 @@ export STARTUP
|
|||||||
export SYSTEM
|
export SYSTEM
|
||||||
export FROZEN_MANIFEST
|
export FROZEN_MANIFEST
|
||||||
export PORT
|
export PORT
|
||||||
|
export HAL_DIR
|
||||||
|
export CMSIS_DIR
|
||||||
###################################################
|
###################################################
|
||||||
all: $(OPENMV)
|
all: $(OPENMV)
|
||||||
|
|
||||||
@ -550,6 +578,10 @@ ifeq ($(OMV_ENABLE_UVC), 1)
|
|||||||
UVC_OBJS: FIRMWARE_OBJS
|
UVC_OBJS: FIRMWARE_OBJS
|
||||||
$(MAKE) -C $(UVC_DIR) BUILD=$(BUILD)/$(UVC_DIR) CFLAGS="$(UVC_CFLAGS) -MMD"
|
$(MAKE) -C $(UVC_DIR) BUILD=$(BUILD)/$(UVC_DIR) CFLAGS="$(UVC_CFLAGS) -MMD"
|
||||||
endif
|
endif
|
||||||
|
ifeq ($(OMV_ENABLE_CM4), 1)
|
||||||
|
CM4_OBJS: FIRMWARE_OBJS
|
||||||
|
$(MAKE) -C $(CM4_DIR) BUILD=$(BUILD)/$(CM4_DIR) CFLAGS="$(CM4_CFLAGS) -MMD"
|
||||||
|
endif
|
||||||
ifeq ($(OMV_ENABLE_BL), 1)
|
ifeq ($(OMV_ENABLE_BL), 1)
|
||||||
BOOTLOADER_OBJS: FIRMWARE_OBJS
|
BOOTLOADER_OBJS: FIRMWARE_OBJS
|
||||||
$(MAKE) -C $(BOOTLDR_DIR) BUILD=$(BUILD)/$(BOOTLDR_DIR) CFLAGS="$(BL_CFLAGS) -MMD"
|
$(MAKE) -C $(BOOTLDR_DIR) BUILD=$(BUILD)/$(BOOTLDR_DIR) CFLAGS="$(BL_CFLAGS) -MMD"
|
||||||
@ -580,8 +612,17 @@ $(UVC): FIRMWARE_OBJS UVC_OBJS
|
|||||||
$(PYTHON) $(MKDFU) -D $(DFU_DEVICE) -b $(MAIN_APP_ADDR):$(FW_DIR)/$(UVC).bin $(FW_DIR)/$(UVC).dfu
|
$(PYTHON) $(MKDFU) -D $(DFU_DEVICE) -b $(MAIN_APP_ADDR):$(FW_DIR)/$(UVC).bin $(FW_DIR)/$(UVC).dfu
|
||||||
endif
|
endif
|
||||||
|
|
||||||
|
ifeq ($(OMV_ENABLE_CM4), 1)
|
||||||
|
# This target generates CM4 firmware for dual core micros.
|
||||||
|
$(CM4): FIRMWARE_OBJS CM4_OBJS
|
||||||
|
$(CPP) -P -E -I$(OMV_BOARD_CONFIG_DIR) $(CM4_DIR)/stm32fxxx.ld.S > $(BUILD)/$(CM4_DIR)/stm32fxxx.lds
|
||||||
|
$(CC) $(CM4_LDFLAGS) $(CM4_OBJ) -o $(FW_DIR)/$(CM4).elf -lgcc
|
||||||
|
$(OBJCOPY) -Obinary $(FW_DIR)/$(CM4).elf $(FW_DIR)/$(CM4).bin
|
||||||
|
$(PYTHON) $(MKDFU) -D $(DFU_DEVICE) -b $(M4_APP_ADDR):$(FW_DIR)/$(CM4).bin $(FW_DIR)/$(CM4).dfu
|
||||||
|
endif
|
||||||
|
|
||||||
# This target generates the uvc, bootloader and firmware images.
|
# This target generates the uvc, bootloader and firmware images.
|
||||||
$(OPENMV): $(BOOTLOADER) $(UVC) $(FIRMWARE)
|
$(OPENMV): $(BOOTLOADER) $(UVC) $(CM4) $(FIRMWARE)
|
||||||
ifeq ($(OMV_ENABLE_BL), 1)
|
ifeq ($(OMV_ENABLE_BL), 1)
|
||||||
$(SIZE) $(FW_DIR)/$(BOOTLOADER).elf
|
$(SIZE) $(FW_DIR)/$(BOOTLOADER).elf
|
||||||
endif
|
endif
|
||||||
|
|||||||
Loading…
Reference in New Issue
Block a user