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Merge pull request #2614 from kwagyeman/kwabena/update_issd_seq
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sensors/genx320: Update ISSD sequence to increase frame rate.
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commit
72be5c373c
@ -121,11 +121,24 @@ static const struct reg_op dcmi_init_seq[] = {
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{.op = WRITE, .args = {.write = {0x111CUL, 0x03000074}} }, // saphir/bias/bias_req_pu_lv0 Write fields: bias_en|bias_ctl
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{.op = WRITE, .args = {.write = {0x1120UL, 0x010000A4}} }, // saphir/bias/bias_sm_pdy_lv0 Write fields: bias_en|bias_ctl
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{.op = WRITE, .args = {.write = {0x1208UL, 0x00000035}} }, // saphir/bias/bgen_ctrl Write fields: burst_transfer_hv_bank_0|burst_transfer_lv_bank_0
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{.op = WRITE, .args = {.write = {0x0000UL, 0x00000802}} } // saphir/roi_ctrl Write fields: roi_td_en
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{.op = WRITE, .args = {.write = {0x0000UL, 0x00000802}} }, // saphir/roi_ctrl Write fields: roi_td_en
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{.op = WRITE, .args = {.write = {0x009008, 0x00000184}} },
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{.op = WRITE, .args = {.write = {0x009008, 0x00010184}} },
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{.op = WRITE, .args = {.write = {0x000200, 0x00000000}} },
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{.op = WRITE, .args = {.write = {0x000214, 0x00000440}} },
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{.op = WRITE, .args = {.write = {0x000214, 0x00000441}} },
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{.op = WRITE, .args = {.write = {0x000204, 0x00000634}} },
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{.op = WRITE, .args = {.write = {0x00020C, 0x00000061}} },
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{.op = WRITE, .args = {.write = {0x000204, 0x00000635}} },
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{.op = WRITE, .args = {.write = {0x000204, 0x00000637}} },
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{.op = WRITE, .args = {.write = {0x000210, 0x00000C00}} },
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{.op = WRITE, .args = {.write = {0x00B00C, 0x00000004}} },
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{.op = WRITE, .args = {.write = {0x009008, 0x00000304}} },
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{.op = WRITE, .args = {.write = {0x00004C, 0x00209600}} }
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};
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static const struct reg_op dcmi_start_seq[] = {
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{.op = WRITE, .args = {.write = {0x9028UL, 0x00000000}} }, // saphir/ro/ro_lp_ctrl Write fields: lp_output_disable
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{.op = WRITE, .args = {.write = {0x9008UL, 0x000000A5}} }, // saphir/ro/time_base_ctrl Write fields: time_base_enable
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{.op = WRITE, .args = {.write = {0x9008UL, 0x00000305}} }, // saphir/ro/time_base_ctrl Write fields: time_base_enable
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{.op = DELAY, .args = {.delay = {1000}} }, // us
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{.op = WRITE, .args = {.write = {0x002CUL, 0x0022C724}} }, // saphir/ro_td_ctrl Write fields: ro_td_ack_y_rstn|ro_td_arb_y_rstn|ro_td_addr_y_rstn|ro_td_sendreq_y_rstn
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{.op = WRITE, .args = {.write = {0x0000UL, 0x00000C02}} }, // saphir/roi_ctrl Write fields: roi_td_en|px_sw_rstn
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@ -136,7 +149,7 @@ static const struct reg_op dcmi_stop_seq[] = {
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{.op = WRITE, .args = {.write = {0x002CUL, 0x00200624}} }, // saphir/ro_td_ctrl Write fields: ro_td_ack_y_rstn|ro_td_arb_y_rstn|ro_td_addr_y_rstn|ro_td_sendreq_y_rstn
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{.op = WRITE, .args = {.write = {0x9028UL, 0x00000002}} }, // saphir/ro/ro_lp_ctrl Write fields: lp_output_disable|lp_keep_th
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{.op = DELAY, .args = {.delay = {1000}} }, // us
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{.op = WRITE, .args = {.write = {0x9008UL, 0x000000A4}} }, // saphir/ro/time_base_ctrl Write fields: time_base_enable
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{.op = WRITE, .args = {.write = {0x9008UL, 0x00000304}} }, // saphir/ro/time_base_ctrl Write fields: time_base_enable
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{.op = WRITE, .args = {.write = {0x8000UL, 0x0001FFA2}} }, // saphir/cpi/pipeline_control Write fields: enable|drop_nbackpressure|hot_disable_enable
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{.op = READ, .args = {.read = {0x8004UL, 0x00000002}} }, // saphir/cpi/pipeline_status Read fields: busy
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{.op = DELAY, .args = {.delay = {1000}} } // us
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@ -120,12 +120,25 @@ static const struct reg_op dcmi_init_seq[] = {
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{.op = WRITE, .args = {.write = {0x111CUL, 0x03000074}} }, // saphir/bias/bias_req_pu_lv0 Write fields: bias_en|bias_ctl
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{.op = WRITE, .args = {.write = {0x1120UL, 0x010000A4}} }, // saphir/bias/bias_sm_pdy_lv0 Write fields: bias_en|bias_ctl
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{.op = WRITE, .args = {.write = {0x1208UL, 0x00000035}} }, // saphir/bias/bgen_ctrl Write fields: burst_transfer_hv_bank_0|burst_transfer_lv_bank_0
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{.op = WRITE, .args = {.write = {0x0000UL, 0x00000802}} } // saphir/roi_ctrl Write fields: roi_td_en
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{.op = WRITE, .args = {.write = {0x0000UL, 0x00000802}} }, // saphir/roi_ctrl Write fields: roi_td_en
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{.op = WRITE, .args = {.write = {0x009008, 0x00000184}} },
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{.op = WRITE, .args = {.write = {0x009008, 0x00010184}} },
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{.op = WRITE, .args = {.write = {0x000200, 0x00000000}} },
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{.op = WRITE, .args = {.write = {0x000214, 0x00000440}} },
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{.op = WRITE, .args = {.write = {0x000214, 0x00000441}} },
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{.op = WRITE, .args = {.write = {0x000204, 0x00000634}} },
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{.op = WRITE, .args = {.write = {0x00020C, 0x00000061}} },
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{.op = WRITE, .args = {.write = {0x000204, 0x00000635}} },
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{.op = WRITE, .args = {.write = {0x000204, 0x00000637}} },
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{.op = WRITE, .args = {.write = {0x000210, 0x00000C00}} },
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{.op = WRITE, .args = {.write = {0x00B00C, 0x00000004}} },
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{.op = WRITE, .args = {.write = {0x009008, 0x00000304}} },
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{.op = WRITE, .args = {.write = {0x00004C, 0x00209600}} }
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};
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static const struct reg_op dcmi_start_seq[] = {
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{.op = WRITE, .args = {.write = {0x8000UL, 0x0001FEA1}} }, // saphir/cpi/pipeline_control
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{.op = WRITE, .args = {.write = {0x9028UL, 0x00000000}} }, // saphir/ro/ro_lp_ctrl Write fields: lp_output_disable
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{.op = WRITE, .args = {.write = {0x9008UL, 0x000000A5}} }, // saphir/ro/time_base_ctrl Write fields: time_base_enable
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{.op = WRITE, .args = {.write = {0x9008UL, 0x00000305}} }, // saphir/ro/time_base_ctrl Write fields: time_base_enable
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{.op = DELAY, .args = {.delay = {1000}} }, // us
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{.op = WRITE, .args = {.write = {0x002CUL, 0x0022C724}} }, // saphir/ro_td_ctrl Write fields: ro_td_ack_y_rstn|ro_td_arb_y_rstn|ro_td_addr_y_rstn|ro_td_sendreq_y_rstn
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{.op = WRITE, .args = {.write = {0x0000UL, 0x00000C02}} }, // saphir/roi_ctrl Write fields: roi_td_en|px_sw_rstn
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@ -136,7 +149,7 @@ static const struct reg_op dcmi_stop_seq[] = {
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{.op = WRITE, .args = {.write = {0x002CUL, 0x00200624}} }, // saphir/ro_td_ctrl Write fields: ro_td_ack_y_rstn|ro_td_arb_y_rstn|ro_td_addr_y_rstn|ro_td_sendreq_y_rstn
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{.op = WRITE, .args = {.write = {0x9028UL, 0x00000002}} }, // saphir/ro/ro_lp_ctrl Write fields: lp_output_disable|lp_keep_th
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{.op = DELAY, .args = {.delay = {1000}} }, // us
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{.op = WRITE, .args = {.write = {0x9008UL, 0x000000A4}} }, // saphir/ro/time_base_ctrl Write fields: time_base_enable
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{.op = WRITE, .args = {.write = {0x9008UL, 0x00000304}} }, // saphir/ro/time_base_ctrl Write fields: time_base_enable
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{.op = WRITE, .args = {.write = {0x8000UL, 0x0001FFA2}} }, // saphir/cpi/pipeline_control Write fields: enable|drop_nbackpressure|hot_disable_enable
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{.op = READ, .args = {.read = {0x8004UL, 0x00000002}} }, // saphir/cpi/pipeline_status Read fields: busy
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{.op = DELAY, .args = {.delay = {1000}} } // us
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@ -158,4 +171,4 @@ const struct issd dcmi_histo = {
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.len = ARRAY_SIZE(dcmi_destroy_seq)},
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};
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#endif
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#endif
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@ -49,8 +49,12 @@
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#define ACTIVE_SENSOR_HEIGHT (SENSOR_HEIGHT - BLANK_LINES)
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#define ACTIVE_SENSOR_SIZE (ACTIVE_SENSOR_WIDTH * ACTIVE_SENSOR_HEIGHT)
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#define HSYNC_CLOCK_CYCLES 32
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#define VSYNC_CLOCK_CYCLES 32
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#ifdef OMV_GENX320_EHC_ENABLE
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#define HSYNC_CLOCK_CYCLES 880 // 320 + 880 = 1200 cycles -> ~122 FPS
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#else
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#define HSYNC_CLOCK_CYCLES 280 // 320 + 280 = 600 cycles
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#endif
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#define VSYNC_CLOCK_CYCLES 8
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#define CONTRAST_DEFAULT 16
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#define BRIGHTNESS_DEFAULT 128
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@ -66,8 +70,8 @@
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#define EVENT_THRESHOLD_TO_CALIBRATE 100000
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#define EVENT_THRESHOLD_SIGMA 10
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#define EVT_CLK_FREQ ((omv_csi_get_xclk_frequency() + 500000) / 1000000)
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#define EVT_SCALE_PERIOD(period) (((period) * EVT_CLK_FREQ) / 10)
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#define EVT_CLK_MULTIPLIER (2)
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#define EVT_CLK_FREQ (((omv_csi_get_xclk_frequency() * EVT_CLK_MULTIPLIER) + 500000) / 1000000)
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#define AFK_50_HZ (50)
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#define AFK_60_HZ (60)
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@ -115,6 +119,7 @@ static int reset(omv_csi_t *csi) {
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// Set EVT20 mode
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psee_sensor_write(EDF_CONTROL, 0);
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#endif // (OMV_GENX320_EHC_ENABLE == 1)
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// Configure Packet and Frame sizes
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psee_sensor_write(CPI_PACKET_SIZE_CONTROL, ACTIVE_SENSOR_WIDTH);
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@ -122,7 +127,6 @@ static int reset(omv_csi_t *csi) {
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HSYNC_CLOCK_CYCLES << CPI_PACKET_TIME_CONTROL_BLANKING_Pos);
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psee_sensor_write(CPI_FRAME_SIZE_CONTROL, ACTIVE_SENSOR_HEIGHT);
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psee_sensor_write(CPI_FRAME_TIME_CONTROL, VSYNC_CLOCK_CYCLES);
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#endif // (OMV_GENX320_EHC_ENABLE == 1)
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// Enable dropping
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psee_sensor_write(RO_READOUT_CTRL, RO_READOUT_CTRL_DIGITAL_PIPE_EN |
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@ -166,7 +170,7 @@ static int reset(omv_csi_t *csi) {
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}
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if (psee_ehc_activate(&psee_ehc, EHC_ALGO_DIFF3D, 0, EHC_DIFF3D_N_BITS_SIZE,
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EVT_SCALE_PERIOD(INTEGRATION_DEF_PREIOD), EHC_WITHOUT_PADDING) != EHC_OK) {
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INTEGRATION_DEF_PREIOD, EHC_WITHOUT_PADDING) != EHC_OK) {
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return -1;
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}
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#else
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@ -231,7 +235,26 @@ static int set_framerate(omv_csi_t *csi, int framerate) {
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return -1;
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}
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psee_sensor_write(EHC_INTEGRATION_PERIOD, EVT_SCALE_PERIOD(us));
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int lines = ACTIVE_SENSOR_HEIGHT + VSYNC_CLOCK_CYCLES;
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int clocks_per_frame = (omv_csi_get_xclk_frequency() * EVT_CLK_MULTIPLIER) / framerate;
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int hsync_clocks = (clocks_per_frame / lines) - ACTIVE_SENSOR_WIDTH;
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if (hsync_clocks <= 0) {
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return -1;
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}
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// Disable any ongoing frame capture.
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omv_csi_abort(true, false);
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psee_sensor_write(EHC_INTEGRATION_PERIOD, us);
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psee_sensor_write(CPI_PACKET_TIME_CONTROL, ACTIVE_SENSOR_WIDTH << CPI_PACKET_TIME_CONTROL_PERIOD_Pos |
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hsync_clocks << CPI_PACKET_TIME_CONTROL_BLANKING_Pos);
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// Wait for the camera to settle
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if (!csi->disable_delays) {
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mp_hal_delay_ms(100);
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}
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#endif // (OMV_GENX320_EHC_ENABLE == 1)
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return 0;
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}
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@ -370,6 +393,12 @@ static void snapshot_post_process(image_t *image) {
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}
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static int snapshot(omv_csi_t *csi, image_t *image, uint32_t flags) {
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#if (OMV_GENX320_EHC_ENABLE != 1)
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if (csi->transpose) {
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return OMV_CSI_ERROR_CAPTURE_FAILED;
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}
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#endif
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#if (OMV_GENX320_CAL_ENABLE == 1)
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if (!hot_pixels_disabled) {
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uint8_t *histogram = fb_alloc0(ACTIVE_SENSOR_SIZE, FB_ALLOC_NO_HINT);
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