mirror of
https://github.com/openmv/openmv.git
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Add Bormio board.
This commit is contained in:
parent
6dfb966204
commit
7677b44feb
@ -1 +1 @@
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Subproject commit 410facda0d86b8f5d29142c2333708b7611a449c
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Subproject commit 02739879284e16bbaeb317f930d5de577c892659
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152
src/omv/boards/BORMIO/imlib_config.h
Normal file
152
src/omv/boards/BORMIO/imlib_config.h
Normal file
@ -0,0 +1,152 @@
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/*
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* This file is part of the OpenMV project.
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*
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* Copyright (c) 2013-2019 Ibrahim Abdelkader <iabdalkader@openmv.io>
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* Copyright (c) 2013-2019 Kwabena W. Agyeman <kwagyeman@openmv.io>
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*
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* This work is licensed under the MIT license, see the file LICENSE for details.
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*
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* Image library configuration.
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*/
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#ifndef __IMLIB_CONFIG_H__
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#define __IMLIB_CONFIG_H__
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// Enable Image I/O
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#define IMLIB_ENABLE_IMAGE_IO
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// Enable Image File I/O
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#define IMLIB_ENABLE_IMAGE_FILE_IO
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// Enable LAB LUT
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//#define IMLIB_ENABLE_LAB_LUT
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// Enable YUV LUT
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//#define IMLIB_ENABLE_YUV_LUT
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// Enable mean pooling
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#define IMLIB_ENABLE_MEAN_POOLING
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// Enable midpoint pooling
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#define IMLIB_ENABLE_MIDPOINT_POOLING
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// Enable binary ops
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#define IMLIB_ENABLE_BINARY_OPS
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// Enable math ops
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#define IMLIB_ENABLE_MATH_OPS
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// Enable flood_fill()
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#define IMLIB_ENABLE_FLOOD_FILL
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// Enable mean()
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#define IMLIB_ENABLE_MEAN
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// Enable median()
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#define IMLIB_ENABLE_MEDIAN
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// Enable mode()
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#define IMLIB_ENABLE_MODE
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// Enable midpoint()
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#define IMLIB_ENABLE_MIDPOINT
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// Enable morph()
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#define IMLIB_ENABLE_MORPH
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// Enable Gaussian
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#define IMLIB_ENABLE_GAUSSIAN
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// Enable Laplacian
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#define IMLIB_ENABLE_LAPLACIAN
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// Enable bilateral()
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#define IMLIB_ENABLE_BILATERAL
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// Enable cartoon()
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// #define IMLIB_ENABLE_CARTOON
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// Enable linpolar()
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#define IMLIB_ENABLE_LINPOLAR
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// Enable logpolar()
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#define IMLIB_ENABLE_LOGPOLAR
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// Enable lens_corr()
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#define IMLIB_ENABLE_LENS_CORR
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// Enable rotation_corr()
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#define IMLIB_ENABLE_ROTATION_CORR
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// Enable phasecorrelate()
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#if defined(IMLIB_ENABLE_ROTATION_CORR)
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#define IMLIB_ENABLE_FIND_DISPLACEMENT
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#endif
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// Enable get_similarity()
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#define IMLIB_ENABLE_GET_SIMILARITY
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// Enable find_lines()
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#define IMLIB_ENABLE_FIND_LINES
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// Enable find_line_segments()
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#define IMLIB_ENABLE_FIND_LINE_SEGMENTS
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// Enable find_circles()
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#define IMLIB_ENABLE_FIND_CIRCLES
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// Enable find_rects()
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#define IMLIB_ENABLE_FIND_RECTS
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// Enable find_qrcodes() (14 KB)
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#define IMLIB_ENABLE_QRCODES
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// Enable find_apriltags() (64 KB)
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#define IMLIB_ENABLE_APRILTAGS
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// Enable fine find_apriltags() - (8-way connectivity versus 4-way connectivity)
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// #define IMLIB_ENABLE_FINE_APRILTAGS
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// Enable high res find_apriltags() - uses more RAM
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// #define IMLIB_ENABLE_HIGH_RES_APRILTAGS
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// Enable find_datamatrices() (26 KB)
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#define IMLIB_ENABLE_DATAMATRICES
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// Enable find_barcodes() (42 KB)
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#define IMLIB_ENABLE_BARCODES
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// Enable CMSIS NN
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// #if !defined(CUBEAI)
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// #define IMLIB_ENABLE_CNN
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// #endif
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// Enable Tensor Flow
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#if !defined(CUBEAI)
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#define IMLIB_ENABLE_TF
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#endif
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// Enable FAST (20+ KBs).
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#define IMLIB_ENABLE_FAST
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// Enable find_template()
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#define IMLIB_FIND_TEMPLATE
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// Enable find_lbp()
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#define IMLIB_ENABLE_FIND_LBP
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// Enable find_keypoints()
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#define IMLIB_ENABLE_FIND_KEYPOINTS
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// Enable load, save and match descriptor
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#define IMLIB_ENABLE_DESCRIPTOR
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// Enable find_hog()
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#define IMLIB_ENABLE_HOG
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// Enable selective_search()
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#define IMLIB_ENABLE_SELECTIVE_SEARCH
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// Enable STM32 DMA2D
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#define IMLIB_ENABLE_DMA2D
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#endif //__IMLIB_CONFIG_H__
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8
src/omv/boards/BORMIO/manifest.py
Normal file
8
src/omv/boards/BORMIO/manifest.py
Normal file
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include("$(MPY_DIR)/extmod/uasyncio/manifest.py")
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freeze ("$(MPY_LIB_DIR)/", "modbus.py")
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freeze ("$(MPY_LIB_DIR)/", "mqtt.py")
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freeze ("$(MPY_LIB_DIR)/", "mutex.py")
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freeze ("$(MPY_LIB_DIR)/", "pid.py")
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freeze ("$(MPY_LIB_DIR)/", "rpc.py")
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freeze ("$(MPY_LIB_DIR)/", "rtsp.py")
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freeze ("$(MPY_LIB_DIR)/", "vl53l1x.py")
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376
src/omv/boards/BORMIO/omv_boardconfig.h
Normal file
376
src/omv/boards/BORMIO/omv_boardconfig.h
Normal file
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/*
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* This file is part of the OpenMV project.
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*
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* Copyright (c) 2013-2019 Ibrahim Abdelkader <iabdalkader@openmv.io>
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* Copyright (c) 2013-2019 Kwabena W. Agyeman <kwagyeman@openmv.io>
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*
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* This work is licensed under the MIT license, see the file LICENSE for details.
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*
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* Board configuration and pin definitions.
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*/
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#ifndef __OMV_BOARDCONFIG_H__
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#define __OMV_BOARDCONFIG_H__
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// Architecture info
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#define OMV_ARCH_STR "BORMIO H7 8192 SDRAM" // 33 chars max
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#define OMV_BOARD_TYPE "BORMIO"
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#define OMV_UNIQUE_ID_ADDR 0x1FF1E800
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#define OMV_UNIQUE_ID_SIZE 3 // 3 words
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#define OMV_XCLK_MCO (0U)
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#define OMV_XCLK_TIM (1U)
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#define OMV_XCLK_OSC (2U)
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// Sensor external clock source.
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#define OMV_XCLK_SOURCE (OMV_XCLK_TIM)
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// Sensor external clock timer frequency.
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#define OMV_XCLK_FREQUENCY (12000000)
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// Bootloader LED GPIO port/pin
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#define OMV_BOOTLDR_LED_PIN (GPIO_PIN_12)
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#define OMV_BOOTLDR_LED_PORT (GPIOI)
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// RAW buffer size
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#define OMV_RAW_BUF_SIZE (409600)
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// Enable hardware JPEG
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#define OMV_HARDWARE_JPEG (1)
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// Enable sensor drivers
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#define OMV_ENABLE_OV2640 (0)
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#define OMV_ENABLE_OV5640 (0)
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#define OMV_ENABLE_OV7690 (1)
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#define OMV_ENABLE_OV7725 (0)
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#define OMV_ENABLE_OV9650 (0)
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#define OMV_ENABLE_MT9V034 (0)
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#define OMV_ENABLE_LEPTON (0)
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#define OMV_ENABLE_HM01B0 (0)
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// Enable sensor features
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#define OMV_ENABLE_OV5640_AF (0)
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// Enable WiFi debug
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#define OMV_ENABLE_WIFIDBG (0)
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// Enable self-tests on first boot
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#define OMV_ENABLE_SELFTEST (0)
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// If buffer size is bigger than this threshold, the quality is reduced.
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// This is only used for JPEG images sent to the IDE not normal compression.
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#define JPEG_QUALITY_THRESH (320*240*2)
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// Low and high JPEG QS.
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#define JPEG_QUALITY_LOW 50
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#define JPEG_QUALITY_HIGH 90
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// FB Heap Block Size
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#define OMV_UMM_BLOCK_SIZE 16
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// Core VBAT for selftests
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#define OMV_CORE_VBAT "3.0"
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// USB IRQn.
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#define OMV_USB_IRQN (OTG_FS_IRQn)
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// PLL1 48MHz for SDMMC and FDCAN
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#define OMV_OSC_PLL1M (4)
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#define OMV_OSC_PLL1N (240)
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#define OMV_OSC_PLL1P (2)
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#define OMV_OSC_PLL1Q (20)
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#define OMV_OSC_PLL1R (2)
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#define OMV_OSC_PLL1VCI (RCC_PLL1VCIRANGE_2)
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#define OMV_OSC_PLL1VCO (RCC_PLL1VCOWIDE)
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#define OMV_OSC_PLL1FRAC (0)
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// PLL2 200MHz for FMC and QSPI.
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#define OMV_OSC_PLL2M (4)
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#define OMV_OSC_PLL2N (100)
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#define OMV_OSC_PLL2P (2)
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#define OMV_OSC_PLL2Q (2)
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#define OMV_OSC_PLL2R (2)
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#define OMV_OSC_PLL2VCI (RCC_PLL2VCIRANGE_2)
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#define OMV_OSC_PLL2VCO (RCC_PLL2VCOWIDE)
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#define OMV_OSC_PLL2FRAC (0)
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// PLL3 160MHz for ADC and SPI123
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#define OMV_OSC_PLL3M (4)
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#define OMV_OSC_PLL3N (80)
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#define OMV_OSC_PLL3P (2)
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#define OMV_OSC_PLL3Q (2)
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#define OMV_OSC_PLL3R (2)
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#define OMV_OSC_PLL3VCI (RCC_PLL3VCIRANGE_2)
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#define OMV_OSC_PLL3VCO (RCC_PLL3VCOWIDE)
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#define OMV_OSC_PLL3FRAC (0)
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// Clock Sources
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#define OMV_OSC_PLL_CLKSOURCE RCC_PLLSOURCE_HSI
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#define OMV_OSC_USB_CLKSOURCE RCC_USBCLKSOURCE_HSI48
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#define OMV_OSC_RNG_CLKSOURCE RCC_RNGCLKSOURCE_HSI48
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#define OMV_OSC_ADC_CLKSOURCE RCC_ADCCLKSOURCE_PLL3
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#define OMV_OSC_SPI123_CLKSOURCE RCC_SPI123CLKSOURCE_PLL3
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// HSE/HSI/CSI State
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#define OMV_OSC_HSI_STATE (RCC_HSI_DIV4)
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#define OMV_OSC_HSI48_STATE (RCC_HSI48_ON)
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// Flash Latency
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#define OMV_FLASH_LATENCY (FLASH_LATENCY_2)
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// Power supply configuration
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#define OMV_PWR_SUPPLY (PWR_LDO_SUPPLY)
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// Linker script constants (see the linker script template stm32fxxx.ld.S).
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// Note: fb_alloc is a stack-based, dynamically allocated memory on FB.
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// The maximum available fb_alloc memory = FB_ALLOC_SIZE + FB_SIZE - (w*h*bpp).
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#define OMV_FFS_MEMORY DTCM // Flash filesystem cache memory
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#define OMV_MAIN_MEMORY SRAM1 // data, bss and heap
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#define OMV_STACK_MEMORY SRAM1 // stack memory
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#define OMV_DMA_MEMORY AXI_SRAM // DMA buffers memory.
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#define OMV_FB_MEMORY AXI_SRAM // Framebuffer, fb_alloc
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#define OMV_JPEG_MEMORY SRAM3 // JPEG buffer memory buffer.
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#define OMV_VOSPI_MEMORY SRAM4 // VoSPI buffer memory.
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#define OMV_CYW43_MEMORY FLASH_EXT // CYW43 firmware in external flash mmap'd flash.
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#define OMV_CYW43_MEMORY_OFFSET (0x90F00000)// Last Mbyte.
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#define OMV_FB_SIZE (400K) // FB memory: header + VGA/GS image
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#define OMV_FB_ALLOC_SIZE (96K) // minimum fb alloc size
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#define OMV_STACK_SIZE (32K)
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#define OMV_HEAP_SIZE (180K)
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#define OMV_LINE_BUF_SIZE (3 * 1024) // Image line buffer round(640 * 2BPP * 2 buffers).
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#define OMV_MSC_BUF_SIZE (2K) // USB MSC bot data
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#define OMV_VFS_BUF_SIZE (1K) // VFS sturct + FATFS file buffer (624 bytes)
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#define OMV_JPEG_BUF_SIZE (32 * 1024) // IDE JPEG buffer (header + data).
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#define OMV_BOOT_ORIGIN 0x08000000
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#define OMV_BOOT_LENGTH 128K
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#define OMV_TEXT_ORIGIN 0x08040000
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#define OMV_TEXT_LENGTH 1792K
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#define OMV_DTCM_ORIGIN 0x20000000 // Note accessible by CPU and MDMA only.
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#define OMV_DTCM_LENGTH 128K
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#define OMV_ITCM_ORIGIN 0x00000000
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#define OMV_ITCM_LENGTH 64K
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#define OMV_SRAM1_ORIGIN 0x30000000
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#define OMV_SRAM1_LENGTH 256K
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#define OMV_SRAM3_ORIGIN 0x30040000
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#define OMV_SRAM3_LENGTH 32K
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#define OMV_SRAM4_ORIGIN 0x38000000
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#define OMV_SRAM4_LENGTH 64K
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#define OMV_AXI_SRAM_ORIGIN 0x24000000
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#define OMV_AXI_SRAM_LENGTH 512K
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#define OMV_FLASH_EXT_ORIGIN 0x90000000
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#define OMV_FLASH_EXT_LENGTH 16M
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// Use the MPU to set an uncacheable memory region.
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#define OMV_DMA_REGION_BASE (OMV_AXI_SRAM_ORIGIN+(496*1024))
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#define OMV_DMA_REGION_SIZE MPU_REGION_SIZE_16KB
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// Image sensor I2C
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#define ISC_I2C (I2C3)
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#define ISC_I2C_ID (3)
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#define ISC_I2C_AF (GPIO_AF4_I2C3)
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#define ISC_I2C_CLK_ENABLE() __I2C3_CLK_ENABLE()
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#define ISC_I2C_CLK_DISABLE() __I2C3_CLK_DISABLE()
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#define ISC_I2C_PORT (GPIOH)
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#define ISC_I2C_SCL_PIN (GPIO_PIN_7)
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#define ISC_I2C_SDA_PIN (GPIO_PIN_8)
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#define ISC_I2C_SPEED (CAMBUS_SPEED_STANDARD)
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#define ISC_I2C_FORCE_RESET() __HAL_RCC_I2C3_FORCE_RESET()
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#define ISC_I2C_RELEASE_RESET() __HAL_RCC_I2C3_RELEASE_RESET()
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// FIR I2C
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#define FIR_I2C (I2C1)
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#define FIR_I2C_ID (1)
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#define FIR_I2C_AF (GPIO_AF4_I2C1)
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#define FIR_I2C_CLK_ENABLE() __I2C1_CLK_ENABLE()
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#define FIR_I2C_CLK_DISABLE() __I2C1_CLK_DISABLE()
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#define FIR_I2C_PORT (GPIOB)
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#define FIR_I2C_SCL_PIN (GPIO_PIN_6)
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#define FIR_I2C_SDA_PIN (GPIO_PIN_7)
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#define FIR_I2C_SPEED (CAMBUS_SPEED_FULL)
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#define FIR_I2C_FORCE_RESET() __HAL_RCC_I2C1_FORCE_RESET()
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#define FIR_I2C_RELEASE_RESET() __HAL_RCC_I2C1_RELEASE_RESET()
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/* DCMI */
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#define DCMI_TIM (TIM1)
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#define DCMI_TIM_PIN (GPIO_PIN_1)
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#define DCMI_TIM_PORT (GPIOK)
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#define DCMI_TIM_AF (GPIO_AF1_TIM1)
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#define DCMI_TIM_CHANNEL (TIM_CHANNEL_1)
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#define DCMI_TIM_CLK_ENABLE() __TIM1_CLK_ENABLE()
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#define DCMI_TIM_CLK_DISABLE() __TIM1_CLK_DISABLE()
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#define DCMI_TIM_PCLK_FREQ() HAL_RCC_GetPCLK2Freq()
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//#define DCMI_RESET_PIN (GPIO_PIN_10)
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//#define DCMI_RESET_PORT (GPIOA)
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#define DCMI_PWDN_PIN (GPIO_PIN_3)
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#define DCMI_PWDN_PORT (GPIOG)
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//#define DCMI_FSYNC_PIN (GPIO_PIN_4)
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//#define DCMI_FSYNC_PORT (GPIOB)
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#define DCMI_D0_PIN (GPIO_PIN_9)
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#define DCMI_D1_PIN (GPIO_PIN_10)
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#define DCMI_D2_PIN (GPIO_PIN_11)
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#define DCMI_D3_PIN (GPIO_PIN_12)
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#define DCMI_D4_PIN (GPIO_PIN_14)
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#define DCMI_D5_PIN (GPIO_PIN_4)
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#define DCMI_D6_PIN (GPIO_PIN_6)
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#define DCMI_D7_PIN (GPIO_PIN_7)
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#define DCMI_D0_PORT (GPIOH)
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#define DCMI_D1_PORT (GPIOH)
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#define DCMI_D2_PORT (GPIOH)
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#define DCMI_D3_PORT (GPIOH)
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#define DCMI_D4_PORT (GPIOH)
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#define DCMI_D5_PORT (GPIOI)
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#define DCMI_D6_PORT (GPIOI)
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#define DCMI_D7_PORT (GPIOI)
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#define DCMI_HSYNC_PIN (GPIO_PIN_4)
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#define DCMI_VSYNC_PIN (GPIO_PIN_5)
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#define DCMI_PXCLK_PIN (GPIO_PIN_6)
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#define DCMI_HSYNC_PORT (GPIOA)
|
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#define DCMI_VSYNC_PORT (GPIOI)
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#define DCMI_PXCLK_PORT (GPIOA)
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#if defined(DCMI_RESET_PIN)
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#define DCMI_RESET_LOW() HAL_GPIO_WritePin(DCMI_RESET_PORT, DCMI_RESET_PIN, GPIO_PIN_RESET)
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||||
#define DCMI_RESET_HIGH() HAL_GPIO_WritePin(DCMI_RESET_PORT, DCMI_RESET_PIN, GPIO_PIN_SET)
|
||||
#else
|
||||
#define DCMI_RESET_LOW()
|
||||
#define DCMI_RESET_HIGH()
|
||||
#endif
|
||||
|
||||
#if defined(DCMI_PWDN_PIN)
|
||||
#define DCMI_PWDN_LOW() HAL_GPIO_WritePin(DCMI_PWDN_PORT, DCMI_PWDN_PIN, GPIO_PIN_SET)
|
||||
#define DCMI_PWDN_HIGH() HAL_GPIO_WritePin(DCMI_PWDN_PORT, DCMI_PWDN_PIN, GPIO_PIN_RESET)
|
||||
#else
|
||||
#define DCMI_PWDN_LOW()
|
||||
#define DCMI_PWDN_HIGH()
|
||||
#endif
|
||||
|
||||
#define DCMI_VSYNC_IRQN EXTI9_5_IRQn
|
||||
#define DCMI_VSYNC_IRQ_LINE (7)
|
||||
|
||||
#define SOFT_I2C_PORT GPIOC
|
||||
#define SOFT_I2C_SIOC_PIN GPIO_PIN_10
|
||||
#define SOFT_I2C_SIOD_PIN GPIO_PIN_11
|
||||
|
||||
#define SOFT_I2C_SIOC_H() HAL_GPIO_WritePin(SOFT_I2C_PORT, SOFT_I2C_SIOC_PIN, GPIO_PIN_SET)
|
||||
#define SOFT_I2C_SIOC_L() HAL_GPIO_WritePin(SOFT_I2C_PORT, SOFT_I2C_SIOC_PIN, GPIO_PIN_RESET)
|
||||
|
||||
#define SOFT_I2C_SIOD_H() HAL_GPIO_WritePin(SOFT_I2C_PORT, SOFT_I2C_SIOD_PIN, GPIO_PIN_SET)
|
||||
#define SOFT_I2C_SIOD_L() HAL_GPIO_WritePin(SOFT_I2C_PORT, SOFT_I2C_SIOD_PIN, GPIO_PIN_RESET)
|
||||
|
||||
#define SOFT_I2C_SIOD_READ() HAL_GPIO_ReadPin (SOFT_I2C_PORT, SOFT_I2C_SIOD_PIN)
|
||||
#define SOFT_I2C_SIOD_WRITE(bit) HAL_GPIO_WritePin(SOFT_I2C_PORT, SOFT_I2C_SIOD_PIN, bit);
|
||||
|
||||
#define SOFT_I2C_SPIN_DELAY 64
|
||||
|
||||
#define IMU_SPI (SPI2)
|
||||
#define IMU_SPI_AF (GPIO_AF5_SPI2)
|
||||
// SPI1/2/3 clock source is PLL2 (160MHz/16 == 10MHz).
|
||||
#define IMU_SPI_PRESCALER (SPI_BAUDRATEPRESCALER_16)
|
||||
|
||||
#define IMU_SPI_RESET() __HAL_RCC_SPI2_FORCE_RESET()
|
||||
#define IMU_SPI_RELEASE() __HAL_RCC_SPI2_RELEASE_RESET()
|
||||
|
||||
#define IMU_SPI_CLK_ENABLE() __HAL_RCC_SPI2_CLK_ENABLE()
|
||||
#define IMU_SPI_CLK_DISABLE() __HAL_RCC_SPI2_CLK_DISABLE()
|
||||
|
||||
#define IMU_SPI_SCLK_PIN (GPIO_PIN_1)
|
||||
#define IMU_SPI_MISO_PIN (GPIO_PIN_2)
|
||||
#define IMU_SPI_MOSI_PIN (GPIO_PIN_3)
|
||||
#define IMU_SPI_SSEL_PIN (GPIO_PIN_0)
|
||||
|
||||
#define IMU_SPI_SCLK_PORT (GPIOI)
|
||||
#define IMU_SPI_MISO_PORT (GPIOC)
|
||||
#define IMU_SPI_MOSI_PORT (GPIOC)
|
||||
#define IMU_SPI_SSEL_PORT (GPIOI)
|
||||
|
||||
// SPI LCD Interface
|
||||
#define OMV_SPI_LCD_CONTROLLER (&spi_obj[3])
|
||||
#define OMV_SPI_LCD_CONTROLLER_INSTANCE (SPI4)
|
||||
|
||||
#define OMV_SPI_LCD_MOSI_PIN (GPIO_PIN_14)
|
||||
#define OMV_SPI_LCD_MOSI_PORT (GPIOE)
|
||||
#define OMV_SPI_LCD_MOSI_ALT (GPIO_AF5_SPI4)
|
||||
|
||||
#define OMV_SPI_LCD_MISO_PIN (GPIO_PIN_13)
|
||||
#define OMV_SPI_LCD_MISO_PORT (GPIOE)
|
||||
#define OMV_SPI_LCD_MISO_ALT (GPIO_AF5_SPI4)
|
||||
|
||||
#define OMV_SPI_LCD_SCLK_PIN (GPIO_PIN_12)
|
||||
#define OMV_SPI_LCD_SCLK_PORT (GPIOE)
|
||||
#define OMV_SPI_LCD_SCLK_ALT (GPIO_AF5_SPI4)
|
||||
|
||||
#define OMV_SPI_LCD_CS_PIN (GPIO_PIN_11)
|
||||
#define OMV_SPI_LCD_CS_PORT (GPIOE)
|
||||
#define OMV_SPI_LCD_CS_HIGH() HAL_GPIO_WritePin(OMV_SPI_LCD_CS_PORT, OMV_SPI_LCD_CS_PIN, GPIO_PIN_SET)
|
||||
#define OMV_SPI_LCD_CS_LOW() HAL_GPIO_WritePin(OMV_SPI_LCD_CS_PORT, OMV_SPI_LCD_CS_PIN, GPIO_PIN_RESET)
|
||||
|
||||
#define OMV_SPI_LCD_RST_PIN (GPIO_PIN_10)
|
||||
#define OMV_SPI_LCD_RST_PORT (GPIOC)
|
||||
#define OMV_SPI_LCD_RST_OFF() HAL_GPIO_WritePin(OMV_SPI_LCD_RST_PORT, OMV_SPI_LCD_RST_PIN, GPIO_PIN_SET)
|
||||
#define OMV_SPI_LCD_RST_ON() HAL_GPIO_WritePin(OMV_SPI_LCD_RST_PORT, OMV_SPI_LCD_RST_PIN, GPIO_PIN_RESET)
|
||||
|
||||
#define OMV_SPI_LCD_RS_PIN (GPIO_PIN_11)
|
||||
#define OMV_SPI_LCD_RS_PORT (GPIOC)
|
||||
#define OMV_SPI_LCD_RS_OFF() HAL_GPIO_WritePin(OMV_SPI_LCD_RS_PORT, OMV_SPI_LCD_RS_PIN, GPIO_PIN_SET)
|
||||
#define OMV_SPI_LCD_RS_ON() HAL_GPIO_WritePin(OMV_SPI_LCD_RS_PORT, OMV_SPI_LCD_RS_PIN, GPIO_PIN_RESET)
|
||||
|
||||
//#define OMV_SPI_LCD_BL_PIN (GPIO_PIN_4)
|
||||
//#define OMV_SPI_LCD_BL_PORT (GPIOA)
|
||||
//#define OMV_SPI_LCD_BL_ON() HAL_GPIO_WritePin(OMV_SPI_LCD_BL_PORT, OMV_SPI_LCD_BL_PIN, GPIO_PIN_SET)
|
||||
//#define OMV_SPI_LCD_BL_OFF() HAL_GPIO_WritePin(OMV_SPI_LCD_BL_PORT, OMV_SPI_LCD_BL_PIN, GPIO_PIN_RESET)
|
||||
|
||||
//#define OMV_SPI_LCD_BL_DAC (DAC1)
|
||||
//#define OMV_SPI_LCD_BL_DAC_CHANNEL (DAC_CHANNEL_1)
|
||||
//#define OMV_SPI_LCD_BL_DAC_CLK_ENABLE() __HAL_RCC_DAC12_CLK_ENABLE()
|
||||
//#define OMV_SPI_LCD_BL_DAC_CLK_DISABLE() __HAL_RCC_DAC12_CLK_DISABLE()
|
||||
//#define OMV_SPI_LCD_BL_DAC_FORCE_RESET() __HAL_RCC_DAC12_FORCE_RESET()
|
||||
//#define OMV_SPI_LCD_BL_DAC_RELEASE_RESET() __HAL_RCC_DAC12_RELEASE_RESET()
|
||||
|
||||
// FIR Module
|
||||
#define OMV_ENABLE_FIR_MLX90621 (1)
|
||||
#define OMV_ENABLE_FIR_MLX90640 (1)
|
||||
#define OMV_ENABLE_FIR_MLX90641 (1)
|
||||
#define OMV_ENABLE_FIR_AMG8833 (1)
|
||||
#define OMV_ENABLE_FIR_LEPTON (1)
|
||||
|
||||
// FIR Lepton
|
||||
#define OMV_FIR_LEPTON_I2C_BUS (FIR_I2C_ID)
|
||||
#define OMV_FIR_LEPTON_I2C_BUS_SPEED (FIR_I2C_SPEED)
|
||||
#define OMV_FIR_LEPTON_CONTROLLER (&spi_obj[3])
|
||||
#define OMV_FIR_LEPTON_CONTROLLER_INSTANCE (SPI4)
|
||||
|
||||
#define OMV_FIR_LEPTON_MOSI_PIN (GPIO_PIN_14)
|
||||
#define OMV_FIR_LEPTON_MOSI_PORT (GPIOE)
|
||||
#define OMV_FIR_LEPTON_MOSI_ALT (GPIO_AF5_SPI4)
|
||||
|
||||
#define OMV_FIR_LEPTON_MISO_PIN (GPIO_PIN_13)
|
||||
#define OMV_FIR_LEPTON_MISO_PORT (GPIOE)
|
||||
#define OMV_FIR_LEPTON_MISO_ALT (GPIO_AF5_SPI4)
|
||||
|
||||
#define OMV_FIR_LEPTON_SCLK_PIN (GPIO_PIN_12)
|
||||
#define OMV_FIR_LEPTON_SCLK_PORT (GPIOE)
|
||||
#define OMV_FIR_LEPTON_SCLK_ALT (GPIO_AF5_SPI4)
|
||||
|
||||
#define OMV_FIR_LEPTON_CS_PIN (GPIO_PIN_11)
|
||||
#define OMV_FIR_LEPTON_CS_PORT (GPIOE)
|
||||
#define OMV_FIR_LEPTON_CS_HIGH() HAL_GPIO_WritePin(OMV_FIR_LEPTON_CS_PORT, OMV_FIR_LEPTON_CS_PIN, GPIO_PIN_SET)
|
||||
#define OMV_FIR_LEPTON_CS_LOW() HAL_GPIO_WritePin(OMV_FIR_LEPTON_CS_PORT, OMV_FIR_LEPTON_CS_PIN, GPIO_PIN_RESET)
|
||||
|
||||
// Enable additional GPIO banks for DRAM...
|
||||
#define OMV_ENABLE_GPIO_BANK_F
|
||||
#define OMV_ENABLE_GPIO_BANK_G
|
||||
#define OMV_ENABLE_GPIO_BANK_H
|
||||
#define OMV_ENABLE_GPIO_BANK_I
|
||||
#define OMV_ENABLE_GPIO_BANK_J
|
||||
//#define OMV_ENABLE_GPIO_BANK_K
|
||||
|
||||
#endif //__OMV_BOARDCONFIG_H__
|
||||
23
src/omv/boards/BORMIO/omv_boardconfig.mk
Executable file
23
src/omv/boards/BORMIO/omv_boardconfig.mk
Executable file
@ -0,0 +1,23 @@
|
||||
MCU=STM32H747xx
|
||||
CPU=cortex-m7
|
||||
FPU=fpv5-sp-d16
|
||||
PORT=stm32
|
||||
HAL_DIR=hal/stm32/h7
|
||||
ARM_MATH=ARM_MATH_CM7
|
||||
HAL_INC='<stm32h7xx_hal.h>'
|
||||
CFLAGS_MCU=MCU_SERIES_H7
|
||||
VECT_TAB_OFFSET=0x40000
|
||||
MAIN_APP_ADDR=0x08040000
|
||||
OMV_HSE_VALUE=64000000
|
||||
DFU_DEVICE=0x2341:0x035b
|
||||
OMV_BOARD_EXTRA_CFLAGS = -DCORE_CM7
|
||||
OMV_ENABLE_BL=0
|
||||
OMV_ENABLE_UVC=1
|
||||
MICROPY_PY_SENSOR = 1
|
||||
MICROPY_PY_ULAB = 1
|
||||
MICROPY_PY_WINC1500 = 0
|
||||
MICROPY_PY_IMU = 1
|
||||
MICROPY_PY_LWIP = 1
|
||||
MICROPY_PY_NETWORK_CYW43 = 1
|
||||
MICROPY_PY_AUDIO = 0
|
||||
MICROPY_PY_MICRO_SPEECH = 0
|
||||
Loading…
Reference in New Issue
Block a user