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boards: Add support for Arduino Giga.
This commit is contained in:
parent
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2
.github/workflows/firmware.yml
vendored
2
.github/workflows/firmware.yml
vendored
@ -28,7 +28,7 @@ jobs:
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runs-on: ubuntu-20.04
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strategy:
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matrix:
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target: [OPENMV2, OPENMV3, OPENMV4, OPENMV4P, ARDUINO_PORTENTA_H7, OPENMVPT, ARDUINO_NICLA_VISION, arduino_nano_33_ble_sense, ARDUINO_NANO_RP2040_CONNECT, OPENMV_RT1060]
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target: [OPENMV2, OPENMV3, OPENMV4, OPENMV4P, OPENMVPT, OPENMV_RT1060, ARDUINO_PORTENTA_H7, ARDUINO_GIGA, ARDUINO_NICLA_VISION, ARDUINO_NANO_RP2040_CONNECT, arduino_nano_33_ble_sense]
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fail-fast: false
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steps:
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- name: '⏳ Checkout repository'
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@ -1 +1 @@
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Subproject commit feeb2c73c3e79159840f914d38b465951af0953b
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Subproject commit c81eeb21621db44cce81c1c81f6cc71363c63658
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162
src/omv/boards/ARDUINO_GIGA/imlib_config.h
Normal file
162
src/omv/boards/ARDUINO_GIGA/imlib_config.h
Normal file
@ -0,0 +1,162 @@
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/*
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* This file is part of the OpenMV project.
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*
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* Copyright (c) 2023 Ibrahim Abdelkader <iabdalkader@openmv.io>
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* Copyright (c) 2023 Kwabena W. Agyeman <kwagyeman@openmv.io>
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*
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* This work is licensed under the MIT license, see the file LICENSE for details.
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*
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* Image library configuration.
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*/
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#ifndef __IMLIB_CONFIG_H__
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#define __IMLIB_CONFIG_H__
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// Enable Image I/O
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#define IMLIB_ENABLE_IMAGE_IO
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// Enable Image File I/O
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#define IMLIB_ENABLE_IMAGE_FILE_IO
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// Enable LAB LUT
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//#define IMLIB_ENABLE_LAB_LUT
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// Enable YUV LUT
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//#define IMLIB_ENABLE_YUV_LUT
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// Enable mean pooling
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#define IMLIB_ENABLE_MEAN_POOLING
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// Enable midpoint pooling
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#define IMLIB_ENABLE_MIDPOINT_POOLING
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// Enable ISP ops
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#define IMLIB_ENABLE_ISP_OPS
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// Enable binary ops
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#define IMLIB_ENABLE_BINARY_OPS
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// Enable math ops
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#define IMLIB_ENABLE_MATH_OPS
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// Enable flood_fill()
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#define IMLIB_ENABLE_FLOOD_FILL
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// Enable mean()
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#define IMLIB_ENABLE_MEAN
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// Enable median()
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#define IMLIB_ENABLE_MEDIAN
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// Enable mode()
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#define IMLIB_ENABLE_MODE
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// Enable midpoint()
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#define IMLIB_ENABLE_MIDPOINT
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// Enable morph()
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#define IMLIB_ENABLE_MORPH
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// Enable Gaussian
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#define IMLIB_ENABLE_GAUSSIAN
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// Enable Laplacian
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#define IMLIB_ENABLE_LAPLACIAN
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// Enable bilateral()
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//#define IMLIB_ENABLE_BILATERAL
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// Enable cartoon()
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// #define IMLIB_ENABLE_CARTOON
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// Enable linpolar()
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#define IMLIB_ENABLE_LINPOLAR
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// Enable logpolar()
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#define IMLIB_ENABLE_LOGPOLAR
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// Enable lens_corr()
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#define IMLIB_ENABLE_LENS_CORR
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// Enable rotation_corr()
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#define IMLIB_ENABLE_ROTATION_CORR
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// Enable phasecorrelate()
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#if defined(IMLIB_ENABLE_ROTATION_CORR)
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#define IMLIB_ENABLE_FIND_DISPLACEMENT
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#endif
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// Enable get_similarity()
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#define IMLIB_ENABLE_GET_SIMILARITY
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// Enable find_lines()
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#define IMLIB_ENABLE_FIND_LINES
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// Enable find_line_segments()
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#define IMLIB_ENABLE_FIND_LINE_SEGMENTS
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// Enable find_circles()
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#define IMLIB_ENABLE_FIND_CIRCLES
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// Enable find_rects()
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#define IMLIB_ENABLE_FIND_RECTS
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// Enable find_qrcodes() (14 KB)
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#define IMLIB_ENABLE_QRCODES
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// Enable find_apriltags() (64 KB)
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#define IMLIB_ENABLE_APRILTAGS
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// Enable fine find_apriltags() - (8-way connectivity versus 4-way connectivity)
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// #define IMLIB_ENABLE_FINE_APRILTAGS
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// Enable high res find_apriltags() - uses more RAM
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// #define IMLIB_ENABLE_HIGH_RES_APRILTAGS
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// Enable find_datamatrices() (26 KB)
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//#define IMLIB_ENABLE_DATAMATRICES
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// Enable find_barcodes() (42 KB)
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#define IMLIB_ENABLE_BARCODES
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// Enable CMSIS NN
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// #if !defined(CUBEAI)
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// #define IMLIB_ENABLE_CNN
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// #endif
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// Enable Tensor Flow
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#if !defined(CUBEAI)
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#define IMLIB_ENABLE_TF
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#endif
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// Enable FAST (20+ KBs).
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//#define IMLIB_ENABLE_FAST
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// Enable find_template()
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#define IMLIB_FIND_TEMPLATE
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// Enable find_lbp()
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//#define IMLIB_ENABLE_FIND_LBP
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// Enable find_keypoints()
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#define IMLIB_ENABLE_FIND_KEYPOINTS
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// Enable load, save and match descriptor
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#define IMLIB_ENABLE_DESCRIPTOR
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// Enable find_hog()
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//#define IMLIB_ENABLE_HOG
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// Enable selective_search()
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//#define IMLIB_ENABLE_SELECTIVE_SEARCH
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// Enable STM32 DMA2D
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#define IMLIB_ENABLE_DMA2D
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// Enable PNG encoder/decoder
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#define IMLIB_ENABLE_PNG_ENCODER
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#define IMLIB_ENABLE_PNG_DECODER
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// Stereo Imaging
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// #define IMLIB_ENABLE_STEREO_DISPARITY
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#endif //__IMLIB_CONFIG_H__
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28
src/omv/boards/ARDUINO_GIGA/manifest.py
Normal file
28
src/omv/boards/ARDUINO_GIGA/manifest.py
Normal file
@ -0,0 +1,28 @@
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include("$(MPY_DIR)/extmod/uasyncio")
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# Drivers
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require("onewire")
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require("dht")
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require("neopixel")
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freeze ("$(OMV_LIB_DIR)/", "modbus.py")
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freeze ("$(OMV_LIB_DIR)/", "pid.py")
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freeze ("$(OMV_LIB_DIR)/", "gt911.py")
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# Networking
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require("ntptime")
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require("webrepl")
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freeze ("$(OMV_LIB_DIR)/", "rpc.py")
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freeze ("$(OMV_LIB_DIR)/", "rtsp.py")
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freeze ("$(OMV_LIB_DIR)/", "mqtt.py")
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freeze ("$(OMV_LIB_DIR)/", "urequests.py")
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freeze ("$(OMV_LIB_DIR)/", "display.py")
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# Utils
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require("time")
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require("senml")
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require("logging")
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freeze ("$(OMV_LIB_DIR)/", "mutex.py")
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# Bluetooth
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require("aioble")
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freeze ("$(OMV_LIB_DIR)/", "ble_advertising.py")
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318
src/omv/boards/ARDUINO_GIGA/omv_boardconfig.h
Normal file
318
src/omv/boards/ARDUINO_GIGA/omv_boardconfig.h
Normal file
@ -0,0 +1,318 @@
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/*
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* This file is part of the OpenMV project.
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*
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* Copyright (c) 2023 Ibrahim Abdelkader <iabdalkader@openmv.io>
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* Copyright (c) 2023 Kwabena W. Agyeman <kwagyeman@openmv.io>
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*
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* This work is licensed under the MIT license, see the file LICENSE for details.
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*
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* Board configuration and pin definitions.
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*/
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#ifndef __OMV_BOARDCONFIG_H__
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#define __OMV_BOARDCONFIG_H__
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// Architecture info
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#define OMV_ARCH_STR "GIGA H7 8192 SDRAM" // 33 chars max
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#define OMV_BOARD_TYPE "H7"
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#define OMV_UNIQUE_ID_ADDR 0x1FF1E800 // Unique ID address.
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#define OMV_UNIQUE_ID_SIZE 3 // Unique ID size in words.
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#define OMV_UNIQUE_ID_OFFSET 4 // Bytes offset for multi-word UIDs.
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#define OMV_XCLK_MCO (0U)
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#define OMV_XCLK_TIM (1U)
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#define OMV_XCLK_OSC (2U)
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// Sensor external clock source.
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#define OMV_XCLK_SOURCE (OMV_XCLK_TIM)
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// Sensor external clock timer frequency.
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#define OMV_XCLK_FREQUENCY (12000000)
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// Enable hardware JPEG
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#define OMV_HARDWARE_JPEG (1)
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// MDMA configuration
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#define OMV_MDMA_CHANNEL_DCMI_0 (0)
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#define OMV_MDMA_CHANNEL_DCMI_1 (1)
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#define OMV_MDMA_CHANNEL_JPEG_IN (7) // in has a lower pri than out
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#define OMV_MDMA_CHANNEL_JPEG_OUT (6) // out has a higher pri than in
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// Enable additional GPIO banks.
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#define OMV_ENABLE_GPIO_BANK_F (1)
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#define OMV_ENABLE_GPIO_BANK_G (1)
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#define OMV_ENABLE_GPIO_BANK_H (1)
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#define OMV_ENABLE_GPIO_BANK_I (1)
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#define OMV_ENABLE_GPIO_BANK_J (1)
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#define OMV_ENABLE_GPIO_BANK_K (1)
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// Enable sensor drivers
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#define OMV_ENABLE_OV2640 (0)
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#define OMV_ENABLE_OV5640 (0)
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#define OMV_ENABLE_OV7670 (1)
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#define OMV_ENABLE_OV7690 (0)
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#define OMV_ENABLE_OV7725 (0)
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#define OMV_ENABLE_OV9650 (0)
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#define OMV_ENABLE_MT9M114 (0)
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#define OMV_ENABLE_MT9V0XX (0)
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#define OMV_ENABLE_LEPTON (0)
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#define OMV_ENABLE_HM01B0 (0)
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#define OMV_ENABLE_PAJ6100 (0)
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#define OMV_ENABLE_FROGEYE2020 (0)
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#define OMV_ENABLE_FIR_MLX90621 (1)
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#define OMV_ENABLE_FIR_MLX90640 (1)
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#define OMV_ENABLE_FIR_MLX90641 (1)
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#define OMV_ENABLE_FIR_AMG8833 (1)
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#define OMV_ENABLE_FIR_LEPTON (0)
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// Set which OV767x sensor is used
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#define OMV_OV7670_VERSION (75)
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// OV7670 clock divider
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#define OMV_OV7670_CLKRC (0)
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// Enable sensor features
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#define OMV_ENABLE_OV5640_AF (0)
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// Enable WiFi debug
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#define OMV_ENABLE_WIFIDBG (0)
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// Enable self-tests on first boot
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#define OMV_ENABLE_SELFTEST (0)
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// If buffer size is bigger than this threshold, the quality is reduced.
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// This is only used for JPEG images sent to the IDE not normal compression.
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#define JPEG_QUALITY_THRESH (320 * 240 * 2)
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// Low and high JPEG QS.
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#define JPEG_QUALITY_LOW 50
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#define JPEG_QUALITY_HIGH 90
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// FB Heap Block Size
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#define OMV_UMM_BLOCK_SIZE 256
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// Core VBAT for selftests
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#define OMV_CORE_VBAT "3.0"
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// USB IRQn.
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#define OMV_USB_IRQN (OTG_FS_IRQn)
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#define OMV_USB_ULPI (0)
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// PLL1 480MHz/48MHz SDMMC and FDCAN
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// USB and RNG are clocked from the HSI48
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#define OMV_OSC_PLL1M (4)
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#define OMV_OSC_PLL1N (240)
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#define OMV_OSC_PLL1P (2)
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#define OMV_OSC_PLL1Q (20)
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#define OMV_OSC_PLL1R (2)
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#define OMV_OSC_PLL1VCI (RCC_PLL1VCIRANGE_2)
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#define OMV_OSC_PLL1VCO (RCC_PLL1VCOWIDE)
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#define OMV_OSC_PLL1FRAC (0)
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// PLL2 200MHz for FMC and QSPI.
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#define OMV_OSC_PLL2M (4)
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#define OMV_OSC_PLL2N (100)
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#define OMV_OSC_PLL2P (2)
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#define OMV_OSC_PLL2Q (2)
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#define OMV_OSC_PLL2R (2)
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#define OMV_OSC_PLL2VCI (RCC_PLL2VCIRANGE_2)
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#define OMV_OSC_PLL2VCO (RCC_PLL2VCOWIDE)
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#define OMV_OSC_PLL2FRAC (0)
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// PLL3 160MHz for ADC and SPI123
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#define OMV_OSC_PLL3M (4)
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#define OMV_OSC_PLL3N (80)
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#define OMV_OSC_PLL3P (2)
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#define OMV_OSC_PLL3Q (2)
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#define OMV_OSC_PLL3R (2)
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#define OMV_OSC_PLL3VCI (RCC_PLL3VCIRANGE_2)
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#define OMV_OSC_PLL3VCO (RCC_PLL3VCOWIDE)
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#define OMV_OSC_PLL3FRAC (0)
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// Clock Sources
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#define OMV_OSC_PLL_CLKSOURCE RCC_PLLSOURCE_HSE
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#define OMV_OSC_USB_CLKSOURCE RCC_USBCLKSOURCE_HSI48
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#define OMV_OSC_RNG_CLKSOURCE RCC_RNGCLKSOURCE_HSI48
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#define OMV_OSC_ADC_CLKSOURCE RCC_ADCCLKSOURCE_PLL3
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#define OMV_OSC_SPI123_CLKSOURCE RCC_SPI123CLKSOURCE_PLL3
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#define OMV_OSC_DFSDM1_CLKSOURCE RCC_DFSDM1CLKSOURCE_D2PCLK1
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// HSE/HSI/CSI State
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#define OMV_OSC_HSE_STATE (RCC_HSE_ON)
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#define OMV_OSC_HSI48_STATE (RCC_HSI48_ON)
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// Flash Latency
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#define OMV_FLASH_LATENCY (FLASH_LATENCY_2)
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// Power supply configuration
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#define OMV_PWR_SUPPLY (PWR_LDO_SUPPLY)
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// Linker script constants (see the linker script template stm32fxxx.ld.S).
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// Note: fb_alloc is a stack-based, dynamically allocated memory on FB.
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// The maximum available fb_alloc memory = FB_ALLOC_SIZE + FB_SIZE - (w*h*bpp).
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#define OMV_MAIN_MEMORY SRAM1 // data, bss and heap
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#define OMV_STACK_MEMORY DTCM // stack memory
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#define OMV_DMA_MEMORY SRAM3 // DMA buffers memory.
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#define OMV_FB_MEMORY DRAM // Framebuffer, fb_alloc
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#define OMV_JPEG_MEMORY DRAM // JPEG buffer memory buffer.
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#define OMV_JPEG_MEMORY_OFFSET (7M) // JPEG buffer is placed after FB/fballoc memory.
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#define OMV_VOSPI_MEMORY SRAM4 // VoSPI buffer memory.
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#define OMV_VOSPI_MEMORY_OFFSET (20K) // SRAM4 reserves 16K for CM4 + 4K D3 DMA buffers.
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#define OMV_FB_OVERLAY_MEMORY AXI_SRAM // Fast fb_alloc memory.
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#define OMV_FB_SIZE (4M) // FB memory: header + VGA/GS image
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#define OMV_FB_ALLOC_SIZE (3M) // minimum fb alloc size
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#define OMV_FB_OVERLAY_SIZE (480 * 1024) // Fast fb_alloc memory size.
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#define OMV_STACK_SIZE (64K)
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#define OMV_HEAP_SIZE (199K)
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#define OMV_SDRAM_SIZE (8 * 1024 * 1024) // This needs to be here for UVC firmware.
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#define OMV_LINE_BUF_SIZE (11 * 1024) // Image line buffer round(2592 * 2BPP * 2 buffers).
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#define OMV_MSC_BUF_SIZE (2K) // USB MSC bot data
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#define OMV_VFS_BUF_SIZE (1K) // VFS struct + FATFS file buffer (624 bytes)
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#define OMV_JPEG_BUF_SIZE (1024 * 1024) // IDE JPEG buffer (header + data).
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// Memory map.
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#define OMV_FLASH_ORIGIN 0x08000000
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#define OMV_FLASH_LENGTH 2048K
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#define OMV_DTCM_ORIGIN 0x20000000 // Note accessible by CPU and MDMA only.
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#define OMV_DTCM_LENGTH 128K
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#define OMV_SRAM1_ORIGIN 0x30000000
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#define OMV_SRAM1_LENGTH 256K
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#define OMV_SRAM3_ORIGIN 0x30040000
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#define OMV_SRAM3_LENGTH 32K
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#define OMV_SRAM4_ORIGIN 0x38000000
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#define OMV_SRAM4_LENGTH 64K
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#define OMV_AXI_SRAM_ORIGIN 0x24000000
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#define OMV_AXI_SRAM_LENGTH 512K
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#define OMV_DRAM_ORIGIN 0xC0000000
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#define OMV_DRAM_LENGTH 8M
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#define OMV_CM4_RAM_ORIGIN 0x38000000 // Cortex-M4 memory @SRAM4.
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#define OMV_CM4_RAM_LENGTH 16K
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// Flash configuration.
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#define OMV_FLASH_FFS_ORIGIN 0x08020000
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#define OMV_FLASH_FFS_LENGTH 128K
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#define OMV_FLASH_TXT_ORIGIN 0x08040000
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#define OMV_FLASH_TXT_LENGTH 1792K
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#define OMV_FLASH_EXT_ORIGIN 0x90000000
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#define OMV_FLASH_EXT_LENGTH 16M
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#define OMV_CM4_FLASH_ORIGIN 0x08020000
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#define OMV_CM4_FLASH_LENGTH 128K
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// Domain 1 DMA buffers region.
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#define OMV_DMA_MEMORY_D1 AXI_SRAM
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#define OMV_DMA_MEMORY_D1_SIZE (8 * 1024) // Reserved memory for DMA buffers
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#define OMV_DMA_REGION_D1_BASE (OMV_AXI_SRAM_ORIGIN + OMV_FB_OVERLAY_SIZE)
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#define OMV_DMA_REGION_D1_SIZE MPU_REGION_SIZE_32KB
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||||
|
||||
// Domain 2 DMA buffers region.
|
||||
#define OMV_DMA_MEMORY_D2 SRAM3
|
||||
#define OMV_DMA_MEMORY_D2_SIZE (4 * 1024) // Reserved memory for DMA buffers
|
||||
#define OMV_DMA_REGION_D2_BASE (OMV_SRAM3_ORIGIN + (0 * 1024))
|
||||
#define OMV_DMA_REGION_D2_SIZE MPU_REGION_SIZE_32KB
|
||||
|
||||
// Domain 3 DMA buffers region.
|
||||
#define OMV_DMA_MEMORY_D3 SRAM4
|
||||
#define OMV_DMA_MEMORY_D3_SIZE (4 * 1024) // Reserved memory for DMA buffers
|
||||
#define OMV_DMA_REGION_D3_BASE (OMV_SRAM4_ORIGIN + (16 * 1024))
|
||||
#define OMV_DMA_REGION_D3_SIZE MPU_REGION_SIZE_4KB
|
||||
|
||||
// AXI QoS - Low-High (0:15) - default 0
|
||||
#define OMV_AXI_QOS_MDMA_R_PRI 15
|
||||
#define OMV_AXI_QOS_MDMA_W_PRI 15
|
||||
#define OMV_AXI_QOS_LTDC_R_PRI 14
|
||||
//#define OMV_AXI_QOS_DMA2D_R_PRI 14
|
||||
//#define OMV_AXI_QOS_DMA2D_W_PRI 14
|
||||
|
||||
// Image sensor I2C
|
||||
#define ISC_I2C_ID (4)
|
||||
#define ISC_I2C_SPEED (OMV_I2C_SPEED_STANDARD)
|
||||
|
||||
// FIR I2C
|
||||
#define FIR_I2C_ID (1)
|
||||
#define FIR_I2C_SPEED (OMV_I2C_SPEED_STANDARD)
|
||||
|
||||
// Soft I2C bus.
|
||||
///#define SOFT_I2C_SIOC_PIN (&omv_pin_B10_GPIO)
|
||||
///#define SOFT_I2C_SIOD_PIN (&omv_pin_B11_GPIO)
|
||||
///#define SOFT_I2C_SPIN_DELAY 64
|
||||
|
||||
// DCMI timer.
|
||||
#define DCMI_TIM (TIM1)
|
||||
#define DCMI_TIM_PIN (&omv_pin_J9_TIM1)
|
||||
#define DCMI_TIM_CHANNEL (TIM_CHANNEL_3)
|
||||
#define DCMI_TIM_CLK_ENABLE() __TIM1_CLK_ENABLE()
|
||||
#define DCMI_TIM_CLK_DISABLE() __TIM1_CLK_DISABLE()
|
||||
#define DCMI_TIM_PCLK_FREQ() HAL_RCC_GetPCLK2Freq()
|
||||
|
||||
// DCMI pins.
|
||||
//#define DCMI_RESET_PIN (&omv_pin_A1_GPIO)
|
||||
#define DCMI_POWER_PIN (&omv_pin_D4_GPIO)
|
||||
|
||||
#define DCMI_D0_PIN (&omv_pin_H9_DCMI)
|
||||
#define DCMI_D1_PIN (&omv_pin_H10_DCMI)
|
||||
#define DCMI_D2_PIN (&omv_pin_H11_DCMI)
|
||||
#define DCMI_D3_PIN (&omv_pin_G11_DCMI)
|
||||
#define DCMI_D4_PIN (&omv_pin_H14_DCMI)
|
||||
#define DCMI_D5_PIN (&omv_pin_I4_DCMI)
|
||||
#define DCMI_D6_PIN (&omv_pin_I6_DCMI)
|
||||
#define DCMI_D7_PIN (&omv_pin_I7_DCMI)
|
||||
|
||||
#define DCMI_HSYNC_PIN (&omv_pin_H8_DCMI)
|
||||
#define DCMI_VSYNC_PIN (&omv_pin_I5_DCMI)
|
||||
#define DCMI_PXCLK_PIN (&omv_pin_A6_DCMI)
|
||||
|
||||
// Physical I2C buses.
|
||||
// I2C bus 1
|
||||
#define I2C1_ID (1)
|
||||
#define I2C1_SCL_PIN (&omv_pin_B8_I2C1)
|
||||
#define I2C1_SDA_PIN (&omv_pin_B9_I2C1)
|
||||
|
||||
// I2C bus 4
|
||||
#define I2C4_ID (4)
|
||||
#define I2C4_SCL_PIN (&omv_pin_B6_I2C4)
|
||||
#define I2C4_SDA_PIN (&omv_pin_H12_I2C4)
|
||||
|
||||
// DFSDM1
|
||||
#define AUDIO_DFSDM (DFSDM1_Channel0)
|
||||
#define AUDIO_DFSDM_CHANNEL (DFSDM_CHANNEL_0)
|
||||
// DFSDM output clock is derived from the Aclk (set in SAI1SEL[2:0])
|
||||
// for SAI1 and DFSDM1, which is clocked from PLL1Q by default (48MHz).
|
||||
#define AUDIO_DFSDM_FREQMHZ (48)
|
||||
#define AUDIO_MAX_CHANNELS (1) // Maximum number of channels.
|
||||
|
||||
#define AUDIO_DFSDM_CK_PIN (&omv_pin_D3_DFSDM1)
|
||||
#define AUDIO_DFSDM_D1_PIN (&omv_pin_C1_DFSDM1)
|
||||
|
||||
#define AUDIO_DFSDM_FLT0 DFSDM1_Filter0
|
||||
#define AUDIO_DFSDM_FLT0_IRQ DFSDM1_FLT0_IRQn
|
||||
#define AUDIO_DFSDM_FLT0_IRQHandler DFSDM1_FLT0_IRQHandler
|
||||
#define AUDIO_DFSDM_FLT0_DMA_STREAM DMA1_Stream1
|
||||
#define AUDIO_DFSDM_FLT0_DMA_REQUEST DMA_REQUEST_DFSDM1_FLT0
|
||||
#define AUDIO_DFSDM_FLT0_DMA_IRQ DMA1_Stream1_IRQn
|
||||
#define AUDIO_DFSDM_FLT0_DMA_IRQHandler DMA1_Stream1_IRQHandler
|
||||
|
||||
#define AUDIO_DFSDM_CLK_ENABLE() __HAL_RCC_DFSDM1_CLK_ENABLE()
|
||||
#define AUDIO_DFSDM_CLK_DISABLE() __HAL_RCC_DFSDM1_CLK_DISABLE()
|
||||
#define AUDIO_DFSDM_DMA_CLK_ENABLE() __HAL_RCC_DMA1_CLK_ENABLE()
|
||||
|
||||
// LCD Interface
|
||||
#define OMV_RGB_DISPLAY_CONTROLLER (LTDC)
|
||||
#define OMV_RGB_DISPLAY_BL_PIN (&omv_pin_B12_GPIO)
|
||||
#define OMV_RGB_DISPLAY_CLK_ENABLE() __HAL_RCC_LTDC_CLK_ENABLE()
|
||||
#define OMV_RGB_DISPLAY_CLK_DISABLE() __HAL_RCC_LTDC_CLK_DISABLE()
|
||||
#define OMV_RGB_DISPLAY_FORCE_RESET() __HAL_RCC_LTDC_FORCE_RESET()
|
||||
#define OMV_RGB_DISPLAY_RELEASE_RESET() __HAL_RCC_LTDC_RELEASE_RESET()
|
||||
|
||||
// DSI Interface
|
||||
#define OMV_DISPLAY_ST7701_ENABLE (1)
|
||||
#define OMV_DSI_DISPLAY_CONTROLLER (DSI)
|
||||
#define OMV_DSI_DISPLAY_CONTROLLER_INIT st7701_init
|
||||
#define OMV_DSI_DISPLAY_TE_ENABLE (1)
|
||||
#define OMV_DSI_DISPLAY_BL_PIN (&omv_pin_B12_GPIO)
|
||||
#define OMV_DSI_DISPLAY_CLK_ENABLE() __HAL_RCC_DSI_CLK_ENABLE()
|
||||
#define OMV_DSI_DISPLAY_CLK_DISABLE() __HAL_RCC_DSI_CLK_DISABLE()
|
||||
#define OMV_DSI_DISPLAY_FORCE_RESET() __HAL_RCC_DSI_FORCE_RESET()
|
||||
#define OMV_DSI_DISPLAY_RELEASE_RESET() __HAL_RCC_DSI_RELEASE_RESET()
|
||||
|
||||
#endif //__OMV_BOARDCONFIG_H__
|
||||
29
src/omv/boards/ARDUINO_GIGA/omv_boardconfig.mk
Executable file
29
src/omv/boards/ARDUINO_GIGA/omv_boardconfig.mk
Executable file
@ -0,0 +1,29 @@
|
||||
MCU=STM32H747xx
|
||||
CPU=cortex-m7
|
||||
FPU=fpv5-sp-d16
|
||||
PORT=stm32
|
||||
HAL_DIR=hal/stm32/h7
|
||||
ARM_MATH=ARM_MATH_CM7
|
||||
HAL_INC='<stm32h7xx_hal.h>'
|
||||
CFLAGS_MCU=MCU_SERIES_H7
|
||||
VECT_TAB_OFFSET=0x40000
|
||||
MAIN_APP_ADDR=0x08040000
|
||||
M4_VECT_TAB_OFFSET=0x20000
|
||||
M4_APP_ADDR=0x08020000
|
||||
OMV_HSE_VALUE=16000000
|
||||
DFU_DEVICE=0x2341:0x035b
|
||||
OMV_BOARD_EXTRA_CFLAGS = -DCORE_CM7 -DUSE_USB_FS \
|
||||
-DCYW43_FIRMWARE_ADDRESS=0x90F00000 \
|
||||
-DCYW43_CHIPSET_FIRMWARE_INCLUDE_FILE="\"$(TOP_DIR)/drivers/cyw4343/firmware/cyw4343_ext_fw.h\""
|
||||
OMV_ENABLE_BL=0
|
||||
OMV_ENABLE_UVC=1
|
||||
OMV_ENABLE_CM4=0
|
||||
MICROPY_PY_SENSOR = 1
|
||||
MICROPY_PY_ULAB = 1
|
||||
MICROPY_PY_LWIP = 1
|
||||
MICROPY_PY_NETWORK_CYW43 = 1
|
||||
MICROPY_PY_BLUETOOTH = 1
|
||||
MICROPY_BLUETOOTH_NIMBLE = 1
|
||||
MICROPY_PY_AUDIO = 1
|
||||
MICROPY_PY_MICRO_SPEECH = 1
|
||||
MICROPY_PY_DISPLAY = 1
|
||||
32
src/omv/boards/ARDUINO_GIGA/omv_pins.h
Normal file
32
src/omv/boards/ARDUINO_GIGA/omv_pins.h
Normal file
@ -0,0 +1,32 @@
|
||||
OMV_GPIO_DEFINE(A, 1, NONE, GPIO)
|
||||
OMV_GPIO_DEFINE(A, 6, AF13, DCMI)
|
||||
OMV_GPIO_DEFINE(A, 8, AF1, TIM1)
|
||||
OMV_GPIO_DEFINE(B, 6, AF6, I2C4)
|
||||
OMV_GPIO_DEFINE(B, 8, AF4, I2C1)
|
||||
OMV_GPIO_DEFINE(B, 9, AF4, I2C1)
|
||||
OMV_GPIO_DEFINE(B, 12, NONE, GPIO)
|
||||
OMV_GPIO_DEFINE(C, 1, AF3, DFSDM1)
|
||||
OMV_GPIO_DEFINE(C, 2, AF5, SPI2)
|
||||
OMV_GPIO_DEFINE(C, 3, AF5, SPI2)
|
||||
OMV_GPIO_DEFINE(C, 13, NONE, GPIO)
|
||||
OMV_GPIO_DEFINE(C, 15, NONE, GPIO)
|
||||
OMV_GPIO_DEFINE(D, 3, AF3, DFSDM1)
|
||||
OMV_GPIO_DEFINE(D, 4, NONE, GPIO)
|
||||
OMV_GPIO_DEFINE(E, 2, AF2, SAI1)
|
||||
OMV_GPIO_DEFINE(E, 2, AF10, SAI4)
|
||||
OMV_GPIO_DEFINE(G, 11, AF13, DCMI)
|
||||
OMV_GPIO_DEFINE(H, 8, AF13, DCMI)
|
||||
OMV_GPIO_DEFINE(H, 9, AF13, DCMI)
|
||||
OMV_GPIO_DEFINE(H, 10, AF13, DCMI)
|
||||
OMV_GPIO_DEFINE(H, 11, AF13, DCMI)
|
||||
OMV_GPIO_DEFINE(H, 12, AF4, I2C4)
|
||||
OMV_GPIO_DEFINE(H, 14, AF13, DCMI)
|
||||
OMV_GPIO_DEFINE(H, 15, NONE, GPIO)
|
||||
OMV_GPIO_DEFINE(I, 0, NONE, GPIO)
|
||||
OMV_GPIO_DEFINE(I, 1, AF5, SPI2)
|
||||
OMV_GPIO_DEFINE(I, 4, AF13, DCMI)
|
||||
OMV_GPIO_DEFINE(I, 5, AF13, DCMI)
|
||||
OMV_GPIO_DEFINE(I, 6, AF13, DCMI)
|
||||
OMV_GPIO_DEFINE(I, 7, AF13, DCMI)
|
||||
OMV_GPIO_DEFINE(J, 9, AF1, TIM1)
|
||||
OMV_GPIO_DEFINE(K, 1, NONE, GPIO)
|
||||
19
src/omv/boards/ARDUINO_GIGA/readme_txt.h
Normal file
19
src/omv/boards/ARDUINO_GIGA/readme_txt.h
Normal file
@ -0,0 +1,19 @@
|
||||
static const char fresh_readme_txt[] =
|
||||
"Thank you for supporting Arduino and the OpenMV project!\r\n"
|
||||
"\r\n"
|
||||
"To download the OpenMV IDE, please visit:\r\n"
|
||||
"https://openmv.io/pages/download\r\n"
|
||||
"\r\n"
|
||||
"For tutorials and documentation, please visit:\r\n"
|
||||
"https://docs.arduino.cc/\r\n"
|
||||
"http://docs.openmv.io/\r\n"
|
||||
"\r\n"
|
||||
"For technical OpenMV support and projects, please visit the forums:\r\n"
|
||||
"http://forums.openmv.io/\r\n"
|
||||
"\r\n"
|
||||
"For Arduino related issues, please visit the Arduino help center:\r\n"
|
||||
"https://support.arduino.cc/\r\n"
|
||||
"\r\n"
|
||||
"Please use Github to report bugs and issues:\r\n"
|
||||
"https://github.com/openmv/openmv\r\n"
|
||||
;
|
||||
18
src/omv/boards/ARDUINO_GIGA/ulab_config.h
Normal file
18
src/omv/boards/ARDUINO_GIGA/ulab_config.h
Normal file
@ -0,0 +1,18 @@
|
||||
/*
|
||||
* This file is part of the OpenMV project.
|
||||
*
|
||||
* Copyright (c) 2023 Ibrahim Abdelkader <iabdalkader@openmv.io>
|
||||
* Copyright (c) 2023 Kwabena W. Agyeman <kwagyeman@openmv.io>
|
||||
*
|
||||
* This work is licensed under the MIT license, see the file LICENSE for details.
|
||||
*
|
||||
* Ulab config file.
|
||||
*/
|
||||
#ifndef __ULAB_CONFIG_H__
|
||||
#define __ULAB_CONFIG_H__
|
||||
// Override ulab defaults here.
|
||||
#define NDARRAY_BINARY_USES_FUN_POINTER (1)
|
||||
#define ULAB_VECTORISE_USES_FUN_POINTER (1)
|
||||
#define ULAB_SCIPY_HAS_OPTIMIZE_MODULE (1)
|
||||
#define ULAB_SCIPY_HAS_SPECIAL_MODULE (0)
|
||||
#endif //__ULAB_CONFIG_H__
|
||||
Loading…
Reference in New Issue
Block a user