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https://github.com/openmv/openmv.git
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commit
816571b40a
@ -215,14 +215,20 @@ void SystemClock_Config(void)
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/* Enable HSE Oscillator and activate PLL with HSE as source */
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#if defined(OMV_OSC_HSE_STATE)
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RCC_OscInitStruct.HSEState = OMV_OSC_HSE_STATE;
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RCC_OscInitStruct.OscillatorType |= RCC_OSCILLATORTYPE_HSE;
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#endif
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#if defined(OMV_OSC_HSI_STATE)
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RCC_OscInitStruct.HSIState = OMV_OSC_HSI_STATE;
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RCC_OscInitStruct.OscillatorType |= RCC_OSCILLATORTYPE_HSI;
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#endif
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#if defined(OMV_OSC_CSI_STATE)
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RCC_OscInitStruct.CSIState = OMV_OSC_CSI_STATE;
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RCC_OscInitStruct.OscillatorType |= RCC_OSCILLATORTYPE_CSI;
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#endif
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#if defined(OMV_OSC_HSI48_STATE)
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RCC_OscInitStruct.HSI48State = OMV_OSC_HSI48_STATE;
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RCC_OscInitStruct.OscillatorType |= RCC_OSCILLATORTYPE_HSI48;
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#endif
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RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
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RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
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RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
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RCC_OscInitStruct.PLL.PLLM = OMV_OSC_PLL1M;
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@ -274,17 +280,19 @@ void SystemClock_Config(void)
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|RCC_PERIPHCLK_SPI3|RCC_PERIPHCLK_SPI2
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|RCC_PERIPHCLK_SDMMC|RCC_PERIPHCLK_I2C2
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|RCC_PERIPHCLK_ADC|RCC_PERIPHCLK_USB
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|RCC_PERIPHCLK_QSPI|RCC_PERIPHCLK_FMC;
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PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_PLL;
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|RCC_PERIPHCLK_QSPI|RCC_PERIPHCLK_FMC
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|RCC_PERIPHCLK_RNG;
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PeriphClkInitStruct.UsbClockSelection = OMV_OSC_USB_CLKSOURCE;
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PeriphClkInitStruct.SdmmcClockSelection = RCC_SDMMCCLKSOURCE_PLL;
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PeriphClkInitStruct.FdcanClockSelection = RCC_FDCANCLKSOURCE_PLL;
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PeriphClkInitStruct.FmcClockSelection = RCC_FMCCLKSOURCE_PLL2;
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PeriphClkInitStruct.QspiClockSelection = RCC_QSPICLKSOURCE_PLL2;
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PeriphClkInitStruct.AdcClockSelection = OMV_OSC_ADC_SOURCE;
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PeriphClkInitStruct.Spi123ClockSelection = OMV_OSC_SPI123_SOURCE;
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PeriphClkInitStruct.AdcClockSelection = OMV_OSC_ADC_CLKSOURCE;
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PeriphClkInitStruct.Spi123ClockSelection = OMV_OSC_SPI123_CLKSOURCE;
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PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_LSI;
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PeriphClkInitStruct.I2c123ClockSelection = RCC_I2C123CLKSOURCE_D2PCLK1;
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PeriphClkInitStruct.Spi45ClockSelection = RCC_SPI45CLKSOURCE_PLL2;
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PeriphClkInitStruct.RngClockSelection = RCC_RNGCLKSOURCE_HSI48;
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if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) {
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// Initialization Error
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@ -38,7 +38,6 @@
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// HSE/HSI/CSI State
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#define OMV_OSC_HSE_STATE (RCC_HSE_ON)
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#define OMV_OSC_HSI_STATE (RCC_HSI_OFF)
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// Flash Latency
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#define OMV_FLASH_LATENCY (FLASH_LATENCY_5)
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@ -77,7 +77,6 @@
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// HSE/HSI/CSI State
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#define OMV_OSC_HSE_STATE (RCC_HSE_ON)
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#define OMV_OSC_HSI_STATE (RCC_HSI_OFF)
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// Flash Latency
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#define OMV_FLASH_LATENCY (FLASH_LATENCY_7)
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@ -78,7 +78,6 @@
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// HSE/HSI/CSI State
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#define OMV_OSC_HSE_STATE (RCC_HSE_ON)
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#define OMV_OSC_HSI_STATE (RCC_HSI_OFF)
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// Flash Latency
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#define OMV_FLASH_LATENCY (FLASH_LATENCY_7)
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@ -106,13 +106,12 @@
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#define OMV_OSC_PLL3FRAC (0)
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// Clock Sources
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#define OMV_OSC_ADC_SOURCE RCC_ADCCLKSOURCE_PLL3
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#define OMV_OSC_SPI123_SOURCE RCC_SPI123CLKSOURCE_PLL3
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#define OMV_OSC_USB_CLKSOURCE RCC_USBCLKSOURCE_PLL
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#define OMV_OSC_ADC_CLKSOURCE RCC_ADCCLKSOURCE_PLL3
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#define OMV_OSC_SPI123_CLKSOURCE RCC_SPI123CLKSOURCE_PLL3
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// HSE/HSI/CSI State
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#define OMV_OSC_HSE_STATE (RCC_HSE_ON)
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#define OMV_OSC_HSI_STATE (RCC_HSI_OFF)
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#define OMV_OSC_CSI_STATE (RCC_CSI_OFF)
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// Flash Latency
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#define OMV_FLASH_LATENCY (FLASH_LATENCY_2)
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@ -110,13 +110,12 @@
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#define OMV_OSC_PLL3FRAC (0)
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// Clock Sources
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#define OMV_OSC_ADC_SOURCE RCC_ADCCLKSOURCE_PLL3
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#define OMV_OSC_SPI123_SOURCE RCC_SPI123CLKSOURCE_PLL3
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#define OMV_OSC_USB_CLKSOURCE RCC_USBCLKSOURCE_PLL
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#define OMV_OSC_ADC_CLKSOURCE RCC_ADCCLKSOURCE_PLL3
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#define OMV_OSC_SPI123_CLKSOURCE RCC_SPI123CLKSOURCE_PLL3
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// HSE/HSI/CSI State
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#define OMV_OSC_HSE_STATE (RCC_HSE_ON)
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#define OMV_OSC_HSI_STATE (RCC_HSI_OFF)
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#define OMV_OSC_CSI_STATE (RCC_CSI_OFF)
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// Flash Latency
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#define OMV_FLASH_LATENCY (FLASH_LATENCY_2)
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@ -80,8 +80,9 @@
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#define OMV_CORE_VBAT "3.3"
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// Clock Sources
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#define OMV_OSC_ADC_SOURCE RCC_ADCCLKSOURCE_PLL2
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#define OMV_OSC_SPI123_SOURCE RCC_SPI123CLKSOURCE_PLL2
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#define OMV_OSC_USB_CLKSOURCE RCC_USBCLKSOURCE_PLL
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#define OMV_OSC_ADC_CLKSOURCE RCC_ADCCLKSOURCE_PLL2
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#define OMV_OSC_SPI123_CLKSOURCE RCC_SPI123CLKSOURCE_PLL2
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//PLL1 48MHz for USB, SDMMC and FDCAN
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#define OMV_OSC_PLL1M (3)
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@ -115,8 +116,6 @@
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// HSE/HSI/CSI State
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#define OMV_OSC_HSE_STATE (RCC_HSE_ON)
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#define OMV_OSC_HSI_STATE (RCC_HSI_OFF)
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#define OMV_OSC_CSI_STATE (RCC_CSI_OFF)
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// Flash Latency
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#define OMV_FLASH_LATENCY (FLASH_LATENCY_2)
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@ -107,13 +107,13 @@
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#define OMV_OSC_PLL3FRAC (0)
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// Clock Sources
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#define OMV_OSC_ADC_SOURCE RCC_ADCCLKSOURCE_PLL3
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#define OMV_OSC_SPI123_SOURCE RCC_SPI123CLKSOURCE_PLL3
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#define OMV_OSC_USB_CLKSOURCE RCC_USBCLKSOURCE_HSI48
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#define OMV_OSC_ADC_CLKSOURCE RCC_ADCCLKSOURCE_PLL3
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#define OMV_OSC_SPI123_CLKSOURCE RCC_SPI123CLKSOURCE_PLL3
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// HSE/HSI/CSI State
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#define OMV_OSC_HSE_STATE (RCC_HSE_BYPASS)
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#define OMV_OSC_HSI_STATE (RCC_HSI_OFF)
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#define OMV_OSC_CSI_STATE (RCC_CSI_OFF)
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#define OMV_OSC_HSI48_STATE (RCC_HSI48_ON)
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// Flash Latency
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#define OMV_FLASH_LATENCY (FLASH_LATENCY_2)
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