Merge pull request #907 from openmv/pll_fixes

Pll fixes
This commit is contained in:
Ibrahim Abd Elkader 2020-09-26 18:03:59 +02:00 committed by GitHub
commit 816571b40a
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8 changed files with 26 additions and 24 deletions

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@ -215,14 +215,20 @@ void SystemClock_Config(void)
/* Enable HSE Oscillator and activate PLL with HSE as source */ /* Enable HSE Oscillator and activate PLL with HSE as source */
#if defined(OMV_OSC_HSE_STATE) #if defined(OMV_OSC_HSE_STATE)
RCC_OscInitStruct.HSEState = OMV_OSC_HSE_STATE; RCC_OscInitStruct.HSEState = OMV_OSC_HSE_STATE;
RCC_OscInitStruct.OscillatorType |= RCC_OSCILLATORTYPE_HSE;
#endif #endif
#if defined(OMV_OSC_HSI_STATE) #if defined(OMV_OSC_HSI_STATE)
RCC_OscInitStruct.HSIState = OMV_OSC_HSI_STATE; RCC_OscInitStruct.HSIState = OMV_OSC_HSI_STATE;
RCC_OscInitStruct.OscillatorType |= RCC_OSCILLATORTYPE_HSI;
#endif #endif
#if defined(OMV_OSC_CSI_STATE) #if defined(OMV_OSC_CSI_STATE)
RCC_OscInitStruct.CSIState = OMV_OSC_CSI_STATE; RCC_OscInitStruct.CSIState = OMV_OSC_CSI_STATE;
RCC_OscInitStruct.OscillatorType |= RCC_OSCILLATORTYPE_CSI;
#endif
#if defined(OMV_OSC_HSI48_STATE)
RCC_OscInitStruct.HSI48State = OMV_OSC_HSI48_STATE;
RCC_OscInitStruct.OscillatorType |= RCC_OSCILLATORTYPE_HSI48;
#endif #endif
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
RCC_OscInitStruct.PLL.PLLM = OMV_OSC_PLL1M; RCC_OscInitStruct.PLL.PLLM = OMV_OSC_PLL1M;
@ -274,17 +280,19 @@ void SystemClock_Config(void)
|RCC_PERIPHCLK_SPI3|RCC_PERIPHCLK_SPI2 |RCC_PERIPHCLK_SPI3|RCC_PERIPHCLK_SPI2
|RCC_PERIPHCLK_SDMMC|RCC_PERIPHCLK_I2C2 |RCC_PERIPHCLK_SDMMC|RCC_PERIPHCLK_I2C2
|RCC_PERIPHCLK_ADC|RCC_PERIPHCLK_USB |RCC_PERIPHCLK_ADC|RCC_PERIPHCLK_USB
|RCC_PERIPHCLK_QSPI|RCC_PERIPHCLK_FMC; |RCC_PERIPHCLK_QSPI|RCC_PERIPHCLK_FMC
PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_PLL; |RCC_PERIPHCLK_RNG;
PeriphClkInitStruct.UsbClockSelection = OMV_OSC_USB_CLKSOURCE;
PeriphClkInitStruct.SdmmcClockSelection = RCC_SDMMCCLKSOURCE_PLL; PeriphClkInitStruct.SdmmcClockSelection = RCC_SDMMCCLKSOURCE_PLL;
PeriphClkInitStruct.FdcanClockSelection = RCC_FDCANCLKSOURCE_PLL; PeriphClkInitStruct.FdcanClockSelection = RCC_FDCANCLKSOURCE_PLL;
PeriphClkInitStruct.FmcClockSelection = RCC_FMCCLKSOURCE_PLL2; PeriphClkInitStruct.FmcClockSelection = RCC_FMCCLKSOURCE_PLL2;
PeriphClkInitStruct.QspiClockSelection = RCC_QSPICLKSOURCE_PLL2; PeriphClkInitStruct.QspiClockSelection = RCC_QSPICLKSOURCE_PLL2;
PeriphClkInitStruct.AdcClockSelection = OMV_OSC_ADC_SOURCE; PeriphClkInitStruct.AdcClockSelection = OMV_OSC_ADC_CLKSOURCE;
PeriphClkInitStruct.Spi123ClockSelection = OMV_OSC_SPI123_SOURCE; PeriphClkInitStruct.Spi123ClockSelection = OMV_OSC_SPI123_CLKSOURCE;
PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_LSI; PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_LSI;
PeriphClkInitStruct.I2c123ClockSelection = RCC_I2C123CLKSOURCE_D2PCLK1; PeriphClkInitStruct.I2c123ClockSelection = RCC_I2C123CLKSOURCE_D2PCLK1;
PeriphClkInitStruct.Spi45ClockSelection = RCC_SPI45CLKSOURCE_PLL2; PeriphClkInitStruct.Spi45ClockSelection = RCC_SPI45CLKSOURCE_PLL2;
PeriphClkInitStruct.RngClockSelection = RCC_RNGCLKSOURCE_HSI48;
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) { if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) {
// Initialization Error // Initialization Error

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@ -38,7 +38,6 @@
// HSE/HSI/CSI State // HSE/HSI/CSI State
#define OMV_OSC_HSE_STATE (RCC_HSE_ON) #define OMV_OSC_HSE_STATE (RCC_HSE_ON)
#define OMV_OSC_HSI_STATE (RCC_HSI_OFF)
// Flash Latency // Flash Latency
#define OMV_FLASH_LATENCY (FLASH_LATENCY_5) #define OMV_FLASH_LATENCY (FLASH_LATENCY_5)

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@ -77,7 +77,6 @@
// HSE/HSI/CSI State // HSE/HSI/CSI State
#define OMV_OSC_HSE_STATE (RCC_HSE_ON) #define OMV_OSC_HSE_STATE (RCC_HSE_ON)
#define OMV_OSC_HSI_STATE (RCC_HSI_OFF)
// Flash Latency // Flash Latency
#define OMV_FLASH_LATENCY (FLASH_LATENCY_7) #define OMV_FLASH_LATENCY (FLASH_LATENCY_7)

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@ -78,7 +78,6 @@
// HSE/HSI/CSI State // HSE/HSI/CSI State
#define OMV_OSC_HSE_STATE (RCC_HSE_ON) #define OMV_OSC_HSE_STATE (RCC_HSE_ON)
#define OMV_OSC_HSI_STATE (RCC_HSI_OFF)
// Flash Latency // Flash Latency
#define OMV_FLASH_LATENCY (FLASH_LATENCY_7) #define OMV_FLASH_LATENCY (FLASH_LATENCY_7)

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@ -106,13 +106,12 @@
#define OMV_OSC_PLL3FRAC (0) #define OMV_OSC_PLL3FRAC (0)
// Clock Sources // Clock Sources
#define OMV_OSC_ADC_SOURCE RCC_ADCCLKSOURCE_PLL3 #define OMV_OSC_USB_CLKSOURCE RCC_USBCLKSOURCE_PLL
#define OMV_OSC_SPI123_SOURCE RCC_SPI123CLKSOURCE_PLL3 #define OMV_OSC_ADC_CLKSOURCE RCC_ADCCLKSOURCE_PLL3
#define OMV_OSC_SPI123_CLKSOURCE RCC_SPI123CLKSOURCE_PLL3
// HSE/HSI/CSI State // HSE/HSI/CSI State
#define OMV_OSC_HSE_STATE (RCC_HSE_ON) #define OMV_OSC_HSE_STATE (RCC_HSE_ON)
#define OMV_OSC_HSI_STATE (RCC_HSI_OFF)
#define OMV_OSC_CSI_STATE (RCC_CSI_OFF)
// Flash Latency // Flash Latency
#define OMV_FLASH_LATENCY (FLASH_LATENCY_2) #define OMV_FLASH_LATENCY (FLASH_LATENCY_2)

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@ -110,13 +110,12 @@
#define OMV_OSC_PLL3FRAC (0) #define OMV_OSC_PLL3FRAC (0)
// Clock Sources // Clock Sources
#define OMV_OSC_ADC_SOURCE RCC_ADCCLKSOURCE_PLL3 #define OMV_OSC_USB_CLKSOURCE RCC_USBCLKSOURCE_PLL
#define OMV_OSC_SPI123_SOURCE RCC_SPI123CLKSOURCE_PLL3 #define OMV_OSC_ADC_CLKSOURCE RCC_ADCCLKSOURCE_PLL3
#define OMV_OSC_SPI123_CLKSOURCE RCC_SPI123CLKSOURCE_PLL3
// HSE/HSI/CSI State // HSE/HSI/CSI State
#define OMV_OSC_HSE_STATE (RCC_HSE_ON) #define OMV_OSC_HSE_STATE (RCC_HSE_ON)
#define OMV_OSC_HSI_STATE (RCC_HSI_OFF)
#define OMV_OSC_CSI_STATE (RCC_CSI_OFF)
// Flash Latency // Flash Latency
#define OMV_FLASH_LATENCY (FLASH_LATENCY_2) #define OMV_FLASH_LATENCY (FLASH_LATENCY_2)

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@ -80,8 +80,9 @@
#define OMV_CORE_VBAT "3.3" #define OMV_CORE_VBAT "3.3"
// Clock Sources // Clock Sources
#define OMV_OSC_ADC_SOURCE RCC_ADCCLKSOURCE_PLL2 #define OMV_OSC_USB_CLKSOURCE RCC_USBCLKSOURCE_PLL
#define OMV_OSC_SPI123_SOURCE RCC_SPI123CLKSOURCE_PLL2 #define OMV_OSC_ADC_CLKSOURCE RCC_ADCCLKSOURCE_PLL2
#define OMV_OSC_SPI123_CLKSOURCE RCC_SPI123CLKSOURCE_PLL2
//PLL1 48MHz for USB, SDMMC and FDCAN //PLL1 48MHz for USB, SDMMC and FDCAN
#define OMV_OSC_PLL1M (3) #define OMV_OSC_PLL1M (3)
@ -115,8 +116,6 @@
// HSE/HSI/CSI State // HSE/HSI/CSI State
#define OMV_OSC_HSE_STATE (RCC_HSE_ON) #define OMV_OSC_HSE_STATE (RCC_HSE_ON)
#define OMV_OSC_HSI_STATE (RCC_HSI_OFF)
#define OMV_OSC_CSI_STATE (RCC_CSI_OFF)
// Flash Latency // Flash Latency
#define OMV_FLASH_LATENCY (FLASH_LATENCY_2) #define OMV_FLASH_LATENCY (FLASH_LATENCY_2)

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@ -107,13 +107,13 @@
#define OMV_OSC_PLL3FRAC (0) #define OMV_OSC_PLL3FRAC (0)
// Clock Sources // Clock Sources
#define OMV_OSC_ADC_SOURCE RCC_ADCCLKSOURCE_PLL3 #define OMV_OSC_USB_CLKSOURCE RCC_USBCLKSOURCE_HSI48
#define OMV_OSC_SPI123_SOURCE RCC_SPI123CLKSOURCE_PLL3 #define OMV_OSC_ADC_CLKSOURCE RCC_ADCCLKSOURCE_PLL3
#define OMV_OSC_SPI123_CLKSOURCE RCC_SPI123CLKSOURCE_PLL3
// HSE/HSI/CSI State // HSE/HSI/CSI State
#define OMV_OSC_HSE_STATE (RCC_HSE_BYPASS) #define OMV_OSC_HSE_STATE (RCC_HSE_BYPASS)
#define OMV_OSC_HSI_STATE (RCC_HSI_OFF) #define OMV_OSC_HSI48_STATE (RCC_HSI48_ON)
#define OMV_OSC_CSI_STATE (RCC_CSI_OFF)
// Flash Latency // Flash Latency
#define OMV_FLASH_LATENCY (FLASH_LATENCY_2) #define OMV_FLASH_LATENCY (FLASH_LATENCY_2)