Merge pull request #2735 from openmv/refactor_csi_init
Some checks are pending
🔥 Firmware Build / build-firmware (ARDUINO_GIGA) (push) Waiting to run
🔥 Firmware Build / build-firmware (ARDUINO_NANO_33_BLE_SENSE) (push) Waiting to run
🔥 Firmware Build / build-firmware (ARDUINO_NANO_RP2040_CONNECT) (push) Waiting to run
🔥 Firmware Build / build-firmware (ARDUINO_NICLA_VISION) (push) Waiting to run
🔥 Firmware Build / build-firmware (ARDUINO_PORTENTA_H7) (push) Waiting to run
🔥 Firmware Build / build-firmware (DOCKER) (push) Waiting to run
🔥 Firmware Build / build-firmware (OPENMV2) (push) Waiting to run
🔥 Firmware Build / build-firmware (OPENMV3) (push) Waiting to run
🔥 Firmware Build / build-firmware (OPENMV4) (push) Waiting to run
🔥 Firmware Build / build-firmware (OPENMV4P) (push) Waiting to run
🔥 Firmware Build / build-firmware (OPENMVPT) (push) Waiting to run
🔥 Firmware Build / build-firmware (OPENMV_AE3) (push) Waiting to run
🔥 Firmware Build / build-firmware (OPENMV_N6) (push) Waiting to run
🔥 Firmware Build / build-firmware (OPENMV_RT1060) (push) Waiting to run
🔥 Firmware Build / code-size-report (push) Blocked by required conditions
🔥 Firmware Build / stable-release (push) Blocked by required conditions
🔥 Firmware Build / development-release (push) Blocked by required conditions

misc: Refactor CSI initialization code.
This commit is contained in:
Ibrahim Abdelkader 2025-06-27 22:42:05 +03:00 committed by GitHub
commit 81dd44aef4
No known key found for this signature in database
GPG Key ID: B5690EEEBB952194
63 changed files with 2281 additions and 2898 deletions

View File

@ -46,11 +46,9 @@
#define OMV_OV2640_ENABLE (1)
#define OMV_OV5640_ENABLE (1)
#define OMV_OV5640_AF_ENABLE (1)
#define OMV_OV5640_CLK_FREQ (24000000)
#define OMV_OV5640_PLL_CTRL2 (0x64)
#define OMV_OV5640_PLL_CTRL3 (0x13)
#define OMV_OV5640_REV_Y_CHECK (1)
#define OMV_OV5640_REV_Y_FREQ (25000000)
#define OMV_OV5640_REV_Y_CTRL2 (0x54)
#define OMV_OV5640_REV_Y_CTRL3 (0x13)

View File

@ -32,11 +32,9 @@
#define OMV_OV5640_ENABLE (1)
#define OMV_OV5640_AF_ENABLE (1)
#define OMV_OV5640_CLK_FREQ (24000000)
#define OMV_OV5640_PLL_CTRL2 (0x64)
#define OMV_OV5640_PLL_CTRL3 (0x13)
#define OMV_OV5640_REV_Y_CHECK (1)
#define OMV_OV5640_REV_Y_FREQ (25000000)
#define OMV_OV5640_REV_Y_CTRL2 (0x54)
#define OMV_OV5640_REV_Y_CTRL3 (0x13)

View File

@ -30,11 +30,9 @@
// CSI drivers configuration.
#define OMV_OV5640_ENABLE (1)
#define OMV_OV5640_AF_ENABLE (1)
#define OMV_OV5640_CLK_FREQ (24000000)
#define OMV_OV5640_PLL_CTRL2 (0x64)
#define OMV_OV5640_PLL_CTRL3 (0x13)
#define OMV_OV5640_REV_Y_CHECK (1)
#define OMV_OV5640_REV_Y_FREQ (25000000)
#define OMV_OV5640_REV_Y_CTRL2 (0x54)
#define OMV_OV5640_REV_Y_CTRL3 (0x13)

View File

@ -40,11 +40,9 @@
#define OMV_OV5640_ENABLE (1)
#define OMV_OV5640_AF_ENABLE (1)
#define OMV_OV5640_CLK_FREQ (24000000)
#define OMV_OV5640_PLL_CTRL2 (0x64)
#define OMV_OV5640_PLL_CTRL3 (0x13)
#define OMV_OV5640_REV_Y_CHECK (1)
#define OMV_OV5640_REV_Y_FREQ (25000000)
#define OMV_OV5640_REV_Y_CTRL2 (0x54)
#define OMV_OV5640_REV_Y_CTRL3 (0x13)

View File

@ -27,11 +27,9 @@
// CSI drivers configuration.
#define OMV_OV5640_ENABLE (1)
#define OMV_OV5640_AF_ENABLE (1)
#define OMV_OV5640_CLK_FREQ (24000000)
#define OMV_OV5640_PLL_CTRL2 (0x64)
#define OMV_OV5640_PLL_CTRL3 (0x13)
#define OMV_OV5640_REV_Y_CHECK (0)
#define OMV_OV5640_REV_Y_FREQ (25000000)
#define OMV_OV5640_REV_Y_CTRL2 (0x54)
#define OMV_OV5640_REV_Y_CTRL3 (0x13)

View File

@ -41,29 +41,9 @@
#include "omv_i2c.h"
#include "omv_csi.h"
#include "omv_boardconfig.h"
#include "ov2640.h"
#include "ov5640.h"
#include "ov7725.h"
#include "ov7670.h"
#include "ov7690.h"
#include "ov9650.h"
#include "mt9v0xx.h"
#include "mt9m114.h"
#include "lepton.h"
#include "boson.h"
#include "hm01b0.h"
#include "hm0360.h"
#include "pag7920.h"
#include "pag7936.h"
#include "paj6100.h"
#include "ps5520.h"
#include "frogeye2020.h"
#include "gc2145.h"
#include "genx320.h"
#include "softcsi.h"
#include "framebuffer.h"
#include "unaligned_memcpy.h"
#include "sensor_config.h"
#ifndef OMV_CSI_RESET_DELAY
#define OMV_CSI_RESET_DELAY (10)
@ -146,6 +126,10 @@ __weak void omv_csi_init0() {
omv_csi_t *csi = &csi_all[i];
omv_i2c_t *i2c = csi->i2c;
if (!csi->detected) {
continue;
}
// Abort ongoing transfer
omv_csi_abort(csi, true, false);
@ -336,12 +320,6 @@ static size_t omv_csi_detect(omv_i2c_t *i2c, i2c_dev_t *dev_list) {
break;
#endif //(OMV_MT9V0XX_ENABLE == 1)
#if (OMV_MT9M114_ENABLE == 1)
case MT9M114_SLV_ADDR:
omv_i2c_readw2(i2c, slv_addr, ON_CHIP_ID, (uint16_t *) &chip_id);
break;
#endif // (OMV_MT9M114_ENABLE == 1)
#if (OMV_BOSON_ENABLE == 1)
case BOSON_SLV_ADDR:
chip_id = BOSON_ID;
@ -366,26 +344,24 @@ static size_t omv_csi_detect(omv_i2c_t *i2c, i2c_dev_t *dev_list) {
break;
#endif // (OMV_FROGEYE2020_ENABLE == 1)
#if (OMV_PAG7920_ENABLE == 1)
#if (OMV_PAG7920_ENABLE == 1) || (OMV_PAG7936_ENABLE == 1)
// PAG720 and PAG7936 share the same I2C address.
case PAG7920_SLV_ADDR:
omv_i2c_readw2(i2c, slv_addr, PIXART_CHIP_ID, (uint16_t *) &chip_id);
chip_id = ((chip_id << 8) | (chip_id >> 8)) & 0xFFFF;
break;
#endif // (OMV_PAG7920_ENABLE == 1)
#if (OMV_PAG7936_ENABLE == 1)
case PAG7936_SLV_ADDR:
case PAG7936_SLV_ADDR_ALT:
omv_i2c_readw2(i2c, slv_addr, PIXART_CHIP_ID, (uint16_t *) &chip_id);
chip_id = ((chip_id << 8) | (chip_id >> 8)) & 0xFFFF;
break;
#endif // (OMV_PAG7936_ENABLE == 1)
#endif // (OMV_PAG7920_ENABLE == 1) || (OMV_PAG7936_ENABLE == 1)
#if (OMV_PS5520_ENABLE == 1)
case PS5520_SLV_ADDR:
omv_i2c_readw2(i2c, slv_addr, PIXART_CHIP_ID, (uint16_t *) &chip_id);
#if (OMV_MT9M114_ENABLE == 1) || (OMV_PS5520_ENABLE == 1)
// MT9M114 and PS5520 share the same I2C address.
case MT9M114_SLV_ADDR:
omv_i2c_readw2(i2c, slv_addr, ON_CHIP_ID, (uint16_t *) &chip_id);
if (slv_addr != MT9M114_ID) {
omv_i2c_readw2(i2c, slv_addr, PIXART_CHIP_ID, (uint16_t *) &chip_id);
}
break;
#endif // (OMV_PS5520_ENABLE == 1)
#endif // (OMV_MT9M114_ENABLE == 1) || (OMV_PS5520_ENABLE == 1)
}
if (chip_id && dev_count < OMV_CSI_MAX_DEVICES) {
@ -397,21 +373,20 @@ static size_t omv_csi_detect(omv_i2c_t *i2c, i2c_dev_t *dev_list) {
}
int omv_csi_probe(omv_i2c_t *i2c) {
int init_ret = 0;
bool reset_pol = OMV_CSI_ACTIVE_HIGH;
bool power_pol = OMV_CSI_ACTIVE_HIGH;
size_t dev_count = 0;
size_t aux_count = 0;
i2c_dev_t dev_list[OMV_CSI_MAX_DEVICES] = { 0 };
bool reset_pol = OMV_CSI_ACTIVE_HIGH;
bool power_pol = OMV_CSI_ACTIVE_HIGH;
// Active power-down state, active reset state
// This order is required for all sensors to work correctly.
const omv_csi_polarity_t polarity_configs[][2] = {
{ OMV_CSI_ACTIVE_LOW, OMV_CSI_ACTIVE_LOW },
{ OMV_CSI_ACTIVE_LOW, OMV_CSI_ACTIVE_HIGH },
{ OMV_CSI_ACTIVE_HIGH, OMV_CSI_ACTIVE_LOW },
{ OMV_CSI_ACTIVE_HIGH, OMV_CSI_ACTIVE_HIGH },
{ OMV_CSI_ACTIVE_HIGH, OMV_CSI_ACTIVE_LOW },
{ OMV_CSI_ACTIVE_LOW, OMV_CSI_ACTIVE_HIGH },
{ OMV_CSI_ACTIVE_LOW, OMV_CSI_ACTIVE_LOW },
};
// Scan the bus multiple times using different reset and power polarities,
@ -419,7 +394,7 @@ int omv_csi_probe(omv_i2c_t *i2c) {
for (size_t i=0; dev_count == 0 && i<OMV_ARRAY_SIZE(polarity_configs); i++) {
// Power cycle
#if defined(OMV_CSI_POWER_PIN)
power_pol = polarity_configs[0][0];
power_pol = polarity_configs[i][0];
omv_gpio_write(OMV_CSI_POWER_PIN, power_pol);
mp_hal_delay_ms(10);
omv_gpio_write(OMV_CSI_POWER_PIN, !power_pol);
@ -428,7 +403,7 @@ int omv_csi_probe(omv_i2c_t *i2c) {
// Reset
#if defined(OMV_CSI_RESET_PIN)
reset_pol = polarity_configs[0][1];
reset_pol = polarity_configs[i][1];
omv_gpio_write(OMV_CSI_RESET_PIN, reset_pol);
mp_hal_delay_ms(10);
omv_gpio_write(OMV_CSI_RESET_PIN, !reset_pol);
@ -439,7 +414,7 @@ int omv_csi_probe(omv_i2c_t *i2c) {
}
// Add special devices, such as SPI sensors, soft-CSI etc...
#if (OMV_SOFTCSI_ENABLE == 1)
#if OMV_SOFTCSI_ENABLE
if (dev_count < OMV_CSI_MAX_DEVICES) {
dev_list[dev_count++] = (i2c_dev_t) { 0, SOFTCSI_ID };
}
@ -462,221 +437,58 @@ int omv_csi_probe(omv_i2c_t *i2c) {
// Initialize detected sensors.
for (size_t i=0; i<dev_count; i++) {
omv_csi_t *csi = &csi_all[i];
csi->power_pol = power_pol;
csi->reset_pol = reset_pol;
csi->chip_id = dev_list[i].chip_id;
csi->slv_addr = dev_list[i].slv_addr;
csi->detected = true;
switch (dev_list[i].chip_id) {
#if (OMV_OV2640_ENABLE == 1)
case OV2640_ID:
if (omv_csi_set_clk_frequency(OMV_OV2640_CLK_FREQ) != 0) {
return OMV_CSI_ERROR_TIM_INIT_FAILED;
}
init_ret = ov2640_init(csi);
break;
#endif // (OMV_OV2640_ENABLE == 1)
uint32_t clk_hz = 0;
sensor_init_t init_fun = NULL;
#if (OMV_OV5640_ENABLE == 1)
case OV5640_ID: {
int freq = OMV_OV5640_CLK_FREQ;
#if (OMV_OV5640_REV_Y_CHECK == 1)
if (HAL_GetREVID() < 0x2003) {
// Is this REV Y?
freq = OMV_OV5640_REV_Y_FREQ;
}
#endif
if (omv_csi_set_clk_frequency(freq) != 0) {
return OMV_CSI_ERROR_TIM_INIT_FAILED;
}
init_ret = ov5640_init(csi);
// Find the sensors init function.
for (size_t i=0; i<OMV_ARRAY_SIZE(sensor_config_table); i++) {
const sensor_config_t *config = &sensor_config_table[i];
if (csi->chip_id == config->chip_id) {
clk_hz = config->clk_hz;
init_fun = config->init_fun;
break;
}
#endif // (OMV_OV5640_ENABLE == 1)
#if (OMV_OV7670_ENABLE == 1)
case OV7670_ID:
if (omv_csi_set_clk_frequency(OMV_OV7670_CLK_FREQ) != 0) {
return OMV_CSI_ERROR_TIM_INIT_FAILED;
}
init_ret = ov7670_init(csi);
break;
#endif // (OMV_OV7670_ENABLE == 1)
#if (OMV_OV7690_ENABLE == 1)
case OV7690_ID:
if (omv_csi_set_clk_frequency(OMV_OV7690_CLK_FREQ) != 0) {
return OMV_CSI_ERROR_TIM_INIT_FAILED;
}
init_ret = ov7690_init(csi);
break;
#endif // (OMV_OV7690_ENABLE == 1)
#if (OMV_OV7725_ENABLE == 1)
case OV7725_ID:
init_ret = ov7725_init(csi);
break;
#endif // (OMV_OV7725_ENABLE == 1)
#if (OMV_OV9650_ENABLE == 1)
case OV9650_ID:
init_ret = ov9650_init(csi);
break;
#endif // (OMV_OV9650_ENABLE == 1)
#if (OMV_MT9V0XX_ENABLE == 1)
case MT9V0X2_ID_V_1:
case MT9V0X2_ID_V_2:
// Force old versions to the newest.
csi->chip_id = MT9V0X2_ID;
case MT9V0X2_ID:
case MT9V0X4_ID:
if (omv_csi_set_clk_frequency(OMV_MT9V0XX_CLK_FREQ) != 0) {
return OMV_CSI_ERROR_TIM_INIT_FAILED;
}
init_ret = mt9v0xx_init(csi);
break;
#endif //(OMV_MT9V0XX_ENABLE == 1)
#if (OMV_MT9M114_ENABLE == 1)
case MT9M114_ID:
if (omv_csi_set_clk_frequency(OMV_MT9M114_CLK_FREQ) != 0) {
return OMV_CSI_ERROR_TIM_INIT_FAILED;
}
init_ret = mt9m114_init(csi);
break;
#endif //(OMV_MT9M114_ENABLE == 1)
#if (OMV_BOSON_ENABLE == 1)
case BOSON_ID:
if (omv_csi_set_clk_frequency(OMV_BOSON_CLK_FREQ) != 0) {
return OMV_CSI_ERROR_TIM_INIT_FAILED;
}
init_ret = boson_init(csi);
break;
#endif // (OMV_BOSON_ENABLE == 1)
#if (OMV_LEPTON_ENABLE == 1)
case LEPTON_ID:
if (dev_count == 1 &&
omv_csi_set_clk_frequency(OMV_LEPTON_CLK_FREQ) != 0) {
return OMV_CSI_ERROR_TIM_INIT_FAILED;
}
init_ret = lepton_init(csi);
break;
#endif // (OMV_LEPTON_ENABLE == 1)
#if (OMV_HM01B0_ENABLE == 1)
case HM01B0_ID:
if (omv_csi_set_clk_frequency(OMV_HM01B0_CLK_FREQ) != 0) {
return OMV_CSI_ERROR_TIM_INIT_FAILED;
}
init_ret = hm01b0_init(csi);
break;
#endif //(OMV_HM01B0_ENABLE == 1)
#if (OMV_HM0360_ENABLE == 1)
case HM0360_ID:
if (omv_csi_set_clk_frequency(OMV_HM0360_CLK_FREQ) != 0) {
return OMV_CSI_ERROR_TIM_INIT_FAILED;
}
init_ret = hm0360_init(csi);
break;
#endif //(OMV_HM0360_ENABLE == 1)
#if (OMV_GC2145_ENABLE == 1)
case GC2145_ID:
if (omv_csi_set_clk_frequency(OMV_GC2145_CLK_FREQ) != 0) {
return OMV_CSI_ERROR_TIM_INIT_FAILED;
}
init_ret = gc2145_init(csi);
break;
#endif //(OMV_GC2145_ENABLE == 1)
#if (OMV_GENX320_ENABLE == 1)
case GENX320_ID_ES:
case GENX320_ID_MP:
if (omv_csi_set_clk_frequency(OMV_GENX320_CLK_FREQ) != 0) {
return OMV_CSI_ERROR_TIM_INIT_FAILED;
}
init_ret = genx320_init(csi);
break;
#endif // (OMV_GENX320_ENABLE == 1)
#if (OMV_PAG7920_ENABLE == 1)
case PAG7920_ID:
if (omv_csi_set_clk_frequency(OMV_PAG7920_CLK_FREQ) != 0) {
return OMV_CSI_ERROR_TIM_INIT_FAILED;
}
init_ret = pag7920_init(csi);
break;
#endif // (OMV_PAG7920_ENABLE == 1)
#if (OMV_PAG7936_ENABLE == 1)
case PAG7936_ID:
if (omv_csi_set_clk_frequency(OMV_PAG7936_CLK_FREQ) != 0) {
return OMV_CSI_ERROR_TIM_INIT_FAILED;
}
init_ret = pag7936_init(csi);
break;
#endif // (OMV_PAG7936_ENABLE == 1)
#if (OMV_PAJ6100_ENABLE == 1)
case PAJ6100_ID:
if (omv_csi_set_clk_frequency(OMV_PAJ6100_CLK_FREQ) != 0) {
return OMV_CSI_ERROR_TIM_INIT_FAILED;
}
init_ret = paj6100_init(csi);
break;
#endif // (OMV_PAJ6100_ENABLE == 1)
#if (OMV_PS5520_ENABLE == 1)
case PS5520_ID:
if (omv_csi_set_clk_frequency(OMV_PS5520_CLK_FREQ) != 0) {
return OMV_CSI_ERROR_TIM_INIT_FAILED;
}
init_ret = ps5520_init(csi);
break;
#endif // (OMV_PS5520_ENABLE == 1)
#if (OMV_FROGEYE2020_ENABLE == 1)
case FROGEYE2020_ID:
if (omv_csi_set_clk_frequency(OMV_FROGEYE2020_CLK_FREQ) != 0) {
return OMV_CSI_ERROR_TIM_INIT_FAILED;
}
init_ret = frogeye2020_init(csi);
break;
#endif // (OMV_FROGEYE2020_ENABLE == 1)
#if (OMV_SOFTCSI_ENABLE == 1)
case SOFTCSI_ID:
init_ret = softcsi_init(csi);
break;
#endif // (OMV_SOFTCSI_ENABLE == 1)
default:
return OMV_CSI_ERROR_ISC_UNSUPPORTED;
break;
}
if (init_ret != 0) {
// Sensor init failed.
if (init_fun == NULL) {
return OMV_CSI_ERROR_ISC_UNSUPPORTED;
} else if (init_fun(csi) != 0) {
return OMV_CSI_ERROR_ISC_INIT_FAILED;
}
// Special case for OV5640.
#if (OMV_OV5640_REV_Y_CHECK == 1)
if (csi->chip_id == OV5640_ID && HAL_GetREVID() < 0x2003) {
clk_hz = OMV_OV5640_REV_Y_FREQ;
}
#endif
// Allow reconfiguring (or disabling) the external clock
// if just one sensor is detected, or for main sensors.
if (dev_count == 1 || !csi->auxiliary) {
omv_csi_set_clk_frequency(clk_hz);
}
// Count aux devices.
aux_count += csi->auxiliary;
}
// In case a single aux sensor was detected, clear
// the aux flag so it gets used as the main sensor.
// Special case: A single aux sensor was detected, clear
// the auxiliary flag so it gets used as the main sensor.
if (dev_count == 1 && csi_all[0].auxiliary) {
csi_all[0].auxiliary = 0;
aux_count--;
}
// Special case: two aux sensors detected, for example
// SoftCSI and Lepton. Use SoftCSI as the main sensor.
// Special case: Soft-CSI and another aux sensor detected,
// (Lepton for example). Use Soft-CSI for the main sensor.
if (dev_count == aux_count) {
for (size_t i=0; i<dev_count; i++) {
omv_csi_t *csi = &csi_all[i];
@ -694,7 +506,8 @@ int omv_csi_probe(omv_i2c_t *i2c) {
return -1;
}
// Auxiliary sensors use dynamically allocated frame buffers.
// Clear the FB pointer for all aux sensors, as they use
// dynamically allocated frame buffers.
for (size_t i=0; i<dev_count; i++) {
omv_csi_t *csi = &csi_all[i];
if (csi->auxiliary) {
@ -707,7 +520,8 @@ int omv_csi_probe(omv_i2c_t *i2c) {
__weak int omv_csi_config(omv_csi_t *csi, omv_csi_config_t config) {
// Call the sensor specific function.
if (csi->config != NULL &&
if (csi->detected &&
csi->config != NULL &&
csi->config(csi, config) != 0) {
return OMV_CSI_ERROR_CTL_FAILED;
}

View File

@ -182,7 +182,7 @@ int boson_init(omv_csi_t *csi) {
resolution[OMV_CSI_FRAMESIZE_QVGA][1] = 256;
if (reset(csi) != 0) {
return -1;
return OMV_CSI_ERROR_CSI_INIT_FAILED;
}
csi->chip_id = (boson_framesize == OMV_CSI_FRAMESIZE_VGA) ? BOSON_640_ID : BOSON_320_ID;

View File

@ -1,37 +0,0 @@
/*
* Copyright (C) 2023-2024 OpenMV, LLC.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Any redistribution, use, or modification in source or binary form
* is done solely for personal benefit and not for any commercial
* purpose or for monetary gain. For commercial licensing options,
* please contact openmv@openmv.io
*
* THIS SOFTWARE IS PROVIDED BY THE LICENSOR AND COPYRIGHT OWNER "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE LICENSOR OR COPYRIGHT
* OWNER BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
* OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Boson driver.
*/
#ifndef __BOSON_H__
#define __BOSON_H__
#define OMV_BOSON_CLK_FREQ (0)
int boson_init(omv_csi_t *csi);
#endif // __BOSON_H__

View File

@ -1,30 +0,0 @@
/*
* SPDX-License-Identifier: MIT
*
* Copyright (C) 2013-2024 OpenMV, LLC.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*
* FrogEye2020 driver.
*/
#ifndef __FROGEYE2020_H__
#define __FROGEYE2020_H__
#define OMV_FROGEYE2020_CLK_FREQ (5000000)
int frogeye2020_init(omv_csi_t *csi);
#endif // __FROGEYE2020_H__

View File

@ -33,7 +33,6 @@
#include "omv_i2c.h"
#include "omv_csi.h"
#include "gc2145.h"
#include "gc2145_regs.h"
#include "py/mphal.h"
#define BLANK_LINES 16

View File

@ -21,10 +21,24 @@
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*
* GC2145 driver.
* GC2145 register definitions.
*/
#ifndef __GC2145_H__
#define __GC2145_H__
#define OMV_GC2145_CLK_FREQ (12000000)
int gc2145_init(omv_csi_t *csi);
#endif // __GC2145_H__
#ifndef __GC2145_REGS_H__
#define __GC2145_REGS_H__
#define REG_AMODE1 (0x17)
#define REG_AMODE1_DEF (0x14)
#define REG_AMODE1_SET_HMIRROR(r, x) ((r & 0xFE) | ((x & 1) << 0))
#define REG_AMODE1_SET_VMIRROR(r, x) ((r & 0xFD) | ((x & 1) << 1))
#define REG_OUTPUT_FMT (0x84)
#define REG_OUTPUT_FMT_RGB565 (0x06)
#define REG_OUTPUT_FMT_YCBYCR (0x02)
#define REG_OUTPUT_FMT_BAYER (0x17)
#define REG_OUTPUT_SET_FMT(r, x) ((r & 0xE0) | (x))
#define REG_SYNC_MODE (0x86)
#define REG_SYNC_MODE_DEF (0x03)
#define REG_SYNC_MODE_COL_SWITCH (0x10)
#define REG_SYNC_MODE_ROW_SWITCH (0x20)
#endif //__GC2145_REGS_H__

View File

@ -1,44 +0,0 @@
/*
* SPDX-License-Identifier: MIT
*
* Copyright (C) 2013-2024 OpenMV, LLC.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*
* GC2145 register definitions.
*/
#ifndef __GC2145_REGS_H__
#define __GC2145_REGS_H__
#define REG_AMODE1 (0x17)
#define REG_AMODE1_DEF (0x14)
#define REG_AMODE1_SET_HMIRROR(r, x) ((r & 0xFE) | ((x & 1) << 0))
#define REG_AMODE1_SET_VMIRROR(r, x) ((r & 0xFD) | ((x & 1) << 1))
#define REG_OUTPUT_FMT (0x84)
#define REG_OUTPUT_FMT_RGB565 (0x06)
#define REG_OUTPUT_FMT_YCBYCR (0x02)
#define REG_OUTPUT_FMT_BAYER (0x17)
#define REG_OUTPUT_SET_FMT(r, x) ((r & 0xE0) | (x))
#define REG_SYNC_MODE (0x86)
#define REG_SYNC_MODE_DEF (0x03)
#define REG_SYNC_MODE_COL_SWITCH (0x10)
#define REG_SYNC_MODE_ROW_SWITCH (0x20)
#endif //__GC2145_REGS_H__

View File

@ -35,7 +35,6 @@
#include "omv_i2c.h"
#include "omv_csi.h"
#include "genx320.h"
#include "evt_2_0.h"
#include "psee_genx320.h"

View File

@ -1,30 +0,0 @@
/*
* SPDX-License-Identifier: MIT
*
* Copyright (C) 2013-2024 OpenMV, LLC.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*
* GENX320 driver.
*/
#ifndef __GENX320_H__
#define __GENX320_H__
#define OMV_GENX320_CLK_FREQ (24000000)
int genx320_init(omv_csi_t *csi);
#endif // __GENX320_H__

View File

@ -33,9 +33,7 @@
#include "omv_i2c.h"
#include "omv_csi.h"
#include "hm01b0.h"
#include "hm01b0_regs.h"
#define HIMAX_BOOT_RETRY (10)
#define HIMAX_LINE_LEN_PCK_FULL 0x178

View File

@ -21,10 +21,121 @@
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*
* HM01B0 driver.
* HM01B0 register definitions.
*/
#ifndef __HM01B0_H__
#define __HM01B0_H__
#define OMV_HM01B0_CLK_FREQ (6000000)
int hm01b0_init(omv_csi_t *csi);
#endif // __HM01B0_H__
#ifndef __REG_REGS_H__
#define __REG_REGS_H__
// Read only registers
#define MODEL_ID_H 0x0000
#define MODEL_ID_L 0x0001
#define FRAME_COUNT 0x0005
#define PIXEL_ORDER 0x0006
// Sensor mode control
#define MODE_SELECT 0x0100
#define IMG_ORIENTATION 0x0101
#define SW_RESET 0x0103
#define GRP_PARAM_HOLD 0x0104
// Sensor exposure gain control
#define INTEGRATION_H 0x0202
#define INTEGRATION_L 0x0203
#define ANALOG_GAIN 0x0205
#define DIGITAL_GAIN_H 0x020E
#define DIGITAL_GAIN_L 0x020F
// Frame timing control
#define FRAME_LEN_LINES_H 0x0340
#define FRAME_LEN_LINES_L 0x0341
#define LINE_LEN_PCK_H 0x0342
#define LINE_LEN_PCK_L 0x0343
// Binning mode control
#define READOUT_X 0x0383
#define READOUT_Y 0x0387
#define BINNING_MODE 0x0390
// Test pattern control
#define TEST_PATTERN_MODE 0x0601
// Black level control
#define BLC_CFG 0x1000
#define BLC_TGT 0x1003
#define BLI_EN 0x1006
#define BLC2_TGT 0x1007
// Sensor reserved
#define DPC_CTRL 0x1008
#define SINGLE_THR_HOT 0x100B
#define SINGLE_THR_COLD 0x100C
// VSYNC,HSYNC and pixel shift register
#define VSYNC_HSYNC_PIXEL_SHIFT_EN 0x1012
// Automatic exposure gain control
#define AE_CTRL 0x2100
#define AE_TARGET_MEAN 0x2101
#define AE_MIN_MEAN 0x2102
#define CONVERGE_IN_TH 0x2103
#define CONVERGE_OUT_TH 0x2104
#define MAX_INTG_H 0x2105
#define MAX_INTG_L 0x2106
#define MIN_INTG 0x2107
#define MAX_AGAIN_FULL 0x2108
#define MAX_AGAIN_BIN2 0x2109
#define MIN_AGAIN 0x210A
#define MAX_DGAIN 0x210B
#define MIN_DGAIN 0x210C
#define DAMPING_FACTOR 0x210D
#define FS_CTRL 0x210E
#define FS_60HZ_H 0x210F
#define FS_60HZ_L 0x2110
#define FS_50HZ_H 0x2111
#define FS_50HZ_L 0x2112
#define FS_HYST_TH 0x2113
// Motion detection control
#define MD_CTRL 0x2150
#define I2C_CLEAR 0x2153
#define WMEAN_DIFF_TH_H 0x2155
#define WMEAN_DIFF_TH_M 0x2156
#define WMEAN_DIFF_TH_L 0x2157
#define MD_THH 0x2158
#define MD_THM1 0x2159
#define MD_THM2 0x215A
#define MD_THL 0x215B
#define STATISTIC_CTRL 0x2000
#define MD_LROI_X_START_H 0x2011
#define MD_LROI_X_START_L 0x2012
#define MD_LROI_Y_START_H 0x2013
#define MD_LROI_Y_START_L 0x2014
#define MD_LROI_X_END_H 0x2015
#define MD_LROI_X_END_L 0x2016
#define MD_LROI_Y_END_H 0x2017
#define MD_LROI_Y_END_L 0x2018
#define MD_INTERRUPT 0x2160
// Sensor timing control
#define QVGA_WIN_EN 0x3010
#define SIX_BIT_MODE_EN 0x3011
#define PMU_AUTOSLEEP_FRAMECNT 0x3020
#define ADVANCE_VSYNC 0x3022
#define ADVANCE_HSYNC 0x3023
#define EARLY_GAIN 0x3035
// IO and clock control
#define BIT_CONTROL 0x3059
#define OSC_CLK_DIV 0x3060
#define ANA_Register_11 0x3061
#define IO_DRIVE_STR 0x3062
#define IO_DRIVE_STR2 0x3063
#define ANA_Register_14 0x3064
#define OUTPUT_PIN_STATUS_CONTROL 0x3065
#define ANA_Register_17 0x3067
#define PCLK_POLARITY 0x3068
/*
* Useful value of Himax registers
*/
#define HIMAX_RESET 0x01
#define HIMAX_MODE_STANDBY 0x00
#define HIMAX_MODE_STREAMING 0x01 // I2C triggered streaming enable
#define HIMAX_MODE_STREAMING_NFRAMES 0x03 // Output N frames
#define HIMAX_MODE_STREAMING_TRIG 0x05 // Hardware Trigger
#define HIMAX_SET_HMIRROR(r, x) ((r & 0xFE) | ((x & 1) << 0))
#define HIMAX_SET_VMIRROR(r, x) ((r & 0xFD) | ((x & 1) << 1))
#define PCLK_RISING_EDGE 0x00
#define PCLK_FALLING_EDGE 0x01
#define AE_CTRL_ENABLE 0x00
#define AE_CTRL_DISABLE 0x01
#endif //__REG_REGS_H__

View File

@ -1,141 +0,0 @@
/*
* SPDX-License-Identifier: MIT
*
* Copyright (C) 2013-2024 OpenMV, LLC.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*
* HM01B0 register definitions.
*/
#ifndef __REG_REGS_H__
#define __REG_REGS_H__
// Read only registers
#define MODEL_ID_H 0x0000
#define MODEL_ID_L 0x0001
#define FRAME_COUNT 0x0005
#define PIXEL_ORDER 0x0006
// Sensor mode control
#define MODE_SELECT 0x0100
#define IMG_ORIENTATION 0x0101
#define SW_RESET 0x0103
#define GRP_PARAM_HOLD 0x0104
// Sensor exposure gain control
#define INTEGRATION_H 0x0202
#define INTEGRATION_L 0x0203
#define ANALOG_GAIN 0x0205
#define DIGITAL_GAIN_H 0x020E
#define DIGITAL_GAIN_L 0x020F
// Frame timing control
#define FRAME_LEN_LINES_H 0x0340
#define FRAME_LEN_LINES_L 0x0341
#define LINE_LEN_PCK_H 0x0342
#define LINE_LEN_PCK_L 0x0343
// Binning mode control
#define READOUT_X 0x0383
#define READOUT_Y 0x0387
#define BINNING_MODE 0x0390
// Test pattern control
#define TEST_PATTERN_MODE 0x0601
// Black level control
#define BLC_CFG 0x1000
#define BLC_TGT 0x1003
#define BLI_EN 0x1006
#define BLC2_TGT 0x1007
// Sensor reserved
#define DPC_CTRL 0x1008
#define SINGLE_THR_HOT 0x100B
#define SINGLE_THR_COLD 0x100C
// VSYNC,HSYNC and pixel shift register
#define VSYNC_HSYNC_PIXEL_SHIFT_EN 0x1012
// Automatic exposure gain control
#define AE_CTRL 0x2100
#define AE_TARGET_MEAN 0x2101
#define AE_MIN_MEAN 0x2102
#define CONVERGE_IN_TH 0x2103
#define CONVERGE_OUT_TH 0x2104
#define MAX_INTG_H 0x2105
#define MAX_INTG_L 0x2106
#define MIN_INTG 0x2107
#define MAX_AGAIN_FULL 0x2108
#define MAX_AGAIN_BIN2 0x2109
#define MIN_AGAIN 0x210A
#define MAX_DGAIN 0x210B
#define MIN_DGAIN 0x210C
#define DAMPING_FACTOR 0x210D
#define FS_CTRL 0x210E
#define FS_60HZ_H 0x210F
#define FS_60HZ_L 0x2110
#define FS_50HZ_H 0x2111
#define FS_50HZ_L 0x2112
#define FS_HYST_TH 0x2113
// Motion detection control
#define MD_CTRL 0x2150
#define I2C_CLEAR 0x2153
#define WMEAN_DIFF_TH_H 0x2155
#define WMEAN_DIFF_TH_M 0x2156
#define WMEAN_DIFF_TH_L 0x2157
#define MD_THH 0x2158
#define MD_THM1 0x2159
#define MD_THM2 0x215A
#define MD_THL 0x215B
#define STATISTIC_CTRL 0x2000
#define MD_LROI_X_START_H 0x2011
#define MD_LROI_X_START_L 0x2012
#define MD_LROI_Y_START_H 0x2013
#define MD_LROI_Y_START_L 0x2014
#define MD_LROI_X_END_H 0x2015
#define MD_LROI_X_END_L 0x2016
#define MD_LROI_Y_END_H 0x2017
#define MD_LROI_Y_END_L 0x2018
#define MD_INTERRUPT 0x2160
// Sensor timing control
#define QVGA_WIN_EN 0x3010
#define SIX_BIT_MODE_EN 0x3011
#define PMU_AUTOSLEEP_FRAMECNT 0x3020
#define ADVANCE_VSYNC 0x3022
#define ADVANCE_HSYNC 0x3023
#define EARLY_GAIN 0x3035
// IO and clock control
#define BIT_CONTROL 0x3059
#define OSC_CLK_DIV 0x3060
#define ANA_Register_11 0x3061
#define IO_DRIVE_STR 0x3062
#define IO_DRIVE_STR2 0x3063
#define ANA_Register_14 0x3064
#define OUTPUT_PIN_STATUS_CONTROL 0x3065
#define ANA_Register_17 0x3067
#define PCLK_POLARITY 0x3068
/*
* Useful value of Himax registers
*/
#define HIMAX_RESET 0x01
#define HIMAX_MODE_STANDBY 0x00
#define HIMAX_MODE_STREAMING 0x01 // I2C triggered streaming enable
#define HIMAX_MODE_STREAMING_NFRAMES 0x03 // Output N frames
#define HIMAX_MODE_STREAMING_TRIG 0x05 // Hardware Trigger
#define HIMAX_SET_HMIRROR(r, x) ((r & 0xFE) | ((x & 1) << 0))
#define HIMAX_SET_VMIRROR(r, x) ((r & 0xFD) | ((x & 1) << 1))
#define PCLK_RISING_EDGE 0x00
#define PCLK_FALLING_EDGE 0x01
#define AE_CTRL_ENABLE 0x00
#define AE_CTRL_DISABLE 0x01
#endif //__REG_REGS_H__

View File

@ -32,7 +32,6 @@
#include "omv_i2c.h"
#include "omv_csi.h"
#include "hm0360.h"
#include "hm0360_regs.h"
#include "py/mphal.h"
#define HIMAX_BOOT_RETRY (10)

View File

@ -21,9 +21,149 @@
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*
* HM0360 driver.
* HM0360 register definitions.
*/
#ifndef __HM0360_H__
#define __HM0360_H__
int hm0360_init(omv_csi_t *csi);
#endif // __HM0360_H__
#ifndef __REG_REGS_H__
#define __REG_REGS_H__
// Read only registers
#define MODEL_ID_H 0x0000
#define MODEL_ID_L 0x0001
#define SILICON_REV 0x0002
#define FRAME_COUNT_H 0x0005
#define FRAME_COUNT_L 0x0006
#define PIXEL_ORDER 0x0007
// Sensor mode control
#define MODE_SELECT 0x0100
#define IMG_ORIENTATION 0x0101
#define EMBEDDED_LINE_EN 0x0102
#define SW_RESET 0x0103
#define COMMAND_UPDATE 0x0104
// Sensor exposure gain control
#define INTEGRATION_H 0x0202
#define INTEGRATION_L 0x0203
#define ANALOG_GAIN 0x0205
#define DIGITAL_GAIN_H 0x020E
#define DIGITAL_GAIN_L 0x020F
// Clock control
#define PLL1_CONFIG 0x0300
#define PLL2_CONFIG 0x0301
#define PLL3_CONFIG 0x0302
// Frame timing control
#define FRAME_LEN_LINES_H 0x0340
#define FRAME_LEN_LINES_L 0x0341
#define LINE_LEN_PCK_H 0x0342
#define LINE_LEN_PCK_L 0x0343
// Monochrome programming
#define MONO_MODE 0x0370
#define MONO_MODE_ISP 0x0371
#define MONO_MODE_SEL 0x0372
// Binning mode control
#define H_SUBSAMPLE 0x0380
#define V_SUBSAMPLE 0x0381
#define BINNING_MODE 0x0382
// Test pattern control
#define TEST_PATTERN_MODE 0x0601
// Black level control
#define BLC_TGT 0x1004
#define BLC2_TGT 0x1009
#define MONO_CTRL 0x100A
// VSYNC / HSYNC / pixel shift registers
#define OPFM_CTRL 0x1014
// Tone mapping registers
#define CMPRS_CTRL 0x102F
#define CMPRS_01 0x1030
#define CMPRS_02 0x1031
#define CMPRS_03 0x1032
#define CMPRS_04 0x1033
#define CMPRS_05 0x1034
#define CMPRS_06 0x1035
#define CMPRS_07 0x1036
#define CMPRS_08 0x1037
#define CMPRS_09 0x1038
#define CMPRS_10 0x1039
#define CMPRS_11 0x103A
#define CMPRS_12 0x103B
#define CMPRS_13 0x103C
#define CMPRS_14 0x103D
#define CMPRS_15 0x103E
#define CMPRS_16 0x103F
// Automatic exposure control
#define AE_CTRL 0x2000
#define AE_CTRL1 0x2001
#define CNT_ORGH_H 0x2002
#define CNT_ORGH_L 0x2003
#define CNT_ORGV_H 0x2004
#define CNT_ORGV_L 0x2005
#define CNT_STH_H 0x2006
#define CNT_STH_L 0x2007
#define CNT_STV_H 0x2008
#define CNT_STV_L 0x2009
#define CTRL_PG_SKIPCNT 0x200A
#define BV_WIN_WEIGHT_EN 0x200D
#define MAX_INTG_H 0x2029
#define MAX_INTG_L 0x202A
#define MAX_AGAIN 0x202B
#define MAX_DGAIN_H 0x202C
#define MAX_DGAIN_L 0x202D
#define MIN_INTG 0x202E
#define MIN_AGAIN 0x202F
#define MIN_DGAIN 0x2030
#define T_DAMPING 0x2031
#define N_DAMPING 0x2032
#define ALC_TH 0x2033
#define AE_TARGET_MEAN 0x2034
#define AE_MIN_MEAN 0x2035
#define AE_TARGET_ZONE 0x2036
#define CONVERGE_IN_TH 0x2037
#define CONVERGE_OUT_TH 0x2038
#define FS_CTRL 0x203B
#define FS_60HZ_H 0x203C
#define FS_60HZ_L 0x203D
#define FS_50HZ_H 0x203E
#define FS_50HZ_L 0x203F
#define FRAME_CNT_TH 0x205B
#define AE_MEAN 0x205D
#define AE_CONVERGE 0x2060
#define AE_BLI_TGT 0x2070
// Interrupt control
#define PULSE_MODE 0x2061
#define PULSE_TH_H 0x2062
#define PULSE_TH_L 0x2063
#define INT_INDIC 0x2064
#define INT_CLEAR 0x2065
// Motion detection control
#define MD_CTRL 0x2080
#define ROI_START_END_V 0x2081
#define ROI_START_END_H 0x2082
#define MD_TH_MIN 0x2083
#define MD_TH_STR_L 0x2084
#define MD_TH_STR_H 0x2085
#define MD_LIGHT_COEF 0x2099
#define MD_BLOCK_NUM_TH 0x209B
#define MD_LATENCY 0x209C
#define MD_LATENCY_TH 0x209D
#define MD_CTRL1 0x209E
// Context switch control registers
#define PMU_CFG_3 0x3024
#define PMU_CFG_4 0x3025
// Operation mode control
#define WIN_MODE 0x3030
// IO and clock control
#define PAD_REGISTER_07 0x3112
// Register bits/values
#define HIMAX_RESET 0x01
#define HIMAX_MODE_STANDBY 0x00
#define HIMAX_MODE_STREAMING 0x01 // I2C triggered streaming enable
#define HIMAX_MODE_STREAMING_NFRAMES 0x03 // Output N frames
#define HIMAX_MODE_STREAMING_TRIG 0x05 // Hardware Trigger
#define HIMAX_SET_HMIRROR(r, x) ((r & 0xFE) | ((x & 1) << 0))
#define HIMAX_SET_VMIRROR(r, x) ((r & 0xFD) | ((x & 1) << 1))
#define PCLK_RISING_EDGE 0x00
#define PCLK_FALLING_EDGE 0x01
#define AE_CTRL_ENABLE 0x00
#define AE_CTRL_DISABLE 0x01
#endif //__REG_REGS_H__

View File

@ -1,169 +0,0 @@
/*
* SPDX-License-Identifier: MIT
*
* Copyright (C) 2013-2024 OpenMV, LLC.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*
* HM0360 register definitions.
*/
#ifndef __REG_REGS_H__
#define __REG_REGS_H__
// Read only registers
#define MODEL_ID_H 0x0000
#define MODEL_ID_L 0x0001
#define SILICON_REV 0x0002
#define FRAME_COUNT_H 0x0005
#define FRAME_COUNT_L 0x0006
#define PIXEL_ORDER 0x0007
// Sensor mode control
#define MODE_SELECT 0x0100
#define IMG_ORIENTATION 0x0101
#define EMBEDDED_LINE_EN 0x0102
#define SW_RESET 0x0103
#define COMMAND_UPDATE 0x0104
// Sensor exposure gain control
#define INTEGRATION_H 0x0202
#define INTEGRATION_L 0x0203
#define ANALOG_GAIN 0x0205
#define DIGITAL_GAIN_H 0x020E
#define DIGITAL_GAIN_L 0x020F
// Clock control
#define PLL1_CONFIG 0x0300
#define PLL2_CONFIG 0x0301
#define PLL3_CONFIG 0x0302
// Frame timing control
#define FRAME_LEN_LINES_H 0x0340
#define FRAME_LEN_LINES_L 0x0341
#define LINE_LEN_PCK_H 0x0342
#define LINE_LEN_PCK_L 0x0343
// Monochrome programming
#define MONO_MODE 0x0370
#define MONO_MODE_ISP 0x0371
#define MONO_MODE_SEL 0x0372
// Binning mode control
#define H_SUBSAMPLE 0x0380
#define V_SUBSAMPLE 0x0381
#define BINNING_MODE 0x0382
// Test pattern control
#define TEST_PATTERN_MODE 0x0601
// Black level control
#define BLC_TGT 0x1004
#define BLC2_TGT 0x1009
#define MONO_CTRL 0x100A
// VSYNC / HSYNC / pixel shift registers
#define OPFM_CTRL 0x1014
// Tone mapping registers
#define CMPRS_CTRL 0x102F
#define CMPRS_01 0x1030
#define CMPRS_02 0x1031
#define CMPRS_03 0x1032
#define CMPRS_04 0x1033
#define CMPRS_05 0x1034
#define CMPRS_06 0x1035
#define CMPRS_07 0x1036
#define CMPRS_08 0x1037
#define CMPRS_09 0x1038
#define CMPRS_10 0x1039
#define CMPRS_11 0x103A
#define CMPRS_12 0x103B
#define CMPRS_13 0x103C
#define CMPRS_14 0x103D
#define CMPRS_15 0x103E
#define CMPRS_16 0x103F
// Automatic exposure control
#define AE_CTRL 0x2000
#define AE_CTRL1 0x2001
#define CNT_ORGH_H 0x2002
#define CNT_ORGH_L 0x2003
#define CNT_ORGV_H 0x2004
#define CNT_ORGV_L 0x2005
#define CNT_STH_H 0x2006
#define CNT_STH_L 0x2007
#define CNT_STV_H 0x2008
#define CNT_STV_L 0x2009
#define CTRL_PG_SKIPCNT 0x200A
#define BV_WIN_WEIGHT_EN 0x200D
#define MAX_INTG_H 0x2029
#define MAX_INTG_L 0x202A
#define MAX_AGAIN 0x202B
#define MAX_DGAIN_H 0x202C
#define MAX_DGAIN_L 0x202D
#define MIN_INTG 0x202E
#define MIN_AGAIN 0x202F
#define MIN_DGAIN 0x2030
#define T_DAMPING 0x2031
#define N_DAMPING 0x2032
#define ALC_TH 0x2033
#define AE_TARGET_MEAN 0x2034
#define AE_MIN_MEAN 0x2035
#define AE_TARGET_ZONE 0x2036
#define CONVERGE_IN_TH 0x2037
#define CONVERGE_OUT_TH 0x2038
#define FS_CTRL 0x203B
#define FS_60HZ_H 0x203C
#define FS_60HZ_L 0x203D
#define FS_50HZ_H 0x203E
#define FS_50HZ_L 0x203F
#define FRAME_CNT_TH 0x205B
#define AE_MEAN 0x205D
#define AE_CONVERGE 0x2060
#define AE_BLI_TGT 0x2070
// Interrupt control
#define PULSE_MODE 0x2061
#define PULSE_TH_H 0x2062
#define PULSE_TH_L 0x2063
#define INT_INDIC 0x2064
#define INT_CLEAR 0x2065
// Motion detection control
#define MD_CTRL 0x2080
#define ROI_START_END_V 0x2081
#define ROI_START_END_H 0x2082
#define MD_TH_MIN 0x2083
#define MD_TH_STR_L 0x2084
#define MD_TH_STR_H 0x2085
#define MD_LIGHT_COEF 0x2099
#define MD_BLOCK_NUM_TH 0x209B
#define MD_LATENCY 0x209C
#define MD_LATENCY_TH 0x209D
#define MD_CTRL1 0x209E
// Context switch control registers
#define PMU_CFG_3 0x3024
#define PMU_CFG_4 0x3025
// Operation mode control
#define WIN_MODE 0x3030
// IO and clock control
#define PAD_REGISTER_07 0x3112
// Register bits/values
#define HIMAX_RESET 0x01
#define HIMAX_MODE_STANDBY 0x00
#define HIMAX_MODE_STREAMING 0x01 // I2C triggered streaming enable
#define HIMAX_MODE_STREAMING_NFRAMES 0x03 // Output N frames
#define HIMAX_MODE_STREAMING_TRIG 0x05 // Hardware Trigger
#define HIMAX_SET_HMIRROR(r, x) ((r & 0xFE) | ((x & 1) << 0))
#define HIMAX_SET_VMIRROR(r, x) ((r & 0xFD) | ((x & 1) << 1))
#define PCLK_RISING_EDGE 0x00
#define PCLK_FALLING_EDGE 0x01
#define AE_CTRL_ENABLE 0x00
#define AE_CTRL_DISABLE 0x01
#endif //__REG_REGS_H__

View File

@ -533,7 +533,7 @@ int lepton_init(omv_csi_t *csi) {
mp_hal_delay_ms(1000);
if (reset(csi) != 0) {
return -1;
return OMV_CSI_ERROR_CSI_INIT_FAILED;
}
LEP_OEM_PART_NUMBER_T part;

View File

@ -1,30 +0,0 @@
/*
* SPDX-License-Identifier: MIT
*
* Copyright (C) 2013-2024 OpenMV, LLC.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*
* Lepton driver.
*/
#ifndef __LEPTON_H__
#define __LEPTON_H__
#define OMV_LEPTON_CLK_FREQ 24000000
int lepton_init(omv_csi_t *csi);
#endif // __LEPTON_H__

View File

@ -32,9 +32,9 @@
#include "omv_i2c.h"
#include "omv_csi.h"
#include "mt9m114.h"
#include "mt9m114_regs.h"
#include "py/mphal.h"
#include "mt9m114.h"
#include "sensor_config.h"
#define DUMMY_LINES 8
#define DUMMY_COLUMNS 8

View File

@ -23,8 +23,138 @@
*
* MT9M114 driver.
*/
#ifndef __MT9M114_H__
#define __MT9M114_H__
#define OMV_MT9M114_CLK_FREQ (24000000)
int mt9m114_init(omv_csi_t *csi);
#endif // __MT9M114_H__
#ifndef __REG_REGS_H__
#define __REG_REGS_H__
#define MT9M114_REG_PAD_SLEW (0x001E)
#define MT9M114_REG_SYSCTL (0x001A)
#define MT9M114_SYSCTL_SOFT_RESET (1 << 0)
#define MT9M114_REG_HOST_COMMAND (0x0080)
#define MT9M114_HC_APPLY_PATCH (0x0001)
#define MT9M114_HC_SET_STATE (0x0002)
#define MT9M114_HC_REFRESH (0x0004)
#define MT9M114_HC_WAIT_FOR_EVENT (0x0008)
#define MT9M114_HC_OK (0x8000)
#define MT9M114_HC_DELAY (1)
#define MT9M114_HC_TIMEOUT (100)
#define MT9M114_SS_ENTER_CONFIG_CHANGE (0x28)
#define MT9M114_SS_STREAMING (0x31)
#define MT9M114_SS_START_STREAMING (0x34)
#define MT9M114_SS_ENTER_SUSPEND (0x40)
#define MT9M114_SS_SUSPENDED (0x41)
#define MT9M114_SS_ENTER_STANDBY (0x50)
#define MT9M114_SS_STANDBY (0x52)
#define MT9M114_SS_LEAVE_STANDBY (0x54)
#define MT9M114_REG_XMDA_ACCESS_CTL_STAT (0x0982)
#define MT9M114_REG_XMDA_PHYSICAL_ADDRESS_ACCESS (0x098A)
#define MT9M114_REG_XMDA_LOGIC_ADDRESS_ACCESS (0x098E)
#define MT9M114_REG_SEQ_ERROR_CODE (0x8406)
#define MT9M114_REG_CAM_OUTPUT_FORMAT (0xC86C)
#define MT9M114_OUTPUT_FORMAT_SWAP_RB (1 << 0)
#define MT9M114_OUTPUT_FORMAT_SWAP_BYTES (1 << 1)
#define MT9M114_OUTPUT_FORMAT_MONO (1 << 2)
#define MT9M114_OUTPUT_FORMAT_BT656 (1 << 3)
#define MT9M114_OUTPUT_FORMAT_BT656_FIXED (1 << 4)
#define MT9M114_OUTPUT_FORMAT_YUV (0 << 8)
#define MT9M114_OUTPUT_FORMAT_RGB (1 << 8)
#define MT9M114_OUTPUT_FORMAT_BAYER (2 << 8)
#define MT9M114_OUTPUT_FORMAT_RAW_BAYER_10 (0 << 10)
#define MT9M114_OUTPUT_FORMAT_RAW_BAYER_10_PRE (1 << 10)
#define MT9M114_OUTPUT_FORMAT_RAW_BAYER_10_POST (2 << 10)
#define MT9M114_OUTPUT_FORMAT_PROCESSED_BAYER (3 << 10)
#define MT9M114_OUTPUT_FORMAT_RGB565 (0 << 12)
#define MT9M114_OUTPUT_FORMAT_RGB555 (1 << 12)
#define MT9M114_OUTPUT_FORMAT_XRGB444 (2 << 12)
#define MT9M114_OUTPUT_FORMAT_RGB444X (3 << 12)
#define MT9M114_REG_LL_ALGO (0xBC04)
#define MT9M114_REG_SENSOR_CFG_Y_ADDR_START (0xC800)
#define MT9M114_REG_SENSOR_CFG_X_ADDR_START (0xC802)
#define MT9M114_REG_SENSOR_CFG_Y_ADDR_END (0xC804)
#define MT9M114_REG_SENSOR_CFG_X_ADDR_END (0xC806)
#define MT9M114_REG_SENSOR_CFG_PIXCLK (0xC808)
#define MT9M114_REG_SENSOR_CFG_FINE_INTEG_TIME_MIN (0xC80E)
#define MT9M114_REG_SENSOR_CFG_FINE_INTEG_TIME_MAX (0xC810)
#define MT9M114_REG_SENSOR_CFG_FRAME_LENGTH_LINES (0xC812)
#define MT9M114_REG_SENSOR_CFG_LINE_LENGTH_PCK (0xC814)
#define MT9M114_REG_SENSOR_CFG_FINE_CORRECTION (0xC816)
#define MT9M114_REG_SENSOR_CFG_CPIPE_LAST_ROW (0xC818)
#define MT9M114_REG_SENSOR_CONTROL_READ_MODE (0xC834)
#define MT9M114_SENSOR_CONTROL_READ_MODE_HMIRROR (0x1)
#define MT9M114_SENSOR_CONTROL_READ_MODE_VFLIP (0x2)
#define MT9M114_SENSOR_CONTROL_READ_MODE_HBIN_MASK (0x30)
#define MT9M114_SENSOR_CONTROL_READ_MODE_HBIN (0x30)
#define MT9M114_SENSOR_CONTROL_READ_MODE_VBIN_MASK (0x300)
#define MT9M114_SENSOR_CONTROL_READ_MODE_VBIN (0x300)
#define MT9M114_REG_CAM_MODE_SELECT (0xC84C)
#define MT9M114_REG_CROP_WINDOW_X_OFFSET (0xC854)
#define MT9M114_REG_CROP_WINDOW_Y_OFFSET (0xC856)
#define MT9M114_REG_CROP_WINDOW_WIDTH (0xC858)
#define MT9M114_REG_CROP_WINDOW_HEIGHT (0xC85A)
#define MT9M114_REG_CAM_OUTPUT_WIDTH (0xC868)
#define MT9M114_REG_CAM_OUTPUT_HEIGHT (0xC86A)
#define MT9M114_REG_CAM_SFX_CONTROL (0xC874)
#define MT9M114_REG_CAM_AET_MAX_FRAME_RATE (0xC88C)
#define MT9M114_REG_CAM_AET_MIN_FRAME_RATE (0xC88E)
#define MT9M114_REG_CAM_AWB_XSCALE (0xC8F2)
#define MT9M114_REG_CAM_AWB_YSCALE (0xC8F3)
#define MT9M114_REG_CAM_AWB_X_SHIFT_PRE_ADJ (0xC904)
#define MT9M114_REG_CAM_AWB_Y_SHIFT_PRE_ADJ (0xC906)
#define MT9M114_REG_AWB_CLIP_WINDOW_X_START (0xC914)
#define MT9M114_REG_AWB_CLIP_WINDOW_Y_START (0xC916)
#define MT9M114_REG_AWB_CLIP_WINDOW_X_END (0xC918)
#define MT9M114_REG_AWB_CLIP_WINDOW_Y_END (0xC91A)
#define MT9M114_REG_CAM_LL_START_SATURATION (0xC92A)
#define MT9M114_REG_AE_INITIAL_WINDOW_X_START (0xC91C)
#define MT9M114_REG_AE_INITIAL_WINDOW_Y_START (0xC91E)
#define MT9M114_REG_AE_INITIAL_WINDOW_X_END (0xC920)
#define MT9M114_REG_AE_INITIAL_WINDOW_Y_END (0xC922)
#define MT9M114_REG_CAM_SYSCTL_PLL_DIVIDER_M_N (0xC980)
#define MT9M114_REG_CAM_PORT_OUTPUT_CONTROL (0xC984)
#define MT9M114_REG_UVC_AE_MODE_CONTROL (0xCC00)
#define MT9M114_REG_UVC_WHITE_BALANCE_AUTO_CONTROL (0xCC01)
#define MT9M114_REG_UVC_EXPOSURE_TIME_ABSOLUTE_CTRL (0xCC04)
#define MT9M114_REG_UVC_BRIGHTNESS_CONTROL (0xCC0A)
#define MT9M114_REG_UVC_CONTRAST_CONTROL (0xCC0C)
#define MT9M114_REG_UVC_GAIN_CONTROL (0xCC0E)
#define MT9M114_REG_UVC_SATURATION_CONTROL (0xCC12)
#define MT9M114_REG_UVC_MANUAL_EXPOSURE_CONFIG (0xCC20)
#define MT9M114_REG_SYSMGR_NEXT_STATE (0xDC00)
#define MT9M114_REG_SYSMGR_CURRENT_STATE (0xDC01)
#define MT9M114_REG_SYSMGR_CMD_STATUS (0xDC02)
#define MT9M114_REG_PATCHLDR_LOADER_ADDRESS (0xE000)
#define MT9M114_REG_PATCHLDR_PATCH_ID (0xE002)
#define MT9M114_REG_PATCHLDR_FIRMWARE_ID_HI (0xE004)
#define MT9M114_REG_PATCHLDR_FIRMWARE_ID_LO (0xE006)
#define MT9M114_REG_PATCHLDR_APPLY_STATUS (0xE008)
#define MT9M114_REG_AUTO_BINNING_MODE (0xE801)
#define MT9M114_REG_CMD_HANDLE_WAIT_EVENT_ID (0xFC00)
#define MT9M114_REG_CMD_HANDLE_NUM_EVENTS (0xFC02)
#endif //__REG_REGS_H__

View File

@ -1,160 +0,0 @@
/*
* SPDX-License-Identifier: MIT
*
* Copyright (C) 2013-2024 OpenMV, LLC.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*
* MT9M114 driver.
*/
#ifndef __REG_REGS_H__
#define __REG_REGS_H__
#define MT9M114_REG_PAD_SLEW (0x001E)
#define MT9M114_REG_SYSCTL (0x001A)
#define MT9M114_SYSCTL_SOFT_RESET (1 << 0)
#define MT9M114_REG_HOST_COMMAND (0x0080)
#define MT9M114_HC_APPLY_PATCH (0x0001)
#define MT9M114_HC_SET_STATE (0x0002)
#define MT9M114_HC_REFRESH (0x0004)
#define MT9M114_HC_WAIT_FOR_EVENT (0x0008)
#define MT9M114_HC_OK (0x8000)
#define MT9M114_HC_DELAY (1)
#define MT9M114_HC_TIMEOUT (100)
#define MT9M114_SS_ENTER_CONFIG_CHANGE (0x28)
#define MT9M114_SS_STREAMING (0x31)
#define MT9M114_SS_START_STREAMING (0x34)
#define MT9M114_SS_ENTER_SUSPEND (0x40)
#define MT9M114_SS_SUSPENDED (0x41)
#define MT9M114_SS_ENTER_STANDBY (0x50)
#define MT9M114_SS_STANDBY (0x52)
#define MT9M114_SS_LEAVE_STANDBY (0x54)
#define MT9M114_REG_XMDA_ACCESS_CTL_STAT (0x0982)
#define MT9M114_REG_XMDA_PHYSICAL_ADDRESS_ACCESS (0x098A)
#define MT9M114_REG_XMDA_LOGIC_ADDRESS_ACCESS (0x098E)
#define MT9M114_REG_SEQ_ERROR_CODE (0x8406)
#define MT9M114_REG_CAM_OUTPUT_FORMAT (0xC86C)
#define MT9M114_OUTPUT_FORMAT_SWAP_RB (1 << 0)
#define MT9M114_OUTPUT_FORMAT_SWAP_BYTES (1 << 1)
#define MT9M114_OUTPUT_FORMAT_MONO (1 << 2)
#define MT9M114_OUTPUT_FORMAT_BT656 (1 << 3)
#define MT9M114_OUTPUT_FORMAT_BT656_FIXED (1 << 4)
#define MT9M114_OUTPUT_FORMAT_YUV (0 << 8)
#define MT9M114_OUTPUT_FORMAT_RGB (1 << 8)
#define MT9M114_OUTPUT_FORMAT_BAYER (2 << 8)
#define MT9M114_OUTPUT_FORMAT_RAW_BAYER_10 (0 << 10)
#define MT9M114_OUTPUT_FORMAT_RAW_BAYER_10_PRE (1 << 10)
#define MT9M114_OUTPUT_FORMAT_RAW_BAYER_10_POST (2 << 10)
#define MT9M114_OUTPUT_FORMAT_PROCESSED_BAYER (3 << 10)
#define MT9M114_OUTPUT_FORMAT_RGB565 (0 << 12)
#define MT9M114_OUTPUT_FORMAT_RGB555 (1 << 12)
#define MT9M114_OUTPUT_FORMAT_XRGB444 (2 << 12)
#define MT9M114_OUTPUT_FORMAT_RGB444X (3 << 12)
#define MT9M114_REG_LL_ALGO (0xBC04)
#define MT9M114_REG_SENSOR_CFG_Y_ADDR_START (0xC800)
#define MT9M114_REG_SENSOR_CFG_X_ADDR_START (0xC802)
#define MT9M114_REG_SENSOR_CFG_Y_ADDR_END (0xC804)
#define MT9M114_REG_SENSOR_CFG_X_ADDR_END (0xC806)
#define MT9M114_REG_SENSOR_CFG_PIXCLK (0xC808)
#define MT9M114_REG_SENSOR_CFG_FINE_INTEG_TIME_MIN (0xC80E)
#define MT9M114_REG_SENSOR_CFG_FINE_INTEG_TIME_MAX (0xC810)
#define MT9M114_REG_SENSOR_CFG_FRAME_LENGTH_LINES (0xC812)
#define MT9M114_REG_SENSOR_CFG_LINE_LENGTH_PCK (0xC814)
#define MT9M114_REG_SENSOR_CFG_FINE_CORRECTION (0xC816)
#define MT9M114_REG_SENSOR_CFG_CPIPE_LAST_ROW (0xC818)
#define MT9M114_REG_SENSOR_CONTROL_READ_MODE (0xC834)
#define MT9M114_SENSOR_CONTROL_READ_MODE_HMIRROR (0x1)
#define MT9M114_SENSOR_CONTROL_READ_MODE_VFLIP (0x2)
#define MT9M114_SENSOR_CONTROL_READ_MODE_HBIN_MASK (0x30)
#define MT9M114_SENSOR_CONTROL_READ_MODE_HBIN (0x30)
#define MT9M114_SENSOR_CONTROL_READ_MODE_VBIN_MASK (0x300)
#define MT9M114_SENSOR_CONTROL_READ_MODE_VBIN (0x300)
#define MT9M114_REG_CAM_MODE_SELECT (0xC84C)
#define MT9M114_REG_CROP_WINDOW_X_OFFSET (0xC854)
#define MT9M114_REG_CROP_WINDOW_Y_OFFSET (0xC856)
#define MT9M114_REG_CROP_WINDOW_WIDTH (0xC858)
#define MT9M114_REG_CROP_WINDOW_HEIGHT (0xC85A)
#define MT9M114_REG_CAM_OUTPUT_WIDTH (0xC868)
#define MT9M114_REG_CAM_OUTPUT_HEIGHT (0xC86A)
#define MT9M114_REG_CAM_SFX_CONTROL (0xC874)
#define MT9M114_REG_CAM_AET_MAX_FRAME_RATE (0xC88C)
#define MT9M114_REG_CAM_AET_MIN_FRAME_RATE (0xC88E)
#define MT9M114_REG_CAM_AWB_XSCALE (0xC8F2)
#define MT9M114_REG_CAM_AWB_YSCALE (0xC8F3)
#define MT9M114_REG_CAM_AWB_X_SHIFT_PRE_ADJ (0xC904)
#define MT9M114_REG_CAM_AWB_Y_SHIFT_PRE_ADJ (0xC906)
#define MT9M114_REG_AWB_CLIP_WINDOW_X_START (0xC914)
#define MT9M114_REG_AWB_CLIP_WINDOW_Y_START (0xC916)
#define MT9M114_REG_AWB_CLIP_WINDOW_X_END (0xC918)
#define MT9M114_REG_AWB_CLIP_WINDOW_Y_END (0xC91A)
#define MT9M114_REG_CAM_LL_START_SATURATION (0xC92A)
#define MT9M114_REG_AE_INITIAL_WINDOW_X_START (0xC91C)
#define MT9M114_REG_AE_INITIAL_WINDOW_Y_START (0xC91E)
#define MT9M114_REG_AE_INITIAL_WINDOW_X_END (0xC920)
#define MT9M114_REG_AE_INITIAL_WINDOW_Y_END (0xC922)
#define MT9M114_REG_CAM_SYSCTL_PLL_DIVIDER_M_N (0xC980)
#define MT9M114_REG_CAM_PORT_OUTPUT_CONTROL (0xC984)
#define MT9M114_REG_UVC_AE_MODE_CONTROL (0xCC00)
#define MT9M114_REG_UVC_WHITE_BALANCE_AUTO_CONTROL (0xCC01)
#define MT9M114_REG_UVC_EXPOSURE_TIME_ABSOLUTE_CTRL (0xCC04)
#define MT9M114_REG_UVC_BRIGHTNESS_CONTROL (0xCC0A)
#define MT9M114_REG_UVC_CONTRAST_CONTROL (0xCC0C)
#define MT9M114_REG_UVC_GAIN_CONTROL (0xCC0E)
#define MT9M114_REG_UVC_SATURATION_CONTROL (0xCC12)
#define MT9M114_REG_UVC_MANUAL_EXPOSURE_CONFIG (0xCC20)
#define MT9M114_REG_SYSMGR_NEXT_STATE (0xDC00)
#define MT9M114_REG_SYSMGR_CURRENT_STATE (0xDC01)
#define MT9M114_REG_SYSMGR_CMD_STATUS (0xDC02)
#define MT9M114_REG_PATCHLDR_LOADER_ADDRESS (0xE000)
#define MT9M114_REG_PATCHLDR_PATCH_ID (0xE002)
#define MT9M114_REG_PATCHLDR_FIRMWARE_ID_HI (0xE004)
#define MT9M114_REG_PATCHLDR_FIRMWARE_ID_LO (0xE006)
#define MT9M114_REG_PATCHLDR_APPLY_STATUS (0xE008)
#define MT9M114_REG_AUTO_BINNING_MODE (0xE801)
#define MT9M114_REG_CMD_HANDLE_WAIT_EVENT_ID (0xFC00)
#define MT9M114_REG_CMD_HANDLE_NUM_EVENTS (0xFC02)
#endif //__REG_REGS_H__

View File

@ -33,7 +33,6 @@
#include "omv_i2c.h"
#include "omv_csi.h"
#include "mt9v0xx.h"
#include "mt9v0xx_regs.h"
#include "py/mphal.h"
#define ACTIVE_SENSOR_WIDTH (752)
@ -537,6 +536,12 @@ int mt9v0xx_init(omv_csi_t *csi) {
csi->mono_bpp = 1;
csi->cfa_format = SUBFORMAT_ID_BGGR;
// Force old versions to the newest.
if (csi->chip_id == MT9V0X2_ID_V_1 ||
csi->chip_id == MT9V0X2_ID_V_2) {
csi->chip_id = MT9V0X2_ID;
}
uint16_t cfa_type_reg;
int ret = omv_i2c_readw(csi->i2c, csi->slv_addr, MT9V0XX_CFA_ID_REG, &cfa_type_reg);
switch ((cfa_type_reg >> 9) & 0x7) {

View File

@ -23,10 +23,163 @@
*
* MT9V0XX driver.
*/
#ifndef __MT9V0XX_H__
#define __MT9V0XX_H__
#ifndef OMV_MT9V0XX_CLK_FREQ
#define OMV_MT9V0XX_CLK_FREQ 26666666
#endif
int mt9v0xx_init(omv_csi_t *csi);
#endif // __MT9V0XX_H__
#define MT9V0XX_CHIP_VERSION (0x00)
#define MT9V0XX_COL_START (0x01)
#define MT9V0X4_COL_START_B (0xC9)
#define MT9V0XX_COL_START_MIN (1)
#define MT9V0XX_COL_START_MAX (752)
#define MT9V0XX_ROW_START (0x02)
#define MT9V0X4_ROW_START_B (0xCA)
#define MT9V0XX_ROW_START_MIN (4)
#define MT9V0XX_ROW_START_MAX (482)
#define MT9V0XX_WINDOW_HEIGHT (0x03)
#define MT9V0X4_WINDOW_HEIGHT_B (0xCB)
#define MT9V0XX_WINDOW_HEIGHT_MIN (1)
#define MT9V0XX_WINDOW_HEIGHT_MAX (480)
#define MT9V0XX_WINDOW_WIDTH (0x04)
#define MT9V0X4_WINDOW_WIDTH_B (0xCC)
#define MT9V0XX_WINDOW_WIDTH_MIN (1)
#define MT9V0XX_WINDOW_WIDTH_MAX (752)
#define MT9V0XX_HORIZONTAL_BLANKING (0x05)
#define MT9V0X4_HORIZONTAL_BLANKING_B (0xCD)
#define MT9V0X2_HORIZONTAL_BLANKING_MIN (43)
#define MT9V0XX_HORIZONTAL_BLANKING_MIN_1 (61)
#define MT9V0XX_HORIZONTAL_BLANKING_MIN_2 (71)
#define MT9V0XX_HORIZONTAL_BLANKING_MIN_4 (91)
#define MT9V0XX_HORIZONTAL_BLANKING_MAX (1023)
#define MT9V0XX_HORIZONTAL_BLANKING_DEF (94)
#define MT9V0XX_VERTICAL_BLANKING (0x06)
#define MT9V0X4_VERTICAL_BLANKING_B (0xCE)
#define MT9V0XX_VERTICAL_BLANKING_MIN (4)
#define MT9V0XX_VERTICAL_BLANKING_MAX (3000)
#define MT9V0XX_VERTICAL_BLANKING_DEF (45)
#define MT9V0XX_CHIP_CONTROL (0x07)
#define MT9V0XX_CHIP_CONTROL_MASTER_MODE (1 << 3)
#define MT9V0XX_CHIP_CONTROL_SNAP_MODE (3 << 3)
#define MT9V0XX_CHIP_CONTROL_MODE_MASK (3 << 3)
#define MT9V0XX_CHIP_CONTROL_DOUT_ENABLE (1 << 7)
#define MT9V0XX_CHIP_CONTROL_SEQUENTIAL (1 << 8)
#define MT9V0X4_CHIP_CONTROL_RESERVED (1 << 9)
#define MT9V0X4_CHIP_CONTROL_CONTEXT (1 << 15)
#define MT9V0XX_SHUTTER_WIDTH1 (0x08)
#define MT9V0X4_SHUTTER_WIDTH1_B (0xCF)
#define MT9V0XX_SHUTTER_WIDTH2 (0x09)
#define MT9V0X4_SHUTTER_WIDTH2_B (0xD0)
#define MT9V0XX_SHUTTER_WIDTH_CONTROL (0x0A)
#define MT9V0X4_SHUTTER_WIDTH_CONTROL_B (0xD1)
#define MT9V0XX_TOTAL_SHUTTER_WIDTH (0x0B)
#define MT9V0X4_TOTAL_SHUTTER_WIDTH_B (0xD2)
#define MT9V0XX_TOTAL_SHUTTER_WIDTH_MIN (1)
#define MT9V0XX_TOTAL_SHUTTER_WIDTH_MAX (32767)
#define MT9V0XX_RESET (0x0C)
#define MT9V0XX_RESET_SOFT_RESET (1 << 0)
#define MT9V0XX_READ_MODE (0x0D)
#define MT9V0X4_READ_MODE_B (0x0E)
#define MT9V0XX_READ_MODE_ROW_BIN_2 (1 << 0)
#define MT9V0XX_READ_MODE_ROW_BIN_4 (1 << 1)
#define MT9V0XX_READ_MODE_COL_BIN_2 (1 << 2)
#define MT9V0XX_READ_MODE_COL_BIN_4 (1 << 3)
#define MT9V0XX_READ_MODE_ROW_FLIP (1 << 4)
#define MT9V0XX_READ_MODE_COL_FLIP (1 << 5)
#define MT9V0XX_READ_MODE_DARK_COLS (1 << 6)
#define MT9V0XX_READ_MODE_DARK_ROWS (1 << 7)
#define MT9V0XX_PIXEL_OPERATION_MODE (0x0F)
#define MT9V0X4_PIXEL_OPERATION_MODE_HDR (1 << 0)
#define MT9V0X4_PIXEL_OPERATION_MODE_COLOR (1 << 1)
#define MT9V0X4_PIXEL_OPERATION_MODE_HDR_B (1 << 8)
#define MT9V0XX_ADC_COMPANDING_MODE (0x1C)
#define MT9V0XX_ADC_COMPANDING_MODE_LINEAR (2 << 0)
#define MT9V0X4_ADC_COMPANDING_MODE_LINEAR_B (2 << 8)
#define MT9V0XX_ANALOG_GAIN (0x35)
#define MT9V0X4_ANALOG_GAIN_B (0x36)
#define MT9V0XX_ANALOG_GAIN_MIN (16)
#define MT9V0XX_ANALOG_GAIN_MAX (64)
#define MT9V0XX_V1_CONTROL (0x31)
#define MT9V0X4_V1_CONTROL_B (0x39)
#define MT9V0XX_V2_CONTROL (0x32)
#define MT9V0X4_V2_CONTROL_B (0x3A)
#define MT9V0XX_V3_CONTROL (0x33)
#define MT9V0X4_V3_CONTROL_B (0x3B)
#define MT9V0XX_V4_CONTROL (0x34)
#define MT9V0X4_V4_CONTROL_B (0x3C)
#define MT9V0XX_FRAME_DARK_AVERAGE (0x42)
#define MT9V0XX_DARK_AVG_THRESH (0x46)
#define MT9V0XX_DARK_AVG_LOW_THRESH_MASK (255 << 0)
#define MT9V0XX_DARK_AVG_LOW_THRESH_SHIFT (0)
#define MT9V0XX_DARK_AVG_HIGH_THRESH_MASK (255 << 8)
#define MT9V0XX_DARK_AVG_HIGH_THRESH_SHIFT (8)
#define MT9V0XX_ROW_NOISE_CORR_CONTROL (0x70)
#define MT9V0X2_ROW_NOISE_CORR_ENABLE (1 << 5)
#define MT9V0X4_ROW_NOISE_CORR_ENABLE (1 << 0)
#define MT9V0X4_ROW_NOISE_CORR_ENABLE_B (1 << 8)
#define MT9V0X2_ROW_NOISE_CORR_USE_BLK_AVG (1 << 11)
#define MT9V0X4_ROW_NOISE_CORR_USE_BLK_AVG (1 << 1)
#define MT9V0X4_ROW_NOISE_CORR_USE_BLK_AVG_B (1 << 9)
#define MT9V0X2_PIXEL_CLOCK (0x74)
#define MT9V0X4_PIXEL_CLOCK (0x72)
#define MT9V0XX_PIXEL_CLOCK_INV_LINE (1 << 0)
#define MT9V0XX_PIXEL_CLOCK_INV_FRAME (1 << 1)
#define MT9V0XX_PIXEL_CLOCK_XOR_LINE (1 << 2)
#define MT9V0XX_PIXEL_CLOCK_CONT_LINE (1 << 3)
#define MT9V0XX_PIXEL_CLOCK_INV_PXL_CLK (1 << 4)
#define MT9V0XX_TEST_PATTERN (0x7F)
#define MT9V0XX_TEST_PATTERN_DATA_MASK (1023 << 0)
#define MT9V0XX_TEST_PATTERN_DATA_SHIFT (0)
#define MT9V0XX_TEST_PATTERN_USE_DATA (1 << 10)
#define MT9V0XX_TEST_PATTERN_GRAY_MASK (3 << 11)
#define MT9V0XX_TEST_PATTERN_GRAY_NONE (0 << 11)
#define MT9V0XX_TEST_PATTERN_GRAY_VERTICAL (1 << 11)
#define MT9V0XX_TEST_PATTERN_GRAY_HORIZONTAL (2 << 11)
#define MT9V0XX_TEST_PATTERN_GRAY_DIAGONAL (3 << 11)
#define MT9V0XX_TEST_PATTERN_ENABLE (1 << 13)
#define MT9V0XX_TEST_PATTERN_FLIP (1 << 14)
#define MT9V0XX_AEC_AGC_ENABLE (0xAF)
#define MT9V0XX_AEC_ENABLE (1 << 0)
#define MT9V0X4_AEC_ENABLE_B (1 << 8)
#define MT9V0XX_AGC_ENABLE (1 << 1)
#define MT9V0X4_AGC_ENABLE_B (1 << 9)
#define MT9V0XX_THERMAL_INFO (0xC1)
#define MT9V0XX_CFA_ID_REG (0x6B)
#define MT9V0X2_MAX_GAIN (0x36)
#define MT9V0X4_MAX_GAIN (0xAB)
#define MT9V0X2_MAX_EXPOSE (0xBD)
#define MT9V0X4_MAX_EXPOSE (0xAD)
#define MT9V0XX_PIXEL_COUNT (0xB0)
#define MT9V0XX_AGC_GAIN_OUTPUT (0xBA)
#define MT9V0XX_AEC_EXPOSURE_OUTPUT (0xBB)
#define MT9V0X4_FINE_SHUTTER_WIDTH_TOTAL (0xD5)
#define MT9V0X4_FINE_SHUTTER_WIDTH_TOTAL_B (0xD8)
#define MICROSECOND_CLKS (1000000)

View File

@ -1,185 +0,0 @@
/*
* SPDX-License-Identifier: MIT
*
* Copyright (C) 2013-2024 OpenMV, LLC.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*
* MT9V0XX driver.
*/
#define MT9V0XX_CHIP_VERSION (0x00)
#define MT9V0XX_COL_START (0x01)
#define MT9V0X4_COL_START_B (0xC9)
#define MT9V0XX_COL_START_MIN (1)
#define MT9V0XX_COL_START_MAX (752)
#define MT9V0XX_ROW_START (0x02)
#define MT9V0X4_ROW_START_B (0xCA)
#define MT9V0XX_ROW_START_MIN (4)
#define MT9V0XX_ROW_START_MAX (482)
#define MT9V0XX_WINDOW_HEIGHT (0x03)
#define MT9V0X4_WINDOW_HEIGHT_B (0xCB)
#define MT9V0XX_WINDOW_HEIGHT_MIN (1)
#define MT9V0XX_WINDOW_HEIGHT_MAX (480)
#define MT9V0XX_WINDOW_WIDTH (0x04)
#define MT9V0X4_WINDOW_WIDTH_B (0xCC)
#define MT9V0XX_WINDOW_WIDTH_MIN (1)
#define MT9V0XX_WINDOW_WIDTH_MAX (752)
#define MT9V0XX_HORIZONTAL_BLANKING (0x05)
#define MT9V0X4_HORIZONTAL_BLANKING_B (0xCD)
#define MT9V0X2_HORIZONTAL_BLANKING_MIN (43)
#define MT9V0XX_HORIZONTAL_BLANKING_MIN_1 (61)
#define MT9V0XX_HORIZONTAL_BLANKING_MIN_2 (71)
#define MT9V0XX_HORIZONTAL_BLANKING_MIN_4 (91)
#define MT9V0XX_HORIZONTAL_BLANKING_MAX (1023)
#define MT9V0XX_HORIZONTAL_BLANKING_DEF (94)
#define MT9V0XX_VERTICAL_BLANKING (0x06)
#define MT9V0X4_VERTICAL_BLANKING_B (0xCE)
#define MT9V0XX_VERTICAL_BLANKING_MIN (4)
#define MT9V0XX_VERTICAL_BLANKING_MAX (3000)
#define MT9V0XX_VERTICAL_BLANKING_DEF (45)
#define MT9V0XX_CHIP_CONTROL (0x07)
#define MT9V0XX_CHIP_CONTROL_MASTER_MODE (1 << 3)
#define MT9V0XX_CHIP_CONTROL_SNAP_MODE (3 << 3)
#define MT9V0XX_CHIP_CONTROL_MODE_MASK (3 << 3)
#define MT9V0XX_CHIP_CONTROL_DOUT_ENABLE (1 << 7)
#define MT9V0XX_CHIP_CONTROL_SEQUENTIAL (1 << 8)
#define MT9V0X4_CHIP_CONTROL_RESERVED (1 << 9)
#define MT9V0X4_CHIP_CONTROL_CONTEXT (1 << 15)
#define MT9V0XX_SHUTTER_WIDTH1 (0x08)
#define MT9V0X4_SHUTTER_WIDTH1_B (0xCF)
#define MT9V0XX_SHUTTER_WIDTH2 (0x09)
#define MT9V0X4_SHUTTER_WIDTH2_B (0xD0)
#define MT9V0XX_SHUTTER_WIDTH_CONTROL (0x0A)
#define MT9V0X4_SHUTTER_WIDTH_CONTROL_B (0xD1)
#define MT9V0XX_TOTAL_SHUTTER_WIDTH (0x0B)
#define MT9V0X4_TOTAL_SHUTTER_WIDTH_B (0xD2)
#define MT9V0XX_TOTAL_SHUTTER_WIDTH_MIN (1)
#define MT9V0XX_TOTAL_SHUTTER_WIDTH_MAX (32767)
#define MT9V0XX_RESET (0x0C)
#define MT9V0XX_RESET_SOFT_RESET (1 << 0)
#define MT9V0XX_READ_MODE (0x0D)
#define MT9V0X4_READ_MODE_B (0x0E)
#define MT9V0XX_READ_MODE_ROW_BIN_2 (1 << 0)
#define MT9V0XX_READ_MODE_ROW_BIN_4 (1 << 1)
#define MT9V0XX_READ_MODE_COL_BIN_2 (1 << 2)
#define MT9V0XX_READ_MODE_COL_BIN_4 (1 << 3)
#define MT9V0XX_READ_MODE_ROW_FLIP (1 << 4)
#define MT9V0XX_READ_MODE_COL_FLIP (1 << 5)
#define MT9V0XX_READ_MODE_DARK_COLS (1 << 6)
#define MT9V0XX_READ_MODE_DARK_ROWS (1 << 7)
#define MT9V0XX_PIXEL_OPERATION_MODE (0x0F)
#define MT9V0X4_PIXEL_OPERATION_MODE_HDR (1 << 0)
#define MT9V0X4_PIXEL_OPERATION_MODE_COLOR (1 << 1)
#define MT9V0X4_PIXEL_OPERATION_MODE_HDR_B (1 << 8)
#define MT9V0XX_ADC_COMPANDING_MODE (0x1C)
#define MT9V0XX_ADC_COMPANDING_MODE_LINEAR (2 << 0)
#define MT9V0X4_ADC_COMPANDING_MODE_LINEAR_B (2 << 8)
#define MT9V0XX_ANALOG_GAIN (0x35)
#define MT9V0X4_ANALOG_GAIN_B (0x36)
#define MT9V0XX_ANALOG_GAIN_MIN (16)
#define MT9V0XX_ANALOG_GAIN_MAX (64)
#define MT9V0XX_V1_CONTROL (0x31)
#define MT9V0X4_V1_CONTROL_B (0x39)
#define MT9V0XX_V2_CONTROL (0x32)
#define MT9V0X4_V2_CONTROL_B (0x3A)
#define MT9V0XX_V3_CONTROL (0x33)
#define MT9V0X4_V3_CONTROL_B (0x3B)
#define MT9V0XX_V4_CONTROL (0x34)
#define MT9V0X4_V4_CONTROL_B (0x3C)
#define MT9V0XX_FRAME_DARK_AVERAGE (0x42)
#define MT9V0XX_DARK_AVG_THRESH (0x46)
#define MT9V0XX_DARK_AVG_LOW_THRESH_MASK (255 << 0)
#define MT9V0XX_DARK_AVG_LOW_THRESH_SHIFT (0)
#define MT9V0XX_DARK_AVG_HIGH_THRESH_MASK (255 << 8)
#define MT9V0XX_DARK_AVG_HIGH_THRESH_SHIFT (8)
#define MT9V0XX_ROW_NOISE_CORR_CONTROL (0x70)
#define MT9V0X2_ROW_NOISE_CORR_ENABLE (1 << 5)
#define MT9V0X4_ROW_NOISE_CORR_ENABLE (1 << 0)
#define MT9V0X4_ROW_NOISE_CORR_ENABLE_B (1 << 8)
#define MT9V0X2_ROW_NOISE_CORR_USE_BLK_AVG (1 << 11)
#define MT9V0X4_ROW_NOISE_CORR_USE_BLK_AVG (1 << 1)
#define MT9V0X4_ROW_NOISE_CORR_USE_BLK_AVG_B (1 << 9)
#define MT9V0X2_PIXEL_CLOCK (0x74)
#define MT9V0X4_PIXEL_CLOCK (0x72)
#define MT9V0XX_PIXEL_CLOCK_INV_LINE (1 << 0)
#define MT9V0XX_PIXEL_CLOCK_INV_FRAME (1 << 1)
#define MT9V0XX_PIXEL_CLOCK_XOR_LINE (1 << 2)
#define MT9V0XX_PIXEL_CLOCK_CONT_LINE (1 << 3)
#define MT9V0XX_PIXEL_CLOCK_INV_PXL_CLK (1 << 4)
#define MT9V0XX_TEST_PATTERN (0x7F)
#define MT9V0XX_TEST_PATTERN_DATA_MASK (1023 << 0)
#define MT9V0XX_TEST_PATTERN_DATA_SHIFT (0)
#define MT9V0XX_TEST_PATTERN_USE_DATA (1 << 10)
#define MT9V0XX_TEST_PATTERN_GRAY_MASK (3 << 11)
#define MT9V0XX_TEST_PATTERN_GRAY_NONE (0 << 11)
#define MT9V0XX_TEST_PATTERN_GRAY_VERTICAL (1 << 11)
#define MT9V0XX_TEST_PATTERN_GRAY_HORIZONTAL (2 << 11)
#define MT9V0XX_TEST_PATTERN_GRAY_DIAGONAL (3 << 11)
#define MT9V0XX_TEST_PATTERN_ENABLE (1 << 13)
#define MT9V0XX_TEST_PATTERN_FLIP (1 << 14)
#define MT9V0XX_AEC_AGC_ENABLE (0xAF)
#define MT9V0XX_AEC_ENABLE (1 << 0)
#define MT9V0X4_AEC_ENABLE_B (1 << 8)
#define MT9V0XX_AGC_ENABLE (1 << 1)
#define MT9V0X4_AGC_ENABLE_B (1 << 9)
#define MT9V0XX_THERMAL_INFO (0xC1)
#define MT9V0XX_CFA_ID_REG (0x6B)
#define MT9V0X2_MAX_GAIN (0x36)
#define MT9V0X4_MAX_GAIN (0xAB)
#define MT9V0X2_MAX_EXPOSE (0xBD)
#define MT9V0X4_MAX_EXPOSE (0xAD)
#define MT9V0XX_PIXEL_COUNT (0xB0)
#define MT9V0XX_AGC_GAIN_OUTPUT (0xBA)
#define MT9V0XX_AEC_EXPOSURE_OUTPUT (0xBB)
#define MT9V0X4_FINE_SHUTTER_WIDTH_TOTAL (0xD5)
#define MT9V0X4_FINE_SHUTTER_WIDTH_TOTAL_B (0xD8)
#define MICROSECOND_CLKS (1000000)

View File

@ -33,7 +33,6 @@
#include "omv_i2c.h"
#include "omv_csi.h"
#include "ov2640.h"
#include "ov2640_regs.h"
#include "py/mphal.h"
#define CIF_WIDTH (400)

View File

@ -21,10 +21,240 @@
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*
* OV2640 driver.
* OV2640 register definitions.
*/
#ifndef __OV2640_H__
#define __OV2640_H__
#define OMV_OV2640_CLK_FREQ 24000000
int ov2640_init(omv_csi_t *csi);
#endif // __OV2640_H__
#ifndef __REG_REGS_H__
#define __REG_REGS_H__
/* DSP register bank FF=0x00*/
#define QS 0x44
#define HSIZE 0x51
#define VSIZE 0x52
#define XOFFL 0x53
#define YOFFL 0x54
#define VHYX 0x55
#define DPRP 0x56
#define TEST 0x57
#define ZMOW 0x5A
#define ZMOH 0x5B
#define ZMHH 0x5C
#define BPADDR 0x7C
#define BPDATA 0x7D
#define SIZEL 0x8C
#define HSIZE8 0xC0
#define VSIZE8 0xC1
#define CTRL1 0xC3
#define MS_SP 0xF0
#define SS_ID 0xF7
#define SS_CTRL 0xF7
#define MC_AL 0xFA
#define MC_AH 0xFB
#define MC_D 0xFC
#define P_CMD 0xFD
#define P_STATUS 0xFE
#define CTRLI 0x50
#define CTRLI_LP_DP 0x80
#define CTRLI_ROUND 0x40
#define CTRL0 0xC2
#define CTRL0_AEC_EN 0x80
#define CTRL0_AEC_SEL 0x40
#define CTRL0_STAT_SEL 0x20
#define CTRL0_VFIRST 0x10
#define CTRL0_YUV422 0x08
#define CTRL0_YUV_EN 0x04
#define CTRL0_RGB_EN 0x02
#define CTRL0_RAW_EN 0x01
#define CTRL2 0x86
#define CTRL2_DCW_EN 0x20
#define CTRL2_SDE_EN 0x10
#define CTRL2_UV_ADJ_EN 0x08
#define CTRL2_UV_AVG_EN 0x04
#define CTRL2_CMX_EN 0x01
#define CTRL3 0x87
#define CTRL3_BPC_EN 0x80
#define CTRL3_WPC_EN 0x40
#define R_DVP_SP 0xD3
#define R_DVP_SP_AUTO_MODE 0x80
#define R_BYPASS 0x05
#define R_BYPASS_DSP_EN 0x00
#define R_BYPASS_DSP_BYPAS 0x01
#define IMAGE_MODE 0xDA
#define IMAGE_MODE_Y8_DVP_EN 0x40
#define IMAGE_MODE_JPEG_EN 0x10
#define IMAGE_MODE_YUV422 0x00
#define IMAGE_MODE_RAW10 0x04
#define IMAGE_MODE_RGB565 0x09
#define IMAGE_MODE_HREF_VSYNC 0x02
#define IMAGE_MODE_LBYTE_FIRST 0x01
#define IMAGE_MODE_GET_FMT(x) ((x) & 0xC)
#define RESET 0xE0
#define RESET_MICROC 0x40
#define RESET_SCCB 0x20
#define RESET_JPEG 0x10
#define RESET_DVP 0x04
#define RESET_IPU 0x02
#define RESET_CIF 0x01
#define MC_BIST 0xF9
#define MC_BIST_RESET 0x80
#define MC_BIST_BOOT_ROM_SEL 0x40
#define MC_BIST_12KB_SEL 0x20
#define MC_BIST_12KB_MASK 0x30
#define MC_BIST_512KB_SEL 0x08
#define MC_BIST_512KB_MASK 0x0C
#define MC_BIST_BUSY_BIT_R 0x02
#define MC_BIST_MC_RES_ONE_SH_W 0x02
#define MC_BIST_LAUNCH 0x01
#define BANK_SEL 0xFF
#define BANK_SEL_DSP 0x00
#define BANK_SEL_SENSOR 0x01
/* Sensor register bank FF=0x01*/
#define GAIN 0x00
#define COM1 0x03
#define REG_PID 0x0A
#define REG_VER 0x0B
#define COM4 0x0D
#define AEC 0x10
#define CLKRC 0x11
#define CLKRC_DOUBLE 0x82
#define CLKRC_DIVIDER_MASK 0x3F
#define COM10 0x15
#define HSTART 0x17
#define HSTOP 0x18
#define VSTART 0x19
#define VSTOP 0x1A
#define MIDH 0x1C
#define MIDL 0x1D
#define AEW 0x24
#define AEB 0x25
#define REG2A 0x2A
#define FRARL 0x2B
#define ADDVSL 0x2D
#define ADDVSH 0x2E
#define YAVG 0x2F
#define HSDY 0x30
#define HEDY 0x31
#define ARCOM2 0x34
#define REG45 0x45
#define FLL 0x46
#define FLH 0x47
#define COM19 0x48
#define ZOOMS 0x49
#define COM22 0x4B
#define COM25 0x4E
#define BD50 0x4F
#define BD60 0x50
#define REG5D 0x5D
#define REG5E 0x5E
#define REG5F 0x5F
#define REG60 0x60
#define HISTO_LOW 0x61
#define HISTO_HIGH 0x62
#define REG04 0x04
#define REG04_DEFAULT 0x28
#define REG04_HFLIP_IMG 0x80
#define REG04_VFLIP_IMG 0x40
#define REG04_VREF_EN 0x10
#define REG04_HREF_EN 0x08
#define REG04_SET(x) (REG04_DEFAULT | x)
#define REG08 0x08
#define COM2 0x09
#define COM2_STDBY 0x10
#define COM2_OUT_DRIVE_1x 0x00
#define COM2_OUT_DRIVE_2x 0x01
#define COM2_OUT_DRIVE_3x 0x02
#define COM2_OUT_DRIVE_4x 0x03
#define COM3 0x0C
#define COM3_DEFAULT 0x38
#define COM3_BAND_50Hz 0x04
#define COM3_BAND_60Hz 0x00
#define COM3_BAND_AUTO 0x02
#define COM3_BAND_SET(x) (COM3_DEFAULT | x)
#define COM7 0x12
#define COM7_SRST 0x80
#define COM7_RES_UXGA 0x00 /* UXGA */
#define COM7_RES_SVGA 0x40 /* SVGA */
#define COM7_RES_CIF 0x20 /* CIF */
#define COM7_ZOOM_EN 0x04 /* Enable Zoom */
#define COM7_COLOR_BAR 0x02 /* Enable Color Bar Test */
#define COM7_GET_RES(x) ((x) & 0x70)
#define COM8 0x13
#define COM8_DEFAULT 0xC0
#define COM8_BNDF_EN 0x20 /* Enable Banding filter */
#define COM8_AGC_EN 0x04 /* AGC Auto/Manual control selection */
#define COM8_AEC_EN 0x01 /* Auto/Manual Exposure control */
#define COM8_SET(x) (COM8_DEFAULT | x)
#define COM8_SET_AEC(r, x) (((r) & 0xFE) | ((x) & 1))
#define COM9 0x14 /* AGC gain ceiling */
#define COM9_DEFAULT 0x08
#define COM9_AGC_GAIN_2x 0x00 /* AGC: 2x */
#define COM9_AGC_GAIN_4x 0x01 /* AGC: 4x */
#define COM9_AGC_GAIN_8x 0x02 /* AGC: 8x */
#define COM9_AGC_GAIN_16x 0x03 /* AGC: 16x */
#define COM9_AGC_GAIN_32x 0x04 /* AGC: 32x */
#define COM9_AGC_GAIN_64x 0x05 /* AGC: 64x */
#define COM9_AGC_GAIN_128x 0x06 /* AGC: 128x */
#define COM9_AGC_SET(x) (COM9_DEFAULT | (x << 5))
#define CTRL1_AWB 0x08 /* Enable AWB */
#define VV 0x26
#define VV_AGC_TH_SET(h, l) ((h << 4) | (l & 0x0F))
#define REG32 0x32
#define REG32_UXGA 0x36
#define REG32_SVGA 0x09
#define REG32_CIF 0x00
#define VAL_SET(x, mask, rshift, lshift) ((((x) >> rshift) & mask) << lshift)
#define CTRLI_V_DIV_SET(x) VAL_SET(x, 0x3, 0, 3)
#define CTRLI_H_DIV_SET(x) VAL_SET(x, 0x3, 0, 0)
#define SIZEL_HSIZE8_11_SET(x) VAL_SET(x, 0x1, 11, 6)
#define SIZEL_HSIZE8_SET(x) VAL_SET(x, 0x7, 0, 3)
#define SIZEL_VSIZE8_SET(x) VAL_SET(x, 0x7, 0, 0)
#define HSIZE8_SET(x) VAL_SET(x, 0xFF, 3, 0)
#define VSIZE8_SET(x) VAL_SET(x, 0xFF, 3, 0)
#define HSIZE_SET(x) VAL_SET(x, 0xFF, 2, 0)
#define VSIZE_SET(x) VAL_SET(x, 0xFF, 2, 0)
#define XOFFL_SET(x) VAL_SET(x, 0xFF, 0, 0)
#define YOFFL_SET(x) VAL_SET(x, 0xFF, 0, 0)
#define VHYX_VSIZE_SET(x) VAL_SET(x, 0x1, (8 + 2), 7)
#define VHYX_HSIZE_SET(x) VAL_SET(x, 0x1, (8 + 2), 3)
#define VHYX_YOFF_SET(x) VAL_SET(x, 0x3, 8, 4)
#define VHYX_XOFF_SET(x) VAL_SET(x, 0x3, 8, 0)
#define TEST_HSIZE_SET(x) VAL_SET(x, 0x1, (9 + 2), 7)
#define ZMOW_OUTW_SET(x) VAL_SET(x, 0xFF, 2, 0)
#define ZMOH_OUTH_SET(x) VAL_SET(x, 0xFF, 2, 0)
#define ZMHH_ZSPEED_SET(x) VAL_SET(x, 0x0F, 0, 4)
#define ZMHH_OUTH_SET(x) VAL_SET(x, 0x1, (8 + 2), 2)
#define ZMHH_OUTW_SET(x) VAL_SET(x, 0x3, (8 + 2), 0)
#endif //__REG_REGS_H__

View File

@ -1,260 +0,0 @@
/*
* SPDX-License-Identifier: MIT
*
* Copyright (C) 2013-2024 OpenMV, LLC.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*
* OV2640 register definitions.
*/
#ifndef __REG_REGS_H__
#define __REG_REGS_H__
/* DSP register bank FF=0x00*/
#define QS 0x44
#define HSIZE 0x51
#define VSIZE 0x52
#define XOFFL 0x53
#define YOFFL 0x54
#define VHYX 0x55
#define DPRP 0x56
#define TEST 0x57
#define ZMOW 0x5A
#define ZMOH 0x5B
#define ZMHH 0x5C
#define BPADDR 0x7C
#define BPDATA 0x7D
#define SIZEL 0x8C
#define HSIZE8 0xC0
#define VSIZE8 0xC1
#define CTRL1 0xC3
#define MS_SP 0xF0
#define SS_ID 0xF7
#define SS_CTRL 0xF7
#define MC_AL 0xFA
#define MC_AH 0xFB
#define MC_D 0xFC
#define P_CMD 0xFD
#define P_STATUS 0xFE
#define CTRLI 0x50
#define CTRLI_LP_DP 0x80
#define CTRLI_ROUND 0x40
#define CTRL0 0xC2
#define CTRL0_AEC_EN 0x80
#define CTRL0_AEC_SEL 0x40
#define CTRL0_STAT_SEL 0x20
#define CTRL0_VFIRST 0x10
#define CTRL0_YUV422 0x08
#define CTRL0_YUV_EN 0x04
#define CTRL0_RGB_EN 0x02
#define CTRL0_RAW_EN 0x01
#define CTRL2 0x86
#define CTRL2_DCW_EN 0x20
#define CTRL2_SDE_EN 0x10
#define CTRL2_UV_ADJ_EN 0x08
#define CTRL2_UV_AVG_EN 0x04
#define CTRL2_CMX_EN 0x01
#define CTRL3 0x87
#define CTRL3_BPC_EN 0x80
#define CTRL3_WPC_EN 0x40
#define R_DVP_SP 0xD3
#define R_DVP_SP_AUTO_MODE 0x80
#define R_BYPASS 0x05
#define R_BYPASS_DSP_EN 0x00
#define R_BYPASS_DSP_BYPAS 0x01
#define IMAGE_MODE 0xDA
#define IMAGE_MODE_Y8_DVP_EN 0x40
#define IMAGE_MODE_JPEG_EN 0x10
#define IMAGE_MODE_YUV422 0x00
#define IMAGE_MODE_RAW10 0x04
#define IMAGE_MODE_RGB565 0x09
#define IMAGE_MODE_HREF_VSYNC 0x02
#define IMAGE_MODE_LBYTE_FIRST 0x01
#define IMAGE_MODE_GET_FMT(x) ((x) & 0xC)
#define RESET 0xE0
#define RESET_MICROC 0x40
#define RESET_SCCB 0x20
#define RESET_JPEG 0x10
#define RESET_DVP 0x04
#define RESET_IPU 0x02
#define RESET_CIF 0x01
#define MC_BIST 0xF9
#define MC_BIST_RESET 0x80
#define MC_BIST_BOOT_ROM_SEL 0x40
#define MC_BIST_12KB_SEL 0x20
#define MC_BIST_12KB_MASK 0x30
#define MC_BIST_512KB_SEL 0x08
#define MC_BIST_512KB_MASK 0x0C
#define MC_BIST_BUSY_BIT_R 0x02
#define MC_BIST_MC_RES_ONE_SH_W 0x02
#define MC_BIST_LAUNCH 0x01
#define BANK_SEL 0xFF
#define BANK_SEL_DSP 0x00
#define BANK_SEL_SENSOR 0x01
/* Sensor register bank FF=0x01*/
#define GAIN 0x00
#define COM1 0x03
#define REG_PID 0x0A
#define REG_VER 0x0B
#define COM4 0x0D
#define AEC 0x10
#define CLKRC 0x11
#define CLKRC_DOUBLE 0x82
#define CLKRC_DIVIDER_MASK 0x3F
#define COM10 0x15
#define HSTART 0x17
#define HSTOP 0x18
#define VSTART 0x19
#define VSTOP 0x1A
#define MIDH 0x1C
#define MIDL 0x1D
#define AEW 0x24
#define AEB 0x25
#define REG2A 0x2A
#define FRARL 0x2B
#define ADDVSL 0x2D
#define ADDVSH 0x2E
#define YAVG 0x2F
#define HSDY 0x30
#define HEDY 0x31
#define ARCOM2 0x34
#define REG45 0x45
#define FLL 0x46
#define FLH 0x47
#define COM19 0x48
#define ZOOMS 0x49
#define COM22 0x4B
#define COM25 0x4E
#define BD50 0x4F
#define BD60 0x50
#define REG5D 0x5D
#define REG5E 0x5E
#define REG5F 0x5F
#define REG60 0x60
#define HISTO_LOW 0x61
#define HISTO_HIGH 0x62
#define REG04 0x04
#define REG04_DEFAULT 0x28
#define REG04_HFLIP_IMG 0x80
#define REG04_VFLIP_IMG 0x40
#define REG04_VREF_EN 0x10
#define REG04_HREF_EN 0x08
#define REG04_SET(x) (REG04_DEFAULT | x)
#define REG08 0x08
#define COM2 0x09
#define COM2_STDBY 0x10
#define COM2_OUT_DRIVE_1x 0x00
#define COM2_OUT_DRIVE_2x 0x01
#define COM2_OUT_DRIVE_3x 0x02
#define COM2_OUT_DRIVE_4x 0x03
#define COM3 0x0C
#define COM3_DEFAULT 0x38
#define COM3_BAND_50Hz 0x04
#define COM3_BAND_60Hz 0x00
#define COM3_BAND_AUTO 0x02
#define COM3_BAND_SET(x) (COM3_DEFAULT | x)
#define COM7 0x12
#define COM7_SRST 0x80
#define COM7_RES_UXGA 0x00 /* UXGA */
#define COM7_RES_SVGA 0x40 /* SVGA */
#define COM7_RES_CIF 0x20 /* CIF */
#define COM7_ZOOM_EN 0x04 /* Enable Zoom */
#define COM7_COLOR_BAR 0x02 /* Enable Color Bar Test */
#define COM7_GET_RES(x) ((x) & 0x70)
#define COM8 0x13
#define COM8_DEFAULT 0xC0
#define COM8_BNDF_EN 0x20 /* Enable Banding filter */
#define COM8_AGC_EN 0x04 /* AGC Auto/Manual control selection */
#define COM8_AEC_EN 0x01 /* Auto/Manual Exposure control */
#define COM8_SET(x) (COM8_DEFAULT | x)
#define COM8_SET_AEC(r, x) (((r) & 0xFE) | ((x) & 1))
#define COM9 0x14 /* AGC gain ceiling */
#define COM9_DEFAULT 0x08
#define COM9_AGC_GAIN_2x 0x00 /* AGC: 2x */
#define COM9_AGC_GAIN_4x 0x01 /* AGC: 4x */
#define COM9_AGC_GAIN_8x 0x02 /* AGC: 8x */
#define COM9_AGC_GAIN_16x 0x03 /* AGC: 16x */
#define COM9_AGC_GAIN_32x 0x04 /* AGC: 32x */
#define COM9_AGC_GAIN_64x 0x05 /* AGC: 64x */
#define COM9_AGC_GAIN_128x 0x06 /* AGC: 128x */
#define COM9_AGC_SET(x) (COM9_DEFAULT | (x << 5))
#define CTRL1_AWB 0x08 /* Enable AWB */
#define VV 0x26
#define VV_AGC_TH_SET(h, l) ((h << 4) | (l & 0x0F))
#define REG32 0x32
#define REG32_UXGA 0x36
#define REG32_SVGA 0x09
#define REG32_CIF 0x00
#define VAL_SET(x, mask, rshift, lshift) ((((x) >> rshift) & mask) << lshift)
#define CTRLI_V_DIV_SET(x) VAL_SET(x, 0x3, 0, 3)
#define CTRLI_H_DIV_SET(x) VAL_SET(x, 0x3, 0, 0)
#define SIZEL_HSIZE8_11_SET(x) VAL_SET(x, 0x1, 11, 6)
#define SIZEL_HSIZE8_SET(x) VAL_SET(x, 0x7, 0, 3)
#define SIZEL_VSIZE8_SET(x) VAL_SET(x, 0x7, 0, 0)
#define HSIZE8_SET(x) VAL_SET(x, 0xFF, 3, 0)
#define VSIZE8_SET(x) VAL_SET(x, 0xFF, 3, 0)
#define HSIZE_SET(x) VAL_SET(x, 0xFF, 2, 0)
#define VSIZE_SET(x) VAL_SET(x, 0xFF, 2, 0)
#define XOFFL_SET(x) VAL_SET(x, 0xFF, 0, 0)
#define YOFFL_SET(x) VAL_SET(x, 0xFF, 0, 0)
#define VHYX_VSIZE_SET(x) VAL_SET(x, 0x1, (8 + 2), 7)
#define VHYX_HSIZE_SET(x) VAL_SET(x, 0x1, (8 + 2), 3)
#define VHYX_YOFF_SET(x) VAL_SET(x, 0x3, 8, 4)
#define VHYX_XOFF_SET(x) VAL_SET(x, 0x3, 8, 0)
#define TEST_HSIZE_SET(x) VAL_SET(x, 0x1, (9 + 2), 7)
#define ZMOW_OUTW_SET(x) VAL_SET(x, 0xFF, 2, 0)
#define ZMOH_OUTH_SET(x) VAL_SET(x, 0xFF, 2, 0)
#define ZMHH_ZSPEED_SET(x) VAL_SET(x, 0x0F, 0, 4)
#define ZMHH_OUTH_SET(x) VAL_SET(x, 0x1, (8 + 2), 2)
#define ZMHH_OUTW_SET(x) VAL_SET(x, 0x3, (8 + 2), 0)
#endif //__REG_REGS_H__

View File

@ -33,7 +33,6 @@
#include "omv_i2c.h"
#include "omv_csi.h"
#include "ov5640.h"
#include "ov5640_regs.h"
#include "py/mphal.h"
#define BLANK_LINES 8

View File

@ -21,9 +21,122 @@
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*
* OV5640 driver.
* OV5640 register definitions.
*/
#ifndef __OV5640_H__
#define __OV5640_H__
int ov5640_init(omv_csi_t *csi);
#endif // __OV5640_H__
#ifndef __REG_REGS_H__
#define __REG_REGS_H__
#define SYSTEM_RESET_00 0x3000
#define SYSTEM_RESET_01 0x3001
#define SYSTEM_RESET_02 0x3002
#define CLOCK_ENABLE_02 0x3006
#define SYSTEM_CTROL0 0x3008
#define AF_CMD_MAIN 0x3022
#define AF_CMD_ACK 0x3023
#define AF_FW_STATUS 0x3029
#define SC_PLL_CONTRL0 0x3034
#define SC_PLL_CONTRL1 0x3035
#define SC_PLL_CONTRL2 0x3036
#define SC_PLL_CONTRL3 0x3037
#define SCCB_SYSTEM_CTRL_1 0x3103
#define SYSTEM_ROOT_DIVIDER 0x3108
#define AWB_R_GAIN_H 0x3400
#define AWB_R_GAIN_L 0x3401
#define AWB_G_GAIN_H 0x3402
#define AWB_G_GAIN_L 0x3403
#define AWB_B_GAIN_H 0x3404
#define AWB_B_GAIN_L 0x3405
#define AWB_MANUAL_CONTROL 0x3406
#define AEC_PK_EXPOSURE_0 0x3500
#define AEC_PK_EXPOSURE_1 0x3501
#define AEC_PK_EXPOSURE_2 0x3502
#define AEC_PK_MANUAL 0x3503
#define AEC_PK_REAL_GAIN_H 0x350A
#define AEC_PK_REAL_GAIN_L 0x350B
#define TIMING_HS_H 0x3800
#define TIMING_HS_L 0x3801
#define TIMING_VS_H 0x3802
#define TIMING_VS_L 0x3803
#define TIMING_HW_H 0x3804
#define TIMING_HW_L 0x3805
#define TIMING_VH_H 0x3806
#define TIMING_VH_L 0x3807
#define TIMING_DVPHO_H 0x3808
#define TIMING_DVPHO_L 0x3809
#define TIMING_DVPVO_H 0x380A
#define TIMING_DVPVO_L 0x380B
#define TIMING_HTS_H 0x380C
#define TIMING_HTS_L 0x380D
#define TIMING_VTS_H 0x380E
#define TIMING_VTS_L 0x380F
#define TIMING_HOFFSET_H 0x3810
#define TIMING_HOFFSET_L 0x3811
#define TIMING_VOFFSET_H 0x3812
#define TIMING_VOFFSET_L 0x3813
#define TIMING_X_INC 0x3814
#define TIMING_Y_INC 0x3815
#define TIMING_TC_REG_20 0x3820
#define TIMING_TC_REG_21 0x3821
#define AEC_CTRL_00 0x3A00
#define AEC_GAIN_CEILING_H 0x3A18
#define AEC_GAIN_CEILING_L 0x3A18
#define BLC_CTRL_00 0x4000
#define BLACK_LEVEL_00_H 0x402C
#define BLACK_LEVEL_00_L 0x402D
#define BLACK_LEVEL_01_H 0x402E
#define BLACK_LEVEL_01_L 0x402F
#define BLACK_LEVEL_10_H 0x4030
#define BLACK_LEVEL_10_L 0x4031
#define BLACK_LEVEL_11_H 0x4032
#define BLACK_LEVEL_11_L 0x4033
#define FORMAT_CONTROL 0x4300
#define VFIFO_HSIZE_H 0x4602
#define VFIFO_HSIZE_L 0x4603
#define VFIFO_VSIZE_H 0x4604
#define VFIFO_VSIZE_L 0x4605
#define JPEG_CTRL07 0x4407
#define ISP_CONTROL_00 0x5300
#define FORMAT_CONTROL_MUX 0x501F
#define PRE_ISP_TEST 0x503D
#define MCU_FIRMWARE_BASE 0x8000
#endif //__REG_REGS_H__

View File

@ -1,142 +0,0 @@
/*
* SPDX-License-Identifier: MIT
*
* Copyright (C) 2013-2024 OpenMV, LLC.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*
* OV5640 register definitions.
*/
#ifndef __REG_REGS_H__
#define __REG_REGS_H__
#define SYSTEM_RESET_00 0x3000
#define SYSTEM_RESET_01 0x3001
#define SYSTEM_RESET_02 0x3002
#define CLOCK_ENABLE_02 0x3006
#define SYSTEM_CTROL0 0x3008
#define AF_CMD_MAIN 0x3022
#define AF_CMD_ACK 0x3023
#define AF_FW_STATUS 0x3029
#define SC_PLL_CONTRL0 0x3034
#define SC_PLL_CONTRL1 0x3035
#define SC_PLL_CONTRL2 0x3036
#define SC_PLL_CONTRL3 0x3037
#define SCCB_SYSTEM_CTRL_1 0x3103
#define SYSTEM_ROOT_DIVIDER 0x3108
#define AWB_R_GAIN_H 0x3400
#define AWB_R_GAIN_L 0x3401
#define AWB_G_GAIN_H 0x3402
#define AWB_G_GAIN_L 0x3403
#define AWB_B_GAIN_H 0x3404
#define AWB_B_GAIN_L 0x3405
#define AWB_MANUAL_CONTROL 0x3406
#define AEC_PK_EXPOSURE_0 0x3500
#define AEC_PK_EXPOSURE_1 0x3501
#define AEC_PK_EXPOSURE_2 0x3502
#define AEC_PK_MANUAL 0x3503
#define AEC_PK_REAL_GAIN_H 0x350A
#define AEC_PK_REAL_GAIN_L 0x350B
#define TIMING_HS_H 0x3800
#define TIMING_HS_L 0x3801
#define TIMING_VS_H 0x3802
#define TIMING_VS_L 0x3803
#define TIMING_HW_H 0x3804
#define TIMING_HW_L 0x3805
#define TIMING_VH_H 0x3806
#define TIMING_VH_L 0x3807
#define TIMING_DVPHO_H 0x3808
#define TIMING_DVPHO_L 0x3809
#define TIMING_DVPVO_H 0x380A
#define TIMING_DVPVO_L 0x380B
#define TIMING_HTS_H 0x380C
#define TIMING_HTS_L 0x380D
#define TIMING_VTS_H 0x380E
#define TIMING_VTS_L 0x380F
#define TIMING_HOFFSET_H 0x3810
#define TIMING_HOFFSET_L 0x3811
#define TIMING_VOFFSET_H 0x3812
#define TIMING_VOFFSET_L 0x3813
#define TIMING_X_INC 0x3814
#define TIMING_Y_INC 0x3815
#define TIMING_TC_REG_20 0x3820
#define TIMING_TC_REG_21 0x3821
#define AEC_CTRL_00 0x3A00
#define AEC_GAIN_CEILING_H 0x3A18
#define AEC_GAIN_CEILING_L 0x3A18
#define BLC_CTRL_00 0x4000
#define BLACK_LEVEL_00_H 0x402C
#define BLACK_LEVEL_00_L 0x402D
#define BLACK_LEVEL_01_H 0x402E
#define BLACK_LEVEL_01_L 0x402F
#define BLACK_LEVEL_10_H 0x4030
#define BLACK_LEVEL_10_L 0x4031
#define BLACK_LEVEL_11_H 0x4032
#define BLACK_LEVEL_11_L 0x4033
#define FORMAT_CONTROL 0x4300
#define VFIFO_HSIZE_H 0x4602
#define VFIFO_HSIZE_L 0x4603
#define VFIFO_VSIZE_H 0x4604
#define VFIFO_VSIZE_L 0x4605
#define JPEG_CTRL07 0x4407
#define ISP_CONTROL_00 0x5300
#define FORMAT_CONTROL_MUX 0x501F
#define PRE_ISP_TEST 0x503D
#define MCU_FIRMWARE_BASE 0x8000
#endif //__REG_REGS_H__

View File

@ -33,7 +33,6 @@
#include "omv_i2c.h"
#include "omv_csi.h"
#include "ov7670.h"
#include "ov7670_regs.h"
#include "py/mphal.h"
static const uint8_t default_regs[][2] = {

View File

@ -21,10 +21,352 @@
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*
* OV7670 driver.
* OV7670 register definitions.
*/
#ifndef __OV7670_H__
#define __OV7670_H__
#define OMV_OV7670_CLK_FREQ 24000000
int ov7670_init(omv_csi_t *csi);
#endif // __OV7725_H__
#ifndef __REG_REGS_H__
#define __REG_REGS_H__
#define GAIN 0x00 /* AGC - Gain control gain setting */
#define BLUE 0x01 /* AWB - Blue channel gain setting */
#define RED 0x02 /* AWB - Red channel gain setting */
#define VREF 0x03 /* Vertical Frame Control */
#define COM1 0x04 /* Common Control 1 */
#define BAVE 0x05 /* U/B Average Level */
#define GBAVE 0x06 /* Y/Gb Average Level */
#define AECHH 0x07 /* Exposure Value - AEC MSB 5 bits */
#define RAVE 0x08 /* V/R Average Level */
#define COM2 0x09 /* Common Control 2 */
#define COM2_SOFT_SLEEP 0x10 /* Soft sleep mode */
#define COM2_OUT_DRIVE_1x 0x00 /* Output drive capability 1x */
#define COM2_OUT_DRIVE_2x 0x01 /* Output drive capability 2x */
#define COM2_OUT_DRIVE_3x 0x02 /* Output drive capability 3x */
#define COM2_OUT_DRIVE_4x 0x03 /* Output drive capability 4x */
#define PID 0x0A /* Product ID Number MSB */
#define VER 0x0B /* Product ID Number LSB */
#define COM3 0x0C /* Common Control 3 */
#define COM3_SWAP_MSB 0x40 /* Output data MSB and LSB swap */
#define COM3_TRI_CLOCK 0x20 /* Tri-state option for output clock at power-down period */
#define COM3_TRI_DATA 0x10 /* Tri-state option for output data at power-down period */
#define COM3_SCALE_EN 0x08 /* Scale enable */
#define COM3_DCW_EN 0x04 /* DCW enable */
#define COM4 0x0D /* Common Control 4 */
#define COM4_AEC_FULL 0x00 /* AEC evaluate full window */
#define COM4_AEC_1_2 0x10 /* AEC evaluate 1/2 window */
#define COM4_AEC_1_4 0x20 /* AEC evaluate 1/4 window */
#define COM4_AEC_2_3 0x30 /* AEC evaluate 2/3 window */
#define COM5 0x0E /* Reserved */
#define COM6 0x0F /* Common Control 6 */
#define COM6_HREF_BLACK_EN 0x80 /* Enable HREF at optical black */
#define COM6_RESET_TIMING 0x02 /* Reset all timing when format changes */
#define AECH 0x10 /* AEC[9:2] (see registers AECHH for AEC[15:10] and COM1 for AEC[1:0]) */
#define CLKRC 0x11 /* Internal Clock */
#define CLKRC_PRESCALER_BYPASS 0x40 /* Use external clock directly */
#define CLKRC_PRESCALER 0x3F /* Internal clock pre-scaler */
#define COM7 0x12 /* Common Control 7 */
#define COM7_RESET 0x80 /* SCCB Register Reset */
#define COM7_RES_VGA 0x00 /* Resolution VGA */
#define COM7_RES_CIF 0x20 /* Resolution CIF */
#define COM7_RES_QVGA 0x10 /* Resolution QVGA */
#define COM7_RES_QCIF 0x08 /* Resolution QCIF */
#define COM7_RGB_FMT 0x04 /* Output format RGB */
#define COM7_CBAR_EN 0x02 /* Color bar selection */
#define COM7_FMT_RAW 0x01 /* Output format Bayer RAW */
#define COM8 0x13 /* Common Control 8 */
#define COM8_FAST_AEC 0x80 /* Enable fast AGC/AEC algorithm */
#define COM8_AEC_STEP 0x40 /* AEC - Step size unlimited step size */
#define COM8_BANDF_EN 0x20 /* Banding filter ON/OFF */
#define COM8_AGC_EN 0x04 /* AGC Enable */
#define COM8_AWB_EN 0x02 /* AWB Enable */
#define COM8_AEC_EN 0x01 /* AEC Enable */
#define COM9 0x14 /* Common Control 9 */
#define COM9_AGC_GAIN_2x 0x00 /* Automatic Gain Ceiling 2x */
#define COM9_AGC_GAIN_4x 0x10 /* Automatic Gain Ceiling 4x */
#define COM9_AGC_GAIN_8x 0x20 /* Automatic Gain Ceiling 8x */
#define COM9_AGC_GAIN_16x 0x30 /* Automatic Gain Ceiling 16x */
#define COM9_AGC_GAIN_32x 0x40 /* Automatic Gain Ceiling 32x */
#define COM9_AGC_GAIN_64x 0x50 /* Automatic Gain Ceiling 64x */
#define COM9_AGC_GAIN_128x 0x60 /* Automatic Gain Ceiling 128x */
#define COM9_SET_AGC(r, x) ((r & 0x8F) | ((x & 0x07) << 4))
#define COM10 0x15 /* Common Control 10 */
#define COM10_HSYNC_EN 0x40 /* HREF changes to HSYNC */
#define COM10_PCLK_FREE 0x00 /* PCLK output option: free running PCLK */
#define COM10_PCLK_MASK 0x20 /* PCLK output option: masked during horizontal blank */
#define COM10_PCLK_REV 0x10 /* PCLK reverse */
#define COM10_HREF_REV 0x08 /* HREF reverse */
#define COM10_VSYNC_FALLING 0x00 /* VSYNC changes on falling edge of PCLK */
#define COM10_VSYNC_RISING 0x04 /* VSYNC changes on rising edge of PCLK */
#define COM10_VSYNC_NEG 0x02 /* VSYNC negative */
#define COM10_HSYNC_NEG 0x01 /* HSYNC negative */
#define HSTART 0x17 /* Output Format - Horizontal Frame (HREF column) start high 8-bit */
#define HSTOP 0x18 /* Output Format - Horizontal Frame (HREF column) end high 8-bit */
#define VSTART 0x19 /* Output Format - Vertical Frame (row) start high 8-bit */
#define VSTOP 0x1A /* Output Format - Vertical Frame (row) end high 8-bit */
#define PSHFT 0x1B /* Data Format - Pixel Delay Select (delays timing of the D[7:0]) */
#define MIDH 0x1C /* Manufacturer ID Byte - High */
#define MIDL 0x1D /* Manufacturer ID Byte - Low */
#define MVFP 0x1E /* Mirror/VFlip Enable */
#define MVFP_MIRROR 0x20 /* Mirror image */
#define MVFP_VFLIP 0x10 /* VFlip image */
#define MVFP_BLACK_SUN_EN 0x04 /* Black sun enable */
#define LAEC 0x1F /* Reserved */
#define ADCCTR0 0x20 /* ADC Control */
#define ADCCTR0_ADC_RANGE_1X 0x00 /* ADC range adjustment 1x range */
#define ADCCTR0_ADC_RANGE_1_5X 0x08 /* ADC range adjustment 1.5x range */
#define ADCCTR0_ADC_REF_0_8 0x00 /* ADC reference adjustment 0.8x */
#define ADCCTR0_ADC_REF_1_0 0x04 /* ADC reference adjustment 1.0x */
#define ADCCTR0_ADC_REF_1_2 0x07 /* ADC reference adjustment 1.2x */
#define ADCCTR1 0x21 /* Reserved */
#define ADCCTR2 0x22 /* Reserved */
#define ADCCTR3 0x23 /* Reserved */
#define AEW 0x24 /* AGC/AEC - Stable Operating Region (Upper Limit) */
#define AEB 0x25 /* AGC/AEC - Stable Operating Region (Lower Limit) */
#define VPT 0x26 /* AGC/AEC Fast Mode Operating Region */
#define BBIAS 0x27 /* B Channel Signal Output Bias (effective only when COM6[3] = 1) */
#define GBIAS 0x28 /* Gb Channel Signal Output Bias (effective only when COM6[3] = 1) */
#define EXHCH 0x2A /* Dummy Pixel Insert MSB */
#define EXHCL 0x2B /* Dummy Pixel Insert LSB */
#define RBIAS 0x2C /* R Channel Signal Output Bias (effective only when COM6[3] = 1) */
#define ADVFL 0x2D /* LSB of insert dummy lines in vertical direction (1 bit equals 1 line) */
#define ADVFH 0x2E /* MSB of insert dummy lines in vertical direction */
#define YAVE 0x2F /* Y/G Channel Average Value */
#define HSYST 0x30 /* HSYNC Rising Edge Delay (low 8 bits) */
#define HSYEN 0x31 /* HSYNC Falling Edge Delay (low 8 bits) */
#define HREF 0x32 /* HREF Control */
#define CHLF 0x33 /* Array Current Control */
#define ARBLM 0x34 /* Array Reference Control */
#define ADC 0x37 /* ADC Control */
#define ACOM 0x38 /* ADC and Analog Common Mode Control */
#define OFON 0x39 /* ADC Offset Control */
#define TSLB 0x3A /* Line Buffer Test Option */
#define TSLB_NEGATIVE 0x20 /* Negative image enable */
#define TSLB_UV_NORMAL 0x00 /* UV output value normal */
#define TSLB_UV_FIXED 0x10 /* UV output value set in registers MANU and MANV */
#define TSLB_AUTO_WINDOW 0x01 /* automatically sets output window when resolution changes */
#define COM11 0x3B /* Common Control 11 */
#define COM11_AFR 0x80 /* Auto frame rate control ON/OFF selection (night mode) */
#define COM11_AFR_0 0x00 /* No reduction of frame rate */
#define COM11_AFR_1_2 0x20 /* Max reduction to 1/2 frame rate */
#define COM11_AFR_1_4 0x40 /* Max reduction to 1/4 frame rate */
#define COM11_AFR_1_8 0x60 /* Max reduction to 1/8 frame rate */
#define COM11_HZAUTO_EN 0x10 /* Enable 50/60 Hz auto detection */
#define COM11_BANDF_SELECT 0x08 /* Banding filter value selection */
#define COM11_AEC_BANDF 0x02 /* Enable AEC below banding value */
#define COM12 0x3C /* Common Control 12 */
#define COM12_HREF_EN 0x80 /* Always has HREF */
#define COM13 0x3D /* Common Control 13 */
#define COM13_GAMMA_EN 0x80 /* Gamma enable */
#define COM13_UVSAT_AUTO 0x40 /* UV saturation level - UV auto adjustment. */
#define COM13_UV_SWAP 0x01 /* UV swap */
#define COM14 0x3E /* Common Control 14 */
#define COM14_DCW_EN 0x10 /* DCW and scaling PCLK */
#define COM14_MANUAL_SCALE 0x08 /* Manual scaling enable for pre-defined resolutions */
#define COM14_PCLK_DIV_1 0x00 /* PCLK divider. Divided by 1 */
#define COM14_PCLK_DIV_2 0x01 /* PCLK divider. Divided by 2 */
#define COM14_PCLK_DIV_4 0x02 /* PCLK divider. Divided by 4 */
#define COM14_PCLK_DIV_8 0x03 /* PCLK divider. Divided by 8 */
#define COM14_PCLK_DIV_16 0x04 /* PCLK divider. Divided by 16 */
#define EDGE 0x3F /* Edge Enhancement Adjustment */
#define EDGE_FACTOR_MASK 0x1F /* Edge enhancement factor */
#define COM15 0x40 /* Common Control 15 */
#define COM15_OUT_10_F0 0x00 /* Output data range 10 to F0 */
#define COM15_OUT_01_FE 0x80 /* Output data range 01 to FE */
#define COM15_OUT_00_FF 0xC0 /* Output data range 00 to FF */
#define COM15_FMT_RGB_NORMAL 0x00 /* Normal RGB normal output */
#define COM15_FMT_RGB565 0x10 /* Normal RGB 565 output */
#define COM15_FMT_RGB555 0x30 /* Normal RGB 555 output */
#define COM16 0x41 /* Common Control 16 */
#define COM16_EDGE_EN 0x20 /* Enable edge enhancement threshold auto-adjustment */
#define COM16_DENOISE_EN 0x10 /* De-noise threshold auto-adjustment */
#define COM16_AWB_GAIN_EN 0x08 /* AWB gain enable */
#define COM16_COLOR_MTX_EN 0x02 /* Color matrix coefficient double option */
#define COM17 0x42 /* Common Control 17 */
#define COM17_AEC_FULL 0x00 /* AEC evaluate full window */
#define COM17_AEC_1_2 0x40 /* AEC evaluate 1/2 window */
#define COM17_AEC_1_4 0x80 /* AEC evaluate 1/4 window */
#define COM17_AEC_2_3 0xC0 /* AEC evaluate 2/3 window */
#define COM17_DSP_CBAR_EN 0x08 /* DSP color bar enable */
#define AWBC1 0x43 /* Reserved */
#define AWBC2 0x44 /* Reserved */
#define AWBC3 0x45 /* Reserved */
#define AWBC4 0x46 /* Reserved */
#define AWBC5 0x47 /* Reserved */
#define AWBC6 0x48 /* Reserved */
#define REG4B 0x4B /* REG4B */
#define REG4B_UV_AVG_EN 0x01 /* UV average enable */
#define DNSTH 0x4C /* De-noise Threshold*/
#define MTX1 0x4F /* Matrix Coefficient 1 */
#define MTX2 0x50 /* Matrix Coefficient 2 */
#define MTX3 0x51 /* Matrix Coefficient 3 */
#define MTX4 0x52 /* Matrix Coefficient 4 */
#define MTX5 0x53 /* Matrix Coefficient 5 */
#define MTX6 0x54 /* Matrix Coefficient 6 */
#define BRIGHTNESS 0x55 /* Brightness Control */
#define CONTRAST 0x56 /* Contrast Control */
#define CONTRAST_CENTER 0x57 /* Contrast Center */
#define MTXS 0x58 /* Matrix Coefficient Sign for coefficient 5 to 0*/
#define LCC1 0x62 /* Lens Correction Option 1 */
#define LCC2 0x63 /* Lens Correction Option 2 */
#define LCC3 0x64 /* Lens Correction Option 3 */
#define LCC4 0x65 /* Lens Correction Option 4 */
#define LCC5 0x66 /* Lens Correction Control */
#define LCC5_LC_EN 0x01 /* Lens Correction Enable */
#define LCC5_LC_CTRL 0x04 /* Lens correction control select */
#define MANU 0x67 /* Manual U Value (effective only when register TSLB[4] is high) */
#define MANV 0x68 /* Manual V Value (effective only when register TSLB[4] is high) */
#define GFIX 0x69 /* Fix Gain Control */
#define GGAIN 0x6A /* G Channel AWB Gain */
#define DBLV 0x6B /* PLL control */
#define DBLV_PLL_BYPASS 0x00 /* Bypass PLL */
#define DBLV_PLL_4x 0x40 /* Input clock 4x */
#define DBLV_PLL_6x 0x80 /* Input clock 8x */
#define DBLV_PLL_8x 0xC0 /* Input clock 16x */
#define DBLV_REG_BYPASS 0x10 /* Bypass internal regulator */
#define AWBCTR3 0x6C /* AWB Control 3 */
#define AWBCTR2 0x6D /* AWB Control 2 */
#define AWBCTR1 0x6E /* AWB Control 1 */
#define AWBCTR0 0x6F /* AWB Control 0 */
#define SCALING_XSC 0x70 /* Test Pattern[0] */
#define SCALING_YSC 0x71 /* Test Pattern[1] */
#define SCALING_DCWCTR 0x72 /* DCW control parameter */
#define SCALING_PCLK_DIV 0x73 /* Clock divider control for DSP.*/
#define SCALING_PCLK_DIV_BYPASS 0x08 /* Bypass clock divider for DSP scale control */
#define SCALING_PCLK_DIV_1 0x00 /* Divided by 1 */
#define SCALING_PCLK_DIV_2 0x01 /* Divided by 2 */
#define SCALING_PCLK_DIV_4 0x02 /* Divided by 4 */
#define SCALING_PCLK_DIV_8 0x03 /* Divided by 8 */
#define SCALING_PCLK_DIV_16 0x04 /* Divided by 16 */
#define REG74 0x74 /* REG74 */
#define REG74_DGAIN_EN 0x10 /* Digital gain control by REG74[1:0] */
#define REG74_DGAIN_BYPASS 0x00 /* Bypass */
#define REG74_DGAIN_1X 0x01 /* 1x */
#define REG74_DGAIN_2X 0x02 /* 2x */
#define REG74_DGAIN_4X 0x03 /* 4x */
#define REG75 0x75 /* REG75 */
#define REG75_EDGE_LOWER 0x1F /* Edge enhancement lower limit */
#define REG76 0x76 /* REG76 */
#define REG76_WHITE_PIX_CORR 0x80 /* White pixel correction enable */
#define REG76_BLACK_PIX_CORR 0x40 /* Black pixel correction enable */
#define REG76_EDGE_HIGHER 0x1F /* Edge enhancement higher limit */
#define REG77 0x77 /* Offset, de-noise range control */
#define SLOP 0x7A /* Gamma Curve Highest Segment Slope */
#define GAM1 0x7B /* Gamma Curve 1st Segment Input End Point 0x04 Output Value */
#define GAM2 0x7C /* Gamma Curve 2nd Segment Input End Point 0x08 Output Value */
#define GAM3 0x7D /* Gamma Curve 3rd Segment Input End Point 0x10 Output Value */
#define GAM4 0x7E /* Gamma Curve 4th Segment Input End Point 0x20 Output Value */
#define GAM5 0x7F /* Gamma Curve 5th Segment Input End Point 0x28 Output Value */
#define GAM6 0x80 /* Gamma Curve 6th Segment Input End Point 0x30 Output Value */
#define GAM7 0x81 /* Gamma Curve 7th Segment Input End Point 0x38 Output Value */
#define GAM8 0x82 /* Gamma Curve 8th Segment Input End Point 0x40 Output Value */
#define GAM9 0x83 /* Gamma Curve 9th Segment Input Enpd Point 0x48 Output Value */
#define GAM10 0x84 /* Gamma Curve 10th Segment Input End Point 0x50 Output Value */
#define GAM11 0x85 /* Gamma Curve 11th Segment Input End Point 0x60 Output Value */
#define GAM12 0x86 /* Gamma Curve 12th Segment Input End Point 0x70 Output Value */
#define GAM13 0x87 /* Gamma Curve 13th Segment Input End Point 0x90 Output Value */
#define GAM14 0x88 /* Gamma Curve 14th Segment Input End Point 0xB0 Output Value */
#define GAM15 0x89 /* Gamma Curve 15th Segment Input End Point 0xD0 Output Value */
#define RGB444 0x8C /* REG444 */
#define RGB444_RGB444_EN 0x02 /* RGB444 enable, effective only when COM15[4] is high */
#define RGB444_RGB444_FMT 0x01 /* RGB444 word format. 0 = xR GB 1 = RG Bx */
#define DM_LNL 0x92 /* Dummy Line low 8 bits */
#define DM_LNH 0x93 /* Dummy Line high 8 bits */
#define LCC6 0x94 /* RW Lens Correction Option 6 (effective only when LCC5[2] is high) */
#define LCC7 0x95 /* RW Lens Correction Option 7 (effective only when LCC5[2] is high) */
#define BD50ST 0x9D /* Hz Banding Filter Value (effective only when COM8[5] is high and COM11[3] is high) */
#define BD60ST 0x9E /* Hz Banding Filter Value (effective only when COM8[5] is high and COM11[3] is low) */
#define HAECC1 0x9F /* Histogram-based AEC/AGC Control 1 */
#define HAECC2 0xA0 /* Histogram-based AEC/AGC Control 2 */
#define SCALING_PCLK 0xA2 /* Pixel Clock Delay */
#define SCALING_PCLK_DELAY 0x7F /* Scaling output delay */
#define NT_CTRL 0xA4 /* Auto frame rate adjustment control */
#define NT_CTRL_AFR_HALF 0x08 /* Reduce frame rate by half */
#define NT_CTRL_AFR_PT_2X 0x00 /* Insert dummy row at 2x gain */
#define NT_CTRL_AFR_PT_4X 0x01 /* Insert dummy row at 4x gain */
#define NT_CTRL_AFR_PT_8X 0x02 /* Insert dummy row at 8x gain */
#define BD50MAX 0xA5 /* 50Hz Banding Step Limit */
#define HAECC3 0xA6 /* Histogram-based AEC/AGC Control 3 */
#define HAECC4 0xA7 /* Histogram-based AEC/AGC Control 4 */
#define HAECC5 0xA8 /* Histogram-based AEC/AGC Control 5 */
#define HAECC6 0xA9 /* Histogram-based AEC/AGC Control 6 */
#define HAECC7 0xAA /* AEC algorithm selection */
#define HAECC7_AEC_AVG 0x00 /* Average-based AEC algorithm */
#define HAECC7_AEC_HIST 0x80 /* Histogram-based AEC algorithm */
#define BD60MAX 0xAB /* 60Hz Banding Step Limit */
#define STR_OPT 0xAC /* Strobe Control */
#define STR_OPT_EN 0x80 /* Strobe Enable */
#define STR_OPT_CTRL 0x40 /* R/G/B gain controlled by STR_R (0xAD) STR_G (0xAE) STR_B (0xAF) for LED output frame */
#define STR_OPT_XENON_1ROW 0x00 /* Xenon mode option 1 row */
#define STR_OPT_XENON_2ROW 0x10 /* Xenon mode option 2 rows */
#define STR_OPT_XENON_3ROW 0x20 /* Xenon mode option 3 rows */
#define STR_OPT_XENON_4ROW 0x30 /* Xenon mode option 4 rows */
#define STR_OPT_MODE_XENON 0x00 /* Mode select */
#define STR_OPT_MODE_LED1 0x01 /* Mode select */
#define STR_OPT_MODE_LED2 0x02 /* Mode select */
#define STR_R 0xAD /* R Gain for LED Output Frame */
#define STR_G 0xAE /* G Gain for LED Output Frame */
#define STR_B 0xAF /* B Gain for LED Output Frame */
#define ABLC1 0xB1 /* ABLC Control */
#define ABLC1_EN 0x04 /* Enable ABLC function */
#define THL_ST 0xB3 /* ABLC Target */
#define AD_CHB 0xBE /* Blue Channel Black Level Compensation */
#define AD_CHR 0xBF /* Red Channel Black Level Compensation */
#define AD_CHGB 0xC0 /* Gb Channel Black Level Compensation */
#define AD_CHGR 0xC1 /* Gr Channel Black Level Compensation */
#define SATCTR 0xC9 /* UV Saturation Control */
#endif //__REG_REGS_H__

View File

@ -1,372 +0,0 @@
/*
* SPDX-License-Identifier: MIT
*
* Copyright (C) 2013-2024 OpenMV, LLC.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*
* OV7670 register definitions.
*/
#ifndef __REG_REGS_H__
#define __REG_REGS_H__
#define GAIN 0x00 /* AGC - Gain control gain setting */
#define BLUE 0x01 /* AWB - Blue channel gain setting */
#define RED 0x02 /* AWB - Red channel gain setting */
#define VREF 0x03 /* Vertical Frame Control */
#define COM1 0x04 /* Common Control 1 */
#define BAVE 0x05 /* U/B Average Level */
#define GBAVE 0x06 /* Y/Gb Average Level */
#define AECHH 0x07 /* Exposure Value - AEC MSB 5 bits */
#define RAVE 0x08 /* V/R Average Level */
#define COM2 0x09 /* Common Control 2 */
#define COM2_SOFT_SLEEP 0x10 /* Soft sleep mode */
#define COM2_OUT_DRIVE_1x 0x00 /* Output drive capability 1x */
#define COM2_OUT_DRIVE_2x 0x01 /* Output drive capability 2x */
#define COM2_OUT_DRIVE_3x 0x02 /* Output drive capability 3x */
#define COM2_OUT_DRIVE_4x 0x03 /* Output drive capability 4x */
#define PID 0x0A /* Product ID Number MSB */
#define VER 0x0B /* Product ID Number LSB */
#define COM3 0x0C /* Common Control 3 */
#define COM3_SWAP_MSB 0x40 /* Output data MSB and LSB swap */
#define COM3_TRI_CLOCK 0x20 /* Tri-state option for output clock at power-down period */
#define COM3_TRI_DATA 0x10 /* Tri-state option for output data at power-down period */
#define COM3_SCALE_EN 0x08 /* Scale enable */
#define COM3_DCW_EN 0x04 /* DCW enable */
#define COM4 0x0D /* Common Control 4 */
#define COM4_AEC_FULL 0x00 /* AEC evaluate full window */
#define COM4_AEC_1_2 0x10 /* AEC evaluate 1/2 window */
#define COM4_AEC_1_4 0x20 /* AEC evaluate 1/4 window */
#define COM4_AEC_2_3 0x30 /* AEC evaluate 2/3 window */
#define COM5 0x0E /* Reserved */
#define COM6 0x0F /* Common Control 6 */
#define COM6_HREF_BLACK_EN 0x80 /* Enable HREF at optical black */
#define COM6_RESET_TIMING 0x02 /* Reset all timing when format changes */
#define AECH 0x10 /* AEC[9:2] (see registers AECHH for AEC[15:10] and COM1 for AEC[1:0]) */
#define CLKRC 0x11 /* Internal Clock */
#define CLKRC_PRESCALER_BYPASS 0x40 /* Use external clock directly */
#define CLKRC_PRESCALER 0x3F /* Internal clock pre-scaler */
#define COM7 0x12 /* Common Control 7 */
#define COM7_RESET 0x80 /* SCCB Register Reset */
#define COM7_RES_VGA 0x00 /* Resolution VGA */
#define COM7_RES_CIF 0x20 /* Resolution CIF */
#define COM7_RES_QVGA 0x10 /* Resolution QVGA */
#define COM7_RES_QCIF 0x08 /* Resolution QCIF */
#define COM7_RGB_FMT 0x04 /* Output format RGB */
#define COM7_CBAR_EN 0x02 /* Color bar selection */
#define COM7_FMT_RAW 0x01 /* Output format Bayer RAW */
#define COM8 0x13 /* Common Control 8 */
#define COM8_FAST_AEC 0x80 /* Enable fast AGC/AEC algorithm */
#define COM8_AEC_STEP 0x40 /* AEC - Step size unlimited step size */
#define COM8_BANDF_EN 0x20 /* Banding filter ON/OFF */
#define COM8_AGC_EN 0x04 /* AGC Enable */
#define COM8_AWB_EN 0x02 /* AWB Enable */
#define COM8_AEC_EN 0x01 /* AEC Enable */
#define COM9 0x14 /* Common Control 9 */
#define COM9_AGC_GAIN_2x 0x00 /* Automatic Gain Ceiling 2x */
#define COM9_AGC_GAIN_4x 0x10 /* Automatic Gain Ceiling 4x */
#define COM9_AGC_GAIN_8x 0x20 /* Automatic Gain Ceiling 8x */
#define COM9_AGC_GAIN_16x 0x30 /* Automatic Gain Ceiling 16x */
#define COM9_AGC_GAIN_32x 0x40 /* Automatic Gain Ceiling 32x */
#define COM9_AGC_GAIN_64x 0x50 /* Automatic Gain Ceiling 64x */
#define COM9_AGC_GAIN_128x 0x60 /* Automatic Gain Ceiling 128x */
#define COM9_SET_AGC(r, x) ((r & 0x8F) | ((x & 0x07) << 4))
#define COM10 0x15 /* Common Control 10 */
#define COM10_HSYNC_EN 0x40 /* HREF changes to HSYNC */
#define COM10_PCLK_FREE 0x00 /* PCLK output option: free running PCLK */
#define COM10_PCLK_MASK 0x20 /* PCLK output option: masked during horizontal blank */
#define COM10_PCLK_REV 0x10 /* PCLK reverse */
#define COM10_HREF_REV 0x08 /* HREF reverse */
#define COM10_VSYNC_FALLING 0x00 /* VSYNC changes on falling edge of PCLK */
#define COM10_VSYNC_RISING 0x04 /* VSYNC changes on rising edge of PCLK */
#define COM10_VSYNC_NEG 0x02 /* VSYNC negative */
#define COM10_HSYNC_NEG 0x01 /* HSYNC negative */
#define HSTART 0x17 /* Output Format - Horizontal Frame (HREF column) start high 8-bit */
#define HSTOP 0x18 /* Output Format - Horizontal Frame (HREF column) end high 8-bit */
#define VSTART 0x19 /* Output Format - Vertical Frame (row) start high 8-bit */
#define VSTOP 0x1A /* Output Format - Vertical Frame (row) end high 8-bit */
#define PSHFT 0x1B /* Data Format - Pixel Delay Select (delays timing of the D[7:0]) */
#define MIDH 0x1C /* Manufacturer ID Byte - High */
#define MIDL 0x1D /* Manufacturer ID Byte - Low */
#define MVFP 0x1E /* Mirror/VFlip Enable */
#define MVFP_MIRROR 0x20 /* Mirror image */
#define MVFP_VFLIP 0x10 /* VFlip image */
#define MVFP_BLACK_SUN_EN 0x04 /* Black sun enable */
#define LAEC 0x1F /* Reserved */
#define ADCCTR0 0x20 /* ADC Control */
#define ADCCTR0_ADC_RANGE_1X 0x00 /* ADC range adjustment 1x range */
#define ADCCTR0_ADC_RANGE_1_5X 0x08 /* ADC range adjustment 1.5x range */
#define ADCCTR0_ADC_REF_0_8 0x00 /* ADC reference adjustment 0.8x */
#define ADCCTR0_ADC_REF_1_0 0x04 /* ADC reference adjustment 1.0x */
#define ADCCTR0_ADC_REF_1_2 0x07 /* ADC reference adjustment 1.2x */
#define ADCCTR1 0x21 /* Reserved */
#define ADCCTR2 0x22 /* Reserved */
#define ADCCTR3 0x23 /* Reserved */
#define AEW 0x24 /* AGC/AEC - Stable Operating Region (Upper Limit) */
#define AEB 0x25 /* AGC/AEC - Stable Operating Region (Lower Limit) */
#define VPT 0x26 /* AGC/AEC Fast Mode Operating Region */
#define BBIAS 0x27 /* B Channel Signal Output Bias (effective only when COM6[3] = 1) */
#define GBIAS 0x28 /* Gb Channel Signal Output Bias (effective only when COM6[3] = 1) */
#define EXHCH 0x2A /* Dummy Pixel Insert MSB */
#define EXHCL 0x2B /* Dummy Pixel Insert LSB */
#define RBIAS 0x2C /* R Channel Signal Output Bias (effective only when COM6[3] = 1) */
#define ADVFL 0x2D /* LSB of insert dummy lines in vertical direction (1 bit equals 1 line) */
#define ADVFH 0x2E /* MSB of insert dummy lines in vertical direction */
#define YAVE 0x2F /* Y/G Channel Average Value */
#define HSYST 0x30 /* HSYNC Rising Edge Delay (low 8 bits) */
#define HSYEN 0x31 /* HSYNC Falling Edge Delay (low 8 bits) */
#define HREF 0x32 /* HREF Control */
#define CHLF 0x33 /* Array Current Control */
#define ARBLM 0x34 /* Array Reference Control */
#define ADC 0x37 /* ADC Control */
#define ACOM 0x38 /* ADC and Analog Common Mode Control */
#define OFON 0x39 /* ADC Offset Control */
#define TSLB 0x3A /* Line Buffer Test Option */
#define TSLB_NEGATIVE 0x20 /* Negative image enable */
#define TSLB_UV_NORMAL 0x00 /* UV output value normal */
#define TSLB_UV_FIXED 0x10 /* UV output value set in registers MANU and MANV */
#define TSLB_AUTO_WINDOW 0x01 /* automatically sets output window when resolution changes */
#define COM11 0x3B /* Common Control 11 */
#define COM11_AFR 0x80 /* Auto frame rate control ON/OFF selection (night mode) */
#define COM11_AFR_0 0x00 /* No reduction of frame rate */
#define COM11_AFR_1_2 0x20 /* Max reduction to 1/2 frame rate */
#define COM11_AFR_1_4 0x40 /* Max reduction to 1/4 frame rate */
#define COM11_AFR_1_8 0x60 /* Max reduction to 1/8 frame rate */
#define COM11_HZAUTO_EN 0x10 /* Enable 50/60 Hz auto detection */
#define COM11_BANDF_SELECT 0x08 /* Banding filter value selection */
#define COM11_AEC_BANDF 0x02 /* Enable AEC below banding value */
#define COM12 0x3C /* Common Control 12 */
#define COM12_HREF_EN 0x80 /* Always has HREF */
#define COM13 0x3D /* Common Control 13 */
#define COM13_GAMMA_EN 0x80 /* Gamma enable */
#define COM13_UVSAT_AUTO 0x40 /* UV saturation level - UV auto adjustment. */
#define COM13_UV_SWAP 0x01 /* UV swap */
#define COM14 0x3E /* Common Control 14 */
#define COM14_DCW_EN 0x10 /* DCW and scaling PCLK */
#define COM14_MANUAL_SCALE 0x08 /* Manual scaling enable for pre-defined resolutions */
#define COM14_PCLK_DIV_1 0x00 /* PCLK divider. Divided by 1 */
#define COM14_PCLK_DIV_2 0x01 /* PCLK divider. Divided by 2 */
#define COM14_PCLK_DIV_4 0x02 /* PCLK divider. Divided by 4 */
#define COM14_PCLK_DIV_8 0x03 /* PCLK divider. Divided by 8 */
#define COM14_PCLK_DIV_16 0x04 /* PCLK divider. Divided by 16 */
#define EDGE 0x3F /* Edge Enhancement Adjustment */
#define EDGE_FACTOR_MASK 0x1F /* Edge enhancement factor */
#define COM15 0x40 /* Common Control 15 */
#define COM15_OUT_10_F0 0x00 /* Output data range 10 to F0 */
#define COM15_OUT_01_FE 0x80 /* Output data range 01 to FE */
#define COM15_OUT_00_FF 0xC0 /* Output data range 00 to FF */
#define COM15_FMT_RGB_NORMAL 0x00 /* Normal RGB normal output */
#define COM15_FMT_RGB565 0x10 /* Normal RGB 565 output */
#define COM15_FMT_RGB555 0x30 /* Normal RGB 555 output */
#define COM16 0x41 /* Common Control 16 */
#define COM16_EDGE_EN 0x20 /* Enable edge enhancement threshold auto-adjustment */
#define COM16_DENOISE_EN 0x10 /* De-noise threshold auto-adjustment */
#define COM16_AWB_GAIN_EN 0x08 /* AWB gain enable */
#define COM16_COLOR_MTX_EN 0x02 /* Color matrix coefficient double option */
#define COM17 0x42 /* Common Control 17 */
#define COM17_AEC_FULL 0x00 /* AEC evaluate full window */
#define COM17_AEC_1_2 0x40 /* AEC evaluate 1/2 window */
#define COM17_AEC_1_4 0x80 /* AEC evaluate 1/4 window */
#define COM17_AEC_2_3 0xC0 /* AEC evaluate 2/3 window */
#define COM17_DSP_CBAR_EN 0x08 /* DSP color bar enable */
#define AWBC1 0x43 /* Reserved */
#define AWBC2 0x44 /* Reserved */
#define AWBC3 0x45 /* Reserved */
#define AWBC4 0x46 /* Reserved */
#define AWBC5 0x47 /* Reserved */
#define AWBC6 0x48 /* Reserved */
#define REG4B 0x4B /* REG4B */
#define REG4B_UV_AVG_EN 0x01 /* UV average enable */
#define DNSTH 0x4C /* De-noise Threshold*/
#define MTX1 0x4F /* Matrix Coefficient 1 */
#define MTX2 0x50 /* Matrix Coefficient 2 */
#define MTX3 0x51 /* Matrix Coefficient 3 */
#define MTX4 0x52 /* Matrix Coefficient 4 */
#define MTX5 0x53 /* Matrix Coefficient 5 */
#define MTX6 0x54 /* Matrix Coefficient 6 */
#define BRIGHTNESS 0x55 /* Brightness Control */
#define CONTRAST 0x56 /* Contrast Control */
#define CONTRAST_CENTER 0x57 /* Contrast Center */
#define MTXS 0x58 /* Matrix Coefficient Sign for coefficient 5 to 0*/
#define LCC1 0x62 /* Lens Correction Option 1 */
#define LCC2 0x63 /* Lens Correction Option 2 */
#define LCC3 0x64 /* Lens Correction Option 3 */
#define LCC4 0x65 /* Lens Correction Option 4 */
#define LCC5 0x66 /* Lens Correction Control */
#define LCC5_LC_EN 0x01 /* Lens Correction Enable */
#define LCC5_LC_CTRL 0x04 /* Lens correction control select */
#define MANU 0x67 /* Manual U Value (effective only when register TSLB[4] is high) */
#define MANV 0x68 /* Manual V Value (effective only when register TSLB[4] is high) */
#define GFIX 0x69 /* Fix Gain Control */
#define GGAIN 0x6A /* G Channel AWB Gain */
#define DBLV 0x6B /* PLL control */
#define DBLV_PLL_BYPASS 0x00 /* Bypass PLL */
#define DBLV_PLL_4x 0x40 /* Input clock 4x */
#define DBLV_PLL_6x 0x80 /* Input clock 8x */
#define DBLV_PLL_8x 0xC0 /* Input clock 16x */
#define DBLV_REG_BYPASS 0x10 /* Bypass internal regulator */
#define AWBCTR3 0x6C /* AWB Control 3 */
#define AWBCTR2 0x6D /* AWB Control 2 */
#define AWBCTR1 0x6E /* AWB Control 1 */
#define AWBCTR0 0x6F /* AWB Control 0 */
#define SCALING_XSC 0x70 /* Test Pattern[0] */
#define SCALING_YSC 0x71 /* Test Pattern[1] */
#define SCALING_DCWCTR 0x72 /* DCW control parameter */
#define SCALING_PCLK_DIV 0x73 /* Clock divider control for DSP.*/
#define SCALING_PCLK_DIV_BYPASS 0x08 /* Bypass clock divider for DSP scale control */
#define SCALING_PCLK_DIV_1 0x00 /* Divided by 1 */
#define SCALING_PCLK_DIV_2 0x01 /* Divided by 2 */
#define SCALING_PCLK_DIV_4 0x02 /* Divided by 4 */
#define SCALING_PCLK_DIV_8 0x03 /* Divided by 8 */
#define SCALING_PCLK_DIV_16 0x04 /* Divided by 16 */
#define REG74 0x74 /* REG74 */
#define REG74_DGAIN_EN 0x10 /* Digital gain control by REG74[1:0] */
#define REG74_DGAIN_BYPASS 0x00 /* Bypass */
#define REG74_DGAIN_1X 0x01 /* 1x */
#define REG74_DGAIN_2X 0x02 /* 2x */
#define REG74_DGAIN_4X 0x03 /* 4x */
#define REG75 0x75 /* REG75 */
#define REG75_EDGE_LOWER 0x1F /* Edge enhancement lower limit */
#define REG76 0x76 /* REG76 */
#define REG76_WHITE_PIX_CORR 0x80 /* White pixel correction enable */
#define REG76_BLACK_PIX_CORR 0x40 /* Black pixel correction enable */
#define REG76_EDGE_HIGHER 0x1F /* Edge enhancement higher limit */
#define REG77 0x77 /* Offset, de-noise range control */
#define SLOP 0x7A /* Gamma Curve Highest Segment Slope */
#define GAM1 0x7B /* Gamma Curve 1st Segment Input End Point 0x04 Output Value */
#define GAM2 0x7C /* Gamma Curve 2nd Segment Input End Point 0x08 Output Value */
#define GAM3 0x7D /* Gamma Curve 3rd Segment Input End Point 0x10 Output Value */
#define GAM4 0x7E /* Gamma Curve 4th Segment Input End Point 0x20 Output Value */
#define GAM5 0x7F /* Gamma Curve 5th Segment Input End Point 0x28 Output Value */
#define GAM6 0x80 /* Gamma Curve 6th Segment Input End Point 0x30 Output Value */
#define GAM7 0x81 /* Gamma Curve 7th Segment Input End Point 0x38 Output Value */
#define GAM8 0x82 /* Gamma Curve 8th Segment Input End Point 0x40 Output Value */
#define GAM9 0x83 /* Gamma Curve 9th Segment Input Enpd Point 0x48 Output Value */
#define GAM10 0x84 /* Gamma Curve 10th Segment Input End Point 0x50 Output Value */
#define GAM11 0x85 /* Gamma Curve 11th Segment Input End Point 0x60 Output Value */
#define GAM12 0x86 /* Gamma Curve 12th Segment Input End Point 0x70 Output Value */
#define GAM13 0x87 /* Gamma Curve 13th Segment Input End Point 0x90 Output Value */
#define GAM14 0x88 /* Gamma Curve 14th Segment Input End Point 0xB0 Output Value */
#define GAM15 0x89 /* Gamma Curve 15th Segment Input End Point 0xD0 Output Value */
#define RGB444 0x8C /* REG444 */
#define RGB444_RGB444_EN 0x02 /* RGB444 enable, effective only when COM15[4] is high */
#define RGB444_RGB444_FMT 0x01 /* RGB444 word format. 0 = xR GB 1 = RG Bx */
#define DM_LNL 0x92 /* Dummy Line low 8 bits */
#define DM_LNH 0x93 /* Dummy Line high 8 bits */
#define LCC6 0x94 /* RW Lens Correction Option 6 (effective only when LCC5[2] is high) */
#define LCC7 0x95 /* RW Lens Correction Option 7 (effective only when LCC5[2] is high) */
#define BD50ST 0x9D /* Hz Banding Filter Value (effective only when COM8[5] is high and COM11[3] is high) */
#define BD60ST 0x9E /* Hz Banding Filter Value (effective only when COM8[5] is high and COM11[3] is low) */
#define HAECC1 0x9F /* Histogram-based AEC/AGC Control 1 */
#define HAECC2 0xA0 /* Histogram-based AEC/AGC Control 2 */
#define SCALING_PCLK 0xA2 /* Pixel Clock Delay */
#define SCALING_PCLK_DELAY 0x7F /* Scaling output delay */
#define NT_CTRL 0xA4 /* Auto frame rate adjustment control */
#define NT_CTRL_AFR_HALF 0x08 /* Reduce frame rate by half */
#define NT_CTRL_AFR_PT_2X 0x00 /* Insert dummy row at 2x gain */
#define NT_CTRL_AFR_PT_4X 0x01 /* Insert dummy row at 4x gain */
#define NT_CTRL_AFR_PT_8X 0x02 /* Insert dummy row at 8x gain */
#define BD50MAX 0xA5 /* 50Hz Banding Step Limit */
#define HAECC3 0xA6 /* Histogram-based AEC/AGC Control 3 */
#define HAECC4 0xA7 /* Histogram-based AEC/AGC Control 4 */
#define HAECC5 0xA8 /* Histogram-based AEC/AGC Control 5 */
#define HAECC6 0xA9 /* Histogram-based AEC/AGC Control 6 */
#define HAECC7 0xAA /* AEC algorithm selection */
#define HAECC7_AEC_AVG 0x00 /* Average-based AEC algorithm */
#define HAECC7_AEC_HIST 0x80 /* Histogram-based AEC algorithm */
#define BD60MAX 0xAB /* 60Hz Banding Step Limit */
#define STR_OPT 0xAC /* Strobe Control */
#define STR_OPT_EN 0x80 /* Strobe Enable */
#define STR_OPT_CTRL 0x40 /* R/G/B gain controlled by STR_R (0xAD) STR_G (0xAE) STR_B (0xAF) for LED output frame */
#define STR_OPT_XENON_1ROW 0x00 /* Xenon mode option 1 row */
#define STR_OPT_XENON_2ROW 0x10 /* Xenon mode option 2 rows */
#define STR_OPT_XENON_3ROW 0x20 /* Xenon mode option 3 rows */
#define STR_OPT_XENON_4ROW 0x30 /* Xenon mode option 4 rows */
#define STR_OPT_MODE_XENON 0x00 /* Mode select */
#define STR_OPT_MODE_LED1 0x01 /* Mode select */
#define STR_OPT_MODE_LED2 0x02 /* Mode select */
#define STR_R 0xAD /* R Gain for LED Output Frame */
#define STR_G 0xAE /* G Gain for LED Output Frame */
#define STR_B 0xAF /* B Gain for LED Output Frame */
#define ABLC1 0xB1 /* ABLC Control */
#define ABLC1_EN 0x04 /* Enable ABLC function */
#define THL_ST 0xB3 /* ABLC Target */
#define AD_CHB 0xBE /* Blue Channel Black Level Compensation */
#define AD_CHR 0xBF /* Red Channel Black Level Compensation */
#define AD_CHGB 0xC0 /* Gb Channel Black Level Compensation */
#define AD_CHGR 0xC1 /* Gr Channel Black Level Compensation */
#define SATCTR 0xC9 /* UV Saturation Control */
#endif //__REG_REGS_H__

View File

@ -33,7 +33,7 @@
#include "omv_i2c.h"
#include "omv_csi.h"
#include "ov7690.h"
#include "ov7690_regs.h"
#include "sensor_config.h"
#include "py/mphal.h"
static const uint8_t default_regs[][2] = {

View File

@ -21,10 +21,43 @@
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*
* OV7690 driver.
* OV7690 register definitions.
*/
#ifndef __OV7690_H__
#define __OV7690_H__
#define OMV_OV7690_CLK_FREQ 24000000
int ov7690_init(omv_csi_t *csi);
#endif // __OV7690_H__
#ifndef __REG_REGS_H__
#define __REG_REGS_H__
#define GAIN 0x00
#define BGAIN 0x01
#define RGAIN 0x02
#define GGAIN 0x03
#define REG0C 0x0C
#define REG0E 0x0E
#define AECH 0x0F
#define AECL 0x10
#define CLKRC 0x11
#define REG12 0x12
#define REG13 0x13
#define REG14 0x14
#define REG15 0x15
#define REG19 0x19
#define PLL 0x29
#define REG3E 0x3E
#define REG82 0x82
#define LCC0 0x85
#define LCC1 0x86
#define LCC4 0x89
#define LCC5 0x8A
#define LCC6 0x8B
#define REGC8 0xC8
#define REGC9 0xC9
#define REGCA 0xCA
#define REGCB 0xCB
#define REGCC 0xCC
#define REGCD 0xCD
#define REGCE 0xCE
#define REGCF 0xCF
#define REGD2 0xD2
#define REGD8 0xD8
#define REGD9 0xD9
#endif //__REG_REGS_H__

View File

@ -1,63 +0,0 @@
/*
* SPDX-License-Identifier: MIT
*
* Copyright (C) 2013-2024 OpenMV, LLC.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*
* OV7690 register definitions.
*/
#ifndef __REG_REGS_H__
#define __REG_REGS_H__
#define GAIN 0x00
#define BGAIN 0x01
#define RGAIN 0x02
#define GGAIN 0x03
#define REG0C 0x0C
#define REG0E 0x0E
#define AECH 0x0F
#define AECL 0x10
#define CLKRC 0x11
#define REG12 0x12
#define REG13 0x13
#define REG14 0x14
#define REG15 0x15
#define REG19 0x19
#define PLL 0x29
#define REG3E 0x3E
#define REG82 0x82
#define LCC0 0x85
#define LCC1 0x86
#define LCC4 0x89
#define LCC5 0x8A
#define LCC6 0x8B
#define REGC8 0xC8
#define REGC9 0xC9
#define REGCA 0xCA
#define REGCB 0xCB
#define REGCC 0xCC
#define REGCD 0xCD
#define REGCE 0xCE
#define REGCF 0xCF
#define REGD2 0xD2
#define REGD8 0xD8
#define REGD9 0xD9
#endif //__REG_REGS_H__

View File

@ -33,7 +33,6 @@
#include "omv_i2c.h"
#include "omv_csi.h"
#include "ov7725.h"
#include "ov7725_regs.h"
#include "py/mphal.h"
static const uint8_t default_regs[][2] = {

View File

@ -21,9 +21,344 @@
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*
* OV7725 driver.
* OV7725 register definitions.
*/
#ifndef __OV7725_H__
#define __OV7725_H__
int ov7725_init(omv_csi_t *csi);
#endif // __OV7725_H__
#ifndef __REG_REGS_H__
#define __REG_REGS_H__
#define GAIN 0x00 /* AGC - Gain control gain setting */
#define BLUE 0x01 /* AWB - Blue channel gain setting */
#define RED 0x02 /* AWB - Red channel gain setting */
#define GREEN 0x03 /* AWB - Green channel gain setting */
#define BAVG 0x05 /* U/B Average Level */
#define GAVG 0x06 /* Y/Gb Average Level */
#define RAVG 0x07 /* V/R Average Level */
#define AECH 0x08 /* Exposure Value - AEC MSBs */
#define COM2 0x09 /* Common Control 2 */
#define COM2_SOFT_SLEEP 0x10 /* Soft sleep mode */
#define COM2_OUT_DRIVE_1x 0x00 /* Output drive capability 1x */
#define COM2_OUT_DRIVE_2x 0x01 /* Output drive capability 2x */
#define COM2_OUT_DRIVE_3x 0x02 /* Output drive capability 3x */
#define COM2_OUT_DRIVE_4x 0x03 /* Output drive capability 4x */
#define PID 0x0A /* Product ID Number MSB */
#define VER 0x0B /* Product ID Number LSB */
#define COM3 0x0C /* Common Control 3 */
#define COM3_VFLIP 0x80 /* Vertical flip image ON/OFF selection */
#define COM3_MIRROR 0x40 /* Horizontal mirror image ON/OFF selection */
#define COM3_SWAP_BR 0x20 /* Swap B/R output sequence in RGB output mode */
#define COM3_SWAP_YUV 0x10 /* Swap Y/UV output sequence in YUV output mode */
#define COM3_SWAP_MSB 0x08 /* Swap output MSB/LSB */
#define COM3_TRI_CLOCK 0x04 /* Tri-state option for output clock at power-down period */
#define COM3_TRI_DATA 0x02 /* Tri-state option for output data at power-down period */
#define COM3_COLOR_BAR 0x01 /* Sensor color bar test pattern output enable */
#define COM3_SET_CBAR(r, x) ((r & 0xFE) | ((x & 1) << 0))
#define COM3_SET_MIRROR(r, x) ((r & 0xBF) | ((x & 1) << 6))
#define COM3_SET_FLIP(r, x) ((r & 0x7F) | ((x & 1) << 7))
#define COM3_GET_CBAR(r) ((r >> 0) & 1)
#define COM3_GET_MIRROR(r) ((r >> 6) & 1)
#define COM3_GET_FLIP(r) ((r >> 7) & 1)
#define COM4 0x0D /* Common Control 4 */
#define COM4_PLL_BYPASS 0x00 /* Bypass PLL */
#define COM4_PLL_4x 0x40 /* PLL frequency 4x */
#define COM4_PLL_6x 0x80 /* PLL frequency 6x */
#define COM4_PLL_8x 0xC0 /* PLL frequency 8x */
#define COM4_AEC_FULL 0x00 /* AEC evaluate full window */
#define COM4_AEC_1_2 0x10 /* AEC evaluate 1/2 window */
#define COM4_AEC_1_4 0x20 /* AEC evaluate 1/4 window */
#define COM4_AEC_2_3 0x30 /* AEC evaluate 2/3 window */
#define COM4_GET_PLL(r) (r & 0xC0)
#define COM5 0x0E /* Common Control 5 */
#define COM5_AFR 0x80 /* Auto frame rate control ON/OFF selection (night mode) */
#define COM5_AFR_SPEED 0x40 /* Auto frame rate control speed selection */
#define COM5_AFR_0 0x00 /* No reduction of frame rate */
#define COM5_AFR_1_2 0x10 /* Max reduction to 1/2 frame rate */
#define COM5_AFR_1_4 0x20 /* Max reduction to 1/4 frame rate */
#define COM5_AFR_1_8 0x30 /* Max reduction to 1/8 frame rate */
#define COM5_AFR_4x 0x04 /* Add frame when AGC reaches 4x gain */
#define COM5_AFR_8x 0x08 /* Add frame when AGC reaches 8x gain */
#define COM5_AFR_16x 0x0c /* Add frame when AGC reaches 16x gain */
#define COM5_AEC_NO_LIMIT 0x01 /* No limit to AEC increase step */
#define COM5_SET_AFR(r, x) ((r & 0x7F) | ((x & 0x1) << 7))
#define COM6 0x0F /* Common Control 6 */
#define COM6_AUTO_WINDOW 0x01 /* Auto window setting ON/OFF selection when format changes */
#define AEC 0x10 /* AEC[7:0] (see register AECH for AEC[15:8]) */
#define CLKRC 0x11 /* Internal Clock */
#define CLKRC_NO_PRESCALE 0x40 /* Use external clock directly */
#define CLKRC_PRESCALER 0x3F /* Internal clock pre-scaler */
#define COM7 0x12 /* Common Control 7 */
#define COM7_RESET 0x80 /* SCCB Register Reset */
#define COM7_RES_VGA 0x00 /* Resolution VGA */
#define COM7_RES_QVGA 0x40 /* Resolution QVGA */
#define COM7_BT656 0x20 /* BT.656 protocol ON/OFF */
#define COM7_SENSOR_RAW 0x10 /* Sensor RAW */
#define COM7_FMT_GBR422 0x00 /* RGB output format GBR422 */
#define COM7_FMT_RGB565 0x04 /* RGB output format RGB565 */
#define COM7_FMT_RGB555 0x08 /* RGB output format RGB555 */
#define COM7_FMT_RGB444 0x0C /* RGB output format RGB444 */
#define COM7_FMT_YUV 0x00 /* Output format YUV */
#define COM7_FMT_P_BAYER 0x01 /* Output format Processed Bayer RAW */
#define COM7_FMT_RGB 0x02 /* Output format RGB */
#define COM7_FMT_R_BAYER 0x03 /* Output format Bayer RAW */
#define COM7_SET_FMT(r, x) ((r & 0xFC) | ((x & 0x3) << 0))
#define COM7_SET_RES(r, x) ((r & 0xBF) | (x))
#define COM7_GET_FMT(r) (r & 0x03)
#define COM8 0x13 /* Common Control 8 */
#define COM8_FAST_AUTO 0x80 /* Enable fast AGC/AEC algorithm */
#define COM8_STEP_VSYNC 0x00 /* AEC - Step size limited to vertical blank */
#define COM8_STEP_UNLIMIT 0x40 /* AEC - Step size unlimited step size */
#define COM8_BANDF_EN 0x20 /* Banding filter ON/OFF */
#define COM8_AEC_BANDF 0x10 /* Enable AEC below banding value */
#define COM8_AEC_FINE_EN 0x08 /* Fine AEC ON/OFF control */
#define COM8_AGC_EN 0x04 /* AGC Enable */
#define COM8_AWB_EN 0x02 /* AWB Enable */
#define COM8_AEC_EN 0x01 /* AEC Enable */
#define COM8_SET_AGC(r, x) ((r & 0xFB) | ((x & 0x1) << 2))
#define COM8_SET_AWB(r, x) ((r & 0xFD) | ((x & 0x1) << 1))
#define COM8_SET_AEC(r, x) ((r & 0x7E) | ((x & 0x1) << 7) | ((x & 0x1) << 0))
#define COM9 0x14 /* Common Control 9 */
#define COM9_HISTO_AVG 0x80 /* Histogram or average based AEC/AGC selection */
#define COM9_AGC_GAIN_2x 0x00 /* Automatic Gain Ceiling 2x */
#define COM9_AGC_GAIN_4x 0x10 /* Automatic Gain Ceiling 4x */
#define COM9_AGC_GAIN_8x 0x20 /* Automatic Gain Ceiling 8x */
#define COM9_AGC_GAIN_16x 0x30 /* Automatic Gain Ceiling 16x */
#define COM9_AGC_GAIN_32x 0x40 /* Automatic Gain Ceiling 32x */
#define COM9_DROP_VSYNC 0x04 /* Drop VSYNC output of corrupt frame */
#define COM9_DROP_HREF 0x02 /* Drop HREF output of corrupt frame */
#define COM9_SET_AGC(r, x) ((r & 0x8F) | ((x & 0x07) << 4))
#define COM10 0x15 /* Common Control 10 */
#define COM10_NEGATIVE 0x80 /* Output negative data */
#define COM10_HSYNC_EN 0x40 /* HREF changes to HSYNC */
#define COM10_PCLK_FREE 0x00 /* PCLK output option: free running PCLK */
#define COM10_PCLK_MASK 0x20 /* PCLK output option: masked during horizontal blank */
#define COM10_PCLK_REV 0x10 /* PCLK reverse */
#define COM10_HREF_REV 0x08 /* HREF reverse */
#define COM10_VSYNC_FALLING 0x00 /* VSYNC changes on falling edge of PCLK */
#define COM10_VSYNC_RISING 0x04 /* VSYNC changes on rising edge of PCLK */
#define COM10_VSYNC_NEG 0x02 /* VSYNC negative */
#define COM10_OUT_RANGE_8 0x01 /* Output data range: Full range */
#define COM10_OUT_RANGE_10 0x00 /* Output data range: Data from [10] to [F0] (8 MSBs) */
#define REG16 0x16 /* Register 16 */
#define REG16_BIT_SHIFT 0x80 /* Bit shift test pattern options */
#define HSTART 0x17 /* Horizontal Frame (HREF column) Start 8 MSBs (2 LSBs are at HREF[5:4]) */
#define HSIZE 0x18 /* Horizontal Sensor Size (2 LSBs are at HREF[1:0]) */
#define VSTART 0x19 /* Vertical Frame (row) Start 8 MSBs (1 LSB is at HREF[6]) */
#define VSIZE 0x1A /* Vertical Sensor Size (1 LSB is at HREF[2]) */
#define PSHFT 0x1B /* Data Format - Pixel Delay Select */
#define MIDH 0x1C /* Manufacturer ID Byte - High */
#define MIDL 0x1D /* Manufacturer ID Byte - Low */
#define LAEC 0x1F /* Fine AEC Value - defines exposure value less than one row period */
#define COM11 0x20 /* Common Control 11 */
#define COM11_SNGL_FRAME_EN 0x02 /* Single frame ON/OFF selection */
#define COM11_SNGL_XFR_TRIG 0x01 /* Single frame transfer trigger */
#define BDBASE 0x22 /* Banding Filter Minimum AEC Value */
#define BDSTEP 0x23 /* Banding Filter Maximum Step */
#define AEW 0x24 /* AGC/AEC - Stable Operating Region (Upper Limit) */
#define AEB 0x25 /* AGC/AEC - Stable Operating Region (Lower Limit) */
#define VPT 0x26 /* AGC/AEC Fast Mode Operating Region */
#define REG28 0x28 /* Selection on the number of dummy rows, N */
#define HOUTSIZE 0x29 /* Horizontal Data Output Size MSBs (2 LSBs at register EXHCH[1:0]) */
#define EXHCH 0x2A /* Dummy Pixel Insert MSB */
#define EXHCL 0x2B /* Dummy Pixel Insert LSB */
#define VOUTSIZE 0x2C /* Vertical Data Output Size MSBs (LSB at register EXHCH[2]) */
#define ADVFL 0x2D /* LSB of Insert Dummy Rows in Vertical Sync (1 bit equals 1 row) */
#define ADVFH 0x2E /* MSB of Insert Dummy Rows in Vertical Sync */
#define YAVE 0x2F /* Y/G Channel Average Value */
#define LUMHTH 0x30 /* Histogram AEC/AGC Luminance High Level Threshold */
#define LUMLTH 0x31 /* Histogram AEC/AGC Luminance Low Level Threshold */
#define HREF 0x32 /* Image Start and Size Control */
#define DM_LNL 0x33 /* Dummy Row Low 8 Bits */
#define DM_LNH 0x34 /* Dummy Row High 8 Bits */
#define ADOFF_B 0x35 /* AD Offset Compensation Value for B Channel */
#define ADOFF_R 0x36 /* AD Offset Compensation Value for R Channel */
#define ADOFF_GB 0x37 /* AD Offset Compensation Value for GB Channel */
#define ADOFF_GR 0x38 /* AD Offset Compensation Value for GR Channel */
#define OFF_B 0x39 /* AD Offset Compensation Value for B Channel */
#define OFF_R 0x3A /* AD Offset Compensation Value for R Channel */
#define OFF_GB 0x3B /* AD Offset Compensation Value for GB Channel */
#define OFF_GR 0x3C /* AD Offset Compensation Value for GR Channel */
#define COM12 0x3D /* DC offset compensation for analog process */
#define COM13 0x3E /* Common Control 13 */
#define COM13_BLC_EN 0x80 /* BLC enable */
#define COM13_ADC_EN 0x40 /* ADC channel BLC ON/OFF control */
#define COM13_ANALOG_BLC 0x20 /* Analog processing channel BLC ON/OFF control */
#define COM13_ABLC_GAIN_EN 0x04 /* ABLC gain trigger enable */
#define COM13_SET_BLC(r, x) ((r & 0x7F) | ((x & 0x1) << 7))
#define COM14 0x3F /* Common Control 14 */
#define COM15 0x40 /* Common Control 15 */
#define COM16 0x41 /* Common Control 16 */
#define TGT_B 0x42 /* BLC Blue Channel Target Value */
#define TGT_R 0x43 /* BLC Red Channel Target Value */
#define TGT_GB 0x44 /* BLC Gb Channel Target Value */
#define TGT_GR 0x45 /* BLC Gr Channel Target Value */
#define LC_CTR 0x46 /* Lens Correction Control */
#define LC_CTR_RGB_COMP_1 0x00 /* R, G, and B channel compensation coefficient is set by LC_COEF (0x49) */
#define LC_CTR_RGB_COMP_3 0x04 /* R, G, and B channel compensation coefficient is set by registers
LC_COEFB (0x4B), LC_COEF (0x49), and LC_COEFR (0x4C), respectively */
#define LC_CTR_EN 0x01 /* Lens correction enable */
#define LC_XC 0x47 /* X Coordinate of Lens Correction Center Relative to Array Center */
#define LC_YC 0x48 /* Y Coordinate of Lens Correction Center Relative to Array Center */
#define LC_COEF 0x49 /* Lens Correction Coefficient */
#define LC_RADI 0x4A /* Lens Correction Radius */
#define LC_COEFB 0x4B /* Lens Correction B Channel Compensation Coefficient */
#define LC_COEFR 0x4C /* Lens Correction R Channel Compensation Coefficient */
#define FIXGAIN 0x4D /* Analog Fix Gain Amplifier */
#define AREF0 0x4E /* Sensor Reference Control */
#define AREF1 0x4F /* Sensor Reference Current Control */
#define AREF2 0x50 /* Analog Reference Control */
#define AREF3 0x51 /* ADC Reference Control */
#define AREF4 0x52 /* ADC Reference Control */
#define AREF5 0x53 /* ADC Reference Control */
#define AREF6 0x54 /* Analog Reference Control */
#define AREF7 0x55 /* Analog Reference Control */
#define UFIX 0x60 /* U Channel Fixed Value Output */
#define VFIX 0x61 /* V Channel Fixed Value Output */
#define AWBB_BLK 0x62 /* AWB Option for Advanced AWB */
#define AWB_CTRL0 0x63 /* AWB Control Byte 0 */
#define AWB_CTRL0_GAIN_EN 0x80 /* AWB gain enable */
#define AWB_CTRL0_CALC_EN 0x40 /* AWB calculate enable */
#define AWB_CTRL0_WBC_MASK 0x0F /* WBC threshold 2 */
#define DSP_CTRL1 0x64 /* DSP Control Byte 1 */
#define DSP_CTRL1_FIFO_EN 0x80 /* FIFO enable/disable selection */
#define DSP_CTRL1_UV_EN 0x40 /* UV adjust function ON/OFF selection */
#define DSP_CTRL1_SDE_EN 0x20 /* SDE enable */
#define DSP_CTRL1_MTRX_EN 0x10 /* Color matrix ON/OFF selection */
#define DSP_CTRL1_INTRP_EN 0x08 /* Interpolation ON/OFF selection */
#define DSP_CTRL1_GAMMA_EN 0x04 /* Gamma function ON/OFF selection */
#define DSP_CTRL1_BLACK_EN 0x02 /* Black defect auto correction ON/OFF */
#define DSP_CTRL1_WHITE_EN 0x01 /* White defect auto correction ON/OFF */
#define DSP_CTRL2 0x65 /* DSP Control Byte 2 */
#define DSP_CTRL2_VDCW_EN 0x08 /* Vertical DCW enable */
#define DSP_CTRL2_HDCW_EN 0x04 /* Horizontal DCW enable */
#define DSP_CTRL2_VZOOM_EN 0x02 /* Vertical zoom out enable */
#define DSP_CTRL2_HZOOM_EN 0x01 /* Horizontal zoom out enable */
#define DSP_CTRL3 0x66 /* DSP Control Byte 3 */
#define DSP_CTRL3_UV_EN 0x80 /* UV output sequence option */
#define DSP_CTRL3_CBAR_EN 0x20 /* DSP color bar ON/OFF selection */
#define DSP_CTRL3_FIFO_EN 0x08 /* FIFO power down ON/OFF selection */
#define DSP_CTRL3_SCAL1_PWDN 0x04 /* Scaling module power down control 1 */
#define DSP_CTRL3_SCAL2_PWDN 0x02 /* Scaling module power down control 2 */
#define DSP_CTRL3_INTRP_PWDN 0x01 /* Interpolation module power down control */
#define DSP_CTRL3_SET_CBAR(r, x) ((r & 0xDF) | ((x & 1) << 5))
#define DSP_CTRL4 0x67 /* DSP Control Byte 4 */
#define DSP_CTRL4_YUV_RGB 0x00 /* Output selection YUV or RGB */
#define DSP_CTRL4_RAW8 0x02 /* Output selection RAW8 */
#define DSP_CTRL4_RAW10 0x03 /* Output selection RAW10 */
#define AWB_BIAS 0x68 /* AWB BLC Level Clip */
#define AWB_CTRL1 0x69 /* AWB Control 1 */
#define AWB_CTRL2 0x6A /* AWB Control 2 */
#define AWB_CTRL3 0x6B /* AWB Control 3 */
#define AWB_CTRL3_ADVANCED 0x80 /* AWB mode select - Advanced AWB */
#define AWB_CTRL3_SIMPLE 0x00 /* AWB mode select - Simple AWB */
#define AWB_CTRL4 0x6C /* AWB Control 4 */
#define AWB_CTRL5 0x6D /* AWB Control 5 */
#define AWB_CTRL6 0x6E /* AWB Control 6 */
#define AWB_CTRL7 0x6F /* AWB Control 7 */
#define AWB_CTRL8 0x70 /* AWB Control 8 */
#define AWB_CTRL9 0x71 /* AWB Control 9 */
#define AWB_CTRL10 0x72 /* AWB Control 10 */
#define AWB_CTRL11 0x73 /* AWB Control 11 */
#define AWB_CTRL12 0x74 /* AWB Control 12 */
#define AWB_CTRL13 0x75 /* AWB Control 13 */
#define AWB_CTRL14 0x76 /* AWB Control 14 */
#define AWB_CTRL15 0x77 /* AWB Control 15 */
#define AWB_CTRL16 0x78 /* AWB Control 16 */
#define AWB_CTRL17 0x79 /* AWB Control 17 */
#define AWB_CTRL18 0x7A /* AWB Control 18 */
#define AWB_CTRL19 0x7B /* AWB Control 19 */
#define AWB_CTRL20 0x7C /* AWB Control 20 */
#define AWB_CTRL21 0x7D /* AWB Control 21 */
#define GAM1 0x7E /* Gamma Curve 1st Segment Input End Point 0x04 Output Value */
#define GAM2 0x7F /* Gamma Curve 2nd Segment Input End Point 0x08 Output Value */
#define GAM3 0x80 /* Gamma Curve 3rd Segment Input End Point 0x10 Output Value */
#define GAM4 0x81 /* Gamma Curve 4th Segment Input End Point 0x20 Output Value */
#define GAM5 0x82 /* Gamma Curve 5th Segment Input End Point 0x28 Output Value */
#define GAM6 0x83 /* Gamma Curve 6th Segment Input End Point 0x30 Output Value */
#define GAM7 0x84 /* Gamma Curve 7th Segment Input End Point 0x38 Output Value */
#define GAM8 0x85 /* Gamma Curve 8th Segment Input End Point 0x40 Output Value */
#define GAM9 0x86 /* Gamma Curve 9th Segment Input Enpd Point 0x48 Output Value */
#define GAM10 0x87 /* Gamma Curve 10th Segment Input End Point 0x50 Output Value */
#define GAM11 0x88 /* Gamma Curve 11th Segment Input End Point 0x60 Output Value */
#define GAM12 0x89 /* Gamma Curve 12th Segment Input End Point 0x70 Output Value */
#define GAM13 0x8A /* Gamma Curve 13th Segment Input End Point 0x90 Output Value */
#define GAM14 0x8B /* Gamma Curve 14th Segment Input End Point 0xB0 Output Value */
#define GAM15 0x8C /* Gamma Curve 15th Segment Input End Point 0xD0 Output Value */
#define SLOP 0x8D /* Gamma Curve Highest Segment Slope */
#define DNSTH 0x8E /* De-noise Threshold */
#define EDGE0 0x8F /* Edge Enhancement Strength Control */
#define EDGE1 0x90 /* Edge Enhancement Threshold Control */
#define DNSOFF 0x91 /* Auto De-noise Threshold Control */
#define EDGE2 0x92 /* Edge Enhancement Strength Upper Limit */
#define EDGE3 0x93 /* Edge Enhancement Strength Upper Limit */
#define MTX1 0x94 /* Matrix Coefficient 1 */
#define MTX2 0x95 /* Matrix Coefficient 2 */
#define MTX3 0x96 /* Matrix Coefficient 3 */
#define MTX4 0x97 /* Matrix Coefficient 4 */
#define MTX5 0x98 /* Matrix Coefficient 5 */
#define MTX6 0x99 /* Matrix Coefficient 6 */
#define MTX_CTRL 0x9A /* Matrix Control */
#define MTX_CTRL_DBL_EN 0x80 /* Matrix double ON/OFF selection */
#define BRIGHTNESS 0x9B /* Brightness Control */
#define CONTRAST 0x9C /* Contrast Gain */
#define UVADJ0 0x9E /* Auto UV Adjust Control 0 */
#define UVADJ1 0x9F /* Auto UV Adjust Control 1 */
#define SCAL0 0xA0 /* DCW Ratio Control */
#define SCAL1 0xA1 /* Horizontal Zoom Out Control */
#define SCAL2 0xA2 /* Vertical Zoom Out Control */
#define FIFODLYM 0xA3 /* FIFO Manual Mode Delay Control */
#define FIFODLYA 0xA4 /* FIFO Auto Mode Delay Control */
#define SDE 0xA6 /* Special Digital Effect Control */
#define SDE_NEGATIVE_EN 0x40 /* Negative image enable */
#define SDE_GRAYSCALE_EN 0x20 /* Gray scale image enable */
#define SDE_V_FIXED_EN 0x10 /* V fixed value enable */
#define SDE_U_FIXED_EN 0x08 /* U fixed value enable */
#define SDE_CONT_BRIGHT_EN 0x04 /* Contrast/Brightness enable */
#define SDE_SATURATION_EN 0x02 /* Saturation enable */
#define SDE_HUE_EN 0x01 /* Hue enable */
#define USAT 0xA7 /* U Component Saturation Gain */
#define VSAT 0xA8 /* V Component Saturation Gain */
#define HUECOS 0xA9 /* Cosine value × 0x80 */
#define HUESIN 0xAA /* Sine value × 0x80 */
#define SIGN_BIT 0xAB /* Sign Bit for Hue and Brightness */
#define DSPAUTO 0xAC /* DSP Auto Function ON/OFF Control */
#define DSPAUTO_AWB_EN 0x80 /* AWB auto threshold control */
#define DSPAUTO_DENOISE_EN 0x40 /* De-noise auto threshold control */
#define DSPAUTO_EDGE_EN 0x20 /* Sharpness (edge enhancement) auto strength control */
#define DSPAUTO_UV_EN 0x10 /* UV adjust auto slope control */
#define DSPAUTO_SCAL0_EN 0x08 /* Auto scaling factor control (register SCAL0 (0xA0)) */
#define DSPAUTO_SCAL1_EN 0x04 /* Auto scaling factor control (registers SCAL1 (0xA1 and SCAL2 (0xA2)) */
#endif //__REG_REGS_H__

View File

@ -1,364 +0,0 @@
/*
* SPDX-License-Identifier: MIT
*
* Copyright (C) 2013-2024 OpenMV, LLC.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*
* OV7725 register definitions.
*/
#ifndef __REG_REGS_H__
#define __REG_REGS_H__
#define GAIN 0x00 /* AGC - Gain control gain setting */
#define BLUE 0x01 /* AWB - Blue channel gain setting */
#define RED 0x02 /* AWB - Red channel gain setting */
#define GREEN 0x03 /* AWB - Green channel gain setting */
#define BAVG 0x05 /* U/B Average Level */
#define GAVG 0x06 /* Y/Gb Average Level */
#define RAVG 0x07 /* V/R Average Level */
#define AECH 0x08 /* Exposure Value - AEC MSBs */
#define COM2 0x09 /* Common Control 2 */
#define COM2_SOFT_SLEEP 0x10 /* Soft sleep mode */
#define COM2_OUT_DRIVE_1x 0x00 /* Output drive capability 1x */
#define COM2_OUT_DRIVE_2x 0x01 /* Output drive capability 2x */
#define COM2_OUT_DRIVE_3x 0x02 /* Output drive capability 3x */
#define COM2_OUT_DRIVE_4x 0x03 /* Output drive capability 4x */
#define PID 0x0A /* Product ID Number MSB */
#define VER 0x0B /* Product ID Number LSB */
#define COM3 0x0C /* Common Control 3 */
#define COM3_VFLIP 0x80 /* Vertical flip image ON/OFF selection */
#define COM3_MIRROR 0x40 /* Horizontal mirror image ON/OFF selection */
#define COM3_SWAP_BR 0x20 /* Swap B/R output sequence in RGB output mode */
#define COM3_SWAP_YUV 0x10 /* Swap Y/UV output sequence in YUV output mode */
#define COM3_SWAP_MSB 0x08 /* Swap output MSB/LSB */
#define COM3_TRI_CLOCK 0x04 /* Tri-state option for output clock at power-down period */
#define COM3_TRI_DATA 0x02 /* Tri-state option for output data at power-down period */
#define COM3_COLOR_BAR 0x01 /* Sensor color bar test pattern output enable */
#define COM3_SET_CBAR(r, x) ((r & 0xFE) | ((x & 1) << 0))
#define COM3_SET_MIRROR(r, x) ((r & 0xBF) | ((x & 1) << 6))
#define COM3_SET_FLIP(r, x) ((r & 0x7F) | ((x & 1) << 7))
#define COM3_GET_CBAR(r) ((r >> 0) & 1)
#define COM3_GET_MIRROR(r) ((r >> 6) & 1)
#define COM3_GET_FLIP(r) ((r >> 7) & 1)
#define COM4 0x0D /* Common Control 4 */
#define COM4_PLL_BYPASS 0x00 /* Bypass PLL */
#define COM4_PLL_4x 0x40 /* PLL frequency 4x */
#define COM4_PLL_6x 0x80 /* PLL frequency 6x */
#define COM4_PLL_8x 0xC0 /* PLL frequency 8x */
#define COM4_AEC_FULL 0x00 /* AEC evaluate full window */
#define COM4_AEC_1_2 0x10 /* AEC evaluate 1/2 window */
#define COM4_AEC_1_4 0x20 /* AEC evaluate 1/4 window */
#define COM4_AEC_2_3 0x30 /* AEC evaluate 2/3 window */
#define COM4_GET_PLL(r) (r & 0xC0)
#define COM5 0x0E /* Common Control 5 */
#define COM5_AFR 0x80 /* Auto frame rate control ON/OFF selection (night mode) */
#define COM5_AFR_SPEED 0x40 /* Auto frame rate control speed selection */
#define COM5_AFR_0 0x00 /* No reduction of frame rate */
#define COM5_AFR_1_2 0x10 /* Max reduction to 1/2 frame rate */
#define COM5_AFR_1_4 0x20 /* Max reduction to 1/4 frame rate */
#define COM5_AFR_1_8 0x30 /* Max reduction to 1/8 frame rate */
#define COM5_AFR_4x 0x04 /* Add frame when AGC reaches 4x gain */
#define COM5_AFR_8x 0x08 /* Add frame when AGC reaches 8x gain */
#define COM5_AFR_16x 0x0c /* Add frame when AGC reaches 16x gain */
#define COM5_AEC_NO_LIMIT 0x01 /* No limit to AEC increase step */
#define COM5_SET_AFR(r, x) ((r & 0x7F) | ((x & 0x1) << 7))
#define COM6 0x0F /* Common Control 6 */
#define COM6_AUTO_WINDOW 0x01 /* Auto window setting ON/OFF selection when format changes */
#define AEC 0x10 /* AEC[7:0] (see register AECH for AEC[15:8]) */
#define CLKRC 0x11 /* Internal Clock */
#define CLKRC_NO_PRESCALE 0x40 /* Use external clock directly */
#define CLKRC_PRESCALER 0x3F /* Internal clock pre-scaler */
#define COM7 0x12 /* Common Control 7 */
#define COM7_RESET 0x80 /* SCCB Register Reset */
#define COM7_RES_VGA 0x00 /* Resolution VGA */
#define COM7_RES_QVGA 0x40 /* Resolution QVGA */
#define COM7_BT656 0x20 /* BT.656 protocol ON/OFF */
#define COM7_SENSOR_RAW 0x10 /* Sensor RAW */
#define COM7_FMT_GBR422 0x00 /* RGB output format GBR422 */
#define COM7_FMT_RGB565 0x04 /* RGB output format RGB565 */
#define COM7_FMT_RGB555 0x08 /* RGB output format RGB555 */
#define COM7_FMT_RGB444 0x0C /* RGB output format RGB444 */
#define COM7_FMT_YUV 0x00 /* Output format YUV */
#define COM7_FMT_P_BAYER 0x01 /* Output format Processed Bayer RAW */
#define COM7_FMT_RGB 0x02 /* Output format RGB */
#define COM7_FMT_R_BAYER 0x03 /* Output format Bayer RAW */
#define COM7_SET_FMT(r, x) ((r & 0xFC) | ((x & 0x3) << 0))
#define COM7_SET_RES(r, x) ((r & 0xBF) | (x))
#define COM7_GET_FMT(r) (r & 0x03)
#define COM8 0x13 /* Common Control 8 */
#define COM8_FAST_AUTO 0x80 /* Enable fast AGC/AEC algorithm */
#define COM8_STEP_VSYNC 0x00 /* AEC - Step size limited to vertical blank */
#define COM8_STEP_UNLIMIT 0x40 /* AEC - Step size unlimited step size */
#define COM8_BANDF_EN 0x20 /* Banding filter ON/OFF */
#define COM8_AEC_BANDF 0x10 /* Enable AEC below banding value */
#define COM8_AEC_FINE_EN 0x08 /* Fine AEC ON/OFF control */
#define COM8_AGC_EN 0x04 /* AGC Enable */
#define COM8_AWB_EN 0x02 /* AWB Enable */
#define COM8_AEC_EN 0x01 /* AEC Enable */
#define COM8_SET_AGC(r, x) ((r & 0xFB) | ((x & 0x1) << 2))
#define COM8_SET_AWB(r, x) ((r & 0xFD) | ((x & 0x1) << 1))
#define COM8_SET_AEC(r, x) ((r & 0x7E) | ((x & 0x1) << 7) | ((x & 0x1) << 0))
#define COM9 0x14 /* Common Control 9 */
#define COM9_HISTO_AVG 0x80 /* Histogram or average based AEC/AGC selection */
#define COM9_AGC_GAIN_2x 0x00 /* Automatic Gain Ceiling 2x */
#define COM9_AGC_GAIN_4x 0x10 /* Automatic Gain Ceiling 4x */
#define COM9_AGC_GAIN_8x 0x20 /* Automatic Gain Ceiling 8x */
#define COM9_AGC_GAIN_16x 0x30 /* Automatic Gain Ceiling 16x */
#define COM9_AGC_GAIN_32x 0x40 /* Automatic Gain Ceiling 32x */
#define COM9_DROP_VSYNC 0x04 /* Drop VSYNC output of corrupt frame */
#define COM9_DROP_HREF 0x02 /* Drop HREF output of corrupt frame */
#define COM9_SET_AGC(r, x) ((r & 0x8F) | ((x & 0x07) << 4))
#define COM10 0x15 /* Common Control 10 */
#define COM10_NEGATIVE 0x80 /* Output negative data */
#define COM10_HSYNC_EN 0x40 /* HREF changes to HSYNC */
#define COM10_PCLK_FREE 0x00 /* PCLK output option: free running PCLK */
#define COM10_PCLK_MASK 0x20 /* PCLK output option: masked during horizontal blank */
#define COM10_PCLK_REV 0x10 /* PCLK reverse */
#define COM10_HREF_REV 0x08 /* HREF reverse */
#define COM10_VSYNC_FALLING 0x00 /* VSYNC changes on falling edge of PCLK */
#define COM10_VSYNC_RISING 0x04 /* VSYNC changes on rising edge of PCLK */
#define COM10_VSYNC_NEG 0x02 /* VSYNC negative */
#define COM10_OUT_RANGE_8 0x01 /* Output data range: Full range */
#define COM10_OUT_RANGE_10 0x00 /* Output data range: Data from [10] to [F0] (8 MSBs) */
#define REG16 0x16 /* Register 16 */
#define REG16_BIT_SHIFT 0x80 /* Bit shift test pattern options */
#define HSTART 0x17 /* Horizontal Frame (HREF column) Start 8 MSBs (2 LSBs are at HREF[5:4]) */
#define HSIZE 0x18 /* Horizontal Sensor Size (2 LSBs are at HREF[1:0]) */
#define VSTART 0x19 /* Vertical Frame (row) Start 8 MSBs (1 LSB is at HREF[6]) */
#define VSIZE 0x1A /* Vertical Sensor Size (1 LSB is at HREF[2]) */
#define PSHFT 0x1B /* Data Format - Pixel Delay Select */
#define MIDH 0x1C /* Manufacturer ID Byte - High */
#define MIDL 0x1D /* Manufacturer ID Byte - Low */
#define LAEC 0x1F /* Fine AEC Value - defines exposure value less than one row period */
#define COM11 0x20 /* Common Control 11 */
#define COM11_SNGL_FRAME_EN 0x02 /* Single frame ON/OFF selection */
#define COM11_SNGL_XFR_TRIG 0x01 /* Single frame transfer trigger */
#define BDBASE 0x22 /* Banding Filter Minimum AEC Value */
#define BDSTEP 0x23 /* Banding Filter Maximum Step */
#define AEW 0x24 /* AGC/AEC - Stable Operating Region (Upper Limit) */
#define AEB 0x25 /* AGC/AEC - Stable Operating Region (Lower Limit) */
#define VPT 0x26 /* AGC/AEC Fast Mode Operating Region */
#define REG28 0x28 /* Selection on the number of dummy rows, N */
#define HOUTSIZE 0x29 /* Horizontal Data Output Size MSBs (2 LSBs at register EXHCH[1:0]) */
#define EXHCH 0x2A /* Dummy Pixel Insert MSB */
#define EXHCL 0x2B /* Dummy Pixel Insert LSB */
#define VOUTSIZE 0x2C /* Vertical Data Output Size MSBs (LSB at register EXHCH[2]) */
#define ADVFL 0x2D /* LSB of Insert Dummy Rows in Vertical Sync (1 bit equals 1 row) */
#define ADVFH 0x2E /* MSB of Insert Dummy Rows in Vertical Sync */
#define YAVE 0x2F /* Y/G Channel Average Value */
#define LUMHTH 0x30 /* Histogram AEC/AGC Luminance High Level Threshold */
#define LUMLTH 0x31 /* Histogram AEC/AGC Luminance Low Level Threshold */
#define HREF 0x32 /* Image Start and Size Control */
#define DM_LNL 0x33 /* Dummy Row Low 8 Bits */
#define DM_LNH 0x34 /* Dummy Row High 8 Bits */
#define ADOFF_B 0x35 /* AD Offset Compensation Value for B Channel */
#define ADOFF_R 0x36 /* AD Offset Compensation Value for R Channel */
#define ADOFF_GB 0x37 /* AD Offset Compensation Value for GB Channel */
#define ADOFF_GR 0x38 /* AD Offset Compensation Value for GR Channel */
#define OFF_B 0x39 /* AD Offset Compensation Value for B Channel */
#define OFF_R 0x3A /* AD Offset Compensation Value for R Channel */
#define OFF_GB 0x3B /* AD Offset Compensation Value for GB Channel */
#define OFF_GR 0x3C /* AD Offset Compensation Value for GR Channel */
#define COM12 0x3D /* DC offset compensation for analog process */
#define COM13 0x3E /* Common Control 13 */
#define COM13_BLC_EN 0x80 /* BLC enable */
#define COM13_ADC_EN 0x40 /* ADC channel BLC ON/OFF control */
#define COM13_ANALOG_BLC 0x20 /* Analog processing channel BLC ON/OFF control */
#define COM13_ABLC_GAIN_EN 0x04 /* ABLC gain trigger enable */
#define COM13_SET_BLC(r, x) ((r & 0x7F) | ((x & 0x1) << 7))
#define COM14 0x3F /* Common Control 14 */
#define COM15 0x40 /* Common Control 15 */
#define COM16 0x41 /* Common Control 16 */
#define TGT_B 0x42 /* BLC Blue Channel Target Value */
#define TGT_R 0x43 /* BLC Red Channel Target Value */
#define TGT_GB 0x44 /* BLC Gb Channel Target Value */
#define TGT_GR 0x45 /* BLC Gr Channel Target Value */
#define LC_CTR 0x46 /* Lens Correction Control */
#define LC_CTR_RGB_COMP_1 0x00 /* R, G, and B channel compensation coefficient is set by LC_COEF (0x49) */
#define LC_CTR_RGB_COMP_3 0x04 /* R, G, and B channel compensation coefficient is set by registers
LC_COEFB (0x4B), LC_COEF (0x49), and LC_COEFR (0x4C), respectively */
#define LC_CTR_EN 0x01 /* Lens correction enable */
#define LC_XC 0x47 /* X Coordinate of Lens Correction Center Relative to Array Center */
#define LC_YC 0x48 /* Y Coordinate of Lens Correction Center Relative to Array Center */
#define LC_COEF 0x49 /* Lens Correction Coefficient */
#define LC_RADI 0x4A /* Lens Correction Radius */
#define LC_COEFB 0x4B /* Lens Correction B Channel Compensation Coefficient */
#define LC_COEFR 0x4C /* Lens Correction R Channel Compensation Coefficient */
#define FIXGAIN 0x4D /* Analog Fix Gain Amplifier */
#define AREF0 0x4E /* Sensor Reference Control */
#define AREF1 0x4F /* Sensor Reference Current Control */
#define AREF2 0x50 /* Analog Reference Control */
#define AREF3 0x51 /* ADC Reference Control */
#define AREF4 0x52 /* ADC Reference Control */
#define AREF5 0x53 /* ADC Reference Control */
#define AREF6 0x54 /* Analog Reference Control */
#define AREF7 0x55 /* Analog Reference Control */
#define UFIX 0x60 /* U Channel Fixed Value Output */
#define VFIX 0x61 /* V Channel Fixed Value Output */
#define AWBB_BLK 0x62 /* AWB Option for Advanced AWB */
#define AWB_CTRL0 0x63 /* AWB Control Byte 0 */
#define AWB_CTRL0_GAIN_EN 0x80 /* AWB gain enable */
#define AWB_CTRL0_CALC_EN 0x40 /* AWB calculate enable */
#define AWB_CTRL0_WBC_MASK 0x0F /* WBC threshold 2 */
#define DSP_CTRL1 0x64 /* DSP Control Byte 1 */
#define DSP_CTRL1_FIFO_EN 0x80 /* FIFO enable/disable selection */
#define DSP_CTRL1_UV_EN 0x40 /* UV adjust function ON/OFF selection */
#define DSP_CTRL1_SDE_EN 0x20 /* SDE enable */
#define DSP_CTRL1_MTRX_EN 0x10 /* Color matrix ON/OFF selection */
#define DSP_CTRL1_INTRP_EN 0x08 /* Interpolation ON/OFF selection */
#define DSP_CTRL1_GAMMA_EN 0x04 /* Gamma function ON/OFF selection */
#define DSP_CTRL1_BLACK_EN 0x02 /* Black defect auto correction ON/OFF */
#define DSP_CTRL1_WHITE_EN 0x01 /* White defect auto correction ON/OFF */
#define DSP_CTRL2 0x65 /* DSP Control Byte 2 */
#define DSP_CTRL2_VDCW_EN 0x08 /* Vertical DCW enable */
#define DSP_CTRL2_HDCW_EN 0x04 /* Horizontal DCW enable */
#define DSP_CTRL2_VZOOM_EN 0x02 /* Vertical zoom out enable */
#define DSP_CTRL2_HZOOM_EN 0x01 /* Horizontal zoom out enable */
#define DSP_CTRL3 0x66 /* DSP Control Byte 3 */
#define DSP_CTRL3_UV_EN 0x80 /* UV output sequence option */
#define DSP_CTRL3_CBAR_EN 0x20 /* DSP color bar ON/OFF selection */
#define DSP_CTRL3_FIFO_EN 0x08 /* FIFO power down ON/OFF selection */
#define DSP_CTRL3_SCAL1_PWDN 0x04 /* Scaling module power down control 1 */
#define DSP_CTRL3_SCAL2_PWDN 0x02 /* Scaling module power down control 2 */
#define DSP_CTRL3_INTRP_PWDN 0x01 /* Interpolation module power down control */
#define DSP_CTRL3_SET_CBAR(r, x) ((r & 0xDF) | ((x & 1) << 5))
#define DSP_CTRL4 0x67 /* DSP Control Byte 4 */
#define DSP_CTRL4_YUV_RGB 0x00 /* Output selection YUV or RGB */
#define DSP_CTRL4_RAW8 0x02 /* Output selection RAW8 */
#define DSP_CTRL4_RAW10 0x03 /* Output selection RAW10 */
#define AWB_BIAS 0x68 /* AWB BLC Level Clip */
#define AWB_CTRL1 0x69 /* AWB Control 1 */
#define AWB_CTRL2 0x6A /* AWB Control 2 */
#define AWB_CTRL3 0x6B /* AWB Control 3 */
#define AWB_CTRL3_ADVANCED 0x80 /* AWB mode select - Advanced AWB */
#define AWB_CTRL3_SIMPLE 0x00 /* AWB mode select - Simple AWB */
#define AWB_CTRL4 0x6C /* AWB Control 4 */
#define AWB_CTRL5 0x6D /* AWB Control 5 */
#define AWB_CTRL6 0x6E /* AWB Control 6 */
#define AWB_CTRL7 0x6F /* AWB Control 7 */
#define AWB_CTRL8 0x70 /* AWB Control 8 */
#define AWB_CTRL9 0x71 /* AWB Control 9 */
#define AWB_CTRL10 0x72 /* AWB Control 10 */
#define AWB_CTRL11 0x73 /* AWB Control 11 */
#define AWB_CTRL12 0x74 /* AWB Control 12 */
#define AWB_CTRL13 0x75 /* AWB Control 13 */
#define AWB_CTRL14 0x76 /* AWB Control 14 */
#define AWB_CTRL15 0x77 /* AWB Control 15 */
#define AWB_CTRL16 0x78 /* AWB Control 16 */
#define AWB_CTRL17 0x79 /* AWB Control 17 */
#define AWB_CTRL18 0x7A /* AWB Control 18 */
#define AWB_CTRL19 0x7B /* AWB Control 19 */
#define AWB_CTRL20 0x7C /* AWB Control 20 */
#define AWB_CTRL21 0x7D /* AWB Control 21 */
#define GAM1 0x7E /* Gamma Curve 1st Segment Input End Point 0x04 Output Value */
#define GAM2 0x7F /* Gamma Curve 2nd Segment Input End Point 0x08 Output Value */
#define GAM3 0x80 /* Gamma Curve 3rd Segment Input End Point 0x10 Output Value */
#define GAM4 0x81 /* Gamma Curve 4th Segment Input End Point 0x20 Output Value */
#define GAM5 0x82 /* Gamma Curve 5th Segment Input End Point 0x28 Output Value */
#define GAM6 0x83 /* Gamma Curve 6th Segment Input End Point 0x30 Output Value */
#define GAM7 0x84 /* Gamma Curve 7th Segment Input End Point 0x38 Output Value */
#define GAM8 0x85 /* Gamma Curve 8th Segment Input End Point 0x40 Output Value */
#define GAM9 0x86 /* Gamma Curve 9th Segment Input Enpd Point 0x48 Output Value */
#define GAM10 0x87 /* Gamma Curve 10th Segment Input End Point 0x50 Output Value */
#define GAM11 0x88 /* Gamma Curve 11th Segment Input End Point 0x60 Output Value */
#define GAM12 0x89 /* Gamma Curve 12th Segment Input End Point 0x70 Output Value */
#define GAM13 0x8A /* Gamma Curve 13th Segment Input End Point 0x90 Output Value */
#define GAM14 0x8B /* Gamma Curve 14th Segment Input End Point 0xB0 Output Value */
#define GAM15 0x8C /* Gamma Curve 15th Segment Input End Point 0xD0 Output Value */
#define SLOP 0x8D /* Gamma Curve Highest Segment Slope */
#define DNSTH 0x8E /* De-noise Threshold */
#define EDGE0 0x8F /* Edge Enhancement Strength Control */
#define EDGE1 0x90 /* Edge Enhancement Threshold Control */
#define DNSOFF 0x91 /* Auto De-noise Threshold Control */
#define EDGE2 0x92 /* Edge Enhancement Strength Upper Limit */
#define EDGE3 0x93 /* Edge Enhancement Strength Upper Limit */
#define MTX1 0x94 /* Matrix Coefficient 1 */
#define MTX2 0x95 /* Matrix Coefficient 2 */
#define MTX3 0x96 /* Matrix Coefficient 3 */
#define MTX4 0x97 /* Matrix Coefficient 4 */
#define MTX5 0x98 /* Matrix Coefficient 5 */
#define MTX6 0x99 /* Matrix Coefficient 6 */
#define MTX_CTRL 0x9A /* Matrix Control */
#define MTX_CTRL_DBL_EN 0x80 /* Matrix double ON/OFF selection */
#define BRIGHTNESS 0x9B /* Brightness Control */
#define CONTRAST 0x9C /* Contrast Gain */
#define UVADJ0 0x9E /* Auto UV Adjust Control 0 */
#define UVADJ1 0x9F /* Auto UV Adjust Control 1 */
#define SCAL0 0xA0 /* DCW Ratio Control */
#define SCAL1 0xA1 /* Horizontal Zoom Out Control */
#define SCAL2 0xA2 /* Vertical Zoom Out Control */
#define FIFODLYM 0xA3 /* FIFO Manual Mode Delay Control */
#define FIFODLYA 0xA4 /* FIFO Auto Mode Delay Control */
#define SDE 0xA6 /* Special Digital Effect Control */
#define SDE_NEGATIVE_EN 0x40 /* Negative image enable */
#define SDE_GRAYSCALE_EN 0x20 /* Gray scale image enable */
#define SDE_V_FIXED_EN 0x10 /* V fixed value enable */
#define SDE_U_FIXED_EN 0x08 /* U fixed value enable */
#define SDE_CONT_BRIGHT_EN 0x04 /* Contrast/Brightness enable */
#define SDE_SATURATION_EN 0x02 /* Saturation enable */
#define SDE_HUE_EN 0x01 /* Hue enable */
#define USAT 0xA7 /* U Component Saturation Gain */
#define VSAT 0xA8 /* V Component Saturation Gain */
#define HUECOS 0xA9 /* Cosine value × 0x80 */
#define HUESIN 0xAA /* Sine value × 0x80 */
#define SIGN_BIT 0xAB /* Sign Bit for Hue and Brightness */
#define DSPAUTO 0xAC /* DSP Auto Function ON/OFF Control */
#define DSPAUTO_AWB_EN 0x80 /* AWB auto threshold control */
#define DSPAUTO_DENOISE_EN 0x40 /* De-noise auto threshold control */
#define DSPAUTO_EDGE_EN 0x20 /* Sharpness (edge enhancement) auto strength control */
#define DSPAUTO_UV_EN 0x10 /* UV adjust auto slope control */
#define DSPAUTO_SCAL0_EN 0x08 /* Auto scaling factor control (register SCAL0 (0xA0)) */
#define DSPAUTO_SCAL1_EN 0x04 /* Auto scaling factor control (registers SCAL1 (0xA1 and SCAL2 (0xA2)) */
#endif //__REG_REGS_H__

View File

@ -34,7 +34,6 @@
#include "omv_csi.h"
#include "ov9650.h"
#include "py/mphal.h"
#include "ov9650_regs.h"
#define NUM_BR_LEVELS 7

View File

@ -21,9 +21,132 @@
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*
* OV9650 driver.
* OV9650 register definitions.
*/
#ifndef __OV9650_H__
#define __OV9650_H__
int ov9650_init(omv_csi_t *csi);
#endif // __OV9650_H__
#ifndef __REG_REGS_H__
#define __REG_REGS_H__
#define REG_GAIN 0x00
#define REG_BLUE 0x01
#define REG_RED 0x02
#define REG_VREF 0x03
#define REG_COM1 0x04
#define REG_BAVE 0x05
#define REG_GEAVE 0x06
#define REG_RAVE 0x08
#define REG_COM2 0x09
#define REG_PID 0x0A
#define REG_VER 0x0B
#define REG_COM3 0x0C
#define REG_COM4 0x0D
#define REG_COM5 0x0E
#define REG_COM6 0x0F
#define REG_AECH 0x10
#define REG_CLKRC 0x11
#define REG_COM7 0x12
#define REG_COM8 0x13
#define REG_COM9 0x14
#define REG_COM10 0x15
#define REG_RSVD16 0x16
#define REG_HSTART 0x17
#define REG_HSTOP 0x18
#define REG_VSTART 0x19
#define REG_VSTOP 0x1A
#define REG_PSHFT 0x1B
#define REG_MIDH 0x1C
#define REG_MIDL 0x1D
#define REG_MVFP 0x1E
#define REG_BOS 0x20
#define REG_GBOS 0x21
#define REG_GROS 0x22
#define REG_ROS 0x23
#define REG_AEW 0x24
#define REG_AEB 0x25
#define REG_VPT 0x26
#define REG_BBIAS 0x27
#define REG_GbBIAS 0x28
#define REG_GRCOM 0x29
#define REG_EXHCH 0x2A
#define REG_EXHCL 0x2B
#define REG_RBIAS 0x2C
#define REG_ADVFL 0x2D
#define REG_ADVFH 0x2E
#define REG_YAVE 0x2F
#define REG_HSYST 0x30
#define REG_HSYEN 0x31
#define REG_HREF 0x32
#define REG_CHLF 0x33
#define REG_ARBLM 0x34
#define REG_RSVD35 0x35
#define REG_RSVD36 0x36
#define REG_ADC 0x37
#define REG_ACOM38 0x38
#define REG_OFON 0x39
#define REG_TSLB 0x3A
#define REG_COM11 0x3B
#define REG_COM12 0x3C
#define REG_COM13 0x3D
#define REG_COM14 0x3E
#define REG_EDGE 0x3F
#define REG_COM15 0x40
#define REG_COM16 0x41
#define REG_COM17 0x42
#define REG_MTX1 0x4F
#define REG_MTX2 0x50
#define REG_MTX3 0x51
#define REG_MTX4 0x52
#define REG_MTX5 0x53
#define REG_MTX6 0x54
#define REG_MTX7 0x55
#define REG_MTX8 0x56
#define REG_MTX9 0x57
#define REG_MTXS 0x58
#define REG_LCC1 0x62
#define REG_LCC2 0x63
#define REG_LCC3 0x64
#define REG_LCC4 0x65
#define REG_LCC5 0x66
#define REG_MANU 0x67
#define REG_MANV 0x68
#define REG_HV 0x69
#define REG_MBD 0x6A
#define REG_DBLV 0x6B
#define REG_COM21 0x8B
#define REG_COM22 0x8C
#define REG_COM23 0x8D
#define REG_COM24 0x8E
#define REG_DBLC1 0x8F
#define REG_DBLC_B 0x90
#define REG_DBLC_R 0x91
#define REG_DMLNL 0x92
#define REG_DMLNH 0x93
#define REG_LCCFB 0x9D
#define REG_LCCFR 0x9E
#define REG_DBLC_GB 0x9F
#define REG_DBLC_GR 0xA0
#define REG_AECHM 0xA1
#define REG_COM25 0xA4
#define REG_COM26 0xA5
#define REG_GGAIN 0xA6
#define REG_VGAST 0xA7
/* register bits */
#define REG_COM1_QQCIF (1 << 5)
#define REG_COM1_QQVGA (1 << 5)
#define REG_COM1_SKIP2 (1 << 2)
#define REG_COM1_SKIP3 (1 << 3)
#define REG_COM7_RGB (1 << 2)
#define REG_COM7_QCIF (1 << 3)
#define REG_COM7_QVGA (1 << 4)
#define REG_COM7_CIF (1 << 5)
#define REG_COM7_VGA (1 << 6)
#define REG_COM8_AGC (1 << 2)
#define REG_COM8_AWB (1 << 1)
#define REG_COM8_AEC (1 << 0)
#define REG_MVFP_HMIRROR (1 << 5)
#define REG_MVFP_VFLIP (1 << 4)
#define REG_CLKRC_DOUBLE (1 << 8)
#define REG_CLKRC_DIVIDER_MASK (0x3F)
#endif //__REG_REGS_H__

View File

@ -1,152 +0,0 @@
/*
* SPDX-License-Identifier: MIT
*
* Copyright (C) 2013-2024 OpenMV, LLC.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*
* OV9650 register definitions.
*/
#ifndef __REG_REGS_H__
#define __REG_REGS_H__
#define REG_GAIN 0x00
#define REG_BLUE 0x01
#define REG_RED 0x02
#define REG_VREF 0x03
#define REG_COM1 0x04
#define REG_BAVE 0x05
#define REG_GEAVE 0x06
#define REG_RAVE 0x08
#define REG_COM2 0x09
#define REG_PID 0x0A
#define REG_VER 0x0B
#define REG_COM3 0x0C
#define REG_COM4 0x0D
#define REG_COM5 0x0E
#define REG_COM6 0x0F
#define REG_AECH 0x10
#define REG_CLKRC 0x11
#define REG_COM7 0x12
#define REG_COM8 0x13
#define REG_COM9 0x14
#define REG_COM10 0x15
#define REG_RSVD16 0x16
#define REG_HSTART 0x17
#define REG_HSTOP 0x18
#define REG_VSTART 0x19
#define REG_VSTOP 0x1A
#define REG_PSHFT 0x1B
#define REG_MIDH 0x1C
#define REG_MIDL 0x1D
#define REG_MVFP 0x1E
#define REG_BOS 0x20
#define REG_GBOS 0x21
#define REG_GROS 0x22
#define REG_ROS 0x23
#define REG_AEW 0x24
#define REG_AEB 0x25
#define REG_VPT 0x26
#define REG_BBIAS 0x27
#define REG_GbBIAS 0x28
#define REG_GRCOM 0x29
#define REG_EXHCH 0x2A
#define REG_EXHCL 0x2B
#define REG_RBIAS 0x2C
#define REG_ADVFL 0x2D
#define REG_ADVFH 0x2E
#define REG_YAVE 0x2F
#define REG_HSYST 0x30
#define REG_HSYEN 0x31
#define REG_HREF 0x32
#define REG_CHLF 0x33
#define REG_ARBLM 0x34
#define REG_RSVD35 0x35
#define REG_RSVD36 0x36
#define REG_ADC 0x37
#define REG_ACOM38 0x38
#define REG_OFON 0x39
#define REG_TSLB 0x3A
#define REG_COM11 0x3B
#define REG_COM12 0x3C
#define REG_COM13 0x3D
#define REG_COM14 0x3E
#define REG_EDGE 0x3F
#define REG_COM15 0x40
#define REG_COM16 0x41
#define REG_COM17 0x42
#define REG_MTX1 0x4F
#define REG_MTX2 0x50
#define REG_MTX3 0x51
#define REG_MTX4 0x52
#define REG_MTX5 0x53
#define REG_MTX6 0x54
#define REG_MTX7 0x55
#define REG_MTX8 0x56
#define REG_MTX9 0x57
#define REG_MTXS 0x58
#define REG_LCC1 0x62
#define REG_LCC2 0x63
#define REG_LCC3 0x64
#define REG_LCC4 0x65
#define REG_LCC5 0x66
#define REG_MANU 0x67
#define REG_MANV 0x68
#define REG_HV 0x69
#define REG_MBD 0x6A
#define REG_DBLV 0x6B
#define REG_COM21 0x8B
#define REG_COM22 0x8C
#define REG_COM23 0x8D
#define REG_COM24 0x8E
#define REG_DBLC1 0x8F
#define REG_DBLC_B 0x90
#define REG_DBLC_R 0x91
#define REG_DMLNL 0x92
#define REG_DMLNH 0x93
#define REG_LCCFB 0x9D
#define REG_LCCFR 0x9E
#define REG_DBLC_GB 0x9F
#define REG_DBLC_GR 0xA0
#define REG_AECHM 0xA1
#define REG_COM25 0xA4
#define REG_COM26 0xA5
#define REG_GGAIN 0xA6
#define REG_VGAST 0xA7
/* register bits */
#define REG_COM1_QQCIF (1 << 5)
#define REG_COM1_QQVGA (1 << 5)
#define REG_COM1_SKIP2 (1 << 2)
#define REG_COM1_SKIP3 (1 << 3)
#define REG_COM7_RGB (1 << 2)
#define REG_COM7_QCIF (1 << 3)
#define REG_COM7_QVGA (1 << 4)
#define REG_COM7_CIF (1 << 5)
#define REG_COM7_VGA (1 << 6)
#define REG_COM8_AGC (1 << 2)
#define REG_COM8_AWB (1 << 1)
#define REG_COM8_AEC (1 << 0)
#define REG_MVFP_HMIRROR (1 << 5)
#define REG_MVFP_VFLIP (1 << 4)
#define REG_CLKRC_DOUBLE (1 << 8)
#define REG_CLKRC_DIVIDER_MASK (0x3F)
#endif //__REG_REGS_H__

View File

@ -34,9 +34,8 @@
#include "omv_csi.h"
#include "framebuffer.h"
#include "omv_i2c.h"
#include "pag7920.h"
#include "pag7920_reg.h"
#include "sensor_config.h"
#define SENSOR_I2C_DEBUG (0)
@ -268,7 +267,10 @@ static int reset(omv_csi_t *csi) {
// Reset internal flag.
g_f_hflip = g_f_vflip = false;
g_bank_cache = -1;
return init_csi(csi);
if (init_csi(csi) != 0) {
return OMV_CSI_ERROR_CSI_INIT_FAILED;
}
return 0;
}
static int sleep(omv_csi_t *csi, int enable) {
@ -661,7 +663,9 @@ int pag7920_init(omv_csi_t *csi) {
csi->frame_sync = 1;
csi->mono_bpp = 1;
init_csi(csi);
if (init_csi(csi) != 0) {
return OMV_CSI_ERROR_CSI_INIT_FAILED;
}
return 0;
}

View File

@ -23,10 +23,92 @@
*
* PAG7920 driver.
*/
#ifndef __PAG7920_H__
#define __PAG7920_H__
#include <stdint.h>
#define OMV_PAG7920_CLK_FREQ 24000000
#define REG_BANK 0xEF
// =======================================
#define BANK_0 0x00
// ---------------------------------------
#define R_PART_ID_L 0x00
#define R_PART_ID_H 0x01
#define TG_En 0x30
#define TG_En_V1 0x01
#define TG_En_V2 0x00
#define R0_09_B1 0x09
#define R0_15 0x15
#define R0_16 0x16
#define R0_1C 0x1C
#define R0_3E_B2 0x3E
#define R0_3E_B5 0x3E
#define R_Frame_Time_0 0x4C
#define R_Frame_Time_1 0x4D
#define R_Frame_Time_2 0x4E
#define R_Frame_Time_3 0x4F
#define R_UPDATE_FLAG 0xEB
#define V_UPDATE_VALUE 0x80
#define R_GLOBAL_RESET 0xEE
#define V_GLOBAL_RESET 0xFF
// =======================================
#define BANK_1 0x01
// ---------------------------------------
#define R1_4B_B0 0x4B
#define R1_4B_B4 0x4B
#define R1_70 0x70
#define R1_C2 0xC2
#define R1_C3 0xC3
#define R1_C8 0xC8
#define R1_CB 0xCB
#define R1_CE_B2 0xCE
// =======================================
#define BANK_2 0x02
// ---------------------------------------
#define R2_19 0x19
#define R2_23 0x23
#define R2_27 0x27
#define R2_2D 0x2D
#define R2_D9_B0 0xD9
#define R2_D9_B1 0xD9
// =======================================
#define BANK_4 0x04
// ---------------------------------------
#define R_AE_EnH 0x30
#define R_AE_manual_En 0x30
#define R_AE_Size__div4_X 0x3A
#define R_AE_Size__div4_Y 0x3B
#define R_AE_MinGain_L 0x40
#define R_AE_MinGain_H 0x41
#define R_AE_MaxGain_L 0x42
#define R_AE_MaxGain_H 0x43
#define R_AE_MinExpo_0 0x44
#define R_AE_MinExpo_1 0x45
#define R_AE_MinExpo_2 0x46
#define R_AE_MinExpo_3 0x47
#define R_AE_MaxExpo_0 0x48
#define R_AE_MaxExpo_1 0x49
#define R_AE_MaxExpo_2 0x4A
#define R_AE_MaxExpo_3 0x4B
#define R_AE_Gain_manual_L 0x51
#define R_AE_Gain_manual_H 0x52
#define R_AE_Expo_manual_0 0x53
#define R_AE_Expo_manual_1 0x54
#define R_AE_Expo_manual_2 0x55
#define R_AE_Expo_manual_3 0x56
#define AE_Total_Gain_L 0xA5
#define AE_Total_Gain_H 0xA6
#define Reg_ExpPxclkNum_0 0xA7
#define Reg_ExpPxclkNum_1 0xA8
#define Reg_ExpPxclkNum_2 0xA9
#define Reg_ExpPxclkNum_3 0xAA
int pag7920_init(omv_csi_t *csi);
#endif
#define V_R009_Q_H_ON (0x02)
#define V_R009_Q_H_OFF (0x10)
#define V_R2D9_Q_H_ON (0x02)
#define V_R2D9_Q_H_OFF (0x00)
#define V_R009_QQ_H_ON (0x02)
#define V_R009_QQ_H_OFF (0x00)
#define V_R1C2_Q_V_ON (0xF7)
#define V_R1C2_Q_V_OFF (0x00)
#define V_R1C2_QQ_V_ON (0xF5)
#define V_R1C2_QQ_V_OFF (0x02)

View File

@ -1,114 +0,0 @@
/*
* SPDX-License-Identifier: MIT
*
* Copyright (c) 2023 Lake Fu <lake_fu@pixart.com> for PixArt Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*
* PAG7920 driver.
*/
#include <stdint.h>
#define REG_BANK 0xEF
// =======================================
#define BANK_0 0x00
// ---------------------------------------
#define R_PART_ID_L 0x00
#define R_PART_ID_H 0x01
#define TG_En 0x30
#define TG_En_V1 0x01
#define TG_En_V2 0x00
#define R0_09_B1 0x09
#define R0_15 0x15
#define R0_16 0x16
#define R0_1C 0x1C
#define R0_3E_B2 0x3E
#define R0_3E_B5 0x3E
#define R_Frame_Time_0 0x4C
#define R_Frame_Time_1 0x4D
#define R_Frame_Time_2 0x4E
#define R_Frame_Time_3 0x4F
#define R_UPDATE_FLAG 0xEB
#define V_UPDATE_VALUE 0x80
#define R_GLOBAL_RESET 0xEE
#define V_GLOBAL_RESET 0xFF
// =======================================
#define BANK_1 0x01
// ---------------------------------------
#define R1_4B_B0 0x4B
#define R1_4B_B4 0x4B
#define R1_70 0x70
#define R1_C2 0xC2
#define R1_C3 0xC3
#define R1_C8 0xC8
#define R1_CB 0xCB
#define R1_CE_B2 0xCE
// =======================================
#define BANK_2 0x02
// ---------------------------------------
#define R2_19 0x19
#define R2_23 0x23
#define R2_27 0x27
#define R2_2D 0x2D
#define R2_D9_B0 0xD9
#define R2_D9_B1 0xD9
// =======================================
#define BANK_4 0x04
// ---------------------------------------
#define R_AE_EnH 0x30
#define R_AE_manual_En 0x30
#define R_AE_Size__div4_X 0x3A
#define R_AE_Size__div4_Y 0x3B
#define R_AE_MinGain_L 0x40
#define R_AE_MinGain_H 0x41
#define R_AE_MaxGain_L 0x42
#define R_AE_MaxGain_H 0x43
#define R_AE_MinExpo_0 0x44
#define R_AE_MinExpo_1 0x45
#define R_AE_MinExpo_2 0x46
#define R_AE_MinExpo_3 0x47
#define R_AE_MaxExpo_0 0x48
#define R_AE_MaxExpo_1 0x49
#define R_AE_MaxExpo_2 0x4A
#define R_AE_MaxExpo_3 0x4B
#define R_AE_Gain_manual_L 0x51
#define R_AE_Gain_manual_H 0x52
#define R_AE_Expo_manual_0 0x53
#define R_AE_Expo_manual_1 0x54
#define R_AE_Expo_manual_2 0x55
#define R_AE_Expo_manual_3 0x56
#define AE_Total_Gain_L 0xA5
#define AE_Total_Gain_H 0xA6
#define Reg_ExpPxclkNum_0 0xA7
#define Reg_ExpPxclkNum_1 0xA8
#define Reg_ExpPxclkNum_2 0xA9
#define Reg_ExpPxclkNum_3 0xAA
#define V_R009_Q_H_ON (0x02)
#define V_R009_Q_H_OFF (0x10)
#define V_R2D9_Q_H_ON (0x02)
#define V_R2D9_Q_H_OFF (0x00)
#define V_R009_QQ_H_ON (0x02)
#define V_R009_QQ_H_OFF (0x00)
#define V_R1C2_Q_V_ON (0xF7)
#define V_R1C2_Q_V_OFF (0x00)
#define V_R1C2_QQ_V_ON (0xF5)
#define V_R1C2_QQ_V_OFF (0x02)

View File

@ -40,7 +40,6 @@
#include "omv_i2c.h"
#include "omv_csi.h"
#include "pag7936.h"
#include "py/mphal.h"
#define FRAME_TIME_20_16 (0x004E)

View File

@ -1,37 +0,0 @@
/*
* Copyright (C) 2023-2024 OpenMV, LLC.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Any redistribution, use, or modification in source or binary form
* is done solely for personal benefit and not for any commercial
* purpose or for monetary gain. For commercial licensing options,
* please contact openmv@openmv.io
*
* THIS SOFTWARE IS PROVIDED BY THE LICENSOR AND COPYRIGHT OWNER "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE LICENSOR OR COPYRIGHT
* OWNER BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
* OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* PixArt PAG7936 driver.
*/
#ifndef __PAG7936_H__
#define __PAG7936_H__
#define OMV_PAG7936_CLK_FREQ (24000000)
int pag7936_init(omv_csi_t *csi);
#endif // __PAG7936_H__

View File

@ -34,8 +34,8 @@
#include "omv_gpio.h"
#include "paj6100.h"
#include "paj6100_reg.h"
#include "pixspi.h"
#include "sensor_config.h"
#define CACHE_BANK
@ -632,7 +632,9 @@ static int reset(omv_csi_t *csi) {
#endif
// Re-init csi every time.
init_sensor(csi);
if (init_sensor(csi) != 0) {
return OMV_CSI_ERROR_CSI_INIT_FAILED;
}
// Fetch default R_Frame_Time
uint8_t buff[3] = {};
@ -711,7 +713,9 @@ int paj6100_init(omv_csi_t *csi) {
csi->frame_sync = 0;
csi->mono_bpp = 1;
init_sensor(csi);
if (init_sensor(csi) != 0) {
return OMV_CSI_ERROR_CSI_INIT_FAILED;
}
return 0;
}

View File

@ -1,7 +1,7 @@
/*
* SPDX-License-Identifier: MIT
*
* Copyright (c) 2019 Lake Fu <lake_fu@pixart.com>
* Copyright (c) 2021 Pixart Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
@ -21,14 +21,116 @@
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*
* PAJ6100 driver.
*
* Author: Lake Fu at <lake_fu@pixart.com>
*/
#ifndef __PAJ6100_H__
#define __PAJ6100_H__
#include <stdint.h>
#define OMV_PAJ6100_CLK_FREQ 6000000
#define REG_BANK_SWITCH 0x7F
bool paj6100_detect(omv_csi_t *csi);
int paj6100_init(omv_csi_t *csi);
#endif
// =======================================
#define BANK_0 0x00
// ---------------------------------------
#define REG_CMD_HSYNC_INV 0X07 // bit7
#define REG_CMD_VSYNC_INV 0X07 // bit6
#define REG_CMD_AAVG_V 0X07 // bit3
#define REG_CMD_AAVG_H 0X07 // bit2
#define REG_ABC_START_LINE 0x0D // bit3:1
#define REG_FGH 0x11 // bit5:4
#define REG_GGH 0x12 // bit7
#define REG_EXP_OFFSET_L 0x18
#define REG_EXP_OFFSET_H 0x19
#define REG_CMD_EXPO_L 0x48
#define REG_CMD_EXPO_H 0x49
#define REG_CMD_EXPO_2H 0x4A
#define REG_FRAME_TIME_L 0x7A
#define REG_FRAME_TIME_H 0x7B
#define REG_FRAME_TIME_2H 0x7C
// =======================================
#define BANK_1 0x01
// ---------------------------------------
#define REG_ISP_UPDATE 0x00
#define REG_CMD_SENSOR_MODE 0X23 // bit7
#define REG_CMD_LPM_ENH 0x23 // bit6
#define REG_CP_WOI_VOFFSET 0x45
#define REG_ABC_SAMPLE_SIZE 0x46 // bit2:0
// 20180504
static const uint8_t low_active_R_ABC_Avg_UBx50_T_BLACINV_EnHx1_T_SIG_REFx1[] = {
//address, value
0x7F, 0x00,
0x0C, 0x1D, // software reset
0x7F, 0x00,
0x07, 0x00, // low active
0x08, 0x03,
0x0B, 0x0E,
0x0D, 0xC5,
0x0F, 0x32, //R_ABC_Avg_UB=50
0x11, 0x41, //R_global=1
0x13, 0xD2,
0x14, 0xFE,
0x15, 0x00, // R_fg_fast=0
0x17, 0x02, //03
0x1A, 0x07,
0x1B, 0x08,
0x20, 0x00, //R_fast_powerdn_WakeupTime=0
0x25, 0x78,
0x29, 0x28,
0x2B, 0x06,
0x2F, 0x0E,
0x30, 0x0E,
0x34, 0x0F,
0x35, 0x0F,
0x3A, 0x28,
0x45, 0x17,
0x46, 0x17,
0x48, 0x10, //EXP
0x49, 0x27, //EXP
0x4A, 0x00, //EXP
0x4D, 0x0D,
0x4E, 0x20,
0x62, 0x12,
0x64, 0x02,
0x67, 0x0A,
0x69, 0x0A,
0x6C, 0x0B,
0x6E, 0x0B,
0x71, 0x0A,
0x73, 0x1D,
0x75, 0x1E,
0x77, 0x0B,
0x7F, 0x01,
0x01, 0x14,
0x02, 0x02, //
0x04, 0x96,
0x05, 0x03,
0x06, 0x46,
0x0D, 0x9F, //T_BLACINV_EnH=1
0x0E, 0x11, //T_SIG_REF=1
0x0F, 0x48,
0x10, 0x10, //T_vcom_lvl=0
0x11, 0x00,
0x12, 0x05,
0x15, 0x00,
0x16, 0x01, //schmitt trigger
0x17, 0x67,
0x18, 0xD0, //T_vrt_lvl=T_vrb_lvl=2
0x21, 0x14,
0x22, 0x80, //
0x2F, 0x30,
0x35, 0x64,
0x39, 0x03,
0x3A, 0x03,
0x46, 0x06,
0x4A, 0x01, // 0x00 //FX2
0x4B, 0x10, // 0x00 //FX2
0x00, 0x01, //updated flag
};

View File

@ -1,136 +0,0 @@
/*
* SPDX-License-Identifier: MIT
*
* Copyright (c) 2021 Pixart Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*
* Author: Lake Fu at <lake_fu@pixart.com>
*/
#include <stdint.h>
#define REG_BANK_SWITCH 0x7F
// =======================================
#define BANK_0 0x00
// ---------------------------------------
#define REG_CMD_HSYNC_INV 0X07 // bit7
#define REG_CMD_VSYNC_INV 0X07 // bit6
#define REG_CMD_AAVG_V 0X07 // bit3
#define REG_CMD_AAVG_H 0X07 // bit2
#define REG_ABC_START_LINE 0x0D // bit3:1
#define REG_FGH 0x11 // bit5:4
#define REG_GGH 0x12 // bit7
#define REG_EXP_OFFSET_L 0x18
#define REG_EXP_OFFSET_H 0x19
#define REG_CMD_EXPO_L 0x48
#define REG_CMD_EXPO_H 0x49
#define REG_CMD_EXPO_2H 0x4A
#define REG_FRAME_TIME_L 0x7A
#define REG_FRAME_TIME_H 0x7B
#define REG_FRAME_TIME_2H 0x7C
// =======================================
#define BANK_1 0x01
// ---------------------------------------
#define REG_ISP_UPDATE 0x00
#define REG_CMD_SENSOR_MODE 0X23 // bit7
#define REG_CMD_LPM_ENH 0x23 // bit6
#define REG_CP_WOI_VOFFSET 0x45
#define REG_ABC_SAMPLE_SIZE 0x46 // bit2:0
// 20180504
static const uint8_t low_active_R_ABC_Avg_UBx50_T_BLACINV_EnHx1_T_SIG_REFx1[] = {
//address, value
0x7F, 0x00,
0x0C, 0x1D, // software reset
0x7F, 0x00,
0x07, 0x00, // low active
0x08, 0x03,
0x0B, 0x0E,
0x0D, 0xC5,
0x0F, 0x32, //R_ABC_Avg_UB=50
0x11, 0x41, //R_global=1
0x13, 0xD2,
0x14, 0xFE,
0x15, 0x00, // R_fg_fast=0
0x17, 0x02, //03
0x1A, 0x07,
0x1B, 0x08,
0x20, 0x00, //R_fast_powerdn_WakeupTime=0
0x25, 0x78,
0x29, 0x28,
0x2B, 0x06,
0x2F, 0x0E,
0x30, 0x0E,
0x34, 0x0F,
0x35, 0x0F,
0x3A, 0x28,
0x45, 0x17,
0x46, 0x17,
0x48, 0x10, //EXP
0x49, 0x27, //EXP
0x4A, 0x00, //EXP
0x4D, 0x0D,
0x4E, 0x20,
0x62, 0x12,
0x64, 0x02,
0x67, 0x0A,
0x69, 0x0A,
0x6C, 0x0B,
0x6E, 0x0B,
0x71, 0x0A,
0x73, 0x1D,
0x75, 0x1E,
0x77, 0x0B,
0x7F, 0x01,
0x01, 0x14,
0x02, 0x02, //
0x04, 0x96,
0x05, 0x03,
0x06, 0x46,
0x0D, 0x9F, //T_BLACINV_EnH=1
0x0E, 0x11, //T_SIG_REF=1
0x0F, 0x48,
0x10, 0x10, //T_vcom_lvl=0
0x11, 0x00,
0x12, 0x05,
0x15, 0x00,
0x16, 0x01, //schmitt trigger
0x17, 0x67,
0x18, 0xD0, //T_vrt_lvl=T_vrb_lvl=2
0x21, 0x14,
0x22, 0x80, //
0x2F, 0x30,
0x35, 0x64,
0x39, 0x03,
0x3A, 0x03,
0x46, 0x06,
0x4A, 0x01, // 0x00 //FX2
0x4B, 0x10, // 0x00 //FX2
0x00, 0x01, //updated flag
};

View File

@ -40,7 +40,6 @@
#include "omv_i2c.h"
#include "omv_csi.h"
#include "ps5520.h"
#include "py/mphal.h"
#define REG_BANK (0xEF)

View File

@ -1,37 +0,0 @@
/*
* Copyright (C) 2025 OpenMV, LLC.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Any redistribution, use, or modification in source or binary form
* is done solely for personal benefit and not for any commercial
* purpose or for monetary gain. For commercial licensing options,
* please contact openmv@openmv.io
*
* THIS SOFTWARE IS PROVIDED BY THE LICENSOR AND COPYRIGHT OWNER "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE LICENSOR OR COPYRIGHT
* OWNER BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
* OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* PixArt PS5520 driver.
*/
#ifndef __PS5520_H__
#define __PS5520_H__
#define OMV_PS5520_CLK_FREQ (24000000)
int ps5520_init(omv_csi_t *csi);
#endif // __PS5520_H__

View File

@ -0,0 +1,207 @@
#ifndef __SENSOR_CONFIG_H__
#define __SENSOR_CONFIG_H__
#include <stdint.h>
#include "omv_csi.h"
#include "omv_boardconfig.h"
typedef int (*sensor_init_t)(omv_csi_t *);
typedef struct {
uint32_t chip_id;
uint32_t clk_hz;
sensor_init_t init_fun;
} sensor_config_t;
#ifndef OMV_OV2640_CLK_FREQ
#define OMV_OV2640_CLK_FREQ (24000000)
#endif
extern int ov2640_init(omv_csi_t *csi);
#ifndef OMV_OV5640_CLK_FREQ
#define OMV_OV5640_CLK_FREQ (24000000)
#endif
#ifndef OMV_OV5640_REV_Y_FREQ
#define OMV_OV5640_REV_Y_FREQ (25000000)
#endif
extern int ov5640_init(omv_csi_t *csi);
#ifndef OMV_OV7670_CLK_FREQ
#define OMV_OV7670_CLK_FREQ (24000000)
#endif
extern int ov7670_init(omv_csi_t *csi);
#ifndef OMV_OV7690_CLK_FREQ
#define OMV_OV7690_CLK_FREQ (24000000)
#endif
extern int ov7690_init(omv_csi_t *csi);
#ifndef OMV_OV7725_CLK_FREQ
#define OMV_OV7725_CLK_FREQ (12000000)
#endif
extern int ov7725_init(omv_csi_t *csi);
#ifndef OMV_OV9650_CLK_FREQ
#define OMV_OV9650_CLK_FREQ (12000000)
#endif
extern int ov9650_init(omv_csi_t *csi);
#ifndef OMV_MT9V0XX_CLK_FREQ
#define OMV_MT9V0XX_CLK_FREQ (26666666)
#endif
extern int mt9v0xx_init(omv_csi_t *csi);
#ifndef OMV_MT9M114_CLK_FREQ
#define OMV_MT9M114_CLK_FREQ (24000000)
#endif
extern int mt9m114_init(omv_csi_t *csi);
#ifndef OMV_BOSON_CLK_FREQ
#define OMV_BOSON_CLK_FREQ (0)
#endif
extern int boson_init(omv_csi_t *csi);
#ifndef OMV_LEPTON_CLK_FREQ
#define OMV_LEPTON_CLK_FREQ (24000000)
#endif
extern int lepton_init(omv_csi_t *csi);
#ifndef OMV_HM01B0_CLK_FREQ
#define OMV_HM01B0_CLK_FREQ (6000000)
#endif
extern int hm01b0_init(omv_csi_t *csi);
#ifndef OMV_HM0360_CLK_FREQ
#define OMV_HM0360_CLK_FREQ (0)
#endif
extern int hm0360_init(omv_csi_t *csi);
#ifndef OMV_GC2145_CLK_FREQ
#define OMV_GC2145_CLK_FREQ (12000000)
#endif
extern int gc2145_init(omv_csi_t *csi);
#ifndef OMV_GENX320_CLK_FREQ
#define OMV_GENX320_CLK_FREQ (24000000)
#endif
extern int genx320_init(omv_csi_t *csi);
#ifndef OMV_PAG7920_CLK_FREQ
#define OMV_PAG7920_CLK_FREQ (24000000)
#endif
extern int pag7920_init(omv_csi_t *csi);
#ifndef OMV_PAG7936_CLK_FREQ
#define OMV_PAG7936_CLK_FREQ (24000000)
#endif
extern int pag7936_init(omv_csi_t *csi);
#ifndef OMV_PAJ6100_CLK_FREQ
#define OMV_PAJ6100_CLK_FREQ (6000000)
#endif
extern int paj6100_init(omv_csi_t *csi);
extern bool paj6100_detect(omv_csi_t *csi);
#ifndef OMV_PS5520_CLK_FREQ
#define OMV_PS5520_CLK_FREQ (24000000)
#endif
extern int ps5520_init(omv_csi_t *csi);
#ifndef OMV_FROGEYE2020_CLK_FREQ
#define OMV_FROGEYE2020_CLK_FREQ (5000000)
#endif
extern int frogeye2020_init(omv_csi_t *csi);
#ifndef OMV_SOFTCSI_CLK_FREQ
#define OMV_SOFTCSI_CLK_FREQ (24000000)
#endif
extern int softcsi_init(omv_csi_t *csi);
// Sensor table
static const sensor_config_t sensor_config_table[] = {
#if OMV_OV2640_ENABLE
{ OV2640_ID, OMV_OV2640_CLK_FREQ, ov2640_init },
#endif
#if OMV_OV5640_ENABLE
{ OV5640_ID, OMV_OV5640_CLK_FREQ, ov5640_init },
#endif
#if OMV_OV7670_ENABLE
{ OV7670_ID, OMV_OV7670_CLK_FREQ, ov7670_init },
#endif
#if OMV_OV7690_ENABLE
{ OV7690_ID, OMV_OV7690_CLK_FREQ, ov7690_init },
#endif
#if OMV_OV7725_ENABLE
{ OV7725_ID, OMV_OV7725_CLK_FREQ, ov7725_init },
#endif
#if OMV_OV9650_ENABLE
{ OV9650_ID, OMV_OV9650_CLK_FREQ, ov9650_init },
#endif
#if OMV_MT9V0XX_ENABLE
{ MT9V0X2_ID_V_1, OMV_MT9V0XX_CLK_FREQ, mt9v0xx_init },
{ MT9V0X2_ID_V_2, OMV_MT9V0XX_CLK_FREQ, mt9v0xx_init },
{ MT9V0X2_ID, OMV_MT9V0XX_CLK_FREQ, mt9v0xx_init },
{ MT9V0X4_ID, OMV_MT9V0XX_CLK_FREQ, mt9v0xx_init },
#endif
#if OMV_MT9M114_ENABLE
{ MT9M114_ID, OMV_MT9M114_CLK_FREQ, mt9m114_init },
#endif
#if OMV_BOSON_ENABLE
{ BOSON_ID, OMV_BOSON_CLK_FREQ, boson_init },
#endif
#if OMV_LEPTON_ENABLE
{ LEPTON_ID, OMV_LEPTON_CLK_FREQ, lepton_init },
#endif
#if OMV_HM01B0_ENABLE
{ HM01B0_ID, OMV_HM01B0_CLK_FREQ, hm01b0_init },
#endif
#if OMV_HM0360_ENABLE
{ HM0360_ID, OMV_HM0360_CLK_FREQ, hm0360_init },
#endif
#if OMV_GC2145_ENABLE
{ GC2145_ID, OMV_GC2145_CLK_FREQ, gc2145_init },
#endif
#if OMV_GENX320_ENABLE
{ GENX320_ID_ES, OMV_GENX320_CLK_FREQ, genx320_init },
{ GENX320_ID_MP, OMV_GENX320_CLK_FREQ, genx320_init },
#endif
#if OMV_PAG7920_ENABLE
{ PAG7920_ID, OMV_PAG7920_CLK_FREQ, pag7920_init },
#endif
#if OMV_PAG7936_ENABLE
{ PAG7936_ID, OMV_PAG7936_CLK_FREQ, pag7936_init },
#endif
#if OMV_PAJ6100_ENABLE
{ PAJ6100_ID, OMV_PAJ6100_CLK_FREQ, paj6100_init },
#endif
#if OMV_PS5520_ENABLE
{ PS5520_ID, OMV_PS5520_CLK_FREQ, ps5520_init },
#endif
#if OMV_FROGEYE2020_ENABLE
{ FROGEYE2020_ID, OMV_FROGEYE2020_CLK_FREQ, frogeye2020_init },
#endif
#if OMV_SOFTCSI_ENABLE
{ SOFTCSI_ID, OMV_SOFTCSI_CLK_FREQ, softcsi_init },
#endif
};
#endif // __CSI_CONFIG_H__

View File

@ -1,30 +0,0 @@
/*
* SPDX-License-Identifier: MIT
*
* Copyright (C) 2025 OpenMV, LLC.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*
* Virtual image sensor.
*/
#ifndef __SOFTCSI_H__
#define __SOFTCSI_H__
#define OMV_SOFTCSI_CLK_FREQ (24000000)
int softcsi_init(omv_csi_t *csi);
#endif // __SOFTCSI_H__

View File

@ -222,7 +222,11 @@ static mp_obj_t py_csi_snapshot(size_t n_args, const mp_obj_t *pos_args, mp_map_
// If an image is provided update it and return.
if (args[ARG_image].u_obj != mp_const_none) {
image_copy(py_helper_arg_to_image(args[ARG_image].u_obj, ARG_IMAGE_ANY), &image, true);
image_t *other = py_helper_arg_to_image(args[ARG_image].u_obj, ARG_IMAGE_MUTABLE);
fb_alloc_mark();
imlib_draw_image(other, &image, 0, 0, 1.f, 1.f, NULL, -1, 255, NULL, NULL,
IMAGE_HINT_SCALE_ASPECT_IGNORE, NULL, NULL, NULL);
fb_alloc_free_till_mark();
return mp_const_none;
}

View File

@ -549,8 +549,6 @@ int omv_csi_init() {
if (omv_csi_config(csi, OMV_CSI_CONFIG_INIT) != 0) {
return OMV_CSI_ERROR_CSI_INIT_FAILED;
}
csi->detected = true;
}
// Clear fb_enabled flag.

View File

@ -256,8 +256,6 @@ int omv_csi_init() {
if (omv_csi_config(csi, OMV_CSI_CONFIG_INIT) != 0) {
return OMV_CSI_ERROR_CSI_INIT_FAILED;
}
csi->detected = true;
}
// Clear fb_enabled flag

View File

@ -279,8 +279,6 @@ int omv_csi_init() {
if (omv_csi_config(csi, OMV_CSI_CONFIG_INIT) != 0) {
return OMV_CSI_ERROR_CSI_INIT_FAILED;
}
csi->detected = true;
}
// Clear fb_enabled flag.

View File

@ -1128,8 +1128,6 @@ int omv_csi_init() {
if (omv_csi_config(csi, OMV_CSI_CONFIG_INIT) != 0) {
return OMV_CSI_ERROR_CSI_INIT_FAILED;
}
csi->detected = true;
}
// Clear fb_enabled flag.