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Merge pull request #2727 from openmv/refactor_csi_i2c
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misc: Refactor CSI I2C bus.
This commit is contained in:
commit
899d645e69
@ -130,6 +130,7 @@ uint16_t resolution[][2] = {
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};
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omv_csi_t csi = {0};
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omv_i2c_t csi_i2c = {0};
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__weak void omv_csi_init0() {
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// Reset the csi state
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@ -180,7 +181,7 @@ __weak int omv_csi_reset() {
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omv_csi_shutdown(false);
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// Disable the bus before reset.
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omv_i2c_enable(&csi.i2c_bus, false);
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omv_i2c_enable(csi.i2c, false);
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#if defined(OMV_CSI_RESET_PIN)
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// Hard-reset the csi
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@ -198,7 +199,7 @@ __weak int omv_csi_reset() {
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mp_hal_delay_ms(OMV_CSI_RESET_DELAY);
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// Re-enable the bus.
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omv_i2c_enable(&csi.i2c_bus, true);
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omv_i2c_enable(csi.i2c, true);
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// Call csi-specific reset function
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if (csi.reset != NULL &&
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@ -214,14 +215,14 @@ __weak int omv_csi_reset() {
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static int omv_csi_detect() {
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uint8_t devs_list[OMV_CSI_MAX_DEVICES];
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int n_devs = omv_i2c_scan(&csi.i2c_bus, devs_list, OMV_ARRAY_SIZE(devs_list));
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int n_devs = omv_i2c_scan(csi.i2c, devs_list, OMV_ARRAY_SIZE(devs_list));
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for (int i = 0; i < OMV_MIN(n_devs, OMV_CSI_MAX_DEVICES); i++) {
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uint8_t slv_addr = devs_list[i];
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switch (slv_addr) {
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#if (OMV_OV2640_ENABLE == 1)
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case OV2640_SLV_ADDR: // Or OV9650.
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omv_i2c_readb(&csi.i2c_bus, slv_addr, OV_CHIP_ID, (uint8_t *) &csi.chip_id);
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omv_i2c_readb(csi.i2c, slv_addr, OV_CHIP_ID, (uint8_t *) &csi.chip_id);
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return slv_addr;
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#endif // (OMV_OV2640_ENABLE == 1)
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@ -229,17 +230,17 @@ static int omv_csi_detect() {
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// OV5640, GC2145, and GENX320 share the same I2C address
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case OV5640_SLV_ADDR: // Or GC2145, or GENX320.
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// Try to read GC2145 chip ID first
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omv_i2c_readb(&csi.i2c_bus, slv_addr, GC_CHIP_ID, (uint8_t *) &csi.chip_id);
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omv_i2c_readb(csi.i2c, slv_addr, GC_CHIP_ID, (uint8_t *) &csi.chip_id);
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if (csi.chip_id != GC2145_ID) {
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// If it fails, try reading OV5640 chip ID.
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omv_i2c_readb2(&csi.i2c_bus, slv_addr, OV5640_CHIP_ID, (uint8_t *) &csi.chip_id);
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omv_i2c_readb2(csi.i2c, slv_addr, OV5640_CHIP_ID, (uint8_t *) &csi.chip_id);
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#if (OMV_GENX320_ENABLE == 1)
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if (csi.chip_id != OV5640_ID) {
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// If it fails, try reading GENX320 chip ID.
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uint8_t buf[] = {(GENX320_CHIP_ID >> 8), GENX320_CHIP_ID};
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omv_i2c_write_bytes(&csi.i2c_bus, slv_addr, buf, 2, OMV_I2C_XFER_NO_STOP);
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omv_i2c_read_bytes(&csi.i2c_bus, slv_addr, (uint8_t *) &csi.chip_id, 4, OMV_I2C_XFER_NO_FLAGS);
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omv_i2c_write_bytes(csi.i2c, slv_addr, buf, 2, OMV_I2C_XFER_NO_STOP);
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omv_i2c_read_bytes(csi.i2c, slv_addr, (uint8_t *) &csi.chip_id, 4, OMV_I2C_XFER_NO_FLAGS);
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csi.chip_id = __REV(csi.chip_id);
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}
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#endif // (OMV_GENX320_ENABLE == 1)
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@ -249,19 +250,19 @@ static int omv_csi_detect() {
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#if (OMV_OV7725_ENABLE == 1) || (OMV_OV7670_ENABLE == 1) || (OMV_OV7690_ENABLE == 1)
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case OV7725_SLV_ADDR: // Or OV7690 or OV7670.
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omv_i2c_readb(&csi.i2c_bus, slv_addr, OV_CHIP_ID, (uint8_t *) &csi.chip_id);
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omv_i2c_readb(csi.i2c, slv_addr, OV_CHIP_ID, (uint8_t *) &csi.chip_id);
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return slv_addr;
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#endif //(OMV_OV7725_ENABLE == 1) || (OMV_OV7670_ENABLE == 1) || (OMV_OV7690_ENABLE == 1)
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#if (OMV_MT9V0XX_ENABLE == 1)
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case MT9V0XX_SLV_ADDR:
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omv_i2c_readw(&csi.i2c_bus, slv_addr, ON_CHIP_ID, (uint16_t *) &csi.chip_id);
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omv_i2c_readw(csi.i2c, slv_addr, ON_CHIP_ID, (uint16_t *) &csi.chip_id);
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return slv_addr;
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#endif //(OMV_MT9V0XX_ENABLE == 1)
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#if (OMV_MT9M114_ENABLE == 1)
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case MT9M114_SLV_ADDR:
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omv_i2c_readw2(&csi.i2c_bus, slv_addr, ON_CHIP_ID, (uint16_t *) &csi.chip_id);
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omv_i2c_readw2(csi.i2c, slv_addr, ON_CHIP_ID, (uint16_t *) &csi.chip_id);
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return slv_addr;
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#endif // (OMV_MT9M114_ENABLE == 1)
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@ -279,7 +280,7 @@ static int omv_csi_detect() {
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#if (OMV_HM01B0_ENABLE == 1) || (OMV_HM0360_ENABLE == 1)
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case HM0XX0_SLV_ADDR:
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omv_i2c_readb2(&csi.i2c_bus, slv_addr, HIMAX_CHIP_ID, (uint8_t *) &csi.chip_id);
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omv_i2c_readb2(csi.i2c, slv_addr, HIMAX_CHIP_ID, (uint8_t *) &csi.chip_id);
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return slv_addr;
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#endif // (OMV_HM01B0_ENABLE == 1) || (OMV_HM0360_ENABLE == 1)
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@ -291,21 +292,21 @@ static int omv_csi_detect() {
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#if (OMV_PAG7920_ENABLE == 1)
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case PAG7920_SLV_ADDR:
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omv_i2c_readw2(&csi.i2c_bus, slv_addr, PIXART_CHIP_ID, (uint16_t *) &csi.chip_id);
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omv_i2c_readw2(csi.i2c, slv_addr, PIXART_CHIP_ID, (uint16_t *) &csi.chip_id);
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csi.chip_id = ((csi.chip_id << 8) | (csi.chip_id >> 8)) & 0xFFFF;
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return slv_addr;
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#endif // (OMV_PAG7920_ENABLE == 1)
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#if (OMV_PAG7936_ENABLE == 1)
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case PAG7936_SLV_ADDR:
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omv_i2c_readw2(&csi.i2c_bus, slv_addr, PIXART_CHIP_ID, (uint16_t *) &csi.chip_id);
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omv_i2c_readw2(csi.i2c, slv_addr, PIXART_CHIP_ID, (uint16_t *) &csi.chip_id);
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csi.chip_id = ((csi.chip_id << 8) | (csi.chip_id >> 8)) & 0xFFFF;
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return slv_addr;
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#endif // (OMV_PAG7936_ENABLE == 1)
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#if (OMV_PS5520_ENABLE == 1)
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case PS5520_SLV_ADDR:
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omv_i2c_readw2(&csi.i2c_bus, slv_addr, PIXART_CHIP_ID, (uint16_t *) &csi.chip_id);
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omv_i2c_readw2(csi.i2c, slv_addr, PIXART_CHIP_ID, (uint16_t *) &csi.chip_id);
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return slv_addr;
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#endif // (OMV_PS5520_ENABLE == 1)
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}
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@ -338,7 +339,7 @@ int omv_csi_probe_init(uint32_t bus_id, uint32_t bus_speed) {
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#endif
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// Initialize the camera bus.
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omv_i2c_init(&csi.i2c_bus, bus_id, bus_speed);
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omv_i2c_init(csi.i2c, bus_id, bus_speed);
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mp_hal_delay_ms(10);
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// Scan the bus multiple times using different reset and power-down
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@ -321,7 +321,7 @@ typedef struct _omv_csi {
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bool auto_rotation; // Rotate Image Automatically
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bool detected; // Set to true when the sensor is initialized.
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omv_i2c_t i2c_bus; // SCCB/I2C bus.
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omv_i2c_t *i2c; // SCCB/I2C bus.
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framebuffer_t *fb; // Frame buffer pointer
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@ -363,6 +363,7 @@ typedef struct _omv_csi {
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} omv_csi_t;
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extern omv_csi_t csi;
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extern omv_i2c_t csi_i2c;
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// Resolution table
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extern uint16_t resolution[][2];
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@ -39,14 +39,14 @@
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static uint8_t read_reg(uint8_t addr){
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uint8_t buf;
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omv_i2c_write_bytes(&csi.i2c_bus, csi.slv_addr, &addr, 1, OMV_I2C_XFER_NO_STOP);
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omv_i2c_read_bytes(&csi.i2c_bus, csi.slv_addr, &buf, 1, OMV_I2C_XFER_NO_FLAGS);
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omv_i2c_write_bytes(csi.i2c, csi.slv_addr, &addr, 1, OMV_I2C_XFER_NO_STOP);
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omv_i2c_read_bytes(csi.i2c, csi.slv_addr, &buf, 1, OMV_I2C_XFER_NO_FLAGS);
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return buf;
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}
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static void write_reg(uint8_t addr, uint8_t data) {
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uint8_t buf[] = {addr, data};
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omv_i2c_write_bytes(&csi.i2c_bus, csi.slv_addr, buf, 2, OMV_I2C_XFER_NO_FLAGS);
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omv_i2c_write_bytes(csi.i2c, csi.slv_addr, buf, 2, OMV_I2C_XFER_NO_FLAGS);
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}
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uint8_t FSLP_open_port() {
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@ -61,8 +61,8 @@
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*/
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void psee_sensor_read(uint16_t register_address, uint32_t *buf) {
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uint8_t addr[] = {(register_address >> 8), register_address};
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omv_i2c_write_bytes(&csi.i2c_bus, csi.slv_addr, addr, 2, OMV_I2C_XFER_NO_STOP);
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omv_i2c_read_bytes(&csi.i2c_bus, csi.slv_addr, (uint8_t *) buf, 4, OMV_I2C_XFER_NO_FLAGS);
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omv_i2c_write_bytes(csi.i2c, csi.slv_addr, addr, 2, OMV_I2C_XFER_NO_STOP);
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omv_i2c_read_bytes(csi.i2c, csi.slv_addr, (uint8_t *) buf, 4, OMV_I2C_XFER_NO_FLAGS);
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*buf = __REV(*buf);
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};
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@ -74,7 +74,7 @@ void psee_sensor_read(uint16_t register_address, uint32_t *buf) {
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void psee_sensor_write(uint16_t register_address, uint32_t register_data) {
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uint8_t buf[] = {(register_address >> 8), register_address,
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(register_data >> 24), (register_data >> 16), (register_data >> 8), register_data};
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omv_i2c_write_bytes(&csi.i2c_bus, csi.slv_addr, buf, 6, OMV_I2C_XFER_NO_FLAGS);
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omv_i2c_write_bytes(csi.i2c, csi.slv_addr, buf, 6, OMV_I2C_XFER_NO_FLAGS);
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};
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/**
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@ -85,8 +85,8 @@ void psee_sensor_write(uint16_t register_address, uint32_t register_data) {
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*/
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void psee_sensor_sequential_read(uint16_t reg, uint32_t *data, uint16_t n_word) {
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uint8_t buf[] = {(reg >> 8), reg};
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omv_i2c_write_bytes(&csi.i2c_bus, csi.slv_addr, buf, sizeof(buf), OMV_I2C_XFER_NO_STOP);
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omv_i2c_read_bytes(&csi.i2c_bus, csi.slv_addr, (uint8_t *) data, n_word * sizeof(uint32_t),
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omv_i2c_write_bytes(csi.i2c, csi.slv_addr, buf, sizeof(buf), OMV_I2C_XFER_NO_STOP);
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omv_i2c_read_bytes(csi.i2c, csi.slv_addr, (uint8_t *) data, n_word * sizeof(uint32_t),
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OMV_I2C_XFER_NO_FLAGS);
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for (int32_t i = 0; i < n_word; i++) {
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data[i] = __builtin_bswap32(data[i]);
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@ -99,7 +99,7 @@ void psee_sensor_sequential_read(uint16_t reg, uint32_t *data, uint16_t n_word)
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* @param n_bytes Total number of bytes that needs to be written
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*/
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void psee_sensor_sequential_write(uint8_t *register_data, uint16_t n_bytes) {
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omv_i2c_write_bytes(&csi.i2c_bus, csi.slv_addr, register_data, n_bytes, OMV_I2C_XFER_NO_FLAGS);
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omv_i2c_write_bytes(csi.i2c, csi.slv_addr, register_data, n_bytes, OMV_I2C_XFER_NO_FLAGS);
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}
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/**
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@ -747,7 +747,7 @@ static int reset(omv_csi_t *csi) {
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// Write default registers
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for (int i = 0; default_regs[i][0]; i++) {
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ret |= omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, default_regs[i][0], default_regs[i][1]);
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ret |= omv_i2c_writeb(csi->i2c, csi->slv_addr, default_regs[i][0], default_regs[i][1]);
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}
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// Delay 10 ms
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@ -760,13 +760,13 @@ static int sleep(omv_csi_t *csi, int enable) {
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int ret = 0;
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if (enable) {
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ret |= omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, 0xF2, 0x0);
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ret |= omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, 0xF7, 0x10);
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ret |= omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, 0xFC, 0x01);
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ret |= omv_i2c_writeb(csi->i2c, csi->slv_addr, 0xF2, 0x0);
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ret |= omv_i2c_writeb(csi->i2c, csi->slv_addr, 0xF7, 0x10);
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ret |= omv_i2c_writeb(csi->i2c, csi->slv_addr, 0xFC, 0x01);
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} else {
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ret |= omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, 0xF2, 0x0F);
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ret |= omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, 0xF7, 0x1d);
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ret |= omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, 0xFC, 0x06);
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ret |= omv_i2c_writeb(csi->i2c, csi->slv_addr, 0xF2, 0x0F);
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ret |= omv_i2c_writeb(csi->i2c, csi->slv_addr, 0xF7, 0x1d);
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ret |= omv_i2c_writeb(csi->i2c, csi->slv_addr, 0xFC, 0x06);
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}
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return ret;
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@ -774,14 +774,14 @@ static int sleep(omv_csi_t *csi, int enable) {
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static int read_reg(omv_csi_t *csi, uint16_t reg_addr) {
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uint8_t reg_data;
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if (omv_i2c_readb(&csi->i2c_bus, csi->slv_addr, reg_addr, ®_data) != 0) {
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if (omv_i2c_readb(csi->i2c, csi->slv_addr, reg_addr, ®_data) != 0) {
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return -1;
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}
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return reg_data;
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}
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static int write_reg(omv_csi_t *csi, uint16_t reg_addr, uint16_t reg_data) {
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return omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, reg_addr, reg_data);
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return omv_i2c_writeb(csi->i2c, csi->slv_addr, reg_addr, reg_data);
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}
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static int set_pixformat(omv_csi_t *csi, pixformat_t pixformat) {
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@ -789,23 +789,23 @@ static int set_pixformat(omv_csi_t *csi, pixformat_t pixformat) {
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uint8_t reg;
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|
||||
// P0 regs
|
||||
ret |= omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, 0xFE, 0x00);
|
||||
ret |= omv_i2c_writeb(csi->i2c, csi->slv_addr, 0xFE, 0x00);
|
||||
|
||||
// Read current output format reg
|
||||
ret |= omv_i2c_readb(&csi->i2c_bus, csi->slv_addr, REG_OUTPUT_FMT, ®);
|
||||
ret |= omv_i2c_readb(csi->i2c, csi->slv_addr, REG_OUTPUT_FMT, ®);
|
||||
|
||||
switch (pixformat) {
|
||||
case PIXFORMAT_RGB565:
|
||||
ret |= omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr,
|
||||
ret |= omv_i2c_writeb(csi->i2c, csi->slv_addr,
|
||||
REG_OUTPUT_FMT, REG_OUTPUT_SET_FMT(reg, REG_OUTPUT_FMT_RGB565));
|
||||
break;
|
||||
case PIXFORMAT_YUV422:
|
||||
case PIXFORMAT_GRAYSCALE:
|
||||
ret |= omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr,
|
||||
ret |= omv_i2c_writeb(csi->i2c, csi->slv_addr,
|
||||
REG_OUTPUT_FMT, REG_OUTPUT_SET_FMT(reg, REG_OUTPUT_FMT_YCBYCR));
|
||||
break;
|
||||
case PIXFORMAT_BAYER:
|
||||
ret |= omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr,
|
||||
ret |= omv_i2c_writeb(csi->i2c, csi->slv_addr,
|
||||
REG_OUTPUT_FMT, REG_OUTPUT_SET_FMT(reg, REG_OUTPUT_FMT_BAYER));
|
||||
break;
|
||||
default:
|
||||
@ -819,23 +819,23 @@ static int set_window(omv_csi_t *csi, uint16_t reg, uint16_t x, uint16_t y, uint
|
||||
int ret = 0;
|
||||
|
||||
// P0 regs
|
||||
ret |= omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, 0xFE, 0x00);
|
||||
ret |= omv_i2c_writeb(csi->i2c, csi->slv_addr, 0xFE, 0x00);
|
||||
|
||||
// Y/row offset
|
||||
ret |= omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, reg++, y >> 8);
|
||||
ret |= omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, reg++, y & 0xff);
|
||||
ret |= omv_i2c_writeb(csi->i2c, csi->slv_addr, reg++, y >> 8);
|
||||
ret |= omv_i2c_writeb(csi->i2c, csi->slv_addr, reg++, y & 0xff);
|
||||
|
||||
// X/col offset
|
||||
ret |= omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, reg++, x >> 8);
|
||||
ret |= omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, reg++, x & 0xff);
|
||||
ret |= omv_i2c_writeb(csi->i2c, csi->slv_addr, reg++, x >> 8);
|
||||
ret |= omv_i2c_writeb(csi->i2c, csi->slv_addr, reg++, x & 0xff);
|
||||
|
||||
// Window height
|
||||
ret |= omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, reg++, h >> 8);
|
||||
ret |= omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, reg++, h & 0xff);
|
||||
ret |= omv_i2c_writeb(csi->i2c, csi->slv_addr, reg++, h >> 8);
|
||||
ret |= omv_i2c_writeb(csi->i2c, csi->slv_addr, reg++, h & 0xff);
|
||||
|
||||
// Window width
|
||||
ret |= omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, reg++, w >> 8);
|
||||
ret |= omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, reg++, w & 0xff);
|
||||
ret |= omv_i2c_writeb(csi->i2c, csi->slv_addr, reg++, w >> 8);
|
||||
ret |= omv_i2c_writeb(csi->i2c, csi->slv_addr, reg++, w & 0xff);
|
||||
|
||||
return ret;
|
||||
}
|
||||
@ -896,11 +896,11 @@ static int set_framesize(omv_csi_t *csi, omv_csi_framesize_t framesize) {
|
||||
ret |= set_window(csi, 0x91, 0, 0, w, h);
|
||||
|
||||
// Enable crop
|
||||
ret |= omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, 0x90, 0x01);
|
||||
ret |= omv_i2c_writeb(csi->i2c, csi->slv_addr, 0x90, 0x01);
|
||||
|
||||
// Set Sub-sampling ratio and mode
|
||||
ret |= omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, 0x99, ((ratio << 4) | (ratio)));
|
||||
ret |= omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, 0x9A, 0x0E);
|
||||
ret |= omv_i2c_writeb(csi->i2c, csi->slv_addr, 0x99, ((ratio << 4) | (ratio)));
|
||||
ret |= omv_i2c_writeb(csi->i2c, csi->slv_addr, 0x9A, 0x0E);
|
||||
|
||||
return ret;
|
||||
}
|
||||
@ -913,9 +913,9 @@ static int set_hmirror(omv_csi_t *csi, int enable) {
|
||||
#endif
|
||||
|
||||
// P0 regs
|
||||
ret |= omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, 0xFE, 0x00);
|
||||
ret |= omv_i2c_readb(&csi->i2c_bus, csi->slv_addr, REG_AMODE1, ®);
|
||||
ret |= omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, REG_AMODE1, REG_AMODE1_SET_HMIRROR(reg, enable));
|
||||
ret |= omv_i2c_writeb(csi->i2c, csi->slv_addr, 0xFE, 0x00);
|
||||
ret |= omv_i2c_readb(csi->i2c, csi->slv_addr, REG_AMODE1, ®);
|
||||
ret |= omv_i2c_writeb(csi->i2c, csi->slv_addr, REG_AMODE1, REG_AMODE1_SET_HMIRROR(reg, enable));
|
||||
return ret;
|
||||
}
|
||||
|
||||
@ -927,27 +927,27 @@ static int set_vflip(omv_csi_t *csi, int enable) {
|
||||
#endif
|
||||
|
||||
// P0 regs
|
||||
ret |= omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, 0xFE, 0x00);
|
||||
ret |= omv_i2c_readb(&csi->i2c_bus, csi->slv_addr, REG_AMODE1, ®);
|
||||
ret |= omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, REG_AMODE1, REG_AMODE1_SET_VMIRROR(reg, enable));
|
||||
ret |= omv_i2c_writeb(csi->i2c, csi->slv_addr, 0xFE, 0x00);
|
||||
ret |= omv_i2c_readb(csi->i2c, csi->slv_addr, REG_AMODE1, ®);
|
||||
ret |= omv_i2c_writeb(csi->i2c, csi->slv_addr, REG_AMODE1, REG_AMODE1_SET_VMIRROR(reg, enable));
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int set_auto_exposure(omv_csi_t *csi, int enable, int exposure_us) {
|
||||
int ret = 0;
|
||||
uint8_t reg;
|
||||
ret |= omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, 0xFE, 0x00);
|
||||
ret |= omv_i2c_readb(&csi->i2c_bus, csi->slv_addr, 0xb6, ®);
|
||||
ret |= omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, 0xb6, (reg & 0xFE) | (enable & 0x01));
|
||||
ret |= omv_i2c_writeb(csi->i2c, csi->slv_addr, 0xFE, 0x00);
|
||||
ret |= omv_i2c_readb(csi->i2c, csi->slv_addr, 0xb6, ®);
|
||||
ret |= omv_i2c_writeb(csi->i2c, csi->slv_addr, 0xb6, (reg & 0xFE) | (enable & 0x01));
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int set_auto_whitebal(omv_csi_t *csi, int enable, float r_gain_db, float g_gain_db, float b_gain_db) {
|
||||
int ret = 0;
|
||||
uint8_t reg;
|
||||
ret |= omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, 0xFE, 0x00);
|
||||
ret |= omv_i2c_readb(&csi->i2c_bus, csi->slv_addr, 0x82, ®);
|
||||
ret |= omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, 0x82, (reg & 0xFD) | ((enable & 0x01) << 1));
|
||||
ret |= omv_i2c_writeb(csi->i2c, csi->slv_addr, 0xFE, 0x00);
|
||||
ret |= omv_i2c_readb(csi->i2c, csi->slv_addr, 0x82, ®);
|
||||
ret |= omv_i2c_writeb(csi->i2c, csi->slv_addr, 0x82, (reg & 0xFD) | ((enable & 0x01) << 1));
|
||||
return ret;
|
||||
}
|
||||
|
||||
|
||||
@ -200,10 +200,10 @@ static int sleep(omv_csi_t *csi, int enable) {
|
||||
static int read_reg(omv_csi_t *csi, uint16_t reg_addr) {
|
||||
uint32_t reg_data;
|
||||
uint8_t addr[] = {(reg_addr >> 8), reg_addr};
|
||||
if (omv_i2c_write_bytes(&csi->i2c_bus, csi->slv_addr, addr, 2, OMV_I2C_XFER_NO_STOP) != 0) {
|
||||
if (omv_i2c_write_bytes(csi->i2c, csi->slv_addr, addr, 2, OMV_I2C_XFER_NO_STOP) != 0) {
|
||||
return -1;
|
||||
}
|
||||
if (omv_i2c_read_bytes(&csi->i2c_bus, csi->slv_addr, (uint8_t *) ®_data, 4, OMV_I2C_XFER_NO_FLAGS) != 0) {
|
||||
if (omv_i2c_read_bytes(csi->i2c, csi->slv_addr, (uint8_t *) ®_data, 4, OMV_I2C_XFER_NO_FLAGS) != 0) {
|
||||
return -1;
|
||||
}
|
||||
reg_data = __REV(reg_data);
|
||||
@ -212,7 +212,7 @@ static int read_reg(omv_csi_t *csi, uint16_t reg_addr) {
|
||||
|
||||
static int write_reg(omv_csi_t *csi, uint16_t reg_addr, uint16_t reg_data) {
|
||||
uint8_t buf[] = {(reg_addr >> 8), reg_addr, (reg_data >> 24), (reg_data >> 16), (reg_data >> 8), reg_data};
|
||||
return omv_i2c_write_bytes(&csi->i2c_bus, csi->slv_addr, buf, 6, OMV_I2C_XFER_NO_FLAGS);
|
||||
return omv_i2c_write_bytes(csi->i2c, csi->slv_addr, buf, 6, OMV_I2C_XFER_NO_FLAGS);
|
||||
}
|
||||
|
||||
static int set_pixformat(omv_csi_t *csi, pixformat_t pixformat) {
|
||||
|
||||
@ -143,13 +143,13 @@ static int reset(omv_csi_t *csi) {
|
||||
// Reset csi.
|
||||
uint8_t reg = 0xff;
|
||||
for (int retry = HIMAX_BOOT_RETRY; retry >= 0 && reg != HIMAX_MODE_STANDBY; retry--) {
|
||||
if (omv_i2c_writeb2(&csi->i2c_bus, csi->slv_addr, SW_RESET, HIMAX_RESET) != 0) {
|
||||
if (omv_i2c_writeb2(csi->i2c, csi->slv_addr, SW_RESET, HIMAX_RESET) != 0) {
|
||||
return -1;
|
||||
}
|
||||
|
||||
mp_hal_delay_ms(1);
|
||||
|
||||
if (omv_i2c_readb2(&csi->i2c_bus, csi->slv_addr, MODE_SELECT, ®) != 0) {
|
||||
if (omv_i2c_readb2(csi->i2c, csi->slv_addr, MODE_SELECT, ®) != 0) {
|
||||
return -1;
|
||||
}
|
||||
|
||||
@ -165,28 +165,28 @@ static int reset(omv_csi_t *csi) {
|
||||
// Write default registers
|
||||
int ret = 0;
|
||||
for (int i = 0; default_regs[i][0] && ret == 0; i++) {
|
||||
ret |= omv_i2c_writeb2(&csi->i2c_bus, csi->slv_addr, default_regs[i][0], default_regs[i][1]);
|
||||
ret |= omv_i2c_writeb2(csi->i2c, csi->slv_addr, default_regs[i][0], default_regs[i][1]);
|
||||
}
|
||||
|
||||
// Set PCLK polarity.
|
||||
ret |= omv_i2c_writeb2(&csi->i2c_bus, csi->slv_addr, PCLK_POLARITY, (0x20 | PCLK_FALLING_EDGE));
|
||||
ret |= omv_i2c_writeb2(csi->i2c, csi->slv_addr, PCLK_POLARITY, (0x20 | PCLK_FALLING_EDGE));
|
||||
|
||||
// Set mode to streaming
|
||||
ret |= omv_i2c_writeb2(&csi->i2c_bus, csi->slv_addr, MODE_SELECT, HIMAX_MODE_STREAMING);
|
||||
ret |= omv_i2c_writeb2(csi->i2c, csi->slv_addr, MODE_SELECT, HIMAX_MODE_STREAMING);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int read_reg(omv_csi_t *csi, uint16_t reg_addr) {
|
||||
uint8_t reg_data;
|
||||
if (omv_i2c_readb2(&csi->i2c_bus, csi->slv_addr, reg_addr, ®_data) != 0) {
|
||||
if (omv_i2c_readb2(csi->i2c, csi->slv_addr, reg_addr, ®_data) != 0) {
|
||||
return -1;
|
||||
}
|
||||
return reg_data;
|
||||
}
|
||||
|
||||
static int write_reg(omv_csi_t *csi, uint16_t reg_addr, uint16_t reg_data) {
|
||||
return omv_i2c_writeb2(&csi->i2c_bus, csi->slv_addr, reg_addr, reg_data);
|
||||
return omv_i2c_writeb2(csi->i2c, csi->slv_addr, reg_addr, reg_data);
|
||||
}
|
||||
|
||||
static int set_pixformat(omv_csi_t *csi, pixformat_t pixformat) {
|
||||
@ -260,17 +260,17 @@ static int set_framesize(omv_csi_t *csi, omv_csi_framesize_t framesize) {
|
||||
switch (framesize) {
|
||||
case OMV_CSI_FRAMESIZE_320X320:
|
||||
for (int i = 0; FULL_regs[i][0] && ret == 0; i++) {
|
||||
ret |= omv_i2c_writeb2(&csi->i2c_bus, csi->slv_addr, FULL_regs[i][0], FULL_regs[i][1]);
|
||||
ret |= omv_i2c_writeb2(csi->i2c, csi->slv_addr, FULL_regs[i][0], FULL_regs[i][1]);
|
||||
}
|
||||
break;
|
||||
case OMV_CSI_FRAMESIZE_QVGA:
|
||||
for (int i = 0; QVGA_regs[i][0] && ret == 0; i++) {
|
||||
ret |= omv_i2c_writeb2(&csi->i2c_bus, csi->slv_addr, QVGA_regs[i][0], QVGA_regs[i][1]);
|
||||
ret |= omv_i2c_writeb2(csi->i2c, csi->slv_addr, QVGA_regs[i][0], QVGA_regs[i][1]);
|
||||
}
|
||||
break;
|
||||
case OMV_CSI_FRAMESIZE_QQVGA:
|
||||
for (int i = 0; QQVGA_regs[i][0] && ret == 0; i++) {
|
||||
ret |= omv_i2c_writeb2(&csi->i2c_bus, csi->slv_addr, QQVGA_regs[i][0], QQVGA_regs[i][1]);
|
||||
ret |= omv_i2c_writeb2(csi->i2c, csi->slv_addr, QQVGA_regs[i][0], QQVGA_regs[i][1]);
|
||||
}
|
||||
break;
|
||||
default:
|
||||
@ -302,7 +302,7 @@ static int set_framerate(omv_csi_t *csi, int framerate) {
|
||||
} else {
|
||||
osc_div = 0x03; // Set to the max possible FPS at this resolution.
|
||||
}
|
||||
return omv_i2c_writeb2(&csi->i2c_bus, csi->slv_addr, OSC_CLK_DIV, 0x08 | osc_div);
|
||||
return omv_i2c_writeb2(csi->i2c, csi->slv_addr, OSC_CLK_DIV, 0x08 | osc_div);
|
||||
}
|
||||
|
||||
static int set_brightness(omv_csi_t *csi, int level) {
|
||||
@ -324,7 +324,7 @@ static int set_brightness(omv_csi_t *csi, int level) {
|
||||
default:
|
||||
ae_mean = 60;
|
||||
}
|
||||
return omv_i2c_writeb2(&csi->i2c_bus, csi->slv_addr, AE_TARGET_MEAN, ae_mean);
|
||||
return omv_i2c_writeb2(csi->i2c, csi->slv_addr, AE_TARGET_MEAN, ae_mean);
|
||||
}
|
||||
|
||||
static int set_gainceiling(omv_csi_t *csi, omv_csi_gainceiling_t gainceiling) {
|
||||
@ -346,13 +346,13 @@ static int set_gainceiling(omv_csi_t *csi, omv_csi_gainceiling_t gainceiling) {
|
||||
default:
|
||||
return -1;
|
||||
}
|
||||
ret |= omv_i2c_writeb2(&csi->i2c_bus, csi->slv_addr, MAX_AGAIN_FULL, gain);
|
||||
ret |= omv_i2c_writeb2(&csi->i2c_bus, csi->slv_addr, MAX_AGAIN_BIN2, gain);
|
||||
ret |= omv_i2c_writeb2(csi->i2c, csi->slv_addr, MAX_AGAIN_FULL, gain);
|
||||
ret |= omv_i2c_writeb2(csi->i2c, csi->slv_addr, MAX_AGAIN_BIN2, gain);
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int set_colorbar(omv_csi_t *csi, int enable) {
|
||||
return omv_i2c_writeb2(&csi->i2c_bus, csi->slv_addr, TEST_PATTERN_MODE, enable & 0x1);
|
||||
return omv_i2c_writeb2(csi->i2c, csi->slv_addr, TEST_PATTERN_MODE, enable & 0x1);
|
||||
}
|
||||
|
||||
static int set_auto_gain(omv_csi_t *csi, int enable, float gain_db, float gain_db_ceiling) {
|
||||
@ -360,22 +360,22 @@ static int set_auto_gain(omv_csi_t *csi, int enable, float gain_db, float gain_d
|
||||
if ((enable == 0) && (!isnanf(gain_db)) && (!isinff(gain_db))) {
|
||||
gain_db = IM_CLAMP(gain_db, 0.0f, 24.0f);
|
||||
int gain = fast_ceilf(logf(expf((gain_db / 20.0f) * M_LN10)) / M_LN2);
|
||||
ret |= omv_i2c_writeb2(&csi->i2c_bus, csi->slv_addr, AE_CTRL, 0); // Must disable AE
|
||||
ret |= omv_i2c_writeb2(&csi->i2c_bus, csi->slv_addr, ANALOG_GAIN, ((gain & 0x7) << 4));
|
||||
ret |= omv_i2c_writeb2(&csi->i2c_bus, csi->slv_addr, GRP_PARAM_HOLD, 0x01);
|
||||
ret |= omv_i2c_writeb2(csi->i2c, csi->slv_addr, AE_CTRL, 0); // Must disable AE
|
||||
ret |= omv_i2c_writeb2(csi->i2c, csi->slv_addr, ANALOG_GAIN, ((gain & 0x7) << 4));
|
||||
ret |= omv_i2c_writeb2(csi->i2c, csi->slv_addr, GRP_PARAM_HOLD, 0x01);
|
||||
} else if ((enable != 0) && (!isnanf(gain_db_ceiling)) && (!isinff(gain_db_ceiling))) {
|
||||
gain_db_ceiling = IM_CLAMP(gain_db_ceiling, 0.0f, 24.0f);
|
||||
int gain = fast_ceilf(logf(expf((gain_db_ceiling / 20.0f) * M_LN10) / M_LN2));
|
||||
ret |= omv_i2c_writeb2(&csi->i2c_bus, csi->slv_addr, MAX_AGAIN_FULL, (gain & 0x7));
|
||||
ret |= omv_i2c_writeb2(&csi->i2c_bus, csi->slv_addr, MAX_AGAIN_BIN2, (gain & 0x7));
|
||||
ret |= omv_i2c_writeb2(&csi->i2c_bus, csi->slv_addr, AE_CTRL, 1);
|
||||
ret |= omv_i2c_writeb2(csi->i2c, csi->slv_addr, MAX_AGAIN_FULL, (gain & 0x7));
|
||||
ret |= omv_i2c_writeb2(csi->i2c, csi->slv_addr, MAX_AGAIN_BIN2, (gain & 0x7));
|
||||
ret |= omv_i2c_writeb2(csi->i2c, csi->slv_addr, AE_CTRL, 1);
|
||||
}
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int get_gain_db(omv_csi_t *csi, float *gain_db) {
|
||||
uint8_t gain;
|
||||
if (omv_i2c_readb2(&csi->i2c_bus, csi->slv_addr, ANALOG_GAIN, &gain) != 0) {
|
||||
if (omv_i2c_readb2(csi->i2c, csi->slv_addr, ANALOG_GAIN, &gain) != 0) {
|
||||
return -1;
|
||||
}
|
||||
*gain_db = fast_floorf(log10f(1 << (gain >> 4)) * 20.0f);
|
||||
@ -384,7 +384,7 @@ static int get_gain_db(omv_csi_t *csi, float *gain_db) {
|
||||
|
||||
static int get_vt_pix_clk(omv_csi_t *csi, uint32_t *vt_pix_clk) {
|
||||
uint8_t reg;
|
||||
if (omv_i2c_readb2(&csi->i2c_bus, csi->slv_addr, OSC_CLK_DIV, ®) != 0) {
|
||||
if (omv_i2c_readb2(csi->i2c, csi->slv_addr, OSC_CLK_DIV, ®) != 0) {
|
||||
return -1;
|
||||
}
|
||||
// 00 -> MCLK / 8
|
||||
@ -402,7 +402,7 @@ static int set_auto_exposure(omv_csi_t *csi, int enable, int exposure_us) {
|
||||
int ret = 0;
|
||||
|
||||
if (enable) {
|
||||
ret |= omv_i2c_writeb2(&csi->i2c_bus, csi->slv_addr, AE_CTRL, 1);
|
||||
ret |= omv_i2c_writeb2(csi->i2c, csi->slv_addr, AE_CTRL, 1);
|
||||
} else {
|
||||
uint32_t line_len;
|
||||
uint32_t frame_len;
|
||||
@ -435,10 +435,10 @@ static int set_auto_exposure(omv_csi_t *csi, int enable, int exposure_us) {
|
||||
coarse_int = frame_len - 2;
|
||||
}
|
||||
|
||||
ret |= omv_i2c_writeb2(&csi->i2c_bus, csi->slv_addr, AE_CTRL, 0);
|
||||
ret |= omv_i2c_writeb2(&csi->i2c_bus, csi->slv_addr, INTEGRATION_H, coarse_int >> 8);
|
||||
ret |= omv_i2c_writeb2(&csi->i2c_bus, csi->slv_addr, INTEGRATION_L, coarse_int & 0xff);
|
||||
ret |= omv_i2c_writeb2(&csi->i2c_bus, csi->slv_addr, GRP_PARAM_HOLD, 0x01);
|
||||
ret |= omv_i2c_writeb2(csi->i2c, csi->slv_addr, AE_CTRL, 0);
|
||||
ret |= omv_i2c_writeb2(csi->i2c, csi->slv_addr, INTEGRATION_H, coarse_int >> 8);
|
||||
ret |= omv_i2c_writeb2(csi->i2c, csi->slv_addr, INTEGRATION_L, coarse_int & 0xff);
|
||||
ret |= omv_i2c_writeb2(csi->i2c, csi->slv_addr, GRP_PARAM_HOLD, 0x01);
|
||||
}
|
||||
|
||||
return ret;
|
||||
@ -455,25 +455,25 @@ static int get_exposure_us(omv_csi_t *csi, int *exposure_us) {
|
||||
line_len = HIMAX_LINE_LEN_PCK_QQVGA;
|
||||
}
|
||||
ret |= get_vt_pix_clk(csi, &vt_pix_clk);
|
||||
ret |= omv_i2c_readb2(&csi->i2c_bus, csi->slv_addr, INTEGRATION_H, &((uint8_t *) &coarse_int)[1]);
|
||||
ret |= omv_i2c_readb2(&csi->i2c_bus, csi->slv_addr, INTEGRATION_L, &((uint8_t *) &coarse_int)[0]);
|
||||
ret |= omv_i2c_readb2(csi->i2c, csi->slv_addr, INTEGRATION_H, &((uint8_t *) &coarse_int)[1]);
|
||||
ret |= omv_i2c_readb2(csi->i2c, csi->slv_addr, INTEGRATION_L, &((uint8_t *) &coarse_int)[0]);
|
||||
*exposure_us = fast_roundf(coarse_int * line_len / (vt_pix_clk / 1000000.0f));
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int set_hmirror(omv_csi_t *csi, int enable) {
|
||||
uint8_t reg;
|
||||
int ret = omv_i2c_readb2(&csi->i2c_bus, csi->slv_addr, IMG_ORIENTATION, ®);
|
||||
ret |= omv_i2c_writeb2(&csi->i2c_bus, csi->slv_addr, IMG_ORIENTATION, HIMAX_SET_HMIRROR(reg, enable));
|
||||
ret |= omv_i2c_writeb2(&csi->i2c_bus, csi->slv_addr, GRP_PARAM_HOLD, 0x01);
|
||||
int ret = omv_i2c_readb2(csi->i2c, csi->slv_addr, IMG_ORIENTATION, ®);
|
||||
ret |= omv_i2c_writeb2(csi->i2c, csi->slv_addr, IMG_ORIENTATION, HIMAX_SET_HMIRROR(reg, enable));
|
||||
ret |= omv_i2c_writeb2(csi->i2c, csi->slv_addr, GRP_PARAM_HOLD, 0x01);
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int set_vflip(omv_csi_t *csi, int enable) {
|
||||
uint8_t reg;
|
||||
int ret = omv_i2c_readb2(&csi->i2c_bus, csi->slv_addr, IMG_ORIENTATION, ®);
|
||||
ret |= omv_i2c_writeb2(&csi->i2c_bus, csi->slv_addr, IMG_ORIENTATION, HIMAX_SET_VMIRROR(reg, enable));
|
||||
ret |= omv_i2c_writeb2(&csi->i2c_bus, csi->slv_addr, GRP_PARAM_HOLD, 0x01);
|
||||
int ret = omv_i2c_readb2(csi->i2c, csi->slv_addr, IMG_ORIENTATION, ®);
|
||||
ret |= omv_i2c_writeb2(csi->i2c, csi->slv_addr, IMG_ORIENTATION, HIMAX_SET_VMIRROR(reg, enable));
|
||||
ret |= omv_i2c_writeb2(csi->i2c, csi->slv_addr, GRP_PARAM_HOLD, 0x01);
|
||||
return ret;
|
||||
}
|
||||
|
||||
@ -483,14 +483,14 @@ static int ioctl(omv_csi_t *csi, int request, va_list ap) {
|
||||
switch (request) {
|
||||
case OMV_CSI_IOCTL_HIMAX_OSC_ENABLE: {
|
||||
uint32_t enable = va_arg(ap, uint32_t);
|
||||
ret = omv_i2c_writeb2(&csi->i2c_bus, csi->slv_addr, ANA_Register_17, enable ? 1:0);
|
||||
ret = omv_i2c_writeb2(csi->i2c, csi->slv_addr, ANA_Register_17, enable ? 1:0);
|
||||
mp_hal_delay_ms(100);
|
||||
break;
|
||||
}
|
||||
|
||||
case OMV_CSI_IOCTL_HIMAX_MD_ENABLE: {
|
||||
uint32_t enable = va_arg(ap, uint32_t);
|
||||
ret = omv_i2c_writeb2(&csi->i2c_bus, csi->slv_addr, MD_CTRL, enable ? 1:0);
|
||||
ret = omv_i2c_writeb2(csi->i2c, csi->slv_addr, MD_CTRL, enable ? 1:0);
|
||||
break;
|
||||
}
|
||||
|
||||
@ -499,25 +499,25 @@ static int ioctl(omv_csi_t *csi, int request, va_list ap) {
|
||||
uint32_t y1 = va_arg(ap, uint32_t);
|
||||
uint32_t x2 = va_arg(ap, uint32_t) + x1;
|
||||
uint32_t y2 = va_arg(ap, uint32_t) + y1;
|
||||
ret |= omv_i2c_writeb2(&csi->i2c_bus, csi->slv_addr, MD_LROI_X_START_H, (x1 >> 8));
|
||||
ret |= omv_i2c_writeb2(&csi->i2c_bus, csi->slv_addr, MD_LROI_X_START_L, (x1 & 0xff));
|
||||
ret |= omv_i2c_writeb2(&csi->i2c_bus, csi->slv_addr, MD_LROI_Y_START_H, (y1 >> 8));
|
||||
ret |= omv_i2c_writeb2(&csi->i2c_bus, csi->slv_addr, MD_LROI_Y_START_L, (y1 & 0xff));
|
||||
ret |= omv_i2c_writeb2(&csi->i2c_bus, csi->slv_addr, MD_LROI_X_END_H, (x2 >> 8));
|
||||
ret |= omv_i2c_writeb2(&csi->i2c_bus, csi->slv_addr, MD_LROI_X_END_L, (x2 & 0xff));
|
||||
ret |= omv_i2c_writeb2(&csi->i2c_bus, csi->slv_addr, MD_LROI_Y_END_H, (y2 >> 8));
|
||||
ret |= omv_i2c_writeb2(&csi->i2c_bus, csi->slv_addr, MD_LROI_Y_END_L, (y2 & 0xff));
|
||||
ret |= omv_i2c_writeb2(csi->i2c, csi->slv_addr, MD_LROI_X_START_H, (x1 >> 8));
|
||||
ret |= omv_i2c_writeb2(csi->i2c, csi->slv_addr, MD_LROI_X_START_L, (x1 & 0xff));
|
||||
ret |= omv_i2c_writeb2(csi->i2c, csi->slv_addr, MD_LROI_Y_START_H, (y1 >> 8));
|
||||
ret |= omv_i2c_writeb2(csi->i2c, csi->slv_addr, MD_LROI_Y_START_L, (y1 & 0xff));
|
||||
ret |= omv_i2c_writeb2(csi->i2c, csi->slv_addr, MD_LROI_X_END_H, (x2 >> 8));
|
||||
ret |= omv_i2c_writeb2(csi->i2c, csi->slv_addr, MD_LROI_X_END_L, (x2 & 0xff));
|
||||
ret |= omv_i2c_writeb2(csi->i2c, csi->slv_addr, MD_LROI_Y_END_H, (y2 >> 8));
|
||||
ret |= omv_i2c_writeb2(csi->i2c, csi->slv_addr, MD_LROI_Y_END_L, (y2 & 0xff));
|
||||
break;
|
||||
}
|
||||
|
||||
case OMV_CSI_IOCTL_HIMAX_MD_THRESHOLD: {
|
||||
uint32_t threshold = va_arg(ap, uint32_t);
|
||||
ret = omv_i2c_writeb2(&csi->i2c_bus, csi->slv_addr, MD_THL, threshold);
|
||||
ret = omv_i2c_writeb2(csi->i2c, csi->slv_addr, MD_THL, threshold);
|
||||
break;
|
||||
}
|
||||
|
||||
case OMV_CSI_IOCTL_HIMAX_MD_CLEAR: {
|
||||
ret = omv_i2c_writeb2(&csi->i2c_bus, csi->slv_addr, I2C_CLEAR, 1);
|
||||
ret = omv_i2c_writeb2(csi->i2c, csi->slv_addr, I2C_CLEAR, 1);
|
||||
break;
|
||||
}
|
||||
|
||||
|
||||
@ -342,13 +342,13 @@ static int reset(omv_csi_t *csi) {
|
||||
// Reset csi.
|
||||
uint8_t reg = 0xff;
|
||||
for (int retry = HIMAX_BOOT_RETRY; retry >= 0 && reg != HIMAX_MODE_STANDBY; retry--) {
|
||||
if (omv_i2c_writeb2(&csi->i2c_bus, csi->slv_addr, SW_RESET, HIMAX_RESET) != 0) {
|
||||
if (omv_i2c_writeb2(csi->i2c, csi->slv_addr, SW_RESET, HIMAX_RESET) != 0) {
|
||||
return -1;
|
||||
}
|
||||
|
||||
mp_hal_delay_ms(1);
|
||||
|
||||
if (omv_i2c_readb2(&csi->i2c_bus, csi->slv_addr, MODE_SELECT, ®) != 0) {
|
||||
if (omv_i2c_readb2(csi->i2c, csi->slv_addr, MODE_SELECT, ®) != 0) {
|
||||
return -1;
|
||||
}
|
||||
|
||||
@ -364,25 +364,25 @@ static int reset(omv_csi_t *csi) {
|
||||
// Write default registers
|
||||
int ret = 0;
|
||||
for (int i = 0; default_regs[i][0] && ret == 0; i++) {
|
||||
ret |= omv_i2c_writeb2(&csi->i2c_bus, csi->slv_addr, default_regs[i][0], default_regs[i][1]);
|
||||
ret |= omv_i2c_writeb2(csi->i2c, csi->slv_addr, default_regs[i][0], default_regs[i][1]);
|
||||
}
|
||||
|
||||
// Set mode to streaming
|
||||
ret |= omv_i2c_writeb2(&csi->i2c_bus, csi->slv_addr, MODE_SELECT, HIMAX_MODE_STREAMING);
|
||||
ret |= omv_i2c_writeb2(csi->i2c, csi->slv_addr, MODE_SELECT, HIMAX_MODE_STREAMING);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int read_reg(omv_csi_t *csi, uint16_t reg_addr) {
|
||||
uint8_t reg_data;
|
||||
if (omv_i2c_readb2(&csi->i2c_bus, csi->slv_addr, reg_addr, ®_data) != 0) {
|
||||
if (omv_i2c_readb2(csi->i2c, csi->slv_addr, reg_addr, ®_data) != 0) {
|
||||
return -1;
|
||||
}
|
||||
return reg_data;
|
||||
}
|
||||
|
||||
static int write_reg(omv_csi_t *csi, uint16_t reg_addr, uint16_t reg_data) {
|
||||
return omv_i2c_writeb2(&csi->i2c_bus, csi->slv_addr, reg_addr, reg_data);
|
||||
return omv_i2c_writeb2(csi->i2c, csi->slv_addr, reg_addr, reg_data);
|
||||
}
|
||||
|
||||
static int set_pixformat(omv_csi_t *csi, pixformat_t pixformat) {
|
||||
@ -454,17 +454,17 @@ static int set_framesize(omv_csi_t *csi, omv_csi_framesize_t framesize) {
|
||||
switch (framesize) {
|
||||
case OMV_CSI_FRAMESIZE_VGA:
|
||||
for (int i = 0; VGA_regs[i][0] && ret == 0; i++) {
|
||||
ret |= omv_i2c_writeb2(&csi->i2c_bus, csi->slv_addr, VGA_regs[i][0], VGA_regs[i][1]);
|
||||
ret |= omv_i2c_writeb2(csi->i2c, csi->slv_addr, VGA_regs[i][0], VGA_regs[i][1]);
|
||||
}
|
||||
break;
|
||||
case OMV_CSI_FRAMESIZE_QVGA:
|
||||
for (int i = 0; QVGA_regs[i][0] && ret == 0; i++) {
|
||||
ret |= omv_i2c_writeb2(&csi->i2c_bus, csi->slv_addr, QVGA_regs[i][0], QVGA_regs[i][1]);
|
||||
ret |= omv_i2c_writeb2(csi->i2c, csi->slv_addr, QVGA_regs[i][0], QVGA_regs[i][1]);
|
||||
}
|
||||
break;
|
||||
case OMV_CSI_FRAMESIZE_QQVGA:
|
||||
for (int i = 0; QQVGA_regs[i][0] && ret == 0; i++) {
|
||||
ret |= omv_i2c_writeb2(&csi->i2c_bus, csi->slv_addr, QQVGA_regs[i][0], QQVGA_regs[i][1]);
|
||||
ret |= omv_i2c_writeb2(csi->i2c, csi->slv_addr, QQVGA_regs[i][0], QQVGA_regs[i][1]);
|
||||
}
|
||||
break;
|
||||
default:
|
||||
@ -494,8 +494,8 @@ static int set_framerate(omv_csi_t *csi, int framerate) {
|
||||
osc_div = (highres == true) ? 0x00 : 0x01;
|
||||
}
|
||||
|
||||
ret |= omv_i2c_readb2(&csi->i2c_bus, csi->slv_addr, PLL1_CONFIG, &pll_cfg);
|
||||
ret |= omv_i2c_writeb2(&csi->i2c_bus, csi->slv_addr, PLL1_CONFIG, (pll_cfg & 0xFC) | osc_div);
|
||||
ret |= omv_i2c_readb2(csi->i2c, csi->slv_addr, PLL1_CONFIG, &pll_cfg);
|
||||
ret |= omv_i2c_writeb2(csi->i2c, csi->slv_addr, PLL1_CONFIG, (pll_cfg & 0xFC) | osc_div);
|
||||
return ret;
|
||||
}
|
||||
|
||||
@ -517,7 +517,7 @@ static int set_brightness(omv_csi_t *csi, int level) {
|
||||
ae_mean = 100;
|
||||
break;
|
||||
}
|
||||
return omv_i2c_writeb2(&csi->i2c_bus, csi->slv_addr, AE_TARGET_MEAN, ae_mean);
|
||||
return omv_i2c_writeb2(csi->i2c, csi->slv_addr, AE_TARGET_MEAN, ae_mean);
|
||||
}
|
||||
|
||||
static int set_gainceiling(omv_csi_t *csi, omv_csi_gainceiling_t gainceiling) {
|
||||
@ -539,35 +539,35 @@ static int set_gainceiling(omv_csi_t *csi, omv_csi_gainceiling_t gainceiling) {
|
||||
default:
|
||||
return -1;
|
||||
}
|
||||
ret |= omv_i2c_writeb2(&csi->i2c_bus, csi->slv_addr, MAX_AGAIN, (gain & 0x07));
|
||||
ret |= omv_i2c_writeb2(csi->i2c, csi->slv_addr, MAX_AGAIN, (gain & 0x07));
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int set_colorbar(omv_csi_t *csi, int enable) {
|
||||
return omv_i2c_writeb2(&csi->i2c_bus, csi->slv_addr, TEST_PATTERN_MODE, enable & 0x1);
|
||||
return omv_i2c_writeb2(csi->i2c, csi->slv_addr, TEST_PATTERN_MODE, enable & 0x1);
|
||||
}
|
||||
|
||||
static int set_auto_gain(omv_csi_t *csi, int enable, float gain_db, float gain_db_ceiling) {
|
||||
uint8_t ae_ctrl = 0;
|
||||
int ret = omv_i2c_readb2(&csi->i2c_bus, csi->slv_addr, AE_CTRL, &ae_ctrl);
|
||||
int ret = omv_i2c_readb2(csi->i2c, csi->slv_addr, AE_CTRL, &ae_ctrl);
|
||||
if (!enable && (!isnanf(gain_db)) && (!isinff(gain_db))) {
|
||||
gain_db = IM_CLAMP(gain_db, 0.0f, 24.0f);
|
||||
uint8_t gain = fast_ceilf(logf(expf((gain_db / 20.0f) * M_LN10)) / M_LN2);
|
||||
ret |= omv_i2c_writeb2(&csi->i2c_bus, csi->slv_addr, AE_CTRL, (ae_ctrl & 0xFE));
|
||||
ret |= omv_i2c_writeb2(&csi->i2c_bus, csi->slv_addr, ANALOG_GAIN, ((gain & 0x7) << 4));
|
||||
ret |= omv_i2c_writeb2(csi->i2c, csi->slv_addr, AE_CTRL, (ae_ctrl & 0xFE));
|
||||
ret |= omv_i2c_writeb2(csi->i2c, csi->slv_addr, ANALOG_GAIN, ((gain & 0x7) << 4));
|
||||
} else if (enable && (!isnanf(gain_db_ceiling)) && (!isinff(gain_db_ceiling))) {
|
||||
gain_db_ceiling = IM_CLAMP(gain_db_ceiling, 0.0f, 24.0f);
|
||||
uint8_t gain = fast_ceilf(logf(expf((gain_db_ceiling / 20.0f) * M_LN10)) / M_LN2);
|
||||
ret |= omv_i2c_writeb2(&csi->i2c_bus, csi->slv_addr, MAX_AGAIN, (gain & 0x07));
|
||||
ret |= omv_i2c_writeb2(&csi->i2c_bus, csi->slv_addr, AE_CTRL, (ae_ctrl | 0x01));
|
||||
ret |= omv_i2c_writeb2(csi->i2c, csi->slv_addr, MAX_AGAIN, (gain & 0x07));
|
||||
ret |= omv_i2c_writeb2(csi->i2c, csi->slv_addr, AE_CTRL, (ae_ctrl | 0x01));
|
||||
}
|
||||
ret |= omv_i2c_writeb2(&csi->i2c_bus, csi->slv_addr, COMMAND_UPDATE, 0x01);
|
||||
ret |= omv_i2c_writeb2(csi->i2c, csi->slv_addr, COMMAND_UPDATE, 0x01);
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int get_gain_db(omv_csi_t *csi, float *gain_db) {
|
||||
uint8_t gain;
|
||||
if (omv_i2c_readb2(&csi->i2c_bus, csi->slv_addr, ANALOG_GAIN, &gain) != 0) {
|
||||
if (omv_i2c_readb2(csi->i2c, csi->slv_addr, ANALOG_GAIN, &gain) != 0) {
|
||||
return -1;
|
||||
}
|
||||
*gain_db = fast_floorf(log10f(1 << (gain >> 4)) * 20.0f);
|
||||
@ -576,7 +576,7 @@ static int get_gain_db(omv_csi_t *csi, float *gain_db) {
|
||||
|
||||
static int get_vt_pix_clk(omv_csi_t *csi, uint32_t *vt_pix_clk) {
|
||||
uint8_t reg;
|
||||
if (omv_i2c_readb2(&csi->i2c_bus, csi->slv_addr, PLL1_CONFIG, ®) != 0) {
|
||||
if (omv_i2c_readb2(csi->i2c, csi->slv_addr, PLL1_CONFIG, ®) != 0) {
|
||||
return -1;
|
||||
}
|
||||
// 00 -> MCLK / 1
|
||||
@ -592,10 +592,10 @@ static int get_vt_pix_clk(omv_csi_t *csi, uint32_t *vt_pix_clk) {
|
||||
|
||||
static int set_auto_exposure(omv_csi_t *csi, int enable, int exposure_us) {
|
||||
uint8_t ae_ctrl = 0;
|
||||
int ret = omv_i2c_readb2(&csi->i2c_bus, csi->slv_addr, AE_CTRL, &ae_ctrl);
|
||||
int ret = omv_i2c_readb2(csi->i2c, csi->slv_addr, AE_CTRL, &ae_ctrl);
|
||||
|
||||
if (enable) {
|
||||
ret |= omv_i2c_writeb2(&csi->i2c_bus, csi->slv_addr, AE_CTRL, (ae_ctrl | 0x01));
|
||||
ret |= omv_i2c_writeb2(csi->i2c, csi->slv_addr, AE_CTRL, (ae_ctrl | 0x01));
|
||||
} else {
|
||||
uint32_t line_len;
|
||||
uint32_t frame_len;
|
||||
@ -628,10 +628,10 @@ static int set_auto_exposure(omv_csi_t *csi, int enable, int exposure_us) {
|
||||
coarse_int = frame_len - 4;
|
||||
}
|
||||
|
||||
ret |= omv_i2c_writeb2(&csi->i2c_bus, csi->slv_addr, AE_CTRL, (ae_ctrl & 0xFE));
|
||||
ret |= omv_i2c_writeb2(&csi->i2c_bus, csi->slv_addr, INTEGRATION_H, coarse_int >> 8);
|
||||
ret |= omv_i2c_writeb2(&csi->i2c_bus, csi->slv_addr, INTEGRATION_L, coarse_int & 0xff);
|
||||
ret |= omv_i2c_writeb2(&csi->i2c_bus, csi->slv_addr, COMMAND_UPDATE, 0x01);
|
||||
ret |= omv_i2c_writeb2(csi->i2c, csi->slv_addr, AE_CTRL, (ae_ctrl & 0xFE));
|
||||
ret |= omv_i2c_writeb2(csi->i2c, csi->slv_addr, INTEGRATION_H, coarse_int >> 8);
|
||||
ret |= omv_i2c_writeb2(csi->i2c, csi->slv_addr, INTEGRATION_L, coarse_int & 0xff);
|
||||
ret |= omv_i2c_writeb2(csi->i2c, csi->slv_addr, COMMAND_UPDATE, 0x01);
|
||||
}
|
||||
|
||||
return ret;
|
||||
@ -656,25 +656,25 @@ static int get_exposure_us(omv_csi_t *csi, int *exposure_us) {
|
||||
return -1;
|
||||
}
|
||||
ret |= get_vt_pix_clk(csi, &vt_pix_clk);
|
||||
ret |= omv_i2c_readb2(&csi->i2c_bus, csi->slv_addr, INTEGRATION_H, &((uint8_t *) &coarse_int)[1]);
|
||||
ret |= omv_i2c_readb2(&csi->i2c_bus, csi->slv_addr, INTEGRATION_L, &((uint8_t *) &coarse_int)[0]);
|
||||
ret |= omv_i2c_readb2(csi->i2c, csi->slv_addr, INTEGRATION_H, &((uint8_t *) &coarse_int)[1]);
|
||||
ret |= omv_i2c_readb2(csi->i2c, csi->slv_addr, INTEGRATION_L, &((uint8_t *) &coarse_int)[0]);
|
||||
*exposure_us = fast_roundf(coarse_int * line_len / (vt_pix_clk / 1000000.0f));
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int set_hmirror(omv_csi_t *csi, int enable) {
|
||||
uint8_t reg;
|
||||
int ret = omv_i2c_readb2(&csi->i2c_bus, csi->slv_addr, IMG_ORIENTATION, ®);
|
||||
ret |= omv_i2c_writeb2(&csi->i2c_bus, csi->slv_addr, IMG_ORIENTATION, HIMAX_SET_HMIRROR(reg, enable));
|
||||
ret |= omv_i2c_writeb2(&csi->i2c_bus, csi->slv_addr, COMMAND_UPDATE, 0x01);
|
||||
int ret = omv_i2c_readb2(csi->i2c, csi->slv_addr, IMG_ORIENTATION, ®);
|
||||
ret |= omv_i2c_writeb2(csi->i2c, csi->slv_addr, IMG_ORIENTATION, HIMAX_SET_HMIRROR(reg, enable));
|
||||
ret |= omv_i2c_writeb2(csi->i2c, csi->slv_addr, COMMAND_UPDATE, 0x01);
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int set_vflip(omv_csi_t *csi, int enable) {
|
||||
uint8_t reg;
|
||||
int ret = omv_i2c_readb2(&csi->i2c_bus, csi->slv_addr, IMG_ORIENTATION, ®);
|
||||
ret |= omv_i2c_writeb2(&csi->i2c_bus, csi->slv_addr, IMG_ORIENTATION, HIMAX_SET_VMIRROR(reg, enable));
|
||||
ret |= omv_i2c_writeb2(&csi->i2c_bus, csi->slv_addr, COMMAND_UPDATE, 0x01);
|
||||
int ret = omv_i2c_readb2(csi->i2c, csi->slv_addr, IMG_ORIENTATION, ®);
|
||||
ret |= omv_i2c_writeb2(csi->i2c, csi->slv_addr, IMG_ORIENTATION, HIMAX_SET_VMIRROR(reg, enable));
|
||||
ret |= omv_i2c_writeb2(csi->i2c, csi->slv_addr, COMMAND_UPDATE, 0x01);
|
||||
return ret;
|
||||
}
|
||||
|
||||
@ -690,8 +690,8 @@ static int ioctl(omv_csi_t *csi, int request, va_list ap) {
|
||||
int ret = 0;
|
||||
uint8_t md_ctrl = 0;
|
||||
uint32_t enable = va_arg(ap, uint32_t) & 0x01;
|
||||
ret |= omv_i2c_readb2(&csi->i2c_bus, csi->slv_addr, MD_CTRL, &md_ctrl);
|
||||
ret |= omv_i2c_writeb2(&csi->i2c_bus, csi->slv_addr, MD_CTRL, (md_ctrl & 0xFE) | enable);
|
||||
ret |= omv_i2c_readb2(csi->i2c, csi->slv_addr, MD_CTRL, &md_ctrl);
|
||||
ret |= omv_i2c_writeb2(csi->i2c, csi->slv_addr, MD_CTRL, (md_ctrl & 0xFE) | enable);
|
||||
break;
|
||||
}
|
||||
|
||||
@ -730,21 +730,21 @@ static int ioctl(omv_csi_t *csi, int request, va_list ap) {
|
||||
y1 = MAX((y1 / roi_h - 1), 0);
|
||||
x2 = MIN((x2 / roi_w) + !!(x2 % roi_w), 0xF);
|
||||
y2 = MIN((y2 / roi_h) + !!(y2 % roi_h), roi_max_h);
|
||||
ret |= omv_i2c_writeb2(&csi->i2c_bus, csi->slv_addr, ROI_START_END_H, ((x2 & 0xF) << 4) | (x1 & 0x0F));
|
||||
ret |= omv_i2c_writeb2(&csi->i2c_bus, csi->slv_addr, ROI_START_END_V, ((y2 & 0xF) << 4) | (y1 & 0x0F));
|
||||
ret |= omv_i2c_writeb2(csi->i2c, csi->slv_addr, ROI_START_END_H, ((x2 & 0xF) << 4) | (x1 & 0x0F));
|
||||
ret |= omv_i2c_writeb2(csi->i2c, csi->slv_addr, ROI_START_END_V, ((y2 & 0xF) << 4) | (y1 & 0x0F));
|
||||
break;
|
||||
}
|
||||
|
||||
case OMV_CSI_IOCTL_HIMAX_MD_THRESHOLD: {
|
||||
uint32_t threshold = va_arg(ap, uint32_t) & 0x3F;
|
||||
ret |= omv_i2c_writeb2(&csi->i2c_bus, csi->slv_addr, MD_TH_STR_L, threshold);
|
||||
ret |= omv_i2c_writeb2(&csi->i2c_bus, csi->slv_addr, MD_TH_STR_H, threshold);
|
||||
ret |= omv_i2c_writeb2(&csi->i2c_bus, csi->slv_addr, MD_LIGHT_COEF, threshold);
|
||||
ret |= omv_i2c_writeb2(csi->i2c, csi->slv_addr, MD_TH_STR_L, threshold);
|
||||
ret |= omv_i2c_writeb2(csi->i2c, csi->slv_addr, MD_TH_STR_H, threshold);
|
||||
ret |= omv_i2c_writeb2(csi->i2c, csi->slv_addr, MD_LIGHT_COEF, threshold);
|
||||
break;
|
||||
}
|
||||
|
||||
case OMV_CSI_IOCTL_HIMAX_MD_CLEAR: {
|
||||
ret = omv_i2c_writeb2(&csi->i2c_bus, csi->slv_addr, INT_CLEAR, (1 << 3));
|
||||
ret = omv_i2c_writeb2(csi->i2c, csi->slv_addr, INT_CLEAR, (1 << 3));
|
||||
break;
|
||||
}
|
||||
|
||||
|
||||
@ -88,14 +88,14 @@ static int sleep(omv_csi_t *csi, int enable) {
|
||||
|
||||
static int read_reg(omv_csi_t *csi, uint16_t reg_addr) {
|
||||
uint16_t reg_data;
|
||||
if (omv_i2c_readw2(&csi->i2c_bus, csi->slv_addr, reg_addr, ®_data)) {
|
||||
if (omv_i2c_readw2(csi->i2c, csi->slv_addr, reg_addr, ®_data)) {
|
||||
return -1;
|
||||
}
|
||||
return reg_data;
|
||||
}
|
||||
|
||||
static int write_reg(omv_csi_t *csi, uint16_t reg_addr, uint16_t reg_data) {
|
||||
return omv_i2c_writew2(&csi->i2c_bus, csi->slv_addr, reg_addr, reg_data);
|
||||
return omv_i2c_writew2(csi->i2c, csi->slv_addr, reg_addr, reg_data);
|
||||
}
|
||||
|
||||
static int set_pixformat(omv_csi_t *csi, pixformat_t pixformat) {
|
||||
@ -299,7 +299,7 @@ static int lepton_reset(omv_csi_t *csi, bool measurement_mode, bool high_temp_mo
|
||||
memset(&lepton.port, 0, sizeof(LEP_CAMERA_PORT_DESC_T));
|
||||
|
||||
for (mp_uint_t start = mp_hal_ticks_ms(); ; mp_hal_delay_ms(1)) {
|
||||
if (LEP_OpenPort(&csi->i2c_bus, LEP_CCI_TWI, 0, &lepton.port) == LEP_OK) {
|
||||
if (LEP_OpenPort(csi->i2c, LEP_CCI_TWI, 0, &lepton.port) == LEP_OK) {
|
||||
break;
|
||||
}
|
||||
if ((mp_hal_ticks_ms() - start) >= LEPTON_BOOT_TIMEOUT) {
|
||||
|
||||
@ -310,14 +310,14 @@ static const uint16_t cpipe_regs_16_bit[][2] = {
|
||||
};
|
||||
|
||||
static int host_command(omv_csi_t *csi, uint16_t command) {
|
||||
if (omv_i2c_writew2(&csi->i2c_bus, csi->slv_addr, MT9M114_REG_HOST_COMMAND, (command | MT9M114_HC_OK)) != 0) {
|
||||
if (omv_i2c_writew2(csi->i2c, csi->slv_addr, MT9M114_REG_HOST_COMMAND, (command | MT9M114_HC_OK)) != 0) {
|
||||
return -1;
|
||||
}
|
||||
|
||||
for (mp_uint_t start = mp_hal_ticks_ms();; mp_hal_delay_ms(MT9M114_HC_DELAY)) {
|
||||
uint16_t reg_data;
|
||||
|
||||
if (omv_i2c_readw2(&csi->i2c_bus, csi->slv_addr, MT9M114_REG_HOST_COMMAND, ®_data) != 0) {
|
||||
if (omv_i2c_readw2(csi->i2c, csi->slv_addr, MT9M114_REG_HOST_COMMAND, ®_data) != 0) {
|
||||
return -1;
|
||||
}
|
||||
|
||||
@ -338,40 +338,40 @@ static int load_patch(omv_csi_t *csi, const uint8_t *patch, size_t patch_len,
|
||||
int ret = 0;
|
||||
// Patch address is stashed in the first two bytes.
|
||||
uint16_t patch_address = (((uint16_t) patch[0]) << 8) | patch[1];
|
||||
ret |= omv_i2c_writew2(&csi->i2c_bus, csi->slv_addr, MT9M114_REG_XMDA_ACCESS_CTL_STAT, patch_address >> 15);
|
||||
ret |= omv_i2c_writew2(csi->i2c, csi->slv_addr, MT9M114_REG_XMDA_ACCESS_CTL_STAT, patch_address >> 15);
|
||||
ret |=
|
||||
omv_i2c_writew2(&csi->i2c_bus, csi->slv_addr, MT9M114_REG_XMDA_PHYSICAL_ADDRESS_ACCESS, patch_address & 0x7FFF);
|
||||
ret |= omv_i2c_write_bytes(&csi->i2c_bus, csi->slv_addr, (uint8_t *) patch, patch_len, OMV_I2C_XFER_NO_FLAGS);
|
||||
ret |= omv_i2c_writew2(&csi->i2c_bus, csi->slv_addr, MT9M114_REG_XMDA_LOGIC_ADDRESS_ACCESS, 0x0000);
|
||||
ret |= omv_i2c_writew2(&csi->i2c_bus, csi->slv_addr, MT9M114_REG_PATCHLDR_LOADER_ADDRESS, patch_loader_address);
|
||||
ret |= omv_i2c_writew2(&csi->i2c_bus, csi->slv_addr, MT9M114_REG_PATCHLDR_PATCH_ID, patch_id);
|
||||
ret |= omv_i2c_writew2(&csi->i2c_bus, csi->slv_addr, MT9M114_REG_PATCHLDR_FIRMWARE_ID_HI, patch_firmware_id >> 16);
|
||||
ret |= omv_i2c_writew2(&csi->i2c_bus, csi->slv_addr, MT9M114_REG_PATCHLDR_FIRMWARE_ID_LO, patch_firmware_id);
|
||||
omv_i2c_writew2(csi->i2c, csi->slv_addr, MT9M114_REG_XMDA_PHYSICAL_ADDRESS_ACCESS, patch_address & 0x7FFF);
|
||||
ret |= omv_i2c_write_bytes(csi->i2c, csi->slv_addr, (uint8_t *) patch, patch_len, OMV_I2C_XFER_NO_FLAGS);
|
||||
ret |= omv_i2c_writew2(csi->i2c, csi->slv_addr, MT9M114_REG_XMDA_LOGIC_ADDRESS_ACCESS, 0x0000);
|
||||
ret |= omv_i2c_writew2(csi->i2c, csi->slv_addr, MT9M114_REG_PATCHLDR_LOADER_ADDRESS, patch_loader_address);
|
||||
ret |= omv_i2c_writew2(csi->i2c, csi->slv_addr, MT9M114_REG_PATCHLDR_PATCH_ID, patch_id);
|
||||
ret |= omv_i2c_writew2(csi->i2c, csi->slv_addr, MT9M114_REG_PATCHLDR_FIRMWARE_ID_HI, patch_firmware_id >> 16);
|
||||
ret |= omv_i2c_writew2(csi->i2c, csi->slv_addr, MT9M114_REG_PATCHLDR_FIRMWARE_ID_LO, patch_firmware_id);
|
||||
|
||||
ret |= host_command(csi, MT9M114_HC_APPLY_PATCH);
|
||||
|
||||
uint8_t reg_data;
|
||||
ret |= omv_i2c_readb2(&csi->i2c_bus, csi->slv_addr, MT9M114_REG_PATCHLDR_APPLY_STATUS, ®_data);
|
||||
ret |= omv_i2c_readb2(csi->i2c, csi->slv_addr, MT9M114_REG_PATCHLDR_APPLY_STATUS, ®_data);
|
||||
ret |= (reg_data == 0) ? 0: -1;
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int load_awb_cmm(omv_csi_t *csi) {
|
||||
return omv_i2c_write_bytes(&csi->i2c_bus, csi->slv_addr, (uint8_t *) awb_ccm, sizeof(awb_ccm), OMV_I2C_XFER_NO_FLAGS);
|
||||
return omv_i2c_write_bytes(csi->i2c, csi->slv_addr, (uint8_t *) awb_ccm, sizeof(awb_ccm), OMV_I2C_XFER_NO_FLAGS);
|
||||
}
|
||||
|
||||
static int load_awb(omv_csi_t *csi) {
|
||||
int ret = 0;
|
||||
|
||||
ret |= omv_i2c_writeb2(&csi->i2c_bus, csi->slv_addr, MT9M114_REG_CAM_AWB_XSCALE, 0x03);
|
||||
ret |= omv_i2c_writeb2(&csi->i2c_bus, csi->slv_addr, MT9M114_REG_CAM_AWB_YSCALE, 0x02);
|
||||
ret |= omv_i2c_writew2(&csi->i2c_bus, csi->slv_addr, MT9M114_REG_CAM_AWB_Y_SHIFT_PRE_ADJ, 0x003C);
|
||||
ret |= omv_i2c_write_bytes(&csi->i2c_bus, csi->slv_addr,
|
||||
ret |= omv_i2c_writeb2(csi->i2c, csi->slv_addr, MT9M114_REG_CAM_AWB_XSCALE, 0x03);
|
||||
ret |= omv_i2c_writeb2(csi->i2c, csi->slv_addr, MT9M114_REG_CAM_AWB_YSCALE, 0x02);
|
||||
ret |= omv_i2c_writew2(csi->i2c, csi->slv_addr, MT9M114_REG_CAM_AWB_Y_SHIFT_PRE_ADJ, 0x003C);
|
||||
ret |= omv_i2c_write_bytes(csi->i2c, csi->slv_addr,
|
||||
(uint8_t *) awb_weights, sizeof(awb_weights), OMV_I2C_XFER_NO_FLAGS);
|
||||
|
||||
for (int i = 0xC90C; i <= 0xC911; i++) {
|
||||
ret |= omv_i2c_writeb2(&csi->i2c_bus, csi->slv_addr, i, 0x80);
|
||||
ret |= omv_i2c_writeb2(csi->i2c, csi->slv_addr, i, 0x80);
|
||||
}
|
||||
|
||||
return ret;
|
||||
@ -384,18 +384,18 @@ static int load_cpipe(omv_csi_t *csi) {
|
||||
int d_size = sizeof(cpipe_regs_8_bit_d) / sizeof(cpipe_regs_8_bit_d[0]);
|
||||
|
||||
for (int i = 0, ii = IM_MIN(a_size, d_size); i < ii; i++) {
|
||||
ret |= omv_i2c_writeb2(&csi->i2c_bus, csi->slv_addr, cpipe_regs_8_bit_a[i], cpipe_regs_8_bit_d[i]);
|
||||
ret |= omv_i2c_writeb2(csi->i2c, csi->slv_addr, cpipe_regs_8_bit_a[i], cpipe_regs_8_bit_d[i]);
|
||||
}
|
||||
|
||||
for (int i = 0; i < (sizeof(cpipe_regs_16_bit) / sizeof(cpipe_regs_16_bit[0])); i++) {
|
||||
ret |= omv_i2c_writew2(&csi->i2c_bus, csi->slv_addr, cpipe_regs_16_bit[i][0], cpipe_regs_16_bit[i][1]);
|
||||
ret |= omv_i2c_writew2(csi->i2c, csi->slv_addr, cpipe_regs_16_bit[i][0], cpipe_regs_16_bit[i][1]);
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int set_system_state(omv_csi_t *csi, uint8_t state) {
|
||||
if (omv_i2c_writeb2(&csi->i2c_bus, csi->slv_addr, MT9M114_REG_SYSMGR_NEXT_STATE, state) != 0) {
|
||||
if (omv_i2c_writeb2(csi->i2c, csi->slv_addr, MT9M114_REG_SYSMGR_NEXT_STATE, state) != 0) {
|
||||
return -1;
|
||||
}
|
||||
|
||||
@ -415,7 +415,7 @@ static int refresh(omv_csi_t *csi) {
|
||||
|
||||
uint8_t reg_data;
|
||||
|
||||
if (omv_i2c_readb2(&csi->i2c_bus, csi->slv_addr, MT9M114_REG_SEQ_ERROR_CODE, ®_data) != 0) {
|
||||
if (omv_i2c_readb2(csi->i2c, csi->slv_addr, MT9M114_REG_SEQ_ERROR_CODE, ®_data) != 0) {
|
||||
return -1;
|
||||
}
|
||||
|
||||
@ -432,16 +432,16 @@ static int reset(omv_csi_t *csi) {
|
||||
readout_w = ACTIVE_SENSOR_WIDTH;
|
||||
readout_h = ACTIVE_SENSOR_HEIGHT;
|
||||
|
||||
ret |= omv_i2c_writew2(&csi->i2c_bus, csi->slv_addr, MT9M114_REG_SYSCTL, MT9M114_SYSCTL_SOFT_RESET);
|
||||
ret |= omv_i2c_writew2(csi->i2c, csi->slv_addr, MT9M114_REG_SYSCTL, MT9M114_SYSCTL_SOFT_RESET);
|
||||
mp_hal_delay_ms(1);
|
||||
|
||||
ret |= omv_i2c_writew2(&csi->i2c_bus, csi->slv_addr, MT9M114_REG_SYSCTL, 0);
|
||||
ret |= omv_i2c_writew2(csi->i2c, csi->slv_addr, MT9M114_REG_SYSCTL, 0);
|
||||
mp_hal_delay_ms(45);
|
||||
|
||||
for (mp_uint_t start = mp_hal_ticks_ms();; mp_hal_delay_ms(MT9M114_HC_DELAY)) {
|
||||
uint16_t reg_data;
|
||||
|
||||
if (omv_i2c_readw2(&csi->i2c_bus, csi->slv_addr, MT9M114_REG_HOST_COMMAND, ®_data) != 0) {
|
||||
if (omv_i2c_readw2(csi->i2c, csi->slv_addr, MT9M114_REG_HOST_COMMAND, ®_data) != 0) {
|
||||
return -1;
|
||||
}
|
||||
|
||||
@ -457,7 +457,7 @@ static int reset(omv_csi_t *csi) {
|
||||
for (mp_uint_t start = mp_hal_ticks_ms();; mp_hal_delay_ms(MT9M114_HC_DELAY)) {
|
||||
uint8_t reg_data;
|
||||
|
||||
if (omv_i2c_readb2(&csi->i2c_bus, csi->slv_addr, MT9M114_REG_SYSMGR_CURRENT_STATE, ®_data) != 0) {
|
||||
if (omv_i2c_readb2(csi->i2c, csi->slv_addr, MT9M114_REG_SYSMGR_CURRENT_STATE, ®_data) != 0) {
|
||||
return -1;
|
||||
}
|
||||
|
||||
@ -472,16 +472,16 @@ static int reset(omv_csi_t *csi) {
|
||||
|
||||
// Errata 2 (Black Frame Output)
|
||||
uint16_t reg;
|
||||
ret |= omv_i2c_readw2(&csi->i2c_bus, csi->slv_addr, 0x301A, ®);
|
||||
ret |= omv_i2c_writew2(&csi->i2c_bus, csi->slv_addr, 0x301A, reg | (1 << 9));
|
||||
ret |= omv_i2c_readw2(csi->i2c, csi->slv_addr, 0x301A, ®);
|
||||
ret |= omv_i2c_writew2(csi->i2c, csi->slv_addr, 0x301A, reg | (1 << 9));
|
||||
|
||||
ret |= omv_i2c_writew2(&csi->i2c_bus, csi->slv_addr, MT9M114_REG_CAM_SYSCTL_PLL_DIVIDER_M_N,
|
||||
ret |= omv_i2c_writew2(csi->i2c, csi->slv_addr, MT9M114_REG_CAM_SYSCTL_PLL_DIVIDER_M_N,
|
||||
(omv_csi_get_clk_frequency() == OMV_MT9M114_CLK_FREQ)
|
||||
? 0x120 // xclk=24MHz, m=32, n=1, csi=48MHz, bus=76.8MHz
|
||||
: 0x448); // xclk=25MHz, m=72, n=4, csi=45MHz, bus=72MHz
|
||||
|
||||
for (int i = 0; i < (sizeof(default_regs) / sizeof(default_regs[0])); i++) {
|
||||
ret |= omv_i2c_writew2(&csi->i2c_bus, csi->slv_addr, default_regs[i][0], default_regs[i][1]);
|
||||
ret |= omv_i2c_writew2(csi->i2c, csi->slv_addr, default_regs[i][0], default_regs[i][1]);
|
||||
}
|
||||
|
||||
ret |= set_framesize(csi, OMV_CSI_FRAMESIZE_SXGAM);
|
||||
@ -499,9 +499,9 @@ static int reset(omv_csi_t *csi) {
|
||||
ret |= load_awb(csi);
|
||||
ret |= load_cpipe(csi);
|
||||
|
||||
ret |= omv_i2c_writew2(&csi->i2c_bus, csi->slv_addr, MT9M114_REG_CAM_PORT_OUTPUT_CONTROL, 0x8008);
|
||||
ret |= omv_i2c_writew2(&csi->i2c_bus, csi->slv_addr, MT9M114_REG_PAD_SLEW, 0x0777);
|
||||
ret |= omv_i2c_writew2(&csi->i2c_bus, csi->slv_addr, MT9M114_REG_SENSOR_CONTROL_READ_MODE,
|
||||
ret |= omv_i2c_writew2(csi->i2c, csi->slv_addr, MT9M114_REG_CAM_PORT_OUTPUT_CONTROL, 0x8008);
|
||||
ret |= omv_i2c_writew2(csi->i2c, csi->slv_addr, MT9M114_REG_PAD_SLEW, 0x0777);
|
||||
ret |= omv_i2c_writew2(csi->i2c, csi->slv_addr, MT9M114_REG_SENSOR_CONTROL_READ_MODE,
|
||||
MT9M114_SENSOR_CONTROL_READ_MODE_HMIRROR | MT9M114_SENSOR_CONTROL_READ_MODE_VFLIP);
|
||||
|
||||
ret |= change_config(csi);
|
||||
@ -525,7 +525,7 @@ static int sleep(omv_csi_t *csi, int enable) {
|
||||
for (mp_uint_t start = mp_hal_ticks_ms();; mp_hal_delay_ms(MT9M114_HC_DELAY)) {
|
||||
uint8_t reg_data;
|
||||
|
||||
if (omv_i2c_readb2(&csi->i2c_bus, csi->slv_addr, MT9M114_REG_SYSMGR_CURRENT_STATE, ®_data) != 0) {
|
||||
if (omv_i2c_readb2(csi->i2c, csi->slv_addr, MT9M114_REG_SYSMGR_CURRENT_STATE, ®_data) != 0) {
|
||||
return -1;
|
||||
}
|
||||
|
||||
@ -543,7 +543,7 @@ static int sleep(omv_csi_t *csi, int enable) {
|
||||
static int read_reg(omv_csi_t *csi, uint16_t reg_addr) {
|
||||
uint16_t reg_data;
|
||||
|
||||
if (omv_i2c_readw2(&csi->i2c_bus, csi->slv_addr, reg_addr, ®_data) != 0) {
|
||||
if (omv_i2c_readw2(csi->i2c, csi->slv_addr, reg_addr, ®_data) != 0) {
|
||||
return -1;
|
||||
}
|
||||
|
||||
@ -551,7 +551,7 @@ static int read_reg(omv_csi_t *csi, uint16_t reg_addr) {
|
||||
}
|
||||
|
||||
static int write_reg(omv_csi_t *csi, uint16_t reg_addr, uint16_t reg_data) {
|
||||
return omv_i2c_writew2(&csi->i2c_bus, csi->slv_addr, reg_addr, reg_data);
|
||||
return omv_i2c_writew2(csi->i2c, csi->slv_addr, reg_addr, reg_data);
|
||||
}
|
||||
|
||||
static int set_pixformat(omv_csi_t *csi, pixformat_t pixformat) {
|
||||
@ -577,7 +577,7 @@ static int set_pixformat(omv_csi_t *csi, pixformat_t pixformat) {
|
||||
return -1;
|
||||
}
|
||||
|
||||
if (omv_i2c_writew2(&csi->i2c_bus, csi->slv_addr, MT9M114_REG_CAM_OUTPUT_FORMAT, reg) != 0) {
|
||||
if (omv_i2c_writew2(csi->i2c, csi->slv_addr, MT9M114_REG_CAM_OUTPUT_FORMAT, reg) != 0) {
|
||||
return -1;
|
||||
}
|
||||
|
||||
@ -612,7 +612,7 @@ static int set_framesize(omv_csi_t *csi, omv_csi_framesize_t framesize) {
|
||||
|
||||
uint16_t read_mode;
|
||||
|
||||
if (omv_i2c_readw2(&csi->i2c_bus, csi->slv_addr, MT9M114_REG_SENSOR_CONTROL_READ_MODE, &read_mode) != 0) {
|
||||
if (omv_i2c_readw2(csi->i2c, csi->slv_addr, MT9M114_REG_SENSOR_CONTROL_READ_MODE, &read_mode) != 0) {
|
||||
return -1;
|
||||
}
|
||||
|
||||
@ -670,66 +670,66 @@ static int set_framesize(omv_csi_t *csi, omv_csi_framesize_t framesize) {
|
||||
line_length_pck += 1;
|
||||
}
|
||||
|
||||
ret |= omv_i2c_writew2(&csi->i2c_bus, csi->slv_addr, MT9M114_REG_SENSOR_CFG_Y_ADDR_START, sensor_hs);
|
||||
ret |= omv_i2c_writew2(&csi->i2c_bus, csi->slv_addr, MT9M114_REG_SENSOR_CFG_X_ADDR_START, sensor_ws);
|
||||
ret |= omv_i2c_writew2(&csi->i2c_bus, csi->slv_addr, MT9M114_REG_SENSOR_CFG_Y_ADDR_END, sensor_he);
|
||||
ret |= omv_i2c_writew2(&csi->i2c_bus, csi->slv_addr, MT9M114_REG_SENSOR_CFG_X_ADDR_END, sensor_we);
|
||||
ret |= omv_i2c_writew2(csi->i2c, csi->slv_addr, MT9M114_REG_SENSOR_CFG_Y_ADDR_START, sensor_hs);
|
||||
ret |= omv_i2c_writew2(csi->i2c, csi->slv_addr, MT9M114_REG_SENSOR_CFG_X_ADDR_START, sensor_ws);
|
||||
ret |= omv_i2c_writew2(csi->i2c, csi->slv_addr, MT9M114_REG_SENSOR_CFG_Y_ADDR_END, sensor_he);
|
||||
ret |= omv_i2c_writew2(csi->i2c, csi->slv_addr, MT9M114_REG_SENSOR_CFG_X_ADDR_END, sensor_we);
|
||||
|
||||
int pixclk = (omv_csi_get_clk_frequency() == OMV_MT9M114_CLK_FREQ) ? 48000000 : 45000000;
|
||||
|
||||
ret |= omv_i2c_writew2(&csi->i2c_bus, csi->slv_addr, MT9M114_REG_SENSOR_CFG_PIXCLK, pixclk >> 16);
|
||||
ret |= omv_i2c_writew2(&csi->i2c_bus, csi->slv_addr, MT9M114_REG_SENSOR_CFG_PIXCLK + 2, pixclk);
|
||||
ret |= omv_i2c_writew2(csi->i2c, csi->slv_addr, MT9M114_REG_SENSOR_CFG_PIXCLK, pixclk >> 16);
|
||||
ret |= omv_i2c_writew2(csi->i2c, csi->slv_addr, MT9M114_REG_SENSOR_CFG_PIXCLK + 2, pixclk);
|
||||
|
||||
ret |= omv_i2c_writew2(&csi->i2c_bus, csi->slv_addr, MT9M114_REG_SENSOR_CFG_FINE_INTEG_TIME_MIN,
|
||||
ret |= omv_i2c_writew2(csi->i2c, csi->slv_addr, MT9M114_REG_SENSOR_CFG_FINE_INTEG_TIME_MIN,
|
||||
(read_mode_div == 2) ? 451 : 219); // figured this out by checking register wizard against datasheet
|
||||
ret |= omv_i2c_writew2(&csi->i2c_bus, csi->slv_addr, MT9M114_REG_SENSOR_CFG_FINE_INTEG_TIME_MAX,
|
||||
ret |= omv_i2c_writew2(csi->i2c, csi->slv_addr, MT9M114_REG_SENSOR_CFG_FINE_INTEG_TIME_MAX,
|
||||
(read_mode_div == 2) ? 947 : 1480); // figured this out by checking register wizard against datasheet
|
||||
ret |= omv_i2c_writew2(&csi->i2c_bus, csi->slv_addr, MT9M114_REG_SENSOR_CFG_FRAME_LENGTH_LINES,
|
||||
ret |= omv_i2c_writew2(csi->i2c, csi->slv_addr, MT9M114_REG_SENSOR_CFG_FRAME_LENGTH_LINES,
|
||||
frame_length_lines); // figured this out by checking register wizard against datasheet
|
||||
ret |= omv_i2c_writew2(&csi->i2c_bus, csi->slv_addr, MT9M114_REG_SENSOR_CFG_LINE_LENGTH_PCK,
|
||||
ret |= omv_i2c_writew2(csi->i2c, csi->slv_addr, MT9M114_REG_SENSOR_CFG_LINE_LENGTH_PCK,
|
||||
line_length_pck); // figured this out by checking register wizard against datasheet
|
||||
ret |= omv_i2c_writew2(&csi->i2c_bus, csi->slv_addr, MT9M114_REG_SENSOR_CFG_FINE_CORRECTION,
|
||||
ret |= omv_i2c_writew2(csi->i2c, csi->slv_addr, MT9M114_REG_SENSOR_CFG_FINE_CORRECTION,
|
||||
(read_mode_div == 2) ? 224 : 96); // figured this out by checking register wizard against datasheet
|
||||
ret |= omv_i2c_writew2(&csi->i2c_bus, csi->slv_addr, MT9M114_REG_SENSOR_CFG_CPIPE_LAST_ROW,
|
||||
ret |= omv_i2c_writew2(csi->i2c, csi->slv_addr, MT9M114_REG_SENSOR_CFG_CPIPE_LAST_ROW,
|
||||
(readout_h / read_mode_div) + 3); // figured this out by checking register wizard against datasheet
|
||||
|
||||
ret |= omv_i2c_writew2(&csi->i2c_bus, csi->slv_addr, MT9M114_REG_SENSOR_CONTROL_READ_MODE, read_mode);
|
||||
ret |= omv_i2c_writew2(csi->i2c, csi->slv_addr, MT9M114_REG_SENSOR_CONTROL_READ_MODE, read_mode);
|
||||
|
||||
ret |= omv_i2c_writew2(&csi->i2c_bus, csi->slv_addr, MT9M114_REG_CROP_WINDOW_X_OFFSET, x_off);
|
||||
ret |= omv_i2c_writew2(&csi->i2c_bus, csi->slv_addr, MT9M114_REG_CROP_WINDOW_Y_OFFSET, y_off);
|
||||
ret |= omv_i2c_writew2(&csi->i2c_bus, csi->slv_addr, MT9M114_REG_CROP_WINDOW_WIDTH, w_mul);
|
||||
ret |= omv_i2c_writew2(&csi->i2c_bus, csi->slv_addr, MT9M114_REG_CROP_WINDOW_HEIGHT, h_mul);
|
||||
ret |= omv_i2c_writew2(csi->i2c, csi->slv_addr, MT9M114_REG_CROP_WINDOW_X_OFFSET, x_off);
|
||||
ret |= omv_i2c_writew2(csi->i2c, csi->slv_addr, MT9M114_REG_CROP_WINDOW_Y_OFFSET, y_off);
|
||||
ret |= omv_i2c_writew2(csi->i2c, csi->slv_addr, MT9M114_REG_CROP_WINDOW_WIDTH, w_mul);
|
||||
ret |= omv_i2c_writew2(csi->i2c, csi->slv_addr, MT9M114_REG_CROP_WINDOW_HEIGHT, h_mul);
|
||||
|
||||
ret |= omv_i2c_writew2(&csi->i2c_bus, csi->slv_addr, MT9M114_REG_CAM_OUTPUT_WIDTH, w);
|
||||
ret |= omv_i2c_writew2(&csi->i2c_bus, csi->slv_addr, MT9M114_REG_CAM_OUTPUT_HEIGHT, h);
|
||||
ret |= omv_i2c_writew2(csi->i2c, csi->slv_addr, MT9M114_REG_CAM_OUTPUT_WIDTH, w);
|
||||
ret |= omv_i2c_writew2(csi->i2c, csi->slv_addr, MT9M114_REG_CAM_OUTPUT_HEIGHT, h);
|
||||
|
||||
float rate = (((float) pixclk) / (frame_length_lines * line_length_pck)) * 256;
|
||||
|
||||
ret |= omv_i2c_writew2(&csi->i2c_bus, csi->slv_addr, MT9M114_REG_CAM_AET_MAX_FRAME_RATE, fast_ceilf(rate));
|
||||
ret |= omv_i2c_writew2(&csi->i2c_bus, csi->slv_addr, MT9M114_REG_CAM_AET_MIN_FRAME_RATE, fast_floorf(rate / 2.f));
|
||||
ret |= omv_i2c_writew2(csi->i2c, csi->slv_addr, MT9M114_REG_CAM_AET_MAX_FRAME_RATE, fast_ceilf(rate));
|
||||
ret |= omv_i2c_writew2(csi->i2c, csi->slv_addr, MT9M114_REG_CAM_AET_MIN_FRAME_RATE, fast_floorf(rate / 2.f));
|
||||
|
||||
ret |= omv_i2c_writew2(&csi->i2c_bus, csi->slv_addr, MT9M114_REG_AWB_CLIP_WINDOW_X_START, 0);
|
||||
ret |= omv_i2c_writew2(&csi->i2c_bus, csi->slv_addr, MT9M114_REG_AWB_CLIP_WINDOW_Y_START, 0);
|
||||
ret |= omv_i2c_writew2(&csi->i2c_bus, csi->slv_addr, MT9M114_REG_AWB_CLIP_WINDOW_X_END, w - 1);
|
||||
ret |= omv_i2c_writew2(&csi->i2c_bus, csi->slv_addr, MT9M114_REG_AWB_CLIP_WINDOW_Y_END, h - 1);
|
||||
ret |= omv_i2c_writew2(csi->i2c, csi->slv_addr, MT9M114_REG_AWB_CLIP_WINDOW_X_START, 0);
|
||||
ret |= omv_i2c_writew2(csi->i2c, csi->slv_addr, MT9M114_REG_AWB_CLIP_WINDOW_Y_START, 0);
|
||||
ret |= omv_i2c_writew2(csi->i2c, csi->slv_addr, MT9M114_REG_AWB_CLIP_WINDOW_X_END, w - 1);
|
||||
ret |= omv_i2c_writew2(csi->i2c, csi->slv_addr, MT9M114_REG_AWB_CLIP_WINDOW_Y_END, h - 1);
|
||||
|
||||
ret |= omv_i2c_writew2(&csi->i2c_bus, csi->slv_addr, MT9M114_REG_AE_INITIAL_WINDOW_X_START, 0);
|
||||
ret |= omv_i2c_writew2(&csi->i2c_bus, csi->slv_addr, MT9M114_REG_AE_INITIAL_WINDOW_Y_START, 0);
|
||||
ret |= omv_i2c_writew2(&csi->i2c_bus, csi->slv_addr, MT9M114_REG_AE_INITIAL_WINDOW_X_END, (w / 5) - 1);
|
||||
ret |= omv_i2c_writew2(&csi->i2c_bus, csi->slv_addr, MT9M114_REG_AE_INITIAL_WINDOW_Y_END, (h / 5) - 1);
|
||||
ret |= omv_i2c_writew2(csi->i2c, csi->slv_addr, MT9M114_REG_AE_INITIAL_WINDOW_X_START, 0);
|
||||
ret |= omv_i2c_writew2(csi->i2c, csi->slv_addr, MT9M114_REG_AE_INITIAL_WINDOW_Y_START, 0);
|
||||
ret |= omv_i2c_writew2(csi->i2c, csi->slv_addr, MT9M114_REG_AE_INITIAL_WINDOW_X_END, (w / 5) - 1);
|
||||
ret |= omv_i2c_writew2(csi->i2c, csi->slv_addr, MT9M114_REG_AE_INITIAL_WINDOW_Y_END, (h / 5) - 1);
|
||||
|
||||
ret |= omv_i2c_writeb2(&csi->i2c_bus, csi->slv_addr, MT9M114_REG_AUTO_BINNING_MODE, 0);
|
||||
ret |= omv_i2c_writew2(&csi->i2c_bus, csi->slv_addr, MT9M114_REG_LL_ALGO, 0);
|
||||
ret |= omv_i2c_writeb2(csi->i2c, csi->slv_addr, MT9M114_REG_AUTO_BINNING_MODE, 0);
|
||||
ret |= omv_i2c_writew2(csi->i2c, csi->slv_addr, MT9M114_REG_LL_ALGO, 0);
|
||||
|
||||
return change_config(csi);
|
||||
}
|
||||
|
||||
static int set_framerate(omv_csi_t *csi, int framerate) {
|
||||
if (omv_i2c_writew2(&csi->i2c_bus, csi->slv_addr, MT9M114_REG_CAM_AET_MAX_FRAME_RATE, framerate * 256) != 0) {
|
||||
if (omv_i2c_writew2(csi->i2c, csi->slv_addr, MT9M114_REG_CAM_AET_MAX_FRAME_RATE, framerate * 256) != 0) {
|
||||
return -1;
|
||||
}
|
||||
|
||||
if (omv_i2c_writew2(&csi->i2c_bus, csi->slv_addr, MT9M114_REG_CAM_AET_MIN_FRAME_RATE, framerate * 128) != 0) {
|
||||
if (omv_i2c_writew2(csi->i2c, csi->slv_addr, MT9M114_REG_CAM_AET_MIN_FRAME_RATE, framerate * 128) != 0) {
|
||||
return -1;
|
||||
}
|
||||
|
||||
@ -744,7 +744,7 @@ static int set_contrast(omv_csi_t *csi, int level) {
|
||||
return -1;
|
||||
}
|
||||
|
||||
if (omv_i2c_writew2(&csi->i2c_bus, csi->slv_addr, MT9M114_REG_UVC_CONTRAST_CONTROL, new_level + 32) != 0) {
|
||||
if (omv_i2c_writew2(csi->i2c, csi->slv_addr, MT9M114_REG_UVC_CONTRAST_CONTROL, new_level + 32) != 0) {
|
||||
return -1;
|
||||
}
|
||||
|
||||
@ -759,7 +759,7 @@ static int set_brightness(omv_csi_t *csi, int level) {
|
||||
return -1;
|
||||
}
|
||||
|
||||
if (omv_i2c_writew2(&csi->i2c_bus, csi->slv_addr, MT9M114_REG_UVC_BRIGHTNESS_CONTROL, new_level + 55) != 0) {
|
||||
if (omv_i2c_writew2(csi->i2c, csi->slv_addr, MT9M114_REG_UVC_BRIGHTNESS_CONTROL, new_level + 55) != 0) {
|
||||
return -1;
|
||||
}
|
||||
|
||||
@ -776,7 +776,7 @@ static int set_saturation(omv_csi_t *csi, int level) {
|
||||
|
||||
new_level = IM_MIN(new_level, 127);
|
||||
|
||||
if (omv_i2c_writew2(&csi->i2c_bus, csi->slv_addr, MT9M114_REG_UVC_SATURATION_CONTROL, new_level + 128) != 0) {
|
||||
if (omv_i2c_writew2(csi->i2c, csi->slv_addr, MT9M114_REG_UVC_SATURATION_CONTROL, new_level + 128) != 0) {
|
||||
return -1;
|
||||
}
|
||||
|
||||
@ -788,7 +788,7 @@ static int set_gainceiling(omv_csi_t *csi, omv_csi_gainceiling_t gainceiling) {
|
||||
}
|
||||
|
||||
static int set_colorbar(omv_csi_t *csi, int enable) {
|
||||
if (omv_i2c_writeb2(&csi->i2c_bus, csi->slv_addr, MT9M114_REG_CAM_MODE_SELECT, enable ? 2 : 0) != 0) {
|
||||
if (omv_i2c_writeb2(csi->i2c, csi->slv_addr, MT9M114_REG_CAM_MODE_SELECT, enable ? 2 : 0) != 0) {
|
||||
return -1;
|
||||
}
|
||||
|
||||
@ -796,14 +796,14 @@ static int set_colorbar(omv_csi_t *csi, int enable) {
|
||||
}
|
||||
|
||||
static int set_auto_gain(omv_csi_t *csi, int enable, float gain_db, float gain_db_ceiling) {
|
||||
if (omv_i2c_writeb2(&csi->i2c_bus, csi->slv_addr, MT9M114_REG_UVC_AE_MODE_CONTROL, enable ? 0x2 : 0x1) != 0) {
|
||||
if (omv_i2c_writeb2(csi->i2c, csi->slv_addr, MT9M114_REG_UVC_AE_MODE_CONTROL, enable ? 0x2 : 0x1) != 0) {
|
||||
return -1;
|
||||
}
|
||||
|
||||
if ((enable == 0) && (!isnanf(gain_db)) && (!isinff(gain_db))) {
|
||||
int gain = __USAT(expf((gain_db / 20.0f) * M_LN10) * 32.0f, 16);
|
||||
|
||||
if (omv_i2c_writew2(&csi->i2c_bus, csi->slv_addr, MT9M114_REG_UVC_GAIN_CONTROL, gain) != 0) {
|
||||
if (omv_i2c_writew2(csi->i2c, csi->slv_addr, MT9M114_REG_UVC_GAIN_CONTROL, gain) != 0) {
|
||||
return -1;
|
||||
}
|
||||
}
|
||||
@ -814,7 +814,7 @@ static int set_auto_gain(omv_csi_t *csi, int enable, float gain_db, float gain_d
|
||||
static int get_gain_db(omv_csi_t *csi, float *gain_db) {
|
||||
uint16_t gain;
|
||||
|
||||
if (omv_i2c_readw2(&csi->i2c_bus, csi->slv_addr, MT9M114_REG_UVC_GAIN_CONTROL, &gain) != 0) {
|
||||
if (omv_i2c_readw2(csi->i2c, csi->slv_addr, MT9M114_REG_UVC_GAIN_CONTROL, &gain) != 0) {
|
||||
return -1;
|
||||
}
|
||||
|
||||
@ -824,23 +824,23 @@ static int get_gain_db(omv_csi_t *csi, float *gain_db) {
|
||||
}
|
||||
|
||||
static int set_auto_exposure(omv_csi_t *csi, int enable, int exposure_us) {
|
||||
if (omv_i2c_writeb2(&csi->i2c_bus, csi->slv_addr, MT9M114_REG_UVC_AE_MODE_CONTROL, enable ? 0x2 : 0x1) != 0) {
|
||||
if (omv_i2c_writeb2(csi->i2c, csi->slv_addr, MT9M114_REG_UVC_AE_MODE_CONTROL, enable ? 0x2 : 0x1) != 0) {
|
||||
return -1;
|
||||
}
|
||||
|
||||
if ((enable == 0) && (exposure_us >= 0)) {
|
||||
if (omv_i2c_writeb2(&csi->i2c_bus, csi->slv_addr, MT9M114_REG_UVC_MANUAL_EXPOSURE_CONFIG, 0x1) != 0) {
|
||||
if (omv_i2c_writeb2(csi->i2c, csi->slv_addr, MT9M114_REG_UVC_MANUAL_EXPOSURE_CONFIG, 0x1) != 0) {
|
||||
return -1;
|
||||
}
|
||||
|
||||
int exposure_100_us = exposure_us / 100;
|
||||
|
||||
if (omv_i2c_writew2(&csi->i2c_bus, csi->slv_addr, MT9M114_REG_UVC_EXPOSURE_TIME_ABSOLUTE_CTRL,
|
||||
if (omv_i2c_writew2(csi->i2c, csi->slv_addr, MT9M114_REG_UVC_EXPOSURE_TIME_ABSOLUTE_CTRL,
|
||||
exposure_100_us >> 16) != 0) {
|
||||
return -1;
|
||||
}
|
||||
|
||||
if (omv_i2c_writew2(&csi->i2c_bus, csi->slv_addr, MT9M114_REG_UVC_EXPOSURE_TIME_ABSOLUTE_CTRL + 2,
|
||||
if (omv_i2c_writew2(csi->i2c, csi->slv_addr, MT9M114_REG_UVC_EXPOSURE_TIME_ABSOLUTE_CTRL + 2,
|
||||
exposure_100_us) != 0) {
|
||||
return -1;
|
||||
}
|
||||
@ -852,11 +852,11 @@ static int set_auto_exposure(omv_csi_t *csi, int enable, int exposure_us) {
|
||||
static int get_exposure_us(omv_csi_t *csi, int *exposure_us) {
|
||||
uint16_t reg_h, reg_l;
|
||||
|
||||
if (omv_i2c_readw2(&csi->i2c_bus, csi->slv_addr, MT9M114_REG_UVC_EXPOSURE_TIME_ABSOLUTE_CTRL, ®_h) != 0) {
|
||||
if (omv_i2c_readw2(csi->i2c, csi->slv_addr, MT9M114_REG_UVC_EXPOSURE_TIME_ABSOLUTE_CTRL, ®_h) != 0) {
|
||||
return -1;
|
||||
}
|
||||
|
||||
if (omv_i2c_readw2(&csi->i2c_bus, csi->slv_addr, MT9M114_REG_UVC_EXPOSURE_TIME_ABSOLUTE_CTRL + 2, ®_l) != 0) {
|
||||
if (omv_i2c_readw2(csi->i2c, csi->slv_addr, MT9M114_REG_UVC_EXPOSURE_TIME_ABSOLUTE_CTRL + 2, ®_l) != 0) {
|
||||
return -1;
|
||||
}
|
||||
|
||||
@ -866,7 +866,7 @@ static int get_exposure_us(omv_csi_t *csi, int *exposure_us) {
|
||||
}
|
||||
|
||||
static int set_auto_whitebal(omv_csi_t *csi, int enable, float r_gain_db, float g_gain_db, float b_gain_db) {
|
||||
if (omv_i2c_writeb2(&csi->i2c_bus, csi->slv_addr, MT9M114_REG_UVC_WHITE_BALANCE_AUTO_CONTROL,
|
||||
if (omv_i2c_writeb2(csi->i2c, csi->slv_addr, MT9M114_REG_UVC_WHITE_BALANCE_AUTO_CONTROL,
|
||||
enable ? 0x1 : 0x0) != 0) {
|
||||
return -1;
|
||||
}
|
||||
@ -885,14 +885,14 @@ static int get_rgb_gain_db(omv_csi_t *csi, float *r_gain_db, float *g_gain_db, f
|
||||
static int set_hmirror(omv_csi_t *csi, int enable) {
|
||||
uint16_t reg_data;
|
||||
|
||||
if (omv_i2c_readw2(&csi->i2c_bus, csi->slv_addr, MT9M114_REG_SENSOR_CONTROL_READ_MODE, ®_data) != 0) {
|
||||
if (omv_i2c_readw2(csi->i2c, csi->slv_addr, MT9M114_REG_SENSOR_CONTROL_READ_MODE, ®_data) != 0) {
|
||||
return -1;
|
||||
}
|
||||
|
||||
reg_data = (reg_data & (~MT9M114_SENSOR_CONTROL_READ_MODE_HMIRROR)) |
|
||||
(enable ? 0x0 : MT9M114_SENSOR_CONTROL_READ_MODE_HMIRROR); // inverted
|
||||
|
||||
if (omv_i2c_writew2(&csi->i2c_bus, csi->slv_addr, MT9M114_REG_SENSOR_CONTROL_READ_MODE, reg_data) != 0) {
|
||||
if (omv_i2c_writew2(csi->i2c, csi->slv_addr, MT9M114_REG_SENSOR_CONTROL_READ_MODE, reg_data) != 0) {
|
||||
return -1;
|
||||
}
|
||||
|
||||
@ -902,14 +902,14 @@ static int set_hmirror(omv_csi_t *csi, int enable) {
|
||||
static int set_vflip(omv_csi_t *csi, int enable) {
|
||||
uint16_t reg_data;
|
||||
|
||||
if (omv_i2c_readw2(&csi->i2c_bus, csi->slv_addr, MT9M114_REG_SENSOR_CONTROL_READ_MODE, ®_data) != 0) {
|
||||
if (omv_i2c_readw2(csi->i2c, csi->slv_addr, MT9M114_REG_SENSOR_CONTROL_READ_MODE, ®_data) != 0) {
|
||||
return -1;
|
||||
}
|
||||
|
||||
reg_data = (reg_data & (~MT9M114_SENSOR_CONTROL_READ_MODE_VFLIP)) |
|
||||
(enable ? 0x0 : MT9M114_SENSOR_CONTROL_READ_MODE_VFLIP); // inverted
|
||||
|
||||
if (omv_i2c_writew2(&csi->i2c_bus, csi->slv_addr, MT9M114_REG_SENSOR_CONTROL_READ_MODE, reg_data) != 0) {
|
||||
if (omv_i2c_writew2(csi->i2c, csi->slv_addr, MT9M114_REG_SENSOR_CONTROL_READ_MODE, reg_data) != 0) {
|
||||
return -1;
|
||||
}
|
||||
|
||||
@ -919,12 +919,12 @@ static int set_vflip(omv_csi_t *csi, int enable) {
|
||||
static int set_special_effect(omv_csi_t *csi, omv_csi_sde_t sde) {
|
||||
switch (sde) {
|
||||
case OMV_CSI_SDE_NEGATIVE:
|
||||
if (omv_i2c_writeb2(&csi->i2c_bus, csi->slv_addr, MT9M114_REG_CAM_SFX_CONTROL, 0x3) != 0) {
|
||||
if (omv_i2c_writeb2(csi->i2c, csi->slv_addr, MT9M114_REG_CAM_SFX_CONTROL, 0x3) != 0) {
|
||||
return -1;
|
||||
}
|
||||
break;
|
||||
case OMV_CSI_SDE_NORMAL:
|
||||
if (omv_i2c_writeb2(&csi->i2c_bus, csi->slv_addr, MT9M114_REG_CAM_SFX_CONTROL, 0x0) != 0) {
|
||||
if (omv_i2c_writeb2(csi->i2c, csi->slv_addr, MT9M114_REG_CAM_SFX_CONTROL, 0x0) != 0) {
|
||||
return -1;
|
||||
}
|
||||
break;
|
||||
|
||||
@ -64,75 +64,75 @@ static int reset(omv_csi_t *csi) {
|
||||
readout_x = 0;
|
||||
readout_y = 0;
|
||||
|
||||
ret |= omv_i2c_writew(&csi->i2c_bus, csi->slv_addr, MT9V0XX_RESET, MT9V0XX_RESET_SOFT_RESET);
|
||||
ret |= omv_i2c_writew(csi->i2c, csi->slv_addr, MT9V0XX_RESET, MT9V0XX_RESET_SOFT_RESET);
|
||||
|
||||
if (is_mt9v0x4(csi)) {
|
||||
uint16_t chip_control;
|
||||
ret |= omv_i2c_readw(&csi->i2c_bus, csi->slv_addr, MT9V0XX_CHIP_CONTROL, &chip_control);
|
||||
ret |= omv_i2c_writew(&csi->i2c_bus, csi->slv_addr, MT9V0XX_CHIP_CONTROL,
|
||||
ret |= omv_i2c_readw(csi->i2c, csi->slv_addr, MT9V0XX_CHIP_CONTROL, &chip_control);
|
||||
ret |= omv_i2c_writew(csi->i2c, csi->slv_addr, MT9V0XX_CHIP_CONTROL,
|
||||
(chip_control & (~MT9V0X4_CHIP_CONTROL_RESERVED)));
|
||||
}
|
||||
|
||||
uint16_t read_mode;
|
||||
ret |= omv_i2c_readw(&csi->i2c_bus, csi->slv_addr, MT9V0XX_READ_MODE, &read_mode);
|
||||
ret |= omv_i2c_writew(&csi->i2c_bus, csi->slv_addr, MT9V0XX_READ_MODE,
|
||||
ret |= omv_i2c_readw(csi->i2c, csi->slv_addr, MT9V0XX_READ_MODE, &read_mode);
|
||||
ret |= omv_i2c_writew(csi->i2c, csi->slv_addr, MT9V0XX_READ_MODE,
|
||||
read_mode | MT9V0XX_READ_MODE_ROW_FLIP | MT9V0XX_READ_MODE_COL_FLIP);
|
||||
|
||||
if (is_mt9v0x4(csi)) {
|
||||
// We have to copy the differences from context A into context B registers so that we can
|
||||
// ping-pong between them seamlessly...
|
||||
|
||||
ret |= omv_i2c_readw(&csi->i2c_bus, csi->slv_addr, MT9V0X4_READ_MODE_B, &read_mode);
|
||||
ret |= omv_i2c_writew(&csi->i2c_bus, csi->slv_addr, MT9V0X4_READ_MODE_B,
|
||||
ret |= omv_i2c_readw(csi->i2c, csi->slv_addr, MT9V0X4_READ_MODE_B, &read_mode);
|
||||
ret |= omv_i2c_writew(csi->i2c, csi->slv_addr, MT9V0X4_READ_MODE_B,
|
||||
read_mode | MT9V0XX_READ_MODE_ROW_FLIP | MT9V0XX_READ_MODE_COL_FLIP);
|
||||
|
||||
uint16_t shutter_width1;
|
||||
ret |= omv_i2c_readw(&csi->i2c_bus, csi->slv_addr, MT9V0XX_SHUTTER_WIDTH1, &shutter_width1);
|
||||
ret |= omv_i2c_writew(&csi->i2c_bus, csi->slv_addr, MT9V0X4_SHUTTER_WIDTH1_B, shutter_width1);
|
||||
ret |= omv_i2c_readw(csi->i2c, csi->slv_addr, MT9V0XX_SHUTTER_WIDTH1, &shutter_width1);
|
||||
ret |= omv_i2c_writew(csi->i2c, csi->slv_addr, MT9V0X4_SHUTTER_WIDTH1_B, shutter_width1);
|
||||
|
||||
uint16_t shutter_width2;
|
||||
ret |= omv_i2c_readw(&csi->i2c_bus, csi->slv_addr, MT9V0XX_SHUTTER_WIDTH2, &shutter_width2);
|
||||
ret |= omv_i2c_writew(&csi->i2c_bus, csi->slv_addr, MT9V0X4_SHUTTER_WIDTH2_B, shutter_width2);
|
||||
ret |= omv_i2c_readw(csi->i2c, csi->slv_addr, MT9V0XX_SHUTTER_WIDTH2, &shutter_width2);
|
||||
ret |= omv_i2c_writew(csi->i2c, csi->slv_addr, MT9V0X4_SHUTTER_WIDTH2_B, shutter_width2);
|
||||
|
||||
uint16_t shutter_control;
|
||||
ret |= omv_i2c_readw(&csi->i2c_bus, csi->slv_addr, MT9V0XX_SHUTTER_WIDTH_CONTROL, &shutter_control);
|
||||
ret |= omv_i2c_writew(&csi->i2c_bus, csi->slv_addr, MT9V0X4_SHUTTER_WIDTH_CONTROL_B, shutter_control);
|
||||
ret |= omv_i2c_readw(csi->i2c, csi->slv_addr, MT9V0XX_SHUTTER_WIDTH_CONTROL, &shutter_control);
|
||||
ret |= omv_i2c_writew(csi->i2c, csi->slv_addr, MT9V0X4_SHUTTER_WIDTH_CONTROL_B, shutter_control);
|
||||
|
||||
uint16_t voltage_level_1;
|
||||
ret |= omv_i2c_readw(&csi->i2c_bus, csi->slv_addr, MT9V0XX_V1_CONTROL, &voltage_level_1);
|
||||
ret |= omv_i2c_writew(&csi->i2c_bus, csi->slv_addr, MT9V0X4_V1_CONTROL_B, voltage_level_1);
|
||||
ret |= omv_i2c_readw(csi->i2c, csi->slv_addr, MT9V0XX_V1_CONTROL, &voltage_level_1);
|
||||
ret |= omv_i2c_writew(csi->i2c, csi->slv_addr, MT9V0X4_V1_CONTROL_B, voltage_level_1);
|
||||
|
||||
uint16_t voltage_level_2;
|
||||
ret |= omv_i2c_readw(&csi->i2c_bus, csi->slv_addr, MT9V0XX_V2_CONTROL, &voltage_level_2);
|
||||
ret |= omv_i2c_writew(&csi->i2c_bus, csi->slv_addr, MT9V0X4_V2_CONTROL_B, voltage_level_2);
|
||||
ret |= omv_i2c_readw(csi->i2c, csi->slv_addr, MT9V0XX_V2_CONTROL, &voltage_level_2);
|
||||
ret |= omv_i2c_writew(csi->i2c, csi->slv_addr, MT9V0X4_V2_CONTROL_B, voltage_level_2);
|
||||
|
||||
uint16_t voltage_level_3;
|
||||
ret |= omv_i2c_readw(&csi->i2c_bus, csi->slv_addr, MT9V0XX_V3_CONTROL, &voltage_level_3);
|
||||
ret |= omv_i2c_writew(&csi->i2c_bus, csi->slv_addr, MT9V0X4_V3_CONTROL_B, voltage_level_3);
|
||||
ret |= omv_i2c_readw(csi->i2c, csi->slv_addr, MT9V0XX_V3_CONTROL, &voltage_level_3);
|
||||
ret |= omv_i2c_writew(csi->i2c, csi->slv_addr, MT9V0X4_V3_CONTROL_B, voltage_level_3);
|
||||
|
||||
uint16_t voltage_level_4;
|
||||
ret |= omv_i2c_readw(&csi->i2c_bus, csi->slv_addr, MT9V0XX_V4_CONTROL, &voltage_level_4);
|
||||
ret |= omv_i2c_writew(&csi->i2c_bus, csi->slv_addr, MT9V0X4_V4_CONTROL_B, voltage_level_4);
|
||||
ret |= omv_i2c_readw(csi->i2c, csi->slv_addr, MT9V0XX_V4_CONTROL, &voltage_level_4);
|
||||
ret |= omv_i2c_writew(csi->i2c, csi->slv_addr, MT9V0X4_V4_CONTROL_B, voltage_level_4);
|
||||
|
||||
uint16_t analog_gain;
|
||||
ret |= omv_i2c_readw(&csi->i2c_bus, csi->slv_addr, MT9V0XX_ANALOG_GAIN, &analog_gain);
|
||||
ret |= omv_i2c_writew(&csi->i2c_bus, csi->slv_addr, MT9V0X4_ANALOG_GAIN_B, analog_gain);
|
||||
ret |= omv_i2c_readw(csi->i2c, csi->slv_addr, MT9V0XX_ANALOG_GAIN, &analog_gain);
|
||||
ret |= omv_i2c_writew(csi->i2c, csi->slv_addr, MT9V0X4_ANALOG_GAIN_B, analog_gain);
|
||||
|
||||
ret |= omv_i2c_writew(&csi->i2c_bus, csi->slv_addr, MT9V0XX_PIXEL_OPERATION_MODE,
|
||||
ret |= omv_i2c_writew(csi->i2c, csi->slv_addr, MT9V0XX_PIXEL_OPERATION_MODE,
|
||||
0);
|
||||
|
||||
ret |= omv_i2c_writew(&csi->i2c_bus, csi->slv_addr, MT9V0XX_ADC_COMPANDING_MODE,
|
||||
ret |= omv_i2c_writew(csi->i2c, csi->slv_addr, MT9V0XX_ADC_COMPANDING_MODE,
|
||||
MT9V0XX_ADC_COMPANDING_MODE_LINEAR | MT9V0X4_ADC_COMPANDING_MODE_LINEAR_B);
|
||||
|
||||
ret |= omv_i2c_writew(&csi->i2c_bus, csi->slv_addr, MT9V0XX_ROW_NOISE_CORR_CONTROL,
|
||||
ret |= omv_i2c_writew(csi->i2c, csi->slv_addr, MT9V0XX_ROW_NOISE_CORR_CONTROL,
|
||||
MT9V0X4_ROW_NOISE_CORR_ENABLE | MT9V0X4_ROW_NOISE_CORR_ENABLE_B);
|
||||
|
||||
ret |= omv_i2c_writew(&csi->i2c_bus, csi->slv_addr, MT9V0XX_AEC_AGC_ENABLE,
|
||||
ret |= omv_i2c_writew(csi->i2c, csi->slv_addr, MT9V0XX_AEC_AGC_ENABLE,
|
||||
MT9V0XX_AEC_ENABLE | MT9V0X4_AEC_ENABLE_B | MT9V0XX_AGC_ENABLE | MT9V0X4_AGC_ENABLE_B);
|
||||
}
|
||||
|
||||
if (is_mt9v0x2(csi)) {
|
||||
ret |= omv_i2c_writew(&csi->i2c_bus, csi->slv_addr, MT9V0X2_PIXEL_CLOCK, MT9V0XX_PIXEL_CLOCK_INV_PXL_CLK);
|
||||
ret |= omv_i2c_writew(csi->i2c, csi->slv_addr, MT9V0X2_PIXEL_CLOCK, MT9V0XX_PIXEL_CLOCK_INV_PXL_CLK);
|
||||
}
|
||||
|
||||
return ret;
|
||||
@ -140,14 +140,14 @@ static int reset(omv_csi_t *csi) {
|
||||
|
||||
static int read_reg(omv_csi_t *csi, uint16_t reg_addr) {
|
||||
uint16_t reg_data;
|
||||
if (omv_i2c_readw(&csi->i2c_bus, csi->slv_addr, reg_addr, ®_data) != 0) {
|
||||
if (omv_i2c_readw(csi->i2c, csi->slv_addr, reg_addr, ®_data) != 0) {
|
||||
return -1;
|
||||
}
|
||||
return reg_data;
|
||||
}
|
||||
|
||||
static int write_reg(omv_csi_t *csi, uint16_t reg_addr, uint16_t reg_data) {
|
||||
return omv_i2c_writew(&csi->i2c_bus, csi->slv_addr, reg_addr, reg_data);
|
||||
return omv_i2c_writew(csi->i2c, csi->slv_addr, reg_addr, reg_data);
|
||||
}
|
||||
|
||||
static int set_pixformat(omv_csi_t *csi, pixformat_t pixformat) {
|
||||
@ -184,7 +184,7 @@ static int set_framesize(omv_csi_t *csi, omv_csi_framesize_t framesize) {
|
||||
return -1;
|
||||
}
|
||||
|
||||
if (omv_i2c_readw(&csi->i2c_bus, csi->slv_addr, MT9V0XX_CHIP_CONTROL, &chip_control) != 0) {
|
||||
if (omv_i2c_readw(csi->i2c, csi->slv_addr, MT9V0XX_CHIP_CONTROL, &chip_control) != 0) {
|
||||
return -1;
|
||||
}
|
||||
|
||||
@ -199,7 +199,7 @@ static int set_framesize(omv_csi_t *csi, omv_csi_framesize_t framesize) {
|
||||
int window_width_addr = context ? MT9V0XX_WINDOW_WIDTH : MT9V0X4_WINDOW_WIDTH_B;
|
||||
int horizontal_blanking_addr = context ? MT9V0XX_HORIZONTAL_BLANKING : MT9V0X4_HORIZONTAL_BLANKING_B;
|
||||
|
||||
if (omv_i2c_readw(&csi->i2c_bus, csi->slv_addr, read_mode_addr, &read_mode) != 0) {
|
||||
if (omv_i2c_readw(csi->i2c, csi->slv_addr, read_mode_addr, &read_mode) != 0) {
|
||||
return -1;
|
||||
}
|
||||
|
||||
@ -221,12 +221,12 @@ static int set_framesize(omv_csi_t *csi, omv_csi_framesize_t framesize) {
|
||||
readout_x = IM_CLAMP(readout_x, -readout_x_max, readout_x_max);
|
||||
readout_y = IM_CLAMP(readout_y, -readout_y_max, readout_y_max);
|
||||
|
||||
ret |= omv_i2c_writew(&csi->i2c_bus, csi->slv_addr, col_start_addr,
|
||||
ret |= omv_i2c_writew(csi->i2c, csi->slv_addr, col_start_addr,
|
||||
readout_x_max - readout_x + MT9V0XX_COL_START_MIN); // sensor is mirrored by default
|
||||
ret |= omv_i2c_writew(&csi->i2c_bus, csi->slv_addr, row_start_addr,
|
||||
ret |= omv_i2c_writew(csi->i2c, csi->slv_addr, row_start_addr,
|
||||
readout_y_max - readout_y + MT9V0XX_ROW_START_MIN); // sensor is mirrored by default
|
||||
ret |= omv_i2c_writew(&csi->i2c_bus, csi->slv_addr, window_width_addr, w * read_mode_mul);
|
||||
ret |= omv_i2c_writew(&csi->i2c_bus, csi->slv_addr, window_height_addr, h * read_mode_mul);
|
||||
ret |= omv_i2c_writew(csi->i2c, csi->slv_addr, window_width_addr, w * read_mode_mul);
|
||||
ret |= omv_i2c_writew(csi->i2c, csi->slv_addr, window_height_addr, h * read_mode_mul);
|
||||
|
||||
// Notes: 1. The MT9V0XX uses column parallel analog-digital converters, thus short row timing is not possible.
|
||||
// The minimum total row time is 690 columns (horizontal width + horizontal blanking). The minimum
|
||||
@ -234,22 +234,22 @@ static int set_framesize(omv_csi_t *csi, omv_csi_framesize_t framesize) {
|
||||
// must be increased.
|
||||
//
|
||||
// The STM32H7 needs more than 94+(752-640) clocks between rows otherwise it can't keep up with the pixel rate.
|
||||
ret |= omv_i2c_writew(&csi->i2c_bus, csi->slv_addr, horizontal_blanking_addr,
|
||||
ret |= omv_i2c_writew(csi->i2c, csi->slv_addr, horizontal_blanking_addr,
|
||||
MT9V0XX_HORIZONTAL_BLANKING_DEF + (ACTIVE_SENSOR_WIDTH - IM_MIN(w * read_mode_mul, 640)));
|
||||
|
||||
ret |= omv_i2c_writew(&csi->i2c_bus, csi->slv_addr, read_mode_addr, read_mode);
|
||||
ret |= omv_i2c_writew(&csi->i2c_bus, csi->slv_addr, MT9V0XX_PIXEL_COUNT, (w * h) / 8);
|
||||
ret |= omv_i2c_writew(csi->i2c, csi->slv_addr, read_mode_addr, read_mode);
|
||||
ret |= omv_i2c_writew(csi->i2c, csi->slv_addr, MT9V0XX_PIXEL_COUNT, (w * h) / 8);
|
||||
|
||||
if (is_mt9v0x4(csi)) {
|
||||
// We need more setup time for the pixel_clk at the full data rate...
|
||||
ret |= omv_i2c_writew(&csi->i2c_bus, csi->slv_addr, MT9V0X4_PIXEL_CLOCK,
|
||||
ret |= omv_i2c_writew(csi->i2c, csi->slv_addr, MT9V0X4_PIXEL_CLOCK,
|
||||
(read_mode_mul == 1) ? MT9V0XX_PIXEL_CLOCK_INV_PXL_CLK : 0);
|
||||
}
|
||||
|
||||
// EDIT: WORKS BETTER TO STAY IN CONTEXT A
|
||||
//
|
||||
// Flip the context.
|
||||
// ret |= omv_i2c_writew(&csi->i2c_bus, csi->slv_addr, MT9V0XX_CHIP_CONTROL,
|
||||
// ret |= omv_i2c_writew(csi->i2c, csi->slv_addr, MT9V0XX_CHIP_CONTROL,
|
||||
// chip_control ^ MT9V0X4_CHIP_CONTROL_CONTEXT);
|
||||
|
||||
return ret;
|
||||
@ -260,12 +260,12 @@ static int set_colorbar(omv_csi_t *csi, int enable) {
|
||||
? (MT9V0X4_ROW_NOISE_CORR_ENABLE | MT9V0X4_ROW_NOISE_CORR_ENABLE_B)
|
||||
: MT9V0X2_ROW_NOISE_CORR_ENABLE;
|
||||
uint16_t reg;
|
||||
int ret = omv_i2c_readw(&csi->i2c_bus, csi->slv_addr, MT9V0XX_TEST_PATTERN, ®);
|
||||
ret |= omv_i2c_writew(&csi->i2c_bus, csi->slv_addr, MT9V0XX_TEST_PATTERN,
|
||||
int ret = omv_i2c_readw(csi->i2c, csi->slv_addr, MT9V0XX_TEST_PATTERN, ®);
|
||||
ret |= omv_i2c_writew(csi->i2c, csi->slv_addr, MT9V0XX_TEST_PATTERN,
|
||||
(reg & (~(MT9V0XX_TEST_PATTERN_ENABLE | MT9V0XX_TEST_PATTERN_GRAY_MASK)))
|
||||
| ((enable != 0) ? (MT9V0XX_TEST_PATTERN_ENABLE | MT9V0XX_TEST_PATTERN_GRAY_VERTICAL) : 0));
|
||||
ret = omv_i2c_readw(&csi->i2c_bus, csi->slv_addr, MT9V0XX_ROW_NOISE_CORR_CONTROL, ®);
|
||||
ret |= omv_i2c_writew(&csi->i2c_bus, csi->slv_addr, MT9V0XX_ROW_NOISE_CORR_CONTROL,
|
||||
ret = omv_i2c_readw(csi->i2c, csi->slv_addr, MT9V0XX_ROW_NOISE_CORR_CONTROL, ®);
|
||||
ret |= omv_i2c_writew(csi->i2c, csi->slv_addr, MT9V0XX_ROW_NOISE_CORR_CONTROL,
|
||||
(reg & (~mask)) | ((enable == 0) ? mask : 0));
|
||||
if (!csi->disable_delays) {
|
||||
ret |= csi->snapshot(csi, NULL, 0); // Force shadow mode register to update...
|
||||
@ -278,8 +278,8 @@ static int set_auto_gain(omv_csi_t *csi, int enable, float gain_db, float gain_d
|
||||
? (MT9V0XX_AGC_ENABLE | MT9V0X4_AGC_ENABLE_B)
|
||||
: MT9V0XX_AGC_ENABLE;
|
||||
uint16_t reg;
|
||||
int ret = omv_i2c_readw(&csi->i2c_bus, csi->slv_addr, MT9V0XX_AEC_AGC_ENABLE, ®);
|
||||
ret |= omv_i2c_writew(&csi->i2c_bus, csi->slv_addr, MT9V0XX_AEC_AGC_ENABLE,
|
||||
int ret = omv_i2c_readw(csi->i2c, csi->slv_addr, MT9V0XX_AEC_AGC_ENABLE, ®);
|
||||
ret |= omv_i2c_writew(csi->i2c, csi->slv_addr, MT9V0XX_AEC_AGC_ENABLE,
|
||||
(reg & (~agc_mask)) | ((enable != 0) ? agc_mask : 0));
|
||||
if (!csi->disable_delays) {
|
||||
ret |= csi->snapshot(csi, NULL, 0); // Force shadow mode register to update...
|
||||
@ -288,19 +288,19 @@ static int set_auto_gain(omv_csi_t *csi, int enable, float gain_db, float gain_d
|
||||
if ((enable == 0) && (!isnanf(gain_db)) && (!isinff(gain_db))) {
|
||||
int gain = IM_CLAMP(fast_roundf(expf((gain_db / 20.0f) * M_LN10) * 16.0f), 16, 64);
|
||||
|
||||
ret |= omv_i2c_readw(&csi->i2c_bus, csi->slv_addr, MT9V0XX_ANALOG_GAIN, ®);
|
||||
ret |= omv_i2c_writew(&csi->i2c_bus, csi->slv_addr, MT9V0XX_ANALOG_GAIN, (reg & 0xFF80) | gain);
|
||||
ret |= omv_i2c_readw(csi->i2c, csi->slv_addr, MT9V0XX_ANALOG_GAIN, ®);
|
||||
ret |= omv_i2c_writew(csi->i2c, csi->slv_addr, MT9V0XX_ANALOG_GAIN, (reg & 0xFF80) | gain);
|
||||
|
||||
if (is_mt9v0x4(csi)) {
|
||||
ret |= omv_i2c_readw(&csi->i2c_bus, csi->slv_addr, MT9V0X4_ANALOG_GAIN_B, ®);
|
||||
ret |= omv_i2c_writew(&csi->i2c_bus, csi->slv_addr, MT9V0X4_ANALOG_GAIN_B, (reg & 0xFF80) | gain);
|
||||
ret |= omv_i2c_readw(csi->i2c, csi->slv_addr, MT9V0X4_ANALOG_GAIN_B, ®);
|
||||
ret |= omv_i2c_writew(csi->i2c, csi->slv_addr, MT9V0X4_ANALOG_GAIN_B, (reg & 0xFF80) | gain);
|
||||
}
|
||||
} else if ((enable != 0) && (!isnanf(gain_db_ceiling)) && (!isinff(gain_db_ceiling))) {
|
||||
int gain_ceiling = IM_CLAMP(fast_roundf(expf((gain_db_ceiling / 20.0f) * M_LN10) * 16.0f), 16, 64);
|
||||
int max_gain = (is_mt9v0x4(csi)) ? MT9V0X4_MAX_GAIN : MT9V0X2_MAX_GAIN;
|
||||
|
||||
ret |= omv_i2c_readw(&csi->i2c_bus, csi->slv_addr, max_gain, ®);
|
||||
ret |= omv_i2c_writew(&csi->i2c_bus, csi->slv_addr, max_gain, (reg & 0xFF80) | gain_ceiling);
|
||||
ret |= omv_i2c_readw(csi->i2c, csi->slv_addr, max_gain, ®);
|
||||
ret |= omv_i2c_writew(csi->i2c, csi->slv_addr, max_gain, (reg & 0xFF80) | gain_ceiling);
|
||||
}
|
||||
|
||||
return ret;
|
||||
@ -308,15 +308,15 @@ static int set_auto_gain(omv_csi_t *csi, int enable, float gain_db, float gain_d
|
||||
|
||||
static int get_gain_db(omv_csi_t *csi, float *gain_db) {
|
||||
uint16_t chip_control, reg, gain;
|
||||
int ret = omv_i2c_readw(&csi->i2c_bus, csi->slv_addr, MT9V0XX_CHIP_CONTROL, &chip_control);
|
||||
int ret = omv_i2c_readw(csi->i2c, csi->slv_addr, MT9V0XX_CHIP_CONTROL, &chip_control);
|
||||
int context = chip_control & MT9V0X4_CHIP_CONTROL_CONTEXT;
|
||||
ret |= omv_i2c_readw(&csi->i2c_bus, csi->slv_addr, MT9V0XX_AEC_AGC_ENABLE, ®);
|
||||
ret |= omv_i2c_readw(csi->i2c, csi->slv_addr, MT9V0XX_AEC_AGC_ENABLE, ®);
|
||||
|
||||
if (reg & (context ? MT9V0X4_AGC_ENABLE_B : MT9V0XX_AGC_ENABLE)) {
|
||||
ret |= omv_i2c_readw(&csi->i2c_bus, csi->slv_addr, MT9V0XX_AGC_GAIN_OUTPUT, &gain);
|
||||
ret |= omv_i2c_readw(csi->i2c, csi->slv_addr, MT9V0XX_AGC_GAIN_OUTPUT, &gain);
|
||||
} else {
|
||||
int analog_gain = context ? MT9V0X4_ANALOG_GAIN_B : MT9V0XX_ANALOG_GAIN;
|
||||
ret |= omv_i2c_readw(&csi->i2c_bus, csi->slv_addr, analog_gain, &gain);
|
||||
ret |= omv_i2c_readw(csi->i2c, csi->slv_addr, analog_gain, &gain);
|
||||
}
|
||||
|
||||
*gain_db = 20.0f * log10f((gain & 0x7F) / 16.0f);
|
||||
@ -328,10 +328,10 @@ static int set_auto_exposure(omv_csi_t *csi, int enable, int exposure_us) {
|
||||
? (MT9V0XX_AEC_ENABLE | MT9V0X4_AEC_ENABLE_B)
|
||||
: MT9V0XX_AEC_ENABLE;
|
||||
uint16_t chip_control, reg, read_mode_reg, row_time_0, row_time_1;
|
||||
int ret = omv_i2c_readw(&csi->i2c_bus, csi->slv_addr, MT9V0XX_CHIP_CONTROL, &chip_control);
|
||||
int ret = omv_i2c_readw(csi->i2c, csi->slv_addr, MT9V0XX_CHIP_CONTROL, &chip_control);
|
||||
int context = chip_control & MT9V0X4_CHIP_CONTROL_CONTEXT;
|
||||
ret |= omv_i2c_readw(&csi->i2c_bus, csi->slv_addr, MT9V0XX_AEC_AGC_ENABLE, ®);
|
||||
ret |= omv_i2c_writew(&csi->i2c_bus, csi->slv_addr, MT9V0XX_AEC_AGC_ENABLE,
|
||||
ret |= omv_i2c_readw(csi->i2c, csi->slv_addr, MT9V0XX_AEC_AGC_ENABLE, ®);
|
||||
ret |= omv_i2c_writew(csi->i2c, csi->slv_addr, MT9V0XX_AEC_AGC_ENABLE,
|
||||
(reg & (~aec_mask)) | ((enable != 0) ? aec_mask : 0));
|
||||
if (!csi->disable_delays) {
|
||||
ret |= csi->snapshot(csi, NULL, 0); // Force shadow mode register to update...
|
||||
@ -339,9 +339,9 @@ static int set_auto_exposure(omv_csi_t *csi, int enable, int exposure_us) {
|
||||
int read_mode = context ? MT9V0X4_READ_MODE_B : MT9V0XX_READ_MODE;
|
||||
int window_width = context ? MT9V0X4_WINDOW_WIDTH_B : MT9V0XX_WINDOW_WIDTH;
|
||||
int horizontal_blanking = context ? MT9V0X4_HORIZONTAL_BLANKING_B : MT9V0XX_HORIZONTAL_BLANKING;
|
||||
ret |= omv_i2c_readw(&csi->i2c_bus, csi->slv_addr, read_mode, &read_mode_reg);
|
||||
ret |= omv_i2c_readw(&csi->i2c_bus, csi->slv_addr, window_width, &row_time_0);
|
||||
ret |= omv_i2c_readw(&csi->i2c_bus, csi->slv_addr, horizontal_blanking, &row_time_1);
|
||||
ret |= omv_i2c_readw(csi->i2c, csi->slv_addr, read_mode, &read_mode_reg);
|
||||
ret |= omv_i2c_readw(csi->i2c, csi->slv_addr, window_width, &row_time_0);
|
||||
ret |= omv_i2c_readw(csi->i2c, csi->slv_addr, horizontal_blanking, &row_time_1);
|
||||
|
||||
int clock = omv_csi_get_clk_frequency();
|
||||
|
||||
@ -352,20 +352,20 @@ static int set_auto_exposure(omv_csi_t *csi, int enable, int exposure_us) {
|
||||
|
||||
// Fine shutter time is global.
|
||||
if ((enable == 0) && (exposure_us >= 0)) {
|
||||
ret |= omv_i2c_writew(&csi->i2c_bus, csi->slv_addr, MT9V0XX_TOTAL_SHUTTER_WIDTH, coarse_time);
|
||||
ret |= omv_i2c_writew(csi->i2c, csi->slv_addr, MT9V0XX_TOTAL_SHUTTER_WIDTH, coarse_time);
|
||||
|
||||
if (is_mt9v0x4(csi)) {
|
||||
ret |= omv_i2c_writew(&csi->i2c_bus, csi->slv_addr, MT9V0X4_FINE_SHUTTER_WIDTH_TOTAL, fine_time);
|
||||
ret |= omv_i2c_writew(&csi->i2c_bus, csi->slv_addr, MT9V0X4_TOTAL_SHUTTER_WIDTH_B, coarse_time);
|
||||
ret |= omv_i2c_writew(&csi->i2c_bus, csi->slv_addr, MT9V0X4_FINE_SHUTTER_WIDTH_TOTAL_B, fine_time);
|
||||
ret |= omv_i2c_writew(csi->i2c, csi->slv_addr, MT9V0X4_FINE_SHUTTER_WIDTH_TOTAL, fine_time);
|
||||
ret |= omv_i2c_writew(csi->i2c, csi->slv_addr, MT9V0X4_TOTAL_SHUTTER_WIDTH_B, coarse_time);
|
||||
ret |= omv_i2c_writew(csi->i2c, csi->slv_addr, MT9V0X4_FINE_SHUTTER_WIDTH_TOTAL_B, fine_time);
|
||||
}
|
||||
} else if ((enable != 0) && (exposure_us >= 0)) {
|
||||
int max_expose = (is_mt9v0x4(csi)) ? MT9V0X4_MAX_EXPOSE : MT9V0X2_MAX_EXPOSE;
|
||||
ret |= omv_i2c_writew(&csi->i2c_bus, csi->slv_addr, max_expose, coarse_time);
|
||||
ret |= omv_i2c_writew(csi->i2c, csi->slv_addr, max_expose, coarse_time);
|
||||
|
||||
if (is_mt9v0x4(csi)) {
|
||||
ret |= omv_i2c_writew(&csi->i2c_bus, csi->slv_addr, MT9V0X4_FINE_SHUTTER_WIDTH_TOTAL, fine_time);
|
||||
ret |= omv_i2c_writew(&csi->i2c_bus, csi->slv_addr, MT9V0X4_FINE_SHUTTER_WIDTH_TOTAL_B, fine_time);
|
||||
ret |= omv_i2c_writew(csi->i2c, csi->slv_addr, MT9V0X4_FINE_SHUTTER_WIDTH_TOTAL, fine_time);
|
||||
ret |= omv_i2c_writew(csi->i2c, csi->slv_addr, MT9V0X4_FINE_SHUTTER_WIDTH_TOTAL_B, fine_time);
|
||||
}
|
||||
}
|
||||
|
||||
@ -374,28 +374,28 @@ static int set_auto_exposure(omv_csi_t *csi, int enable, int exposure_us) {
|
||||
|
||||
static int get_exposure_us(omv_csi_t *csi, int *exposure_us) {
|
||||
uint16_t chip_control, reg, read_mode_reg, row_time_0, row_time_1, int_pixels = 0, int_rows = 0;
|
||||
int ret = omv_i2c_readw(&csi->i2c_bus, csi->slv_addr, MT9V0XX_CHIP_CONTROL, &chip_control);
|
||||
int ret = omv_i2c_readw(csi->i2c, csi->slv_addr, MT9V0XX_CHIP_CONTROL, &chip_control);
|
||||
int context = chip_control & MT9V0X4_CHIP_CONTROL_CONTEXT;
|
||||
ret |= omv_i2c_readw(&csi->i2c_bus, csi->slv_addr, MT9V0XX_AEC_AGC_ENABLE, ®);
|
||||
ret |= omv_i2c_readw(csi->i2c, csi->slv_addr, MT9V0XX_AEC_AGC_ENABLE, ®);
|
||||
|
||||
int read_mode = context ? MT9V0X4_READ_MODE_B : MT9V0XX_READ_MODE;
|
||||
int window_width = context ? MT9V0X4_WINDOW_WIDTH_B : MT9V0XX_WINDOW_WIDTH;
|
||||
int horizontal_blanking = context ? MT9V0X4_HORIZONTAL_BLANKING_B : MT9V0XX_HORIZONTAL_BLANKING;
|
||||
int fine_shutter_width_total = context ? MT9V0X4_FINE_SHUTTER_WIDTH_TOTAL_B : MT9V0X4_FINE_SHUTTER_WIDTH_TOTAL;
|
||||
ret |= omv_i2c_readw(&csi->i2c_bus, csi->slv_addr, read_mode, &read_mode_reg);
|
||||
ret |= omv_i2c_readw(&csi->i2c_bus, csi->slv_addr, window_width, &row_time_0);
|
||||
ret |= omv_i2c_readw(&csi->i2c_bus, csi->slv_addr, horizontal_blanking, &row_time_1);
|
||||
ret |= omv_i2c_readw(csi->i2c, csi->slv_addr, read_mode, &read_mode_reg);
|
||||
ret |= omv_i2c_readw(csi->i2c, csi->slv_addr, window_width, &row_time_0);
|
||||
ret |= omv_i2c_readw(csi->i2c, csi->slv_addr, horizontal_blanking, &row_time_1);
|
||||
if (is_mt9v0x4(csi)) {
|
||||
ret |= omv_i2c_readw(&csi->i2c_bus, csi->slv_addr, fine_shutter_width_total, &int_pixels);
|
||||
ret |= omv_i2c_readw(csi->i2c, csi->slv_addr, fine_shutter_width_total, &int_pixels);
|
||||
}
|
||||
|
||||
int clock = omv_csi_get_clk_frequency();
|
||||
|
||||
if (reg & (context ? MT9V0X4_AEC_ENABLE_B : MT9V0XX_AEC_ENABLE)) {
|
||||
ret |= omv_i2c_readw(&csi->i2c_bus, csi->slv_addr, MT9V0XX_AEC_EXPOSURE_OUTPUT, &int_rows);
|
||||
ret |= omv_i2c_readw(csi->i2c, csi->slv_addr, MT9V0XX_AEC_EXPOSURE_OUTPUT, &int_rows);
|
||||
} else {
|
||||
int total_shutter_width = context ? MT9V0X4_TOTAL_SHUTTER_WIDTH_B : MT9V0XX_TOTAL_SHUTTER_WIDTH;
|
||||
ret |= omv_i2c_readw(&csi->i2c_bus, csi->slv_addr, total_shutter_width, &int_rows);
|
||||
ret |= omv_i2c_readw(csi->i2c, csi->slv_addr, total_shutter_width, &int_rows);
|
||||
}
|
||||
|
||||
*exposure_us = ((int_rows * (row_time_0 + row_time_1)) + int_pixels) / (clock / MICROSECOND_CLKS);
|
||||
@ -404,13 +404,13 @@ static int get_exposure_us(omv_csi_t *csi, int *exposure_us) {
|
||||
|
||||
static int set_hmirror(omv_csi_t *csi, int enable) {
|
||||
uint16_t read_mode;
|
||||
int ret = omv_i2c_readw(&csi->i2c_bus, csi->slv_addr, MT9V0XX_READ_MODE, &read_mode);
|
||||
ret |= omv_i2c_writew(&csi->i2c_bus, csi->slv_addr, MT9V0XX_READ_MODE, // inverted behavior
|
||||
int ret = omv_i2c_readw(csi->i2c, csi->slv_addr, MT9V0XX_READ_MODE, &read_mode);
|
||||
ret |= omv_i2c_writew(csi->i2c, csi->slv_addr, MT9V0XX_READ_MODE, // inverted behavior
|
||||
(read_mode & (~MT9V0XX_READ_MODE_COL_FLIP)) | ((enable == 0) ? MT9V0XX_READ_MODE_COL_FLIP : 0));
|
||||
|
||||
if (is_mt9v0x4(csi)) {
|
||||
ret |= omv_i2c_readw(&csi->i2c_bus, csi->slv_addr, MT9V0X4_READ_MODE_B, &read_mode);
|
||||
ret |= omv_i2c_writew(&csi->i2c_bus, csi->slv_addr, MT9V0X4_READ_MODE_B, // inverted behavior
|
||||
ret |= omv_i2c_readw(csi->i2c, csi->slv_addr, MT9V0X4_READ_MODE_B, &read_mode);
|
||||
ret |= omv_i2c_writew(csi->i2c, csi->slv_addr, MT9V0X4_READ_MODE_B, // inverted behavior
|
||||
(read_mode & (~MT9V0XX_READ_MODE_COL_FLIP)) | ((enable == 0) ? MT9V0XX_READ_MODE_COL_FLIP : 0));
|
||||
}
|
||||
|
||||
@ -422,13 +422,13 @@ static int set_hmirror(omv_csi_t *csi, int enable) {
|
||||
|
||||
static int set_vflip(omv_csi_t *csi, int enable) {
|
||||
uint16_t read_mode;
|
||||
int ret = omv_i2c_readw(&csi->i2c_bus, csi->slv_addr, MT9V0XX_READ_MODE, &read_mode);
|
||||
ret |= omv_i2c_writew(&csi->i2c_bus, csi->slv_addr, MT9V0XX_READ_MODE, // inverted behavior
|
||||
int ret = omv_i2c_readw(csi->i2c, csi->slv_addr, MT9V0XX_READ_MODE, &read_mode);
|
||||
ret |= omv_i2c_writew(csi->i2c, csi->slv_addr, MT9V0XX_READ_MODE, // inverted behavior
|
||||
(read_mode & (~MT9V0XX_READ_MODE_ROW_FLIP)) | ((enable == 0) ? MT9V0XX_READ_MODE_ROW_FLIP : 0));
|
||||
|
||||
if (is_mt9v0x4(csi)) {
|
||||
ret |= omv_i2c_readw(&csi->i2c_bus, csi->slv_addr, MT9V0X4_READ_MODE_B, &read_mode);
|
||||
ret |= omv_i2c_writew(&csi->i2c_bus, csi->slv_addr, MT9V0X4_READ_MODE_B, // inverted behavior
|
||||
ret |= omv_i2c_readw(csi->i2c, csi->slv_addr, MT9V0X4_READ_MODE_B, &read_mode);
|
||||
ret |= omv_i2c_writew(csi->i2c, csi->slv_addr, MT9V0X4_READ_MODE_B, // inverted behavior
|
||||
(read_mode & (~MT9V0XX_READ_MODE_ROW_FLIP)) | ((enable == 0) ? MT9V0XX_READ_MODE_ROW_FLIP : 0));
|
||||
}
|
||||
|
||||
@ -487,8 +487,8 @@ static int ioctl(omv_csi_t *csi, int request, va_list ap) {
|
||||
}
|
||||
case OMV_CSI_IOCTL_SET_TRIGGERED_MODE: {
|
||||
int enable = va_arg(ap, int);
|
||||
ret = omv_i2c_readw(&csi->i2c_bus, csi->slv_addr, MT9V0XX_CHIP_CONTROL, &chip_control);
|
||||
ret |= omv_i2c_writew(&csi->i2c_bus, csi->slv_addr, MT9V0XX_CHIP_CONTROL,
|
||||
ret = omv_i2c_readw(csi->i2c, csi->slv_addr, MT9V0XX_CHIP_CONTROL, &chip_control);
|
||||
ret |= omv_i2c_writew(csi->i2c, csi->slv_addr, MT9V0XX_CHIP_CONTROL,
|
||||
(chip_control & (~MT9V0XX_CHIP_CONTROL_MODE_MASK))
|
||||
| ((enable != 0) ? MT9V0XX_CHIP_CONTROL_SNAP_MODE : MT9V0XX_CHIP_CONTROL_MASTER_MODE));
|
||||
if (!csi->disable_delays) {
|
||||
@ -498,7 +498,7 @@ static int ioctl(omv_csi_t *csi, int request, va_list ap) {
|
||||
}
|
||||
case OMV_CSI_IOCTL_GET_TRIGGERED_MODE: {
|
||||
int *enable = va_arg(ap, int *);
|
||||
ret = omv_i2c_readw(&csi->i2c_bus, csi->slv_addr, MT9V0XX_CHIP_CONTROL, &chip_control);
|
||||
ret = omv_i2c_readw(csi->i2c, csi->slv_addr, MT9V0XX_CHIP_CONTROL, &chip_control);
|
||||
if (ret >= 0) {
|
||||
*enable = ((chip_control & MT9V0XX_CHIP_CONTROL_MODE_MASK) == MT9V0XX_CHIP_CONTROL_SNAP_MODE);
|
||||
}
|
||||
@ -538,7 +538,7 @@ int mt9v0xx_init(omv_csi_t *csi) {
|
||||
csi->cfa_format = SUBFORMAT_ID_BGGR;
|
||||
|
||||
uint16_t cfa_type_reg;
|
||||
int ret = omv_i2c_readw(&csi->i2c_bus, csi->slv_addr, MT9V0XX_CFA_ID_REG, &cfa_type_reg);
|
||||
int ret = omv_i2c_readw(csi->i2c, csi->slv_addr, MT9V0XX_CFA_ID_REG, &cfa_type_reg);
|
||||
switch ((cfa_type_reg >> 9) & 0x7) {
|
||||
case BAYER_CFA_ID: {
|
||||
cfa_type = BAYER_CFA;
|
||||
|
||||
@ -362,15 +362,15 @@ static const uint8_t saturation_regs[NUM_SATURATION_LEVELS + 1][5] = {
|
||||
|
||||
static int reset(omv_csi_t *csi) {
|
||||
// Reset all registers
|
||||
int ret = omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, BANK_SEL, BANK_SEL_SENSOR);
|
||||
ret |= omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, COM7, COM7_SRST);
|
||||
int ret = omv_i2c_writeb(csi->i2c, csi->slv_addr, BANK_SEL, BANK_SEL_SENSOR);
|
||||
ret |= omv_i2c_writeb(csi->i2c, csi->slv_addr, COM7, COM7_SRST);
|
||||
|
||||
// Delay 5 ms
|
||||
mp_hal_delay_ms(5);
|
||||
|
||||
// Write default registers
|
||||
for (int i = 0; default_regs[i][0]; i++) {
|
||||
ret |= omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, default_regs[i][0], default_regs[i][1]);
|
||||
ret |= omv_i2c_writeb(csi->i2c, csi->slv_addr, default_regs[i][0], default_regs[i][1]);
|
||||
}
|
||||
|
||||
// Delay 300 ms
|
||||
@ -383,7 +383,7 @@ static int reset(omv_csi_t *csi) {
|
||||
|
||||
static int sleep(omv_csi_t *csi, int enable) {
|
||||
uint8_t reg;
|
||||
int ret = omv_i2c_readb(&csi->i2c_bus, csi->slv_addr, COM2, ®);
|
||||
int ret = omv_i2c_readb(csi->i2c, csi->slv_addr, COM2, ®);
|
||||
|
||||
if (enable) {
|
||||
reg |= COM2_STDBY;
|
||||
@ -392,19 +392,19 @@ static int sleep(omv_csi_t *csi, int enable) {
|
||||
}
|
||||
|
||||
// Write back register
|
||||
return omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, COM2, reg) | ret;
|
||||
return omv_i2c_writeb(csi->i2c, csi->slv_addr, COM2, reg) | ret;
|
||||
}
|
||||
|
||||
static int read_reg(omv_csi_t *csi, uint16_t reg_addr) {
|
||||
uint8_t reg_data;
|
||||
if (omv_i2c_readb(&csi->i2c_bus, csi->slv_addr, reg_addr, ®_data) != 0) {
|
||||
if (omv_i2c_readb(csi->i2c, csi->slv_addr, reg_addr, ®_data) != 0) {
|
||||
return -1;
|
||||
}
|
||||
return reg_data;
|
||||
}
|
||||
|
||||
static int write_reg(omv_csi_t *csi, uint16_t reg_addr, uint16_t reg_data) {
|
||||
return omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, reg_addr, reg_data);
|
||||
return omv_i2c_writeb(csi->i2c, csi->slv_addr, reg_addr, reg_data);
|
||||
}
|
||||
|
||||
static int set_pixformat(omv_csi_t *csi, pixformat_t pixformat) {
|
||||
@ -431,7 +431,7 @@ static int set_pixformat(omv_csi_t *csi, pixformat_t pixformat) {
|
||||
|
||||
// Write registers
|
||||
for (int i = 0; regs[i][0]; i++) {
|
||||
ret |= omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, regs[i][0], regs[i][1]);
|
||||
ret |= omv_i2c_writeb(csi->i2c, csi->slv_addr, regs[i][0], regs[i][1]);
|
||||
}
|
||||
|
||||
return ret;
|
||||
@ -467,7 +467,7 @@ static int set_framesize(omv_csi_t *csi, omv_csi_framesize_t framesize) {
|
||||
|
||||
// Write setup registers
|
||||
for (int i = 0; regs[i][0]; i++) {
|
||||
ret |= omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, regs[i][0], regs[i][1]);
|
||||
ret |= omv_i2c_writeb(csi->i2c, csi->slv_addr, regs[i][0], regs[i][1]);
|
||||
}
|
||||
|
||||
uint64_t tmp_div = IM_MIN(sensor_w / w, sensor_h / h);
|
||||
@ -479,22 +479,22 @@ static int set_framesize(omv_csi_t *csi, omv_csi_framesize_t framesize) {
|
||||
uint16_t y_off = (sensor_h - h_mul) / 2;
|
||||
|
||||
ret |=
|
||||
omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, CTRLI,
|
||||
omv_i2c_writeb(csi->i2c, csi->slv_addr, CTRLI,
|
||||
CTRLI_LP_DP | CTRLI_V_DIV_SET(log_div) | CTRLI_H_DIV_SET(log_div));
|
||||
ret |= omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, HSIZE, HSIZE_SET(w_mul));
|
||||
ret |= omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, VSIZE, VSIZE_SET(h_mul));
|
||||
ret |= omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, XOFFL, XOFFL_SET(x_off));
|
||||
ret |= omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, YOFFL, YOFFL_SET(y_off));
|
||||
ret |= omv_i2c_writeb(&csi->i2c_bus,
|
||||
ret |= omv_i2c_writeb(csi->i2c, csi->slv_addr, HSIZE, HSIZE_SET(w_mul));
|
||||
ret |= omv_i2c_writeb(csi->i2c, csi->slv_addr, VSIZE, VSIZE_SET(h_mul));
|
||||
ret |= omv_i2c_writeb(csi->i2c, csi->slv_addr, XOFFL, XOFFL_SET(x_off));
|
||||
ret |= omv_i2c_writeb(csi->i2c, csi->slv_addr, YOFFL, YOFFL_SET(y_off));
|
||||
ret |= omv_i2c_writeb(csi->i2c,
|
||||
csi->slv_addr,
|
||||
VHYX,
|
||||
VHYX_HSIZE_SET(w_mul) | VHYX_VSIZE_SET(h_mul) | VHYX_XOFF_SET(x_off) | VHYX_YOFF_SET(y_off));
|
||||
ret |= omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, TEST, TEST_HSIZE_SET(w_mul));
|
||||
ret |= omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, ZMOW, ZMOW_OUTW_SET(w));
|
||||
ret |= omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, ZMOH, ZMOH_OUTH_SET(h));
|
||||
ret |= omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, ZMHH, ZMHH_OUTW_SET(w) | ZMHH_OUTH_SET(h));
|
||||
ret |= omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, R_DVP_SP, div);
|
||||
ret |= omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, RESET, 0x00);
|
||||
ret |= omv_i2c_writeb(csi->i2c, csi->slv_addr, TEST, TEST_HSIZE_SET(w_mul));
|
||||
ret |= omv_i2c_writeb(csi->i2c, csi->slv_addr, ZMOW, ZMOW_OUTW_SET(w));
|
||||
ret |= omv_i2c_writeb(csi->i2c, csi->slv_addr, ZMOH, ZMOH_OUTH_SET(h));
|
||||
ret |= omv_i2c_writeb(csi->i2c, csi->slv_addr, ZMHH, ZMHH_OUTW_SET(w) | ZMHH_OUTH_SET(h));
|
||||
ret |= omv_i2c_writeb(csi->i2c, csi->slv_addr, R_DVP_SP, div);
|
||||
ret |= omv_i2c_writeb(csi->i2c, csi->slv_addr, RESET, 0x00);
|
||||
|
||||
return ret;
|
||||
}
|
||||
@ -508,11 +508,11 @@ static int set_contrast(omv_csi_t *csi, int level) {
|
||||
}
|
||||
|
||||
/* Switch to DSP register bank */
|
||||
ret |= omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, BANK_SEL, BANK_SEL_DSP);
|
||||
ret |= omv_i2c_writeb(csi->i2c, csi->slv_addr, BANK_SEL, BANK_SEL_DSP);
|
||||
|
||||
/* Write contrast registers */
|
||||
for (int i = 0; i < sizeof(contrast_regs[0]) / sizeof(contrast_regs[0][0]); i++) {
|
||||
ret |= omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, contrast_regs[0][i], contrast_regs[level][i]);
|
||||
ret |= omv_i2c_writeb(csi->i2c, csi->slv_addr, contrast_regs[0][i], contrast_regs[level][i]);
|
||||
}
|
||||
|
||||
return ret;
|
||||
@ -527,11 +527,11 @@ static int set_brightness(omv_csi_t *csi, int level) {
|
||||
}
|
||||
|
||||
/* Switch to DSP register bank */
|
||||
ret |= omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, BANK_SEL, BANK_SEL_DSP);
|
||||
ret |= omv_i2c_writeb(csi->i2c, csi->slv_addr, BANK_SEL, BANK_SEL_DSP);
|
||||
|
||||
/* Write brightness registers */
|
||||
for (int i = 0; i < sizeof(brightness_regs[0]) / sizeof(brightness_regs[0][0]); i++) {
|
||||
ret |= omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, brightness_regs[0][i], brightness_regs[level][i]);
|
||||
ret |= omv_i2c_writeb(csi->i2c, csi->slv_addr, brightness_regs[0][i], brightness_regs[level][i]);
|
||||
}
|
||||
|
||||
return ret;
|
||||
@ -546,11 +546,11 @@ static int set_saturation(omv_csi_t *csi, int level) {
|
||||
}
|
||||
|
||||
/* Switch to DSP register bank */
|
||||
ret |= omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, BANK_SEL, BANK_SEL_DSP);
|
||||
ret |= omv_i2c_writeb(csi->i2c, csi->slv_addr, BANK_SEL, BANK_SEL_DSP);
|
||||
|
||||
/* Write saturation registers */
|
||||
for (int i = 0; i < sizeof(saturation_regs[0]) / sizeof(saturation_regs[0][0]); i++) {
|
||||
ret |= omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, saturation_regs[0][i], saturation_regs[level][i]);
|
||||
ret |= omv_i2c_writeb(csi->i2c, csi->slv_addr, saturation_regs[0][i], saturation_regs[level][i]);
|
||||
}
|
||||
|
||||
return ret;
|
||||
@ -560,10 +560,10 @@ static int set_gainceiling(omv_csi_t *csi, omv_csi_gainceiling_t gainceiling) {
|
||||
int ret = 0;
|
||||
|
||||
/* Switch to SENSOR register bank */
|
||||
ret |= omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, BANK_SEL, BANK_SEL_SENSOR);
|
||||
ret |= omv_i2c_writeb(csi->i2c, csi->slv_addr, BANK_SEL, BANK_SEL_SENSOR);
|
||||
|
||||
/* Write gain ceiling register */
|
||||
ret |= omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, COM9, COM9_AGC_SET(gainceiling));
|
||||
ret |= omv_i2c_writeb(csi->i2c, csi->slv_addr, COM9, COM9_AGC_SET(gainceiling));
|
||||
|
||||
return ret;
|
||||
}
|
||||
@ -572,18 +572,18 @@ static int set_quality(omv_csi_t *csi, int qs) {
|
||||
int ret = 0;
|
||||
|
||||
/* Switch to DSP register bank */
|
||||
ret |= omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, BANK_SEL, BANK_SEL_DSP);
|
||||
ret |= omv_i2c_writeb(csi->i2c, csi->slv_addr, BANK_SEL, BANK_SEL_DSP);
|
||||
|
||||
/* Write QS register */
|
||||
ret |= omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, QS, qs);
|
||||
ret |= omv_i2c_writeb(csi->i2c, csi->slv_addr, QS, qs);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int set_colorbar(omv_csi_t *csi, int enable) {
|
||||
uint8_t reg;
|
||||
int ret = omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, BANK_SEL, BANK_SEL_SENSOR);
|
||||
ret |= omv_i2c_readb(&csi->i2c_bus, csi->slv_addr, COM7, ®);
|
||||
int ret = omv_i2c_writeb(csi->i2c, csi->slv_addr, BANK_SEL, BANK_SEL_SENSOR);
|
||||
ret |= omv_i2c_readb(csi->i2c, csi->slv_addr, COM7, ®);
|
||||
|
||||
if (enable) {
|
||||
reg |= COM7_COLOR_BAR;
|
||||
@ -591,14 +591,14 @@ static int set_colorbar(omv_csi_t *csi, int enable) {
|
||||
reg &= ~COM7_COLOR_BAR;
|
||||
}
|
||||
|
||||
return omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, COM7, reg) | ret;
|
||||
return omv_i2c_writeb(csi->i2c, csi->slv_addr, COM7, reg) | ret;
|
||||
}
|
||||
|
||||
static int set_auto_gain(omv_csi_t *csi, int enable, float gain_db, float gain_db_ceiling) {
|
||||
uint8_t reg;
|
||||
int ret = omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, BANK_SEL, BANK_SEL_SENSOR);
|
||||
ret |= omv_i2c_readb(&csi->i2c_bus, csi->slv_addr, COM8, ®);
|
||||
ret |= omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, COM8, (reg & (~COM8_AGC_EN)) | ((enable != 0) ? COM8_AGC_EN : 0));
|
||||
int ret = omv_i2c_writeb(csi->i2c, csi->slv_addr, BANK_SEL, BANK_SEL_SENSOR);
|
||||
ret |= omv_i2c_readb(csi->i2c, csi->slv_addr, COM8, ®);
|
||||
ret |= omv_i2c_writeb(csi->i2c, csi->slv_addr, COM8, (reg & (~COM8_AGC_EN)) | ((enable != 0) ? COM8_AGC_EN : 0));
|
||||
|
||||
if ((enable == 0) && (!isnanf(gain_db)) && (!isinff(gain_db))) {
|
||||
float gain = IM_CLAMP(expf((gain_db / 20.0f) * M_LN10), 1.0f, 32.0f);
|
||||
@ -607,13 +607,13 @@ static int set_auto_gain(omv_csi_t *csi, int enable, float gain_db, float gain_d
|
||||
int gain_hi = 0xF >> (4 - gain_temp);
|
||||
int gain_lo = IM_MIN(fast_roundf(((gain / (1 << gain_temp)) - 1.0f) * 16.0f), 15);
|
||||
|
||||
ret |= omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, GAIN, (gain_hi << 4) | (gain_lo << 0));
|
||||
ret |= omv_i2c_writeb(csi->i2c, csi->slv_addr, GAIN, (gain_hi << 4) | (gain_lo << 0));
|
||||
} else if ((enable != 0) && (!isnanf(gain_db_ceiling)) && (!isinff(gain_db_ceiling))) {
|
||||
float gain_ceiling = IM_CLAMP(expf((gain_db_ceiling / 20.0f) * M_LN10), 2.0f, 128.0f);
|
||||
|
||||
ret |= omv_i2c_readb(&csi->i2c_bus, csi->slv_addr, COM9, ®);
|
||||
ret |= omv_i2c_readb(csi->i2c, csi->slv_addr, COM9, ®);
|
||||
ret |=
|
||||
omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, COM9,
|
||||
omv_i2c_writeb(csi->i2c, csi->slv_addr, COM9,
|
||||
(reg & 0x1F) | ((fast_ceilf(logf(gain_ceiling) / M_LN2) - 1) << 5));
|
||||
}
|
||||
|
||||
@ -622,20 +622,20 @@ static int set_auto_gain(omv_csi_t *csi, int enable, float gain_db, float gain_d
|
||||
|
||||
static int get_gain_db(omv_csi_t *csi, float *gain_db) {
|
||||
uint8_t reg, gain;
|
||||
int ret = omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, BANK_SEL, BANK_SEL_SENSOR);
|
||||
ret |= omv_i2c_readb(&csi->i2c_bus, csi->slv_addr, COM8, ®);
|
||||
int ret = omv_i2c_writeb(csi->i2c, csi->slv_addr, BANK_SEL, BANK_SEL_SENSOR);
|
||||
ret |= omv_i2c_readb(csi->i2c, csi->slv_addr, COM8, ®);
|
||||
|
||||
// DISABLED
|
||||
// if (reg & COM8_AGC_EN) {
|
||||
// ret |= omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, COM8, reg & (~COM8_AGC_EN));
|
||||
// ret |= omv_i2c_writeb(csi->i2c, csi->slv_addr, COM8, reg & (~COM8_AGC_EN));
|
||||
// }
|
||||
// DISABLED
|
||||
|
||||
ret |= omv_i2c_readb(&csi->i2c_bus, csi->slv_addr, GAIN, &gain);
|
||||
ret |= omv_i2c_readb(csi->i2c, csi->slv_addr, GAIN, &gain);
|
||||
|
||||
// DISABLED
|
||||
// if (reg & COM8_AGC_EN) {
|
||||
// ret |= omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, COM8, reg | COM8_AGC_EN);
|
||||
// ret |= omv_i2c_writeb(csi->i2c, csi->slv_addr, COM8, reg | COM8_AGC_EN);
|
||||
// }
|
||||
// DISABLED
|
||||
|
||||
@ -648,12 +648,12 @@ static int get_gain_db(omv_csi_t *csi, float *gain_db) {
|
||||
|
||||
static int set_auto_exposure(omv_csi_t *csi, int enable, int exposure_us) {
|
||||
uint8_t reg;
|
||||
int ret = omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, BANK_SEL, BANK_SEL_SENSOR);
|
||||
ret |= omv_i2c_readb(&csi->i2c_bus, csi->slv_addr, COM8, ®);
|
||||
ret |= omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, COM8, COM8_SET_AEC(reg, (enable != 0)));
|
||||
int ret = omv_i2c_writeb(csi->i2c, csi->slv_addr, BANK_SEL, BANK_SEL_SENSOR);
|
||||
ret |= omv_i2c_readb(csi->i2c, csi->slv_addr, COM8, ®);
|
||||
ret |= omv_i2c_writeb(csi->i2c, csi->slv_addr, COM8, COM8_SET_AEC(reg, (enable != 0)));
|
||||
|
||||
if ((enable == 0) && (exposure_us >= 0)) {
|
||||
ret |= omv_i2c_readb(&csi->i2c_bus, csi->slv_addr, COM7, ®);
|
||||
ret |= omv_i2c_readb(csi->i2c, csi->slv_addr, COM7, ®);
|
||||
int t_line = 0;
|
||||
|
||||
if (COM7_GET_RES(reg) == COM7_RES_UXGA) {
|
||||
@ -666,12 +666,12 @@ static int set_auto_exposure(omv_csi_t *csi, int enable, int exposure_us) {
|
||||
t_line = 400 + 195;
|
||||
}
|
||||
|
||||
ret |= omv_i2c_readb(&csi->i2c_bus, csi->slv_addr, CLKRC, ®);
|
||||
ret |= omv_i2c_readb(csi->i2c, csi->slv_addr, CLKRC, ®);
|
||||
int pll_mult = ((reg & CLKRC_DOUBLE) ? 2 : 1) * 3;
|
||||
int clk_rc = (reg & CLKRC_DIVIDER_MASK) + 2;
|
||||
|
||||
ret |= omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, BANK_SEL, BANK_SEL_DSP);
|
||||
ret |= omv_i2c_readb(&csi->i2c_bus, csi->slv_addr, IMAGE_MODE, ®);
|
||||
ret |= omv_i2c_writeb(csi->i2c, csi->slv_addr, BANK_SEL, BANK_SEL_DSP);
|
||||
ret |= omv_i2c_readb(csi->i2c, csi->slv_addr, IMAGE_MODE, ®);
|
||||
int t_pclk = 0;
|
||||
|
||||
if (IMAGE_MODE_GET_FMT(reg) == IMAGE_MODE_YUV422) {
|
||||
@ -687,16 +687,16 @@ static int set_auto_exposure(omv_csi_t *csi, int enable, int exposure_us) {
|
||||
int exposure =
|
||||
__USAT(((exposure_us * (((OMV_CSI_CLK_FREQUENCY / clk_rc) * pll_mult) / 1000000)) / t_pclk) / t_line, 16);
|
||||
|
||||
ret |= omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, BANK_SEL, BANK_SEL_SENSOR);
|
||||
ret |= omv_i2c_writeb(csi->i2c, csi->slv_addr, BANK_SEL, BANK_SEL_SENSOR);
|
||||
|
||||
ret |= omv_i2c_readb(&csi->i2c_bus, csi->slv_addr, REG04, ®);
|
||||
ret |= omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, REG04, (reg & 0xFC) | ((exposure >> 0) & 0x3));
|
||||
ret |= omv_i2c_readb(csi->i2c, csi->slv_addr, REG04, ®);
|
||||
ret |= omv_i2c_writeb(csi->i2c, csi->slv_addr, REG04, (reg & 0xFC) | ((exposure >> 0) & 0x3));
|
||||
|
||||
ret |= omv_i2c_readb(&csi->i2c_bus, csi->slv_addr, AEC, ®);
|
||||
ret |= omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, AEC, (reg & 0x00) | ((exposure >> 2) & 0xFF));
|
||||
ret |= omv_i2c_readb(csi->i2c, csi->slv_addr, AEC, ®);
|
||||
ret |= omv_i2c_writeb(csi->i2c, csi->slv_addr, AEC, (reg & 0x00) | ((exposure >> 2) & 0xFF));
|
||||
|
||||
ret |= omv_i2c_readb(&csi->i2c_bus, csi->slv_addr, REG45, ®);
|
||||
ret |= omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, REG45, (reg & 0xC0) | ((exposure >> 10) & 0x3F));
|
||||
ret |= omv_i2c_readb(csi->i2c, csi->slv_addr, REG45, ®);
|
||||
ret |= omv_i2c_writeb(csi->i2c, csi->slv_addr, REG45, (reg & 0xC0) | ((exposure >> 10) & 0x3F));
|
||||
}
|
||||
|
||||
return ret;
|
||||
@ -704,26 +704,26 @@ static int set_auto_exposure(omv_csi_t *csi, int enable, int exposure_us) {
|
||||
|
||||
static int get_exposure_us(omv_csi_t *csi, int *exposure_us) {
|
||||
uint8_t reg, aec_10, aec_92, aec_1510;
|
||||
int ret = omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, BANK_SEL, BANK_SEL_SENSOR);
|
||||
ret |= omv_i2c_readb(&csi->i2c_bus, csi->slv_addr, COM8, ®);
|
||||
int ret = omv_i2c_writeb(csi->i2c, csi->slv_addr, BANK_SEL, BANK_SEL_SENSOR);
|
||||
ret |= omv_i2c_readb(csi->i2c, csi->slv_addr, COM8, ®);
|
||||
|
||||
// DISABLED
|
||||
// if (reg & COM8_AEC_EN) {
|
||||
// ret |= omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, COM8, reg & (~COM8_AEC_EN));
|
||||
// ret |= omv_i2c_writeb(csi->i2c, csi->slv_addr, COM8, reg & (~COM8_AEC_EN));
|
||||
// }
|
||||
// DISABLED
|
||||
|
||||
ret |= omv_i2c_readb(&csi->i2c_bus, csi->slv_addr, REG04, &aec_10);
|
||||
ret |= omv_i2c_readb(&csi->i2c_bus, csi->slv_addr, AEC, &aec_92);
|
||||
ret |= omv_i2c_readb(&csi->i2c_bus, csi->slv_addr, REG45, &aec_1510);
|
||||
ret |= omv_i2c_readb(csi->i2c, csi->slv_addr, REG04, &aec_10);
|
||||
ret |= omv_i2c_readb(csi->i2c, csi->slv_addr, AEC, &aec_92);
|
||||
ret |= omv_i2c_readb(csi->i2c, csi->slv_addr, REG45, &aec_1510);
|
||||
|
||||
// DISABLED
|
||||
// if (reg & COM8_AEC_EN) {
|
||||
// ret |= omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, COM8, reg | COM8_AEC_EN);
|
||||
// ret |= omv_i2c_writeb(csi->i2c, csi->slv_addr, COM8, reg | COM8_AEC_EN);
|
||||
// }
|
||||
// DISABLED
|
||||
|
||||
ret |= omv_i2c_readb(&csi->i2c_bus, csi->slv_addr, COM7, ®);
|
||||
ret |= omv_i2c_readb(csi->i2c, csi->slv_addr, COM7, ®);
|
||||
int t_line = 0;
|
||||
|
||||
if (COM7_GET_RES(reg) == COM7_RES_UXGA) {
|
||||
@ -736,12 +736,12 @@ static int get_exposure_us(omv_csi_t *csi, int *exposure_us) {
|
||||
t_line = 400 + 195;
|
||||
}
|
||||
|
||||
ret |= omv_i2c_readb(&csi->i2c_bus, csi->slv_addr, CLKRC, ®);
|
||||
ret |= omv_i2c_readb(csi->i2c, csi->slv_addr, CLKRC, ®);
|
||||
int pll_mult = ((reg & CLKRC_DOUBLE) ? 2 : 1) * 3;
|
||||
int clk_rc = (reg & CLKRC_DIVIDER_MASK) + 2;
|
||||
|
||||
ret |= omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, BANK_SEL, BANK_SEL_DSP);
|
||||
ret |= omv_i2c_readb(&csi->i2c_bus, csi->slv_addr, IMAGE_MODE, ®);
|
||||
ret |= omv_i2c_writeb(csi->i2c, csi->slv_addr, BANK_SEL, BANK_SEL_DSP);
|
||||
ret |= omv_i2c_readb(csi->i2c, csi->slv_addr, IMAGE_MODE, ®);
|
||||
int t_pclk = 0;
|
||||
|
||||
if (IMAGE_MODE_GET_FMT(reg) == IMAGE_MODE_YUV422) {
|
||||
@ -762,9 +762,9 @@ static int get_exposure_us(omv_csi_t *csi, int *exposure_us) {
|
||||
|
||||
static int set_auto_whitebal(omv_csi_t *csi, int enable, float r_gain_db, float g_gain_db, float b_gain_db) {
|
||||
uint8_t reg;
|
||||
int ret = omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, BANK_SEL, BANK_SEL_DSP);
|
||||
ret |= omv_i2c_readb(&csi->i2c_bus, csi->slv_addr, CTRL1, ®);
|
||||
ret |= omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, CTRL1, (reg & (~CTRL1_AWB)) | ((enable != 0) ? CTRL1_AWB : 0));
|
||||
int ret = omv_i2c_writeb(csi->i2c, csi->slv_addr, BANK_SEL, BANK_SEL_DSP);
|
||||
ret |= omv_i2c_readb(csi->i2c, csi->slv_addr, CTRL1, ®);
|
||||
ret |= omv_i2c_writeb(csi->i2c, csi->slv_addr, CTRL1, (reg & (~CTRL1_AWB)) | ((enable != 0) ? CTRL1_AWB : 0));
|
||||
|
||||
if ((enable == 0) && (!isnanf(r_gain_db)) && (!isnanf(g_gain_db)) && (!isnanf(b_gain_db))
|
||||
&& (!isinff(r_gain_db)) && (!isinff(g_gain_db)) && (!isinff(b_gain_db))) {
|
||||
@ -775,18 +775,18 @@ static int set_auto_whitebal(omv_csi_t *csi, int enable, float r_gain_db, float
|
||||
|
||||
static int get_rgb_gain_db(omv_csi_t *csi, float *r_gain_db, float *g_gain_db, float *b_gain_db) {
|
||||
uint8_t reg;
|
||||
int ret = omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, BANK_SEL, BANK_SEL_DSP);
|
||||
ret |= omv_i2c_readb(&csi->i2c_bus, csi->slv_addr, CTRL1, ®);
|
||||
int ret = omv_i2c_writeb(csi->i2c, csi->slv_addr, BANK_SEL, BANK_SEL_DSP);
|
||||
ret |= omv_i2c_readb(csi->i2c, csi->slv_addr, CTRL1, ®);
|
||||
|
||||
// DISABLED
|
||||
// if (reg & CTRL1_AWB) {
|
||||
// ret |= omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, CTRL1, reg & (~CTRL1_AWB));
|
||||
// ret |= omv_i2c_writeb(csi->i2c, csi->slv_addr, CTRL1, reg & (~CTRL1_AWB));
|
||||
// }
|
||||
// DISABLED
|
||||
|
||||
// DISABLED
|
||||
// if (reg & CTRL1_AWB) {
|
||||
// ret |= omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, CTRL1, reg | CTRL1_AWB);
|
||||
// ret |= omv_i2c_writeb(csi->i2c, csi->slv_addr, CTRL1, reg | CTRL1_AWB);
|
||||
// }
|
||||
// DISABLED
|
||||
|
||||
@ -799,8 +799,8 @@ static int get_rgb_gain_db(omv_csi_t *csi, float *r_gain_db, float *g_gain_db, f
|
||||
|
||||
static int set_hmirror(omv_csi_t *csi, int enable) {
|
||||
uint8_t reg;
|
||||
int ret = omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, BANK_SEL, BANK_SEL_SENSOR);
|
||||
ret |= omv_i2c_readb(&csi->i2c_bus, csi->slv_addr, REG04, ®);
|
||||
int ret = omv_i2c_writeb(csi->i2c, csi->slv_addr, BANK_SEL, BANK_SEL_SENSOR);
|
||||
ret |= omv_i2c_readb(csi->i2c, csi->slv_addr, REG04, ®);
|
||||
|
||||
if (!enable) {
|
||||
// Already mirrored.
|
||||
@ -809,13 +809,13 @@ static int set_hmirror(omv_csi_t *csi, int enable) {
|
||||
reg &= ~REG04_HFLIP_IMG;
|
||||
}
|
||||
|
||||
return omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, REG04, reg) | ret;
|
||||
return omv_i2c_writeb(csi->i2c, csi->slv_addr, REG04, reg) | ret;
|
||||
}
|
||||
|
||||
static int set_vflip(omv_csi_t *csi, int enable) {
|
||||
uint8_t reg;
|
||||
int ret = omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, BANK_SEL, BANK_SEL_SENSOR);
|
||||
ret |= omv_i2c_readb(&csi->i2c_bus, csi->slv_addr, REG04, ®);
|
||||
int ret = omv_i2c_writeb(csi->i2c, csi->slv_addr, BANK_SEL, BANK_SEL_SENSOR);
|
||||
ret |= omv_i2c_readb(csi->i2c, csi->slv_addr, REG04, ®);
|
||||
|
||||
if (!enable) {
|
||||
// Already flipped.
|
||||
@ -824,7 +824,7 @@ static int set_vflip(omv_csi_t *csi, int enable) {
|
||||
reg &= ~(REG04_VFLIP_IMG | REG04_VREF_EN);
|
||||
}
|
||||
|
||||
return omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, REG04, reg) | ret;
|
||||
return omv_i2c_writeb(csi->i2c, csi->slv_addr, REG04, reg) | ret;
|
||||
}
|
||||
|
||||
static int set_special_effect(omv_csi_t *csi, omv_csi_sde_t sde) {
|
||||
@ -832,20 +832,20 @@ static int set_special_effect(omv_csi_t *csi, omv_csi_sde_t sde) {
|
||||
|
||||
switch (sde) {
|
||||
case OMV_CSI_SDE_NEGATIVE:
|
||||
ret |= omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, BANK_SEL, BANK_SEL_DSP);
|
||||
ret |= omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, BPADDR, 0x00);
|
||||
ret |= omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, BPDATA, 0x40);
|
||||
ret |= omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, BPADDR, 0x05);
|
||||
ret |= omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, BPDATA, 0x80);
|
||||
ret |= omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, BPDATA, 0x80);
|
||||
ret |= omv_i2c_writeb(csi->i2c, csi->slv_addr, BANK_SEL, BANK_SEL_DSP);
|
||||
ret |= omv_i2c_writeb(csi->i2c, csi->slv_addr, BPADDR, 0x00);
|
||||
ret |= omv_i2c_writeb(csi->i2c, csi->slv_addr, BPDATA, 0x40);
|
||||
ret |= omv_i2c_writeb(csi->i2c, csi->slv_addr, BPADDR, 0x05);
|
||||
ret |= omv_i2c_writeb(csi->i2c, csi->slv_addr, BPDATA, 0x80);
|
||||
ret |= omv_i2c_writeb(csi->i2c, csi->slv_addr, BPDATA, 0x80);
|
||||
break;
|
||||
case OMV_CSI_SDE_NORMAL:
|
||||
ret |= omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, BANK_SEL, BANK_SEL_DSP);
|
||||
ret |= omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, BPADDR, 0x00);
|
||||
ret |= omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, BPDATA, 0x00);
|
||||
ret |= omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, BPADDR, 0x05);
|
||||
ret |= omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, BPDATA, 0x80);
|
||||
ret |= omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, BPDATA, 0x80);
|
||||
ret |= omv_i2c_writeb(csi->i2c, csi->slv_addr, BANK_SEL, BANK_SEL_DSP);
|
||||
ret |= omv_i2c_writeb(csi->i2c, csi->slv_addr, BPADDR, 0x00);
|
||||
ret |= omv_i2c_writeb(csi->i2c, csi->slv_addr, BPDATA, 0x00);
|
||||
ret |= omv_i2c_writeb(csi->i2c, csi->slv_addr, BPADDR, 0x05);
|
||||
ret |= omv_i2c_writeb(csi->i2c, csi->slv_addr, BPDATA, 0x80);
|
||||
ret |= omv_i2c_writeb(csi->i2c, csi->slv_addr, BPDATA, 0x80);
|
||||
break;
|
||||
default:
|
||||
return -1;
|
||||
|
||||
@ -668,8 +668,8 @@ static int reset(omv_csi_t *csi) {
|
||||
hts_target = 0;
|
||||
|
||||
// Reset all registers
|
||||
ret |= omv_i2c_writeb2(&csi->i2c_bus, csi->slv_addr, SCCB_SYSTEM_CTRL_1, 0x11);
|
||||
ret |= omv_i2c_writeb2(&csi->i2c_bus, csi->slv_addr, SYSTEM_CTROL0, 0x82);
|
||||
ret |= omv_i2c_writeb2(csi->i2c, csi->slv_addr, SCCB_SYSTEM_CTRL_1, 0x11);
|
||||
ret |= omv_i2c_writeb2(csi->i2c, csi->slv_addr, SYSTEM_CTROL0, 0x82);
|
||||
|
||||
// Delay 5 ms
|
||||
mp_hal_delay_ms(5);
|
||||
@ -693,16 +693,16 @@ static int reset(omv_csi_t *csi) {
|
||||
}
|
||||
#endif
|
||||
|
||||
ret |= omv_i2c_writeb2(&csi->i2c_bus, csi->slv_addr, addr, data);
|
||||
ret |= omv_i2c_writeb2(csi->i2c, csi->slv_addr, addr, data);
|
||||
}
|
||||
|
||||
#if (OMV_OV5640_AF_ENABLE == 1)
|
||||
ret |= omv_i2c_writeb2(&csi->i2c_bus, csi->slv_addr, SYSTEM_RESET_00, 0x20); // force mcu reset
|
||||
ret |= omv_i2c_writeb2(csi->i2c, csi->slv_addr, SYSTEM_RESET_00, 0x20); // force mcu reset
|
||||
|
||||
// Write firmware
|
||||
uint16_t fw_addr = __REV16(MCU_FIRMWARE_BASE);
|
||||
ret |= omv_i2c_write_bytes(&csi->i2c_bus, csi->slv_addr, (uint8_t *) &fw_addr, 2, OMV_I2C_XFER_SUSPEND);
|
||||
ret |= omv_i2c_write_bytes(&csi->i2c_bus,
|
||||
ret |= omv_i2c_write_bytes(csi->i2c, csi->slv_addr, (uint8_t *) &fw_addr, 2, OMV_I2C_XFER_SUSPEND);
|
||||
ret |= omv_i2c_write_bytes(csi->i2c,
|
||||
csi->slv_addr,
|
||||
(uint8_t *) af_firmware_regs,
|
||||
sizeof(af_firmware_regs),
|
||||
@ -710,13 +710,13 @@ static int reset(omv_csi_t *csi) {
|
||||
|
||||
for (int i = 0; af_firmware_command_regs[i][0]; i++) {
|
||||
ret |=
|
||||
omv_i2c_writeb2(&csi->i2c_bus,
|
||||
omv_i2c_writeb2(csi->i2c,
|
||||
csi->slv_addr,
|
||||
(af_firmware_command_regs[i][0] << 8) | (af_firmware_command_regs[i][1] << 0),
|
||||
af_firmware_command_regs[i][2]);
|
||||
}
|
||||
|
||||
ret |= omv_i2c_writeb2(&csi->i2c_bus, csi->slv_addr, SYSTEM_RESET_00, 0x00); // release mcu reset
|
||||
ret |= omv_i2c_writeb2(csi->i2c, csi->slv_addr, SYSTEM_RESET_00, 0x00); // release mcu reset
|
||||
#endif
|
||||
|
||||
// Delay 300 ms
|
||||
@ -735,19 +735,19 @@ static int sleep(omv_csi_t *csi, int enable) {
|
||||
reg = 0x02;
|
||||
}
|
||||
|
||||
return omv_i2c_writeb2(&csi->i2c_bus, csi->slv_addr, SYSTEM_CTROL0, reg);
|
||||
return omv_i2c_writeb2(csi->i2c, csi->slv_addr, SYSTEM_CTROL0, reg);
|
||||
}
|
||||
|
||||
static int read_reg(omv_csi_t *csi, uint16_t reg_addr) {
|
||||
uint8_t reg_data;
|
||||
if (omv_i2c_readb2(&csi->i2c_bus, csi->slv_addr, reg_addr, ®_data) != 0) {
|
||||
if (omv_i2c_readb2(csi->i2c, csi->slv_addr, reg_addr, ®_data) != 0) {
|
||||
return -1;
|
||||
}
|
||||
return reg_data;
|
||||
}
|
||||
|
||||
static int write_reg(omv_csi_t *csi, uint16_t reg_addr, uint16_t reg_data) {
|
||||
return omv_i2c_writeb2(&csi->i2c_bus, csi->slv_addr, reg_addr, reg_data);
|
||||
return omv_i2c_writeb2(csi->i2c, csi->slv_addr, reg_addr, reg_data);
|
||||
}
|
||||
|
||||
// HTS (Horizontal Time) is the readout width plus the HSYNC_TIME time. However, if this value gets
|
||||
@ -810,49 +810,49 @@ static int set_pixformat(omv_csi_t *csi, pixformat_t pixformat) {
|
||||
|
||||
switch (pixformat) {
|
||||
case PIXFORMAT_GRAYSCALE:
|
||||
ret |= omv_i2c_writeb2(&csi->i2c_bus, csi->slv_addr, FORMAT_CONTROL, 0x10);
|
||||
ret |= omv_i2c_writeb2(&csi->i2c_bus, csi->slv_addr, FORMAT_CONTROL_MUX, 0x00);
|
||||
ret |= omv_i2c_writeb2(csi->i2c, csi->slv_addr, FORMAT_CONTROL, 0x10);
|
||||
ret |= omv_i2c_writeb2(csi->i2c, csi->slv_addr, FORMAT_CONTROL_MUX, 0x00);
|
||||
break;
|
||||
case PIXFORMAT_RGB565:
|
||||
ret |= omv_i2c_writeb2(&csi->i2c_bus, csi->slv_addr, FORMAT_CONTROL, 0x6F);
|
||||
ret |= omv_i2c_writeb2(&csi->i2c_bus, csi->slv_addr, FORMAT_CONTROL_MUX, 0x01);
|
||||
ret |= omv_i2c_writeb2(csi->i2c, csi->slv_addr, FORMAT_CONTROL, 0x6F);
|
||||
ret |= omv_i2c_writeb2(csi->i2c, csi->slv_addr, FORMAT_CONTROL_MUX, 0x01);
|
||||
break;
|
||||
case PIXFORMAT_YUV422:
|
||||
ret |= omv_i2c_writeb2(&csi->i2c_bus, csi->slv_addr, FORMAT_CONTROL, 0x30);
|
||||
ret |= omv_i2c_writeb2(&csi->i2c_bus, csi->slv_addr, FORMAT_CONTROL_MUX, 0x00);
|
||||
ret |= omv_i2c_writeb2(csi->i2c, csi->slv_addr, FORMAT_CONTROL, 0x30);
|
||||
ret |= omv_i2c_writeb2(csi->i2c, csi->slv_addr, FORMAT_CONTROL_MUX, 0x00);
|
||||
break;
|
||||
case PIXFORMAT_BAYER:
|
||||
ret |= omv_i2c_writeb2(&csi->i2c_bus, csi->slv_addr, FORMAT_CONTROL, 0x00);
|
||||
ret |= omv_i2c_writeb2(&csi->i2c_bus, csi->slv_addr, FORMAT_CONTROL_MUX, 0x01);
|
||||
ret |= omv_i2c_writeb2(csi->i2c, csi->slv_addr, FORMAT_CONTROL, 0x00);
|
||||
ret |= omv_i2c_writeb2(csi->i2c, csi->slv_addr, FORMAT_CONTROL_MUX, 0x01);
|
||||
break;
|
||||
case PIXFORMAT_JPEG:
|
||||
ret |= omv_i2c_writeb2(&csi->i2c_bus, csi->slv_addr, FORMAT_CONTROL, 0x30);
|
||||
ret |= omv_i2c_writeb2(&csi->i2c_bus, csi->slv_addr, FORMAT_CONTROL_MUX, 0x00);
|
||||
ret |= omv_i2c_writeb2(csi->i2c, csi->slv_addr, FORMAT_CONTROL, 0x30);
|
||||
ret |= omv_i2c_writeb2(csi->i2c, csi->slv_addr, FORMAT_CONTROL_MUX, 0x00);
|
||||
break;
|
||||
default:
|
||||
return -1;
|
||||
}
|
||||
|
||||
ret |= omv_i2c_readb2(&csi->i2c_bus, csi->slv_addr, TIMING_TC_REG_21, ®);
|
||||
ret |= omv_i2c_readb2(csi->i2c, csi->slv_addr, TIMING_TC_REG_21, ®);
|
||||
ret |=
|
||||
omv_i2c_writeb2(&csi->i2c_bus, csi->slv_addr, TIMING_TC_REG_21,
|
||||
omv_i2c_writeb2(csi->i2c, csi->slv_addr, TIMING_TC_REG_21,
|
||||
(reg & 0xDF) | ((pixformat == PIXFORMAT_JPEG) ? 0x20 : 0x00));
|
||||
|
||||
ret |= omv_i2c_readb2(&csi->i2c_bus, csi->slv_addr, SYSTEM_RESET_02, ®);
|
||||
ret |= omv_i2c_readb2(csi->i2c, csi->slv_addr, SYSTEM_RESET_02, ®);
|
||||
ret |=
|
||||
omv_i2c_writeb2(&csi->i2c_bus, csi->slv_addr, SYSTEM_RESET_02,
|
||||
omv_i2c_writeb2(csi->i2c, csi->slv_addr, SYSTEM_RESET_02,
|
||||
(reg & 0xE3) | ((pixformat == PIXFORMAT_JPEG) ? 0x00 : 0x1C));
|
||||
|
||||
ret |= omv_i2c_readb2(&csi->i2c_bus, csi->slv_addr, CLOCK_ENABLE_02, ®);
|
||||
ret |= omv_i2c_readb2(csi->i2c, csi->slv_addr, CLOCK_ENABLE_02, ®);
|
||||
ret |=
|
||||
omv_i2c_writeb2(&csi->i2c_bus, csi->slv_addr, CLOCK_ENABLE_02,
|
||||
omv_i2c_writeb2(csi->i2c, csi->slv_addr, CLOCK_ENABLE_02,
|
||||
(reg & 0xD7) | ((pixformat == PIXFORMAT_JPEG) ? 0x28 : 0x00));
|
||||
|
||||
if (hts_target) {
|
||||
uint16_t sensor_hts = calculate_hts(csi, resolution[csi->framesize][0]);
|
||||
|
||||
ret |= omv_i2c_writeb2(&csi->i2c_bus, csi->slv_addr, TIMING_HTS_H, sensor_hts >> 8);
|
||||
ret |= omv_i2c_writeb2(&csi->i2c_bus, csi->slv_addr, TIMING_HTS_L, sensor_hts);
|
||||
ret |= omv_i2c_writeb2(csi->i2c, csi->slv_addr, TIMING_HTS_H, sensor_hts >> 8);
|
||||
ret |= omv_i2c_writeb2(csi->i2c, csi->slv_addr, TIMING_HTS_L, sensor_hts);
|
||||
}
|
||||
|
||||
return ret;
|
||||
@ -950,50 +950,50 @@ static int set_framesize(omv_csi_t *csi, omv_csi_framesize_t framesize) {
|
||||
|
||||
// Step 5: Write regs.
|
||||
|
||||
ret |= omv_i2c_writeb2(&csi->i2c_bus, csi->slv_addr, TIMING_HS_H, sensor_ws >> 8);
|
||||
ret |= omv_i2c_writeb2(&csi->i2c_bus, csi->slv_addr, TIMING_HS_L, sensor_ws);
|
||||
ret |= omv_i2c_writeb2(csi->i2c, csi->slv_addr, TIMING_HS_H, sensor_ws >> 8);
|
||||
ret |= omv_i2c_writeb2(csi->i2c, csi->slv_addr, TIMING_HS_L, sensor_ws);
|
||||
|
||||
ret |= omv_i2c_writeb2(&csi->i2c_bus, csi->slv_addr, TIMING_VS_H, sensor_hs >> 8);
|
||||
ret |= omv_i2c_writeb2(&csi->i2c_bus, csi->slv_addr, TIMING_VS_L, sensor_hs);
|
||||
ret |= omv_i2c_writeb2(csi->i2c, csi->slv_addr, TIMING_VS_H, sensor_hs >> 8);
|
||||
ret |= omv_i2c_writeb2(csi->i2c, csi->slv_addr, TIMING_VS_L, sensor_hs);
|
||||
|
||||
ret |= omv_i2c_writeb2(&csi->i2c_bus, csi->slv_addr, TIMING_HW_H, sensor_we >> 8);
|
||||
ret |= omv_i2c_writeb2(&csi->i2c_bus, csi->slv_addr, TIMING_HW_L, sensor_we);
|
||||
ret |= omv_i2c_writeb2(csi->i2c, csi->slv_addr, TIMING_HW_H, sensor_we >> 8);
|
||||
ret |= omv_i2c_writeb2(csi->i2c, csi->slv_addr, TIMING_HW_L, sensor_we);
|
||||
|
||||
ret |= omv_i2c_writeb2(&csi->i2c_bus, csi->slv_addr, TIMING_VH_H, sensor_he >> 8);
|
||||
ret |= omv_i2c_writeb2(&csi->i2c_bus, csi->slv_addr, TIMING_VH_L, sensor_he);
|
||||
ret |= omv_i2c_writeb2(csi->i2c, csi->slv_addr, TIMING_VH_H, sensor_he >> 8);
|
||||
ret |= omv_i2c_writeb2(csi->i2c, csi->slv_addr, TIMING_VH_L, sensor_he);
|
||||
|
||||
ret |= omv_i2c_writeb2(&csi->i2c_bus, csi->slv_addr, TIMING_DVPHO_H, w >> 8);
|
||||
ret |= omv_i2c_writeb2(&csi->i2c_bus, csi->slv_addr, TIMING_DVPHO_L, w);
|
||||
ret |= omv_i2c_writeb2(csi->i2c, csi->slv_addr, TIMING_DVPHO_H, w >> 8);
|
||||
ret |= omv_i2c_writeb2(csi->i2c, csi->slv_addr, TIMING_DVPHO_L, w);
|
||||
|
||||
ret |= omv_i2c_writeb2(&csi->i2c_bus, csi->slv_addr, TIMING_DVPVO_H, h >> 8);
|
||||
ret |= omv_i2c_writeb2(&csi->i2c_bus, csi->slv_addr, TIMING_DVPVO_L, h);
|
||||
ret |= omv_i2c_writeb2(csi->i2c, csi->slv_addr, TIMING_DVPVO_H, h >> 8);
|
||||
ret |= omv_i2c_writeb2(csi->i2c, csi->slv_addr, TIMING_DVPVO_L, h);
|
||||
|
||||
ret |= omv_i2c_writeb2(&csi->i2c_bus, csi->slv_addr, TIMING_HTS_H, sensor_hts >> 8);
|
||||
ret |= omv_i2c_writeb2(&csi->i2c_bus, csi->slv_addr, TIMING_HTS_L, sensor_hts);
|
||||
ret |= omv_i2c_writeb2(csi->i2c, csi->slv_addr, TIMING_HTS_H, sensor_hts >> 8);
|
||||
ret |= omv_i2c_writeb2(csi->i2c, csi->slv_addr, TIMING_HTS_L, sensor_hts);
|
||||
|
||||
ret |= omv_i2c_writeb2(&csi->i2c_bus, csi->slv_addr, TIMING_VTS_H, sensor_vts >> 8);
|
||||
ret |= omv_i2c_writeb2(&csi->i2c_bus, csi->slv_addr, TIMING_VTS_L, sensor_vts);
|
||||
ret |= omv_i2c_writeb2(csi->i2c, csi->slv_addr, TIMING_VTS_H, sensor_vts >> 8);
|
||||
ret |= omv_i2c_writeb2(csi->i2c, csi->slv_addr, TIMING_VTS_L, sensor_vts);
|
||||
|
||||
ret |= omv_i2c_writeb2(&csi->i2c_bus, csi->slv_addr, TIMING_HOFFSET_H, x_off >> 8);
|
||||
ret |= omv_i2c_writeb2(&csi->i2c_bus, csi->slv_addr, TIMING_HOFFSET_L, x_off);
|
||||
ret |= omv_i2c_writeb2(csi->i2c, csi->slv_addr, TIMING_HOFFSET_H, x_off >> 8);
|
||||
ret |= omv_i2c_writeb2(csi->i2c, csi->slv_addr, TIMING_HOFFSET_L, x_off);
|
||||
|
||||
ret |= omv_i2c_writeb2(&csi->i2c_bus, csi->slv_addr, TIMING_VOFFSET_H, y_off >> 8);
|
||||
ret |= omv_i2c_writeb2(&csi->i2c_bus, csi->slv_addr, TIMING_VOFFSET_L, y_off);
|
||||
ret |= omv_i2c_writeb2(csi->i2c, csi->slv_addr, TIMING_VOFFSET_H, y_off >> 8);
|
||||
ret |= omv_i2c_writeb2(csi->i2c, csi->slv_addr, TIMING_VOFFSET_L, y_off);
|
||||
|
||||
ret |= omv_i2c_writeb2(&csi->i2c_bus, csi->slv_addr, TIMING_X_INC, sensor_x_inc);
|
||||
ret |= omv_i2c_writeb2(&csi->i2c_bus, csi->slv_addr, TIMING_Y_INC, sensor_y_inc);
|
||||
ret |= omv_i2c_writeb2(csi->i2c, csi->slv_addr, TIMING_X_INC, sensor_x_inc);
|
||||
ret |= omv_i2c_writeb2(csi->i2c, csi->slv_addr, TIMING_Y_INC, sensor_y_inc);
|
||||
|
||||
ret |= omv_i2c_readb2(&csi->i2c_bus, csi->slv_addr, TIMING_TC_REG_20, ®);
|
||||
ret |= omv_i2c_writeb2(&csi->i2c_bus, csi->slv_addr, TIMING_TC_REG_20, (reg & 0xFE) | (sensor_div > 1));
|
||||
ret |= omv_i2c_readb2(csi->i2c, csi->slv_addr, TIMING_TC_REG_20, ®);
|
||||
ret |= omv_i2c_writeb2(csi->i2c, csi->slv_addr, TIMING_TC_REG_20, (reg & 0xFE) | (sensor_div > 1));
|
||||
|
||||
ret |= omv_i2c_readb2(&csi->i2c_bus, csi->slv_addr, TIMING_TC_REG_21, ®);
|
||||
ret |= omv_i2c_writeb2(&csi->i2c_bus, csi->slv_addr, TIMING_TC_REG_21, (reg & 0xFE) | (sensor_div > 1));
|
||||
ret |= omv_i2c_readb2(csi->i2c, csi->slv_addr, TIMING_TC_REG_21, ®);
|
||||
ret |= omv_i2c_writeb2(csi->i2c, csi->slv_addr, TIMING_TC_REG_21, (reg & 0xFE) | (sensor_div > 1));
|
||||
|
||||
ret |= omv_i2c_writeb2(&csi->i2c_bus, csi->slv_addr, VFIFO_HSIZE_H, w >> 8);
|
||||
ret |= omv_i2c_writeb2(&csi->i2c_bus, csi->slv_addr, VFIFO_HSIZE_L, w);
|
||||
ret |= omv_i2c_writeb2(csi->i2c, csi->slv_addr, VFIFO_HSIZE_H, w >> 8);
|
||||
ret |= omv_i2c_writeb2(csi->i2c, csi->slv_addr, VFIFO_HSIZE_L, w);
|
||||
|
||||
ret |= omv_i2c_writeb2(&csi->i2c_bus, csi->slv_addr, VFIFO_VSIZE_H, h >> 8);
|
||||
ret |= omv_i2c_writeb2(&csi->i2c_bus, csi->slv_addr, VFIFO_VSIZE_L, h);
|
||||
ret |= omv_i2c_writeb2(csi->i2c, csi->slv_addr, VFIFO_VSIZE_H, h >> 8);
|
||||
ret |= omv_i2c_writeb2(csi->i2c, csi->slv_addr, VFIFO_VSIZE_L, h);
|
||||
|
||||
return ret;
|
||||
}
|
||||
@ -1006,11 +1006,11 @@ static int set_contrast(omv_csi_t *csi, int level) {
|
||||
return -1;
|
||||
}
|
||||
|
||||
ret |= omv_i2c_writeb2(&csi->i2c_bus, csi->slv_addr, 0x3212, 0x03); // start group 3
|
||||
ret |= omv_i2c_writeb2(&csi->i2c_bus, csi->slv_addr, 0x5586, (new_level + 5) << 2);
|
||||
ret |= omv_i2c_writeb2(&csi->i2c_bus, csi->slv_addr, 0x5585, contrast_regs[new_level][0]);
|
||||
ret |= omv_i2c_writeb2(&csi->i2c_bus, csi->slv_addr, 0x3212, 0x13); // end group 3
|
||||
ret |= omv_i2c_writeb2(&csi->i2c_bus, csi->slv_addr, 0x3212, 0xa3); // launch group 3
|
||||
ret |= omv_i2c_writeb2(csi->i2c, csi->slv_addr, 0x3212, 0x03); // start group 3
|
||||
ret |= omv_i2c_writeb2(csi->i2c, csi->slv_addr, 0x5586, (new_level + 5) << 2);
|
||||
ret |= omv_i2c_writeb2(csi->i2c, csi->slv_addr, 0x5585, contrast_regs[new_level][0]);
|
||||
ret |= omv_i2c_writeb2(csi->i2c, csi->slv_addr, 0x3212, 0x13); // end group 3
|
||||
ret |= omv_i2c_writeb2(csi->i2c, csi->slv_addr, 0x3212, 0xa3); // launch group 3
|
||||
|
||||
return ret;
|
||||
}
|
||||
@ -1023,11 +1023,11 @@ static int set_brightness(omv_csi_t *csi, int level) {
|
||||
return -1;
|
||||
}
|
||||
|
||||
ret |= omv_i2c_writeb2(&csi->i2c_bus, csi->slv_addr, 0x3212, 0x03); // start group 3
|
||||
ret |= omv_i2c_writeb2(&csi->i2c_bus, csi->slv_addr, 0x5587, abs(level) << 4);
|
||||
ret |= omv_i2c_writeb2(&csi->i2c_bus, csi->slv_addr, 0x5588, (level < 0) ? 0x09 : 0x01);
|
||||
ret |= omv_i2c_writeb2(&csi->i2c_bus, csi->slv_addr, 0x3212, 0x13); // end group 3
|
||||
ret |= omv_i2c_writeb2(&csi->i2c_bus, csi->slv_addr, 0x3212, 0xa3); // launch group 3
|
||||
ret |= omv_i2c_writeb2(csi->i2c, csi->slv_addr, 0x3212, 0x03); // start group 3
|
||||
ret |= omv_i2c_writeb2(csi->i2c, csi->slv_addr, 0x5587, abs(level) << 4);
|
||||
ret |= omv_i2c_writeb2(csi->i2c, csi->slv_addr, 0x5588, (level < 0) ? 0x09 : 0x01);
|
||||
ret |= omv_i2c_writeb2(csi->i2c, csi->slv_addr, 0x3212, 0x13); // end group 3
|
||||
ret |= omv_i2c_writeb2(csi->i2c, csi->slv_addr, 0x3212, 0xa3); // launch group 3
|
||||
|
||||
return ret;
|
||||
}
|
||||
@ -1040,20 +1040,20 @@ static int set_saturation(omv_csi_t *csi, int level) {
|
||||
return -1;
|
||||
}
|
||||
|
||||
ret |= omv_i2c_writeb2(&csi->i2c_bus, csi->slv_addr, 0x3212, 0x03); // start group 3
|
||||
ret |= omv_i2c_writeb2(&csi->i2c_bus, csi->slv_addr, 0x5581, 0x1c);
|
||||
ret |= omv_i2c_writeb2(&csi->i2c_bus, csi->slv_addr, 0x5582, 0x5a);
|
||||
ret |= omv_i2c_writeb2(&csi->i2c_bus, csi->slv_addr, 0x5583, 0x06);
|
||||
ret |= omv_i2c_writeb2(&csi->i2c_bus, csi->slv_addr, 0x5584, saturation_regs[new_level][0]);
|
||||
ret |= omv_i2c_writeb2(&csi->i2c_bus, csi->slv_addr, 0x5585, saturation_regs[new_level][1]);
|
||||
ret |= omv_i2c_writeb2(&csi->i2c_bus, csi->slv_addr, 0x5586, saturation_regs[new_level][2]);
|
||||
ret |= omv_i2c_writeb2(&csi->i2c_bus, csi->slv_addr, 0x5587, saturation_regs[new_level][3]);
|
||||
ret |= omv_i2c_writeb2(&csi->i2c_bus, csi->slv_addr, 0x5588, saturation_regs[new_level][4]);
|
||||
ret |= omv_i2c_writeb2(&csi->i2c_bus, csi->slv_addr, 0x5589, saturation_regs[new_level][5]);
|
||||
ret |= omv_i2c_writeb2(&csi->i2c_bus, csi->slv_addr, 0x558b, 0x98);
|
||||
ret |= omv_i2c_writeb2(&csi->i2c_bus, csi->slv_addr, 0x558a, 0x01);
|
||||
ret |= omv_i2c_writeb2(&csi->i2c_bus, csi->slv_addr, 0x3212, 0x13); // end group 3
|
||||
ret |= omv_i2c_writeb2(&csi->i2c_bus, csi->slv_addr, 0x3212, 0xa3); // launch group 3
|
||||
ret |= omv_i2c_writeb2(csi->i2c, csi->slv_addr, 0x3212, 0x03); // start group 3
|
||||
ret |= omv_i2c_writeb2(csi->i2c, csi->slv_addr, 0x5581, 0x1c);
|
||||
ret |= omv_i2c_writeb2(csi->i2c, csi->slv_addr, 0x5582, 0x5a);
|
||||
ret |= omv_i2c_writeb2(csi->i2c, csi->slv_addr, 0x5583, 0x06);
|
||||
ret |= omv_i2c_writeb2(csi->i2c, csi->slv_addr, 0x5584, saturation_regs[new_level][0]);
|
||||
ret |= omv_i2c_writeb2(csi->i2c, csi->slv_addr, 0x5585, saturation_regs[new_level][1]);
|
||||
ret |= omv_i2c_writeb2(csi->i2c, csi->slv_addr, 0x5586, saturation_regs[new_level][2]);
|
||||
ret |= omv_i2c_writeb2(csi->i2c, csi->slv_addr, 0x5587, saturation_regs[new_level][3]);
|
||||
ret |= omv_i2c_writeb2(csi->i2c, csi->slv_addr, 0x5588, saturation_regs[new_level][4]);
|
||||
ret |= omv_i2c_writeb2(csi->i2c, csi->slv_addr, 0x5589, saturation_regs[new_level][5]);
|
||||
ret |= omv_i2c_writeb2(csi->i2c, csi->slv_addr, 0x558b, 0x98);
|
||||
ret |= omv_i2c_writeb2(csi->i2c, csi->slv_addr, 0x558a, 0x01);
|
||||
ret |= omv_i2c_writeb2(csi->i2c, csi->slv_addr, 0x3212, 0x13); // end group 3
|
||||
ret |= omv_i2c_writeb2(csi->i2c, csi->slv_addr, 0x3212, 0xa3); // launch group 3
|
||||
|
||||
return ret;
|
||||
}
|
||||
@ -1067,44 +1067,44 @@ static int set_gainceiling(omv_csi_t *csi, omv_csi_gainceiling_t gainceiling) {
|
||||
return -1;
|
||||
}
|
||||
|
||||
ret |= omv_i2c_readb2(&csi->i2c_bus, csi->slv_addr, AEC_GAIN_CEILING_H, ®);
|
||||
ret |= omv_i2c_writeb2(&csi->i2c_bus, csi->slv_addr, AEC_GAIN_CEILING_H, (reg & 0xFC) | (new_gainceiling >> 8));
|
||||
ret |= omv_i2c_writeb2(&csi->i2c_bus, csi->slv_addr, AEC_GAIN_CEILING_L, new_gainceiling);
|
||||
ret |= omv_i2c_readb2(csi->i2c, csi->slv_addr, AEC_GAIN_CEILING_H, ®);
|
||||
ret |= omv_i2c_writeb2(csi->i2c, csi->slv_addr, AEC_GAIN_CEILING_H, (reg & 0xFC) | (new_gainceiling >> 8));
|
||||
ret |= omv_i2c_writeb2(csi->i2c, csi->slv_addr, AEC_GAIN_CEILING_L, new_gainceiling);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int set_quality(omv_csi_t *csi, int qs) {
|
||||
uint8_t reg;
|
||||
int ret = omv_i2c_readb2(&csi->i2c_bus, csi->slv_addr, JPEG_CTRL07, ®);
|
||||
ret |= omv_i2c_writeb2(&csi->i2c_bus, csi->slv_addr, JPEG_CTRL07, (reg & 0xC0) | (qs >> 2));
|
||||
int ret = omv_i2c_readb2(csi->i2c, csi->slv_addr, JPEG_CTRL07, ®);
|
||||
ret |= omv_i2c_writeb2(csi->i2c, csi->slv_addr, JPEG_CTRL07, (reg & 0xC0) | (qs >> 2));
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int set_colorbar(omv_csi_t *csi, int enable) {
|
||||
uint8_t reg;
|
||||
int ret = omv_i2c_readb2(&csi->i2c_bus, csi->slv_addr, PRE_ISP_TEST, ®);
|
||||
return omv_i2c_writeb2(&csi->i2c_bus, csi->slv_addr, PRE_ISP_TEST, (reg & 0x7F) | (enable ? 0x80 : 0x00)) | ret;
|
||||
int ret = omv_i2c_readb2(csi->i2c, csi->slv_addr, PRE_ISP_TEST, ®);
|
||||
return omv_i2c_writeb2(csi->i2c, csi->slv_addr, PRE_ISP_TEST, (reg & 0x7F) | (enable ? 0x80 : 0x00)) | ret;
|
||||
}
|
||||
|
||||
static int set_auto_gain(omv_csi_t *csi, int enable, float gain_db, float gain_db_ceiling) {
|
||||
uint8_t reg;
|
||||
int ret = omv_i2c_readb2(&csi->i2c_bus, csi->slv_addr, AEC_PK_MANUAL, ®);
|
||||
ret |= omv_i2c_writeb2(&csi->i2c_bus, csi->slv_addr, AEC_PK_MANUAL, (reg & 0xFD) | ((enable == 0) << 1));
|
||||
int ret = omv_i2c_readb2(csi->i2c, csi->slv_addr, AEC_PK_MANUAL, ®);
|
||||
ret |= omv_i2c_writeb2(csi->i2c, csi->slv_addr, AEC_PK_MANUAL, (reg & 0xFD) | ((enable == 0) << 1));
|
||||
|
||||
if ((enable == 0) && (!isnanf(gain_db)) && (!isinff(gain_db))) {
|
||||
int gain = __USAT(fast_roundf(expf((gain_db / 20.0f) * M_LN10) * 16.0f), 10);
|
||||
|
||||
ret |= omv_i2c_readb2(&csi->i2c_bus, csi->slv_addr, AEC_PK_REAL_GAIN_H, ®);
|
||||
ret |= omv_i2c_writeb2(&csi->i2c_bus, csi->slv_addr, AEC_PK_REAL_GAIN_H, (reg & 0xFC) | (gain >> 8));
|
||||
ret |= omv_i2c_writeb2(&csi->i2c_bus, csi->slv_addr, AEC_PK_REAL_GAIN_L, gain);
|
||||
ret |= omv_i2c_readb2(csi->i2c, csi->slv_addr, AEC_PK_REAL_GAIN_H, ®);
|
||||
ret |= omv_i2c_writeb2(csi->i2c, csi->slv_addr, AEC_PK_REAL_GAIN_H, (reg & 0xFC) | (gain >> 8));
|
||||
ret |= omv_i2c_writeb2(csi->i2c, csi->slv_addr, AEC_PK_REAL_GAIN_L, gain);
|
||||
} else if ((enable != 0) && (!isnanf(gain_db_ceiling)) && (!isinff(gain_db_ceiling))) {
|
||||
int gain_ceiling = __USAT(fast_roundf(expf((gain_db_ceiling / 20.0f) * M_LN10) * 16.0f), 10);
|
||||
|
||||
ret |= omv_i2c_readb2(&csi->i2c_bus, csi->slv_addr, AEC_GAIN_CEILING_H, ®);
|
||||
ret |= omv_i2c_writeb2(&csi->i2c_bus, csi->slv_addr, AEC_GAIN_CEILING_H, (reg & 0xFC) | (gain_ceiling >> 8));
|
||||
ret |= omv_i2c_writeb2(&csi->i2c_bus, csi->slv_addr, AEC_GAIN_CEILING_L, gain_ceiling);
|
||||
ret |= omv_i2c_readb2(csi->i2c, csi->slv_addr, AEC_GAIN_CEILING_H, ®);
|
||||
ret |= omv_i2c_writeb2(csi->i2c, csi->slv_addr, AEC_GAIN_CEILING_H, (reg & 0xFC) | (gain_ceiling >> 8));
|
||||
ret |= omv_i2c_writeb2(csi->i2c, csi->slv_addr, AEC_GAIN_CEILING_L, gain_ceiling);
|
||||
}
|
||||
|
||||
return ret;
|
||||
@ -1113,8 +1113,8 @@ static int set_auto_gain(omv_csi_t *csi, int enable, float gain_db, float gain_d
|
||||
static int get_gain_db(omv_csi_t *csi, float *gain_db) {
|
||||
uint8_t gainh, gainl;
|
||||
|
||||
int ret = omv_i2c_readb2(&csi->i2c_bus, csi->slv_addr, AEC_PK_REAL_GAIN_H, &gainh);
|
||||
ret |= omv_i2c_readb2(&csi->i2c_bus, csi->slv_addr, AEC_PK_REAL_GAIN_L, &gainl);
|
||||
int ret = omv_i2c_readb2(csi->i2c, csi->slv_addr, AEC_PK_REAL_GAIN_H, &gainh);
|
||||
ret |= omv_i2c_readb2(csi->i2c, csi->slv_addr, AEC_PK_REAL_GAIN_L, &gainl);
|
||||
|
||||
*gain_db = 20.0f * log10f((((gainh & 0x3) << 8) | gainl) / 16.0f);
|
||||
|
||||
@ -1153,21 +1153,21 @@ static int calc_pclk_freq(uint8_t sc_pll_ctrl_0,
|
||||
|
||||
static int set_auto_exposure(omv_csi_t *csi, int enable, int exposure_us) {
|
||||
uint8_t reg, spc0, spc1, spc2, spc3, sysrootdiv, hts_h, hts_l, vts_h, vts_l;
|
||||
int ret = omv_i2c_readb2(&csi->i2c_bus, csi->slv_addr, AEC_PK_MANUAL, ®);
|
||||
ret |= omv_i2c_writeb2(&csi->i2c_bus, csi->slv_addr, AEC_PK_MANUAL, (reg & 0xFE) | ((enable == 0) << 0));
|
||||
int ret = omv_i2c_readb2(csi->i2c, csi->slv_addr, AEC_PK_MANUAL, ®);
|
||||
ret |= omv_i2c_writeb2(csi->i2c, csi->slv_addr, AEC_PK_MANUAL, (reg & 0xFE) | ((enable == 0) << 0));
|
||||
|
||||
if ((enable == 0) && (exposure_us >= 0)) {
|
||||
ret |= omv_i2c_readb2(&csi->i2c_bus, csi->slv_addr, SC_PLL_CONTRL0, &spc0);
|
||||
ret |= omv_i2c_readb2(&csi->i2c_bus, csi->slv_addr, SC_PLL_CONTRL1, &spc1);
|
||||
ret |= omv_i2c_readb2(&csi->i2c_bus, csi->slv_addr, SC_PLL_CONTRL2, &spc2);
|
||||
ret |= omv_i2c_readb2(&csi->i2c_bus, csi->slv_addr, SC_PLL_CONTRL3, &spc3);
|
||||
ret |= omv_i2c_readb2(&csi->i2c_bus, csi->slv_addr, SYSTEM_ROOT_DIVIDER, &sysrootdiv);
|
||||
ret |= omv_i2c_readb2(csi->i2c, csi->slv_addr, SC_PLL_CONTRL0, &spc0);
|
||||
ret |= omv_i2c_readb2(csi->i2c, csi->slv_addr, SC_PLL_CONTRL1, &spc1);
|
||||
ret |= omv_i2c_readb2(csi->i2c, csi->slv_addr, SC_PLL_CONTRL2, &spc2);
|
||||
ret |= omv_i2c_readb2(csi->i2c, csi->slv_addr, SC_PLL_CONTRL3, &spc3);
|
||||
ret |= omv_i2c_readb2(csi->i2c, csi->slv_addr, SYSTEM_ROOT_DIVIDER, &sysrootdiv);
|
||||
|
||||
ret |= omv_i2c_readb2(&csi->i2c_bus, csi->slv_addr, TIMING_HTS_H, &hts_h);
|
||||
ret |= omv_i2c_readb2(&csi->i2c_bus, csi->slv_addr, TIMING_HTS_L, &hts_l);
|
||||
ret |= omv_i2c_readb2(csi->i2c, csi->slv_addr, TIMING_HTS_H, &hts_h);
|
||||
ret |= omv_i2c_readb2(csi->i2c, csi->slv_addr, TIMING_HTS_L, &hts_l);
|
||||
|
||||
ret |= omv_i2c_readb2(&csi->i2c_bus, csi->slv_addr, TIMING_VTS_H, &vts_h);
|
||||
ret |= omv_i2c_readb2(&csi->i2c_bus, csi->slv_addr, TIMING_VTS_L, &vts_l);
|
||||
ret |= omv_i2c_readb2(csi->i2c, csi->slv_addr, TIMING_VTS_H, &vts_h);
|
||||
ret |= omv_i2c_readb2(csi->i2c, csi->slv_addr, TIMING_VTS_L, &vts_l);
|
||||
|
||||
uint16_t hts = (hts_h << 8) | hts_l;
|
||||
uint16_t vts = (vts_h << 8) | vts_l;
|
||||
@ -1178,12 +1178,12 @@ static int set_auto_exposure(omv_csi_t *csi, int enable, int exposure_us) {
|
||||
|
||||
int new_vts = IM_MAX(exposure, vts);
|
||||
|
||||
ret |= omv_i2c_writeb2(&csi->i2c_bus, csi->slv_addr, AEC_PK_EXPOSURE_0, exposure >> 12);
|
||||
ret |= omv_i2c_writeb2(&csi->i2c_bus, csi->slv_addr, AEC_PK_EXPOSURE_1, exposure >> 4);
|
||||
ret |= omv_i2c_writeb2(&csi->i2c_bus, csi->slv_addr, AEC_PK_EXPOSURE_2, exposure << 4);
|
||||
ret |= omv_i2c_writeb2(csi->i2c, csi->slv_addr, AEC_PK_EXPOSURE_0, exposure >> 12);
|
||||
ret |= omv_i2c_writeb2(csi->i2c, csi->slv_addr, AEC_PK_EXPOSURE_1, exposure >> 4);
|
||||
ret |= omv_i2c_writeb2(csi->i2c, csi->slv_addr, AEC_PK_EXPOSURE_2, exposure << 4);
|
||||
|
||||
ret |= omv_i2c_writeb2(&csi->i2c_bus, csi->slv_addr, TIMING_VTS_H, new_vts >> 8);
|
||||
ret |= omv_i2c_writeb2(&csi->i2c_bus, csi->slv_addr, TIMING_VTS_L, new_vts);
|
||||
ret |= omv_i2c_writeb2(csi->i2c, csi->slv_addr, TIMING_VTS_H, new_vts >> 8);
|
||||
ret |= omv_i2c_writeb2(csi->i2c, csi->slv_addr, TIMING_VTS_L, new_vts);
|
||||
}
|
||||
|
||||
return ret;
|
||||
@ -1193,21 +1193,21 @@ static int get_exposure_us(omv_csi_t *csi, int *exposure_us) {
|
||||
uint8_t spc0, spc1, spc2, spc3, sysrootdiv, aec_0, aec_1, aec_2, hts_h, hts_l, vts_h, vts_l;
|
||||
int ret = 0;
|
||||
|
||||
ret |= omv_i2c_readb2(&csi->i2c_bus, csi->slv_addr, SC_PLL_CONTRL0, &spc0);
|
||||
ret |= omv_i2c_readb2(&csi->i2c_bus, csi->slv_addr, SC_PLL_CONTRL1, &spc1);
|
||||
ret |= omv_i2c_readb2(&csi->i2c_bus, csi->slv_addr, SC_PLL_CONTRL2, &spc2);
|
||||
ret |= omv_i2c_readb2(&csi->i2c_bus, csi->slv_addr, SC_PLL_CONTRL3, &spc3);
|
||||
ret |= omv_i2c_readb2(&csi->i2c_bus, csi->slv_addr, SYSTEM_ROOT_DIVIDER, &sysrootdiv);
|
||||
ret |= omv_i2c_readb2(csi->i2c, csi->slv_addr, SC_PLL_CONTRL0, &spc0);
|
||||
ret |= omv_i2c_readb2(csi->i2c, csi->slv_addr, SC_PLL_CONTRL1, &spc1);
|
||||
ret |= omv_i2c_readb2(csi->i2c, csi->slv_addr, SC_PLL_CONTRL2, &spc2);
|
||||
ret |= omv_i2c_readb2(csi->i2c, csi->slv_addr, SC_PLL_CONTRL3, &spc3);
|
||||
ret |= omv_i2c_readb2(csi->i2c, csi->slv_addr, SYSTEM_ROOT_DIVIDER, &sysrootdiv);
|
||||
|
||||
ret |= omv_i2c_readb2(&csi->i2c_bus, csi->slv_addr, AEC_PK_EXPOSURE_0, &aec_0);
|
||||
ret |= omv_i2c_readb2(&csi->i2c_bus, csi->slv_addr, AEC_PK_EXPOSURE_1, &aec_1);
|
||||
ret |= omv_i2c_readb2(&csi->i2c_bus, csi->slv_addr, AEC_PK_EXPOSURE_2, &aec_2);
|
||||
ret |= omv_i2c_readb2(csi->i2c, csi->slv_addr, AEC_PK_EXPOSURE_0, &aec_0);
|
||||
ret |= omv_i2c_readb2(csi->i2c, csi->slv_addr, AEC_PK_EXPOSURE_1, &aec_1);
|
||||
ret |= omv_i2c_readb2(csi->i2c, csi->slv_addr, AEC_PK_EXPOSURE_2, &aec_2);
|
||||
|
||||
ret |= omv_i2c_readb2(&csi->i2c_bus, csi->slv_addr, TIMING_HTS_H, &hts_h);
|
||||
ret |= omv_i2c_readb2(&csi->i2c_bus, csi->slv_addr, TIMING_HTS_L, &hts_l);
|
||||
ret |= omv_i2c_readb2(csi->i2c, csi->slv_addr, TIMING_HTS_H, &hts_h);
|
||||
ret |= omv_i2c_readb2(csi->i2c, csi->slv_addr, TIMING_HTS_L, &hts_l);
|
||||
|
||||
ret |= omv_i2c_readb2(&csi->i2c_bus, csi->slv_addr, TIMING_VTS_H, &vts_h);
|
||||
ret |= omv_i2c_readb2(&csi->i2c_bus, csi->slv_addr, TIMING_VTS_L, &vts_l);
|
||||
ret |= omv_i2c_readb2(csi->i2c, csi->slv_addr, TIMING_VTS_H, &vts_h);
|
||||
ret |= omv_i2c_readb2(csi->i2c, csi->slv_addr, TIMING_VTS_L, &vts_l);
|
||||
|
||||
uint32_t aec = ((aec_0 << 16) | (aec_1 << 8) | aec_2) >> 4;
|
||||
uint16_t hts = (hts_h << 8) | hts_l;
|
||||
@ -1224,8 +1224,8 @@ static int get_exposure_us(omv_csi_t *csi, int *exposure_us) {
|
||||
|
||||
static int set_auto_whitebal(omv_csi_t *csi, int enable, float r_gain_db, float g_gain_db, float b_gain_db) {
|
||||
uint8_t reg;
|
||||
int ret = omv_i2c_readb2(&csi->i2c_bus, csi->slv_addr, AWB_MANUAL_CONTROL, ®);
|
||||
ret |= omv_i2c_writeb2(&csi->i2c_bus, csi->slv_addr, AWB_MANUAL_CONTROL, (reg & 0xFE) | (enable == 0));
|
||||
int ret = omv_i2c_readb2(csi->i2c, csi->slv_addr, AWB_MANUAL_CONTROL, ®);
|
||||
ret |= omv_i2c_writeb2(csi->i2c, csi->slv_addr, AWB_MANUAL_CONTROL, (reg & 0xFE) | (enable == 0));
|
||||
|
||||
if ((enable == 0) && (!isnanf(r_gain_db)) && (!isnanf(g_gain_db)) && (!isnanf(b_gain_db))
|
||||
&& (!isinff(r_gain_db)) && (!isinff(g_gain_db)) && (!isinff(b_gain_db))) {
|
||||
@ -1234,12 +1234,12 @@ static int set_auto_whitebal(omv_csi_t *csi, int enable, float r_gain_db, float
|
||||
int g_gain = __USAT(fast_roundf(expf((g_gain_db / 20.0f) * M_LN10)), 12);
|
||||
int b_gain = __USAT(fast_roundf(expf((b_gain_db / 20.0f) * M_LN10)), 12);
|
||||
|
||||
ret |= omv_i2c_writeb2(&csi->i2c_bus, csi->slv_addr, AWB_R_GAIN_H, r_gain >> 8);
|
||||
ret |= omv_i2c_writeb2(&csi->i2c_bus, csi->slv_addr, AWB_R_GAIN_L, r_gain);
|
||||
ret |= omv_i2c_writeb2(&csi->i2c_bus, csi->slv_addr, AWB_G_GAIN_H, g_gain >> 8);
|
||||
ret |= omv_i2c_writeb2(&csi->i2c_bus, csi->slv_addr, AWB_G_GAIN_L, g_gain);
|
||||
ret |= omv_i2c_writeb2(&csi->i2c_bus, csi->slv_addr, AWB_B_GAIN_H, b_gain >> 8);
|
||||
ret |= omv_i2c_writeb2(&csi->i2c_bus, csi->slv_addr, AWB_B_GAIN_L, b_gain);
|
||||
ret |= omv_i2c_writeb2(csi->i2c, csi->slv_addr, AWB_R_GAIN_H, r_gain >> 8);
|
||||
ret |= omv_i2c_writeb2(csi->i2c, csi->slv_addr, AWB_R_GAIN_L, r_gain);
|
||||
ret |= omv_i2c_writeb2(csi->i2c, csi->slv_addr, AWB_G_GAIN_H, g_gain >> 8);
|
||||
ret |= omv_i2c_writeb2(csi->i2c, csi->slv_addr, AWB_G_GAIN_L, g_gain);
|
||||
ret |= omv_i2c_writeb2(csi->i2c, csi->slv_addr, AWB_B_GAIN_H, b_gain >> 8);
|
||||
ret |= omv_i2c_writeb2(csi->i2c, csi->slv_addr, AWB_B_GAIN_L, b_gain);
|
||||
}
|
||||
|
||||
return ret;
|
||||
@ -1248,12 +1248,12 @@ static int set_auto_whitebal(omv_csi_t *csi, int enable, float r_gain_db, float
|
||||
static int get_rgb_gain_db(omv_csi_t *csi, float *r_gain_db, float *g_gain_db, float *b_gain_db) {
|
||||
uint8_t redh, redl, greenh, greenl, blueh, bluel;
|
||||
|
||||
int ret = omv_i2c_readb2(&csi->i2c_bus, csi->slv_addr, AWB_R_GAIN_H, &redh);
|
||||
ret |= omv_i2c_readb2(&csi->i2c_bus, csi->slv_addr, AWB_R_GAIN_L, &redl);
|
||||
ret |= omv_i2c_readb2(&csi->i2c_bus, csi->slv_addr, AWB_G_GAIN_H, &greenh);
|
||||
ret |= omv_i2c_readb2(&csi->i2c_bus, csi->slv_addr, AWB_G_GAIN_L, &greenl);
|
||||
ret |= omv_i2c_readb2(&csi->i2c_bus, csi->slv_addr, AWB_B_GAIN_H, &blueh);
|
||||
ret |= omv_i2c_readb2(&csi->i2c_bus, csi->slv_addr, AWB_B_GAIN_L, &bluel);
|
||||
int ret = omv_i2c_readb2(csi->i2c, csi->slv_addr, AWB_R_GAIN_H, &redh);
|
||||
ret |= omv_i2c_readb2(csi->i2c, csi->slv_addr, AWB_R_GAIN_L, &redl);
|
||||
ret |= omv_i2c_readb2(csi->i2c, csi->slv_addr, AWB_G_GAIN_H, &greenh);
|
||||
ret |= omv_i2c_readb2(csi->i2c, csi->slv_addr, AWB_G_GAIN_L, &greenl);
|
||||
ret |= omv_i2c_readb2(csi->i2c, csi->slv_addr, AWB_B_GAIN_H, &blueh);
|
||||
ret |= omv_i2c_readb2(csi->i2c, csi->slv_addr, AWB_B_GAIN_L, &bluel);
|
||||
|
||||
*r_gain_db = 20.0f * log10f(((redh & 0xF) << 8) | redl);
|
||||
*g_gain_db = 20.0f * log10f(((greenh & 0xF) << 8) | greenl);
|
||||
@ -1264,12 +1264,12 @@ static int get_rgb_gain_db(omv_csi_t *csi, float *r_gain_db, float *g_gain_db, f
|
||||
|
||||
static int set_auto_blc(omv_csi_t *csi, int enable, int *regs) {
|
||||
uint8_t reg;
|
||||
int ret = omv_i2c_readb2(&csi->i2c_bus, csi->slv_addr, BLC_CTRL_00, ®);
|
||||
ret |= omv_i2c_writeb2(&csi->i2c_bus, csi->slv_addr, BLC_CTRL_00, (reg & 0xFE) | (enable != 0));
|
||||
int ret = omv_i2c_readb2(csi->i2c, csi->slv_addr, BLC_CTRL_00, ®);
|
||||
ret |= omv_i2c_writeb2(csi->i2c, csi->slv_addr, BLC_CTRL_00, (reg & 0xFE) | (enable != 0));
|
||||
|
||||
if ((enable == 0) && (regs != NULL)) {
|
||||
for (uint32_t i = 0; i < csi->blc_size; i++) {
|
||||
ret |= omv_i2c_writeb2(&csi->i2c_bus, csi->slv_addr, BLACK_LEVEL_00_H + i, regs[i]);
|
||||
ret |= omv_i2c_writeb2(csi->i2c, csi->slv_addr, BLACK_LEVEL_00_H + i, regs[i]);
|
||||
}
|
||||
}
|
||||
|
||||
@ -1281,7 +1281,7 @@ static int get_blc_regs(omv_csi_t *csi, int *regs) {
|
||||
|
||||
for (uint32_t i = 0; i < csi->blc_size; i++) {
|
||||
uint8_t reg;
|
||||
ret |= omv_i2c_readb2(&csi->i2c_bus, csi->slv_addr, BLACK_LEVEL_00_H + i, ®);
|
||||
ret |= omv_i2c_readb2(csi->i2c, csi->slv_addr, BLACK_LEVEL_00_H + i, ®);
|
||||
regs[i] = reg;
|
||||
}
|
||||
|
||||
@ -1290,22 +1290,22 @@ static int get_blc_regs(omv_csi_t *csi, int *regs) {
|
||||
|
||||
static int set_hmirror(omv_csi_t *csi, int enable) {
|
||||
uint8_t reg;
|
||||
int ret = omv_i2c_readb2(&csi->i2c_bus, csi->slv_addr, TIMING_TC_REG_21, ®);
|
||||
int ret = omv_i2c_readb2(csi->i2c, csi->slv_addr, TIMING_TC_REG_21, ®);
|
||||
if (enable) {
|
||||
ret |= omv_i2c_writeb2(&csi->i2c_bus, csi->slv_addr, TIMING_TC_REG_21, reg | 0x06);
|
||||
ret |= omv_i2c_writeb2(csi->i2c, csi->slv_addr, TIMING_TC_REG_21, reg | 0x06);
|
||||
} else {
|
||||
ret |= omv_i2c_writeb2(&csi->i2c_bus, csi->slv_addr, TIMING_TC_REG_21, reg & 0xF9);
|
||||
ret |= omv_i2c_writeb2(csi->i2c, csi->slv_addr, TIMING_TC_REG_21, reg & 0xF9);
|
||||
}
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int set_vflip(omv_csi_t *csi, int enable) {
|
||||
uint8_t reg;
|
||||
int ret = omv_i2c_readb2(&csi->i2c_bus, csi->slv_addr, TIMING_TC_REG_20, ®);
|
||||
int ret = omv_i2c_readb2(csi->i2c, csi->slv_addr, TIMING_TC_REG_20, ®);
|
||||
if (!enable) {
|
||||
ret |= omv_i2c_writeb2(&csi->i2c_bus, csi->slv_addr, TIMING_TC_REG_20, reg | 0x06);
|
||||
ret |= omv_i2c_writeb2(csi->i2c, csi->slv_addr, TIMING_TC_REG_20, reg | 0x06);
|
||||
} else {
|
||||
ret |= omv_i2c_writeb2(&csi->i2c_bus, csi->slv_addr, TIMING_TC_REG_20, reg & 0xF9);
|
||||
ret |= omv_i2c_writeb2(csi->i2c, csi->slv_addr, TIMING_TC_REG_20, reg & 0xF9);
|
||||
}
|
||||
return ret;
|
||||
}
|
||||
@ -1315,22 +1315,22 @@ static int set_special_effect(omv_csi_t *csi, omv_csi_sde_t sde) {
|
||||
|
||||
switch (sde) {
|
||||
case OMV_CSI_SDE_NEGATIVE:
|
||||
ret |= omv_i2c_writeb2(&csi->i2c_bus, csi->slv_addr, 0x3212, 0x03); // start group 3
|
||||
ret |= omv_i2c_writeb2(&csi->i2c_bus, csi->slv_addr, 0x5580, 0x40);
|
||||
ret |= omv_i2c_writeb2(&csi->i2c_bus, csi->slv_addr, 0x5003, 0x08);
|
||||
ret |= omv_i2c_writeb2(&csi->i2c_bus, csi->slv_addr, 0x5583, 0x40); // sat U
|
||||
ret |= omv_i2c_writeb2(&csi->i2c_bus, csi->slv_addr, 0x5584, 0x10); // sat V
|
||||
ret |= omv_i2c_writeb2(&csi->i2c_bus, csi->slv_addr, 0x3212, 0x13); // end group 3
|
||||
ret |= omv_i2c_writeb2(&csi->i2c_bus, csi->slv_addr, 0x3212, 0xa3); // latch group 3
|
||||
ret |= omv_i2c_writeb2(csi->i2c, csi->slv_addr, 0x3212, 0x03); // start group 3
|
||||
ret |= omv_i2c_writeb2(csi->i2c, csi->slv_addr, 0x5580, 0x40);
|
||||
ret |= omv_i2c_writeb2(csi->i2c, csi->slv_addr, 0x5003, 0x08);
|
||||
ret |= omv_i2c_writeb2(csi->i2c, csi->slv_addr, 0x5583, 0x40); // sat U
|
||||
ret |= omv_i2c_writeb2(csi->i2c, csi->slv_addr, 0x5584, 0x10); // sat V
|
||||
ret |= omv_i2c_writeb2(csi->i2c, csi->slv_addr, 0x3212, 0x13); // end group 3
|
||||
ret |= omv_i2c_writeb2(csi->i2c, csi->slv_addr, 0x3212, 0xa3); // latch group 3
|
||||
break;
|
||||
case OMV_CSI_SDE_NORMAL:
|
||||
ret |= omv_i2c_writeb2(&csi->i2c_bus, csi->slv_addr, 0x3212, 0x03); // start group 3
|
||||
ret |= omv_i2c_writeb2(&csi->i2c_bus, csi->slv_addr, 0x5580, 0x06);
|
||||
ret |= omv_i2c_writeb2(&csi->i2c_bus, csi->slv_addr, 0x5583, 0x40); // sat U
|
||||
ret |= omv_i2c_writeb2(&csi->i2c_bus, csi->slv_addr, 0x5584, 0x10); // sat V
|
||||
ret |= omv_i2c_writeb2(&csi->i2c_bus, csi->slv_addr, 0x5003, 0x08);
|
||||
ret |= omv_i2c_writeb2(&csi->i2c_bus, csi->slv_addr, 0x3212, 0x13); // end group 3
|
||||
ret |= omv_i2c_writeb2(&csi->i2c_bus, csi->slv_addr, 0x3212, 0xa3); // latch group 3
|
||||
ret |= omv_i2c_writeb2(csi->i2c, csi->slv_addr, 0x3212, 0x03); // start group 3
|
||||
ret |= omv_i2c_writeb2(csi->i2c, csi->slv_addr, 0x5580, 0x06);
|
||||
ret |= omv_i2c_writeb2(csi->i2c, csi->slv_addr, 0x5583, 0x40); // sat U
|
||||
ret |= omv_i2c_writeb2(csi->i2c, csi->slv_addr, 0x5584, 0x10); // sat V
|
||||
ret |= omv_i2c_writeb2(csi->i2c, csi->slv_addr, 0x5003, 0x08);
|
||||
ret |= omv_i2c_writeb2(csi->i2c, csi->slv_addr, 0x3212, 0x13); // end group 3
|
||||
ret |= omv_i2c_writeb2(csi->i2c, csi->slv_addr, 0x3212, 0xa3); // latch group 3
|
||||
break;
|
||||
default:
|
||||
return -1;
|
||||
@ -1341,8 +1341,8 @@ static int set_special_effect(omv_csi_t *csi, omv_csi_sde_t sde) {
|
||||
|
||||
static int set_lens_correction(omv_csi_t *csi, int enable, int radi, int coef) {
|
||||
uint8_t reg;
|
||||
int ret = omv_i2c_readb2(&csi->i2c_bus, csi->slv_addr, ISP_CONTROL_00, ®);
|
||||
return omv_i2c_writeb2(&csi->i2c_bus, csi->slv_addr, ISP_CONTROL_00, (reg & 0x7F) | (enable ? 0x80 : 0x00)) | ret;
|
||||
int ret = omv_i2c_readb2(csi->i2c, csi->slv_addr, ISP_CONTROL_00, ®);
|
||||
return omv_i2c_writeb2(csi->i2c, csi->slv_addr, ISP_CONTROL_00, (reg & 0x7F) | (enable ? 0x80 : 0x00)) | ret;
|
||||
}
|
||||
|
||||
static int ioctl(omv_csi_t *csi, int request, va_list ap) {
|
||||
@ -1379,21 +1379,21 @@ static int ioctl(omv_csi_t *csi, int request, va_list ap) {
|
||||
}
|
||||
#if (OMV_OV5640_AF_ENABLE == 1)
|
||||
case OMV_CSI_IOCTL_TRIGGER_AUTO_FOCUS: {
|
||||
ret = omv_i2c_writeb2(&csi->i2c_bus, csi->slv_addr, AF_CMD_MAIN, 0x03);
|
||||
ret = omv_i2c_writeb2(csi->i2c, csi->slv_addr, AF_CMD_MAIN, 0x03);
|
||||
break;
|
||||
}
|
||||
case OMV_CSI_IOCTL_PAUSE_AUTO_FOCUS: {
|
||||
ret = omv_i2c_writeb2(&csi->i2c_bus, csi->slv_addr, AF_CMD_MAIN, 0x06);
|
||||
ret = omv_i2c_writeb2(csi->i2c, csi->slv_addr, AF_CMD_MAIN, 0x06);
|
||||
break;
|
||||
}
|
||||
case OMV_CSI_IOCTL_RESET_AUTO_FOCUS: {
|
||||
ret = omv_i2c_writeb2(&csi->i2c_bus, csi->slv_addr, AF_CMD_MAIN, 0x08);
|
||||
ret = omv_i2c_writeb2(csi->i2c, csi->slv_addr, AF_CMD_MAIN, 0x08);
|
||||
break;
|
||||
}
|
||||
case OMV_CSI_IOCTL_WAIT_ON_AUTO_FOCUS: {
|
||||
mp_uint_t start_tick = mp_hal_ticks_ms(), delay_ms = va_arg(ap, uint32_t);
|
||||
for (;;) {
|
||||
ret = omv_i2c_readb2(&csi->i2c_bus, csi->slv_addr, AF_CMD_ACK, ®);
|
||||
ret = omv_i2c_readb2(csi->i2c, csi->slv_addr, AF_CMD_ACK, ®);
|
||||
if ((ret < 0) || (!reg)) {
|
||||
break;
|
||||
}
|
||||
@ -1407,14 +1407,14 @@ static int ioctl(omv_csi_t *csi, int request, va_list ap) {
|
||||
#endif
|
||||
case OMV_CSI_IOCTL_SET_NIGHT_MODE: {
|
||||
int enable = va_arg(ap, int);
|
||||
ret = omv_i2c_readb2(&csi->i2c_bus, csi->slv_addr, AEC_CTRL_00, ®);
|
||||
ret |= omv_i2c_writeb2(&csi->i2c_bus, csi->slv_addr, AEC_CTRL_00,
|
||||
ret = omv_i2c_readb2(csi->i2c, csi->slv_addr, AEC_CTRL_00, ®);
|
||||
ret |= omv_i2c_writeb2(csi->i2c, csi->slv_addr, AEC_CTRL_00,
|
||||
(reg & 0xFB) | ((enable != 0) << 2));
|
||||
break;
|
||||
}
|
||||
case OMV_CSI_IOCTL_GET_NIGHT_MODE: {
|
||||
int *enable = va_arg(ap, int *);
|
||||
ret = omv_i2c_readb2(&csi->i2c_bus, csi->slv_addr, AEC_CTRL_00, ®);
|
||||
ret = omv_i2c_readb2(csi->i2c, csi->slv_addr, AEC_CTRL_00, ®);
|
||||
if (ret >= 0) {
|
||||
*enable = reg & 0x4;
|
||||
}
|
||||
|
||||
@ -340,14 +340,14 @@ static const uint8_t qqvga_regs[][2] = {
|
||||
|
||||
static int reset(omv_csi_t *csi) {
|
||||
// Reset all registers
|
||||
int ret = omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, COM7, COM7_RESET);
|
||||
int ret = omv_i2c_writeb(csi->i2c, csi->slv_addr, COM7, COM7_RESET);
|
||||
|
||||
// Delay 2 ms
|
||||
mp_hal_delay_ms(2);
|
||||
|
||||
// Write default registers
|
||||
for (int i = 0; default_regs[i][0] != 0xff; i++) {
|
||||
ret |= omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, default_regs[i][0], default_regs[i][1]);
|
||||
ret |= omv_i2c_writeb(csi->i2c, csi->slv_addr, default_regs[i][0], default_regs[i][1]);
|
||||
}
|
||||
|
||||
// Delay 300 ms
|
||||
@ -360,7 +360,7 @@ static int reset(omv_csi_t *csi) {
|
||||
|
||||
static int sleep(omv_csi_t *csi, int enable) {
|
||||
uint8_t reg;
|
||||
int ret = omv_i2c_readb(&csi->i2c_bus, csi->slv_addr, COM2, ®);
|
||||
int ret = omv_i2c_readb(csi->i2c, csi->slv_addr, COM2, ®);
|
||||
|
||||
if (enable) {
|
||||
reg |= COM2_SOFT_SLEEP;
|
||||
@ -369,19 +369,19 @@ static int sleep(omv_csi_t *csi, int enable) {
|
||||
}
|
||||
|
||||
// Write back register
|
||||
return omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, COM2, reg) | ret;
|
||||
return omv_i2c_writeb(csi->i2c, csi->slv_addr, COM2, reg) | ret;
|
||||
}
|
||||
|
||||
static int read_reg(omv_csi_t *csi, uint16_t reg_addr) {
|
||||
uint8_t reg_data;
|
||||
if (omv_i2c_readb(&csi->i2c_bus, csi->slv_addr, reg_addr, ®_data) != 0) {
|
||||
if (omv_i2c_readb(csi->i2c, csi->slv_addr, reg_addr, ®_data) != 0) {
|
||||
return -1;
|
||||
}
|
||||
return reg_data;
|
||||
}
|
||||
|
||||
static int write_reg(omv_csi_t *csi, uint16_t reg_addr, uint16_t reg_data) {
|
||||
return omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, reg_addr, reg_data);
|
||||
return omv_i2c_writeb(csi->i2c, csi->slv_addr, reg_addr, reg_data);
|
||||
}
|
||||
|
||||
static int set_pixformat(omv_csi_t *csi, pixformat_t pixformat) {
|
||||
@ -402,7 +402,7 @@ static int set_pixformat(omv_csi_t *csi, pixformat_t pixformat) {
|
||||
|
||||
// Write pixel format registers
|
||||
for (int i = 0; regs[i][0] != 0xff; i++) {
|
||||
ret |= omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, regs[i][0], regs[i][1]);
|
||||
ret |= omv_i2c_writeb(csi->i2c, csi->slv_addr, regs[i][0], regs[i][1]);
|
||||
}
|
||||
|
||||
return ret;
|
||||
@ -428,16 +428,16 @@ static int set_framesize(omv_csi_t *csi, omv_csi_framesize_t framesize) {
|
||||
|
||||
// Write pixel format registers
|
||||
for (int i = 0; regs[i][0] != 0xFF; i++) {
|
||||
ret |= omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, regs[i][0], regs[i][1]);
|
||||
ret |= omv_i2c_writeb(csi->i2c, csi->slv_addr, regs[i][0], regs[i][1]);
|
||||
}
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int set_hmirror(omv_csi_t *csi, int enable) {
|
||||
uint8_t val;
|
||||
int ret = omv_i2c_readb(&csi->i2c_bus, csi->slv_addr, MVFP, &val);
|
||||
int ret = omv_i2c_readb(csi->i2c, csi->slv_addr, MVFP, &val);
|
||||
ret |=
|
||||
omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, MVFP,
|
||||
omv_i2c_writeb(csi->i2c, csi->slv_addr, MVFP,
|
||||
enable ? (val | MVFP_MIRROR) : (val & (~MVFP_MIRROR)));
|
||||
|
||||
return ret;
|
||||
@ -445,9 +445,9 @@ static int set_hmirror(omv_csi_t *csi, int enable) {
|
||||
|
||||
static int set_vflip(omv_csi_t *csi, int enable) {
|
||||
uint8_t val;
|
||||
int ret = omv_i2c_readb(&csi->i2c_bus, csi->slv_addr, MVFP, &val);
|
||||
int ret = omv_i2c_readb(csi->i2c, csi->slv_addr, MVFP, &val);
|
||||
ret |=
|
||||
omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, MVFP,
|
||||
omv_i2c_writeb(csi->i2c, csi->slv_addr, MVFP,
|
||||
enable ? (val | MVFP_VFLIP) : (val & (~MVFP_VFLIP)));
|
||||
|
||||
return ret;
|
||||
|
||||
@ -200,14 +200,14 @@ static const uint8_t contrast_regs[NUM_CONTRAST_LEVELS][1] = {
|
||||
|
||||
static int reset(omv_csi_t *csi) {
|
||||
// Reset all registers
|
||||
int ret = omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, REG12, 0x80);
|
||||
int ret = omv_i2c_writeb(csi->i2c, csi->slv_addr, REG12, 0x80);
|
||||
|
||||
// Delay 2 ms
|
||||
mp_hal_delay_ms(2);
|
||||
|
||||
// Write default registers
|
||||
for (int i = 0; default_regs[i][0]; i++) {
|
||||
ret |= omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, default_regs[i][0], default_regs[i][1]);
|
||||
ret |= omv_i2c_writeb(csi->i2c, csi->slv_addr, default_regs[i][0], default_regs[i][1]);
|
||||
}
|
||||
|
||||
// Delay 300 ms
|
||||
@ -220,7 +220,7 @@ static int reset(omv_csi_t *csi) {
|
||||
|
||||
static int sleep(omv_csi_t *csi, int enable) {
|
||||
uint8_t reg;
|
||||
int ret = omv_i2c_readb(&csi->i2c_bus, csi->slv_addr, REG0E, ®);
|
||||
int ret = omv_i2c_readb(csi->i2c, csi->slv_addr, REG0E, ®);
|
||||
|
||||
if (enable) {
|
||||
reg |= 0x8;
|
||||
@ -229,19 +229,19 @@ static int sleep(omv_csi_t *csi, int enable) {
|
||||
}
|
||||
|
||||
// Write back register
|
||||
return omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, REG0E, reg) | ret;
|
||||
return omv_i2c_writeb(csi->i2c, csi->slv_addr, REG0E, reg) | ret;
|
||||
}
|
||||
|
||||
static int read_reg(omv_csi_t *csi, uint16_t reg_addr) {
|
||||
uint8_t reg_data;
|
||||
if (omv_i2c_readb(&csi->i2c_bus, csi->slv_addr, reg_addr, ®_data) != 0) {
|
||||
if (omv_i2c_readb(csi->i2c, csi->slv_addr, reg_addr, ®_data) != 0) {
|
||||
return -1;
|
||||
}
|
||||
return reg_data;
|
||||
}
|
||||
|
||||
static int write_reg(omv_csi_t *csi, uint16_t reg_addr, uint16_t reg_data) {
|
||||
return omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, reg_addr, reg_data);
|
||||
return omv_i2c_writeb(csi->i2c, csi->slv_addr, reg_addr, reg_data);
|
||||
}
|
||||
|
||||
static int set_pixformat(omv_csi_t *csi, pixformat_t pixformat) {
|
||||
@ -251,31 +251,31 @@ static int set_pixformat(omv_csi_t *csi, pixformat_t pixformat) {
|
||||
}
|
||||
|
||||
uint8_t reg;
|
||||
int ret = omv_i2c_readb(&csi->i2c_bus, csi->slv_addr, REG12, ®);
|
||||
int ret = omv_i2c_readb(csi->i2c, csi->slv_addr, REG12, ®);
|
||||
|
||||
switch (pixformat) {
|
||||
case PIXFORMAT_RGB565:
|
||||
reg = (reg & 0xFC) | 0x2;
|
||||
ret |= omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, REG3E, 0x30);
|
||||
ret |= omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, REG82, 0x07);
|
||||
ret |= omv_i2c_writeb(csi->i2c, csi->slv_addr, REG3E, 0x30);
|
||||
ret |= omv_i2c_writeb(csi->i2c, csi->slv_addr, REG82, 0x07);
|
||||
break;
|
||||
case PIXFORMAT_YUV422:
|
||||
case PIXFORMAT_GRAYSCALE:
|
||||
reg = (reg & 0xFC) | 0x0;
|
||||
ret |= omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, REG3E, 0x30);
|
||||
ret |= omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, REG82, 0x07);
|
||||
ret |= omv_i2c_writeb(csi->i2c, csi->slv_addr, REG3E, 0x30);
|
||||
ret |= omv_i2c_writeb(csi->i2c, csi->slv_addr, REG82, 0x07);
|
||||
break;
|
||||
case PIXFORMAT_BAYER:
|
||||
reg = (reg & 0xFC) | 0x1;
|
||||
ret |= omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, REG3E, 0x20);
|
||||
ret |= omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, REG82, 0x00);
|
||||
ret |= omv_i2c_writeb(csi->i2c, csi->slv_addr, REG3E, 0x20);
|
||||
ret |= omv_i2c_writeb(csi->i2c, csi->slv_addr, REG82, 0x00);
|
||||
break;
|
||||
default:
|
||||
return -1;
|
||||
}
|
||||
|
||||
// Write back register
|
||||
return omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, REG12, reg) | ret;
|
||||
return omv_i2c_writeb(csi->i2c, csi->slv_addr, REG12, reg) | ret;
|
||||
}
|
||||
|
||||
static int set_framesize(omv_csi_t *csi, omv_csi_framesize_t framesize) {
|
||||
@ -292,41 +292,41 @@ static int set_framesize(omv_csi_t *csi, omv_csi_framesize_t framesize) {
|
||||
}
|
||||
|
||||
// Sample VFLIP
|
||||
ret |= omv_i2c_readb(&csi->i2c_bus, csi->slv_addr, REG0C, ®);
|
||||
ret |= omv_i2c_readb(csi->i2c, csi->slv_addr, REG0C, ®);
|
||||
vflip = !(reg & 0x80);
|
||||
|
||||
if ((w <= 320) && (h <= 240)) {
|
||||
// Set QVGA Resolution
|
||||
uint8_t reg;
|
||||
int ret = omv_i2c_readb(&csi->i2c_bus, csi->slv_addr, REG12, ®);
|
||||
int ret = omv_i2c_readb(csi->i2c, csi->slv_addr, REG12, ®);
|
||||
reg = (reg & 0xBF) | 0x40;
|
||||
ret |= omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, REG12, reg);
|
||||
ret |= omv_i2c_writeb(csi->i2c, csi->slv_addr, REG12, reg);
|
||||
|
||||
// Set QVGA Window Size
|
||||
ret |= omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, REG19, 0x03 - vflip);
|
||||
ret |= omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, REGC8, 0x02);
|
||||
ret |= omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, REGC9, 0x80);
|
||||
ret |= omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, REGCA, 0x00);
|
||||
ret |= omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, REGCB, 0xF0);
|
||||
ret |= omv_i2c_writeb(csi->i2c, csi->slv_addr, REG19, 0x03 - vflip);
|
||||
ret |= omv_i2c_writeb(csi->i2c, csi->slv_addr, REGC8, 0x02);
|
||||
ret |= omv_i2c_writeb(csi->i2c, csi->slv_addr, REGC9, 0x80);
|
||||
ret |= omv_i2c_writeb(csi->i2c, csi->slv_addr, REGCA, 0x00);
|
||||
ret |= omv_i2c_writeb(csi->i2c, csi->slv_addr, REGCB, 0xF0);
|
||||
} else {
|
||||
// Set VGA Resolution
|
||||
uint8_t reg;
|
||||
int ret = omv_i2c_readb(&csi->i2c_bus, csi->slv_addr, REG12, ®);
|
||||
int ret = omv_i2c_readb(csi->i2c, csi->slv_addr, REG12, ®);
|
||||
reg = (reg & 0xBF) | 0x00;
|
||||
ret |= omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, REG12, reg);
|
||||
ret |= omv_i2c_writeb(csi->i2c, csi->slv_addr, REG12, reg);
|
||||
|
||||
// Set VGA Window Size
|
||||
ret |= omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, REG19, 0x0b - vflip);
|
||||
ret |= omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, REGC8, 0x02);
|
||||
ret |= omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, REGC9, 0x80);
|
||||
ret |= omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, REGCA, 0x01);
|
||||
ret |= omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, REGCB, 0xE0);
|
||||
ret |= omv_i2c_writeb(csi->i2c, csi->slv_addr, REG19, 0x0b - vflip);
|
||||
ret |= omv_i2c_writeb(csi->i2c, csi->slv_addr, REGC8, 0x02);
|
||||
ret |= omv_i2c_writeb(csi->i2c, csi->slv_addr, REGC9, 0x80);
|
||||
ret |= omv_i2c_writeb(csi->i2c, csi->slv_addr, REGCA, 0x01);
|
||||
ret |= omv_i2c_writeb(csi->i2c, csi->slv_addr, REGCB, 0xE0);
|
||||
}
|
||||
|
||||
ret |= omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, REGCC, w >> 8);
|
||||
ret |= omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, REGCD, w);
|
||||
ret |= omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, REGCE, h >> 8);
|
||||
ret |= omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, REGCF, h);
|
||||
ret |= omv_i2c_writeb(csi->i2c, csi->slv_addr, REGCC, w >> 8);
|
||||
ret |= omv_i2c_writeb(csi->i2c, csi->slv_addr, REGCD, w);
|
||||
ret |= omv_i2c_writeb(csi->i2c, csi->slv_addr, REGCE, h >> 8);
|
||||
ret |= omv_i2c_writeb(csi->i2c, csi->slv_addr, REGCF, h);
|
||||
|
||||
return ret;
|
||||
}
|
||||
@ -339,13 +339,13 @@ static int set_contrast(omv_csi_t *csi, int level) {
|
||||
return -1;
|
||||
}
|
||||
|
||||
ret |= omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, 0xd5, 0x20);
|
||||
ret |= omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, 0xd4, 0x10 + (4 * new_level));
|
||||
ret |= omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, 0xd3, contrast_regs[new_level][0]);
|
||||
ret |= omv_i2c_readb(&csi->i2c_bus, csi->slv_addr, REGD2, ®);
|
||||
ret |= omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, REGD2, (reg & 0xFB) | ((level != 0) << 2));
|
||||
ret |= omv_i2c_readb(&csi->i2c_bus, csi->slv_addr, 0xdc, ®);
|
||||
ret |= omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, 0xdc, (level < 0) ? (reg | 0x04) : (reg & 0xFB));
|
||||
ret |= omv_i2c_writeb(csi->i2c, csi->slv_addr, 0xd5, 0x20);
|
||||
ret |= omv_i2c_writeb(csi->i2c, csi->slv_addr, 0xd4, 0x10 + (4 * new_level));
|
||||
ret |= omv_i2c_writeb(csi->i2c, csi->slv_addr, 0xd3, contrast_regs[new_level][0]);
|
||||
ret |= omv_i2c_readb(csi->i2c, csi->slv_addr, REGD2, ®);
|
||||
ret |= omv_i2c_writeb(csi->i2c, csi->slv_addr, REGD2, (reg & 0xFB) | ((level != 0) << 2));
|
||||
ret |= omv_i2c_readb(csi->i2c, csi->slv_addr, 0xdc, ®);
|
||||
ret |= omv_i2c_writeb(csi->i2c, csi->slv_addr, 0xdc, (level < 0) ? (reg | 0x04) : (reg & 0xFB));
|
||||
return ret;
|
||||
}
|
||||
|
||||
@ -361,20 +361,20 @@ static int set_saturation(omv_csi_t *csi, int level) {
|
||||
return -1;
|
||||
}
|
||||
|
||||
ret |= omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, REGD8, 0x10 * new_level);
|
||||
ret |= omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, REGD9, 0x10 * new_level);
|
||||
ret |= omv_i2c_readb(&csi->i2c_bus, csi->slv_addr, REGD2, ®);
|
||||
ret |= omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, REGD2, (reg & 0xFD) | ((level != 0) << 1));
|
||||
ret |= omv_i2c_writeb(csi->i2c, csi->slv_addr, REGD8, 0x10 * new_level);
|
||||
ret |= omv_i2c_writeb(csi->i2c, csi->slv_addr, REGD9, 0x10 * new_level);
|
||||
ret |= omv_i2c_readb(csi->i2c, csi->slv_addr, REGD2, ®);
|
||||
ret |= omv_i2c_writeb(csi->i2c, csi->slv_addr, REGD2, (reg & 0xFD) | ((level != 0) << 1));
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int set_gainceiling(omv_csi_t *csi, omv_csi_gainceiling_t gainceiling) {
|
||||
uint8_t reg;
|
||||
int ret = omv_i2c_readb(&csi->i2c_bus, csi->slv_addr, REG14, ®);
|
||||
int ret = omv_i2c_readb(csi->i2c, csi->slv_addr, REG14, ®);
|
||||
|
||||
// Set gain ceiling
|
||||
reg = (reg & 0x8F) | (gainceiling << 4);
|
||||
return omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, REG14, reg) | ret;
|
||||
return omv_i2c_writeb(csi->i2c, csi->slv_addr, REG14, reg) | ret;
|
||||
}
|
||||
|
||||
static int set_quality(omv_csi_t *csi, int qs) {
|
||||
@ -383,17 +383,17 @@ static int set_quality(omv_csi_t *csi, int qs) {
|
||||
|
||||
static int set_colorbar(omv_csi_t *csi, int enable) {
|
||||
uint8_t reg;
|
||||
int ret = omv_i2c_readb(&csi->i2c_bus, csi->slv_addr, REG82, ®);
|
||||
int ret = omv_i2c_readb(csi->i2c, csi->slv_addr, REG82, ®);
|
||||
|
||||
// Enable colorbars
|
||||
reg = (reg & 0xF7) | ((enable != 0) << 3);
|
||||
return omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, REG82, reg) | ret;
|
||||
return omv_i2c_writeb(csi->i2c, csi->slv_addr, REG82, reg) | ret;
|
||||
}
|
||||
|
||||
static int set_auto_gain(omv_csi_t *csi, int enable, float gain_db, float gain_db_ceiling) {
|
||||
uint8_t reg;
|
||||
int ret = omv_i2c_readb(&csi->i2c_bus, csi->slv_addr, REG13, ®);
|
||||
ret |= omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, REG13, (reg & 0xFB) | ((enable != 0) << 2));
|
||||
int ret = omv_i2c_readb(csi->i2c, csi->slv_addr, REG13, ®);
|
||||
ret |= omv_i2c_writeb(csi->i2c, csi->slv_addr, REG13, (reg & 0xFB) | ((enable != 0) << 2));
|
||||
|
||||
if ((enable == 0) && (!isnanf(gain_db)) && (!isinff(gain_db))) {
|
||||
float gain = IM_CLAMP(expf((gain_db / 20.0f) * M_LN10), 1.0f, 128.0f);
|
||||
@ -402,15 +402,15 @@ static int set_auto_gain(omv_csi_t *csi, int enable, float gain_db, float gain_d
|
||||
int gain_hi = 0x3F >> (6 - gain_temp);
|
||||
int gain_lo = IM_MIN(fast_roundf(((gain / (1 << gain_temp)) - 1.0f) * 16.0f), 15);
|
||||
|
||||
ret |= omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, GAIN, (gain_hi << 4) | (gain_lo << 0));
|
||||
ret |= omv_i2c_readb(&csi->i2c_bus, csi->slv_addr, REG15, ®);
|
||||
ret |= omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, REG15, (reg & 0xFC) | (gain_hi >> 4));
|
||||
ret |= omv_i2c_writeb(csi->i2c, csi->slv_addr, GAIN, (gain_hi << 4) | (gain_lo << 0));
|
||||
ret |= omv_i2c_readb(csi->i2c, csi->slv_addr, REG15, ®);
|
||||
ret |= omv_i2c_writeb(csi->i2c, csi->slv_addr, REG15, (reg & 0xFC) | (gain_hi >> 4));
|
||||
} else if ((enable != 0) && (!isnanf(gain_db_ceiling)) && (!isinff(gain_db_ceiling))) {
|
||||
float gain_ceiling = IM_CLAMP(expf((gain_db_ceiling / 20.0f) * M_LN10), 2.0f, 128.0f);
|
||||
|
||||
ret |= omv_i2c_readb(&csi->i2c_bus, csi->slv_addr, REG14, ®);
|
||||
ret |= omv_i2c_readb(csi->i2c, csi->slv_addr, REG14, ®);
|
||||
ret |=
|
||||
omv_i2c_writeb(&csi->i2c_bus,
|
||||
omv_i2c_writeb(csi->i2c,
|
||||
csi->slv_addr,
|
||||
REG14,
|
||||
(reg & 0x8F) | ((fast_ceilf(logf(gain_ceiling) / M_LN2) - 1) << 4));
|
||||
@ -423,8 +423,8 @@ static int get_gain_db(omv_csi_t *csi, float *gain_db) {
|
||||
uint8_t gain, reg15;
|
||||
int ret = 0;
|
||||
|
||||
ret |= omv_i2c_readb(&csi->i2c_bus, csi->slv_addr, GAIN, &gain);
|
||||
ret |= omv_i2c_readb(&csi->i2c_bus, csi->slv_addr, REG15, ®15);
|
||||
ret |= omv_i2c_readb(csi->i2c, csi->slv_addr, GAIN, &gain);
|
||||
ret |= omv_i2c_readb(csi->i2c, csi->slv_addr, REG15, ®15);
|
||||
|
||||
int hi_gain = 1 <<
|
||||
(((reg15 >>
|
||||
@ -438,17 +438,17 @@ static int get_gain_db(omv_csi_t *csi, float *gain_db) {
|
||||
|
||||
static int set_auto_exposure(omv_csi_t *csi, int enable, int exposure_us) {
|
||||
uint8_t reg;
|
||||
int ret = omv_i2c_readb(&csi->i2c_bus, csi->slv_addr, REG13, ®);
|
||||
ret |= omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, REG13, (reg & 0xFE) | ((enable != 0) << 0));
|
||||
int ret = omv_i2c_readb(csi->i2c, csi->slv_addr, REG13, ®);
|
||||
ret |= omv_i2c_writeb(csi->i2c, csi->slv_addr, REG13, (reg & 0xFE) | ((enable != 0) << 0));
|
||||
|
||||
if ((enable == 0) && (exposure_us >= 0)) {
|
||||
ret |= omv_i2c_readb(&csi->i2c_bus, csi->slv_addr, REG12, ®);
|
||||
ret |= omv_i2c_readb(csi->i2c, csi->slv_addr, REG12, ®);
|
||||
int t_line = (reg & 0x40) ? (320 + 456) : (640 + 136);
|
||||
|
||||
ret |= omv_i2c_readb(&csi->i2c_bus, csi->slv_addr, REG3E, ®);
|
||||
ret |= omv_i2c_readb(csi->i2c, csi->slv_addr, REG3E, ®);
|
||||
int t_pclk = (reg & 0x10) ? 2 : 1;
|
||||
|
||||
ret |= omv_i2c_readb(&csi->i2c_bus, csi->slv_addr, PLL, ®);
|
||||
ret |= omv_i2c_readb(csi->i2c, csi->slv_addr, PLL, ®);
|
||||
int pll_div = reg >> 6, pll_mult = 1;
|
||||
|
||||
switch ((reg >> 4) & 0x3) {
|
||||
@ -458,7 +458,7 @@ static int set_auto_exposure(omv_csi_t *csi, int enable, int exposure_us) {
|
||||
case 3: pll_mult = 8; break;
|
||||
}
|
||||
|
||||
ret |= omv_i2c_readb(&csi->i2c_bus, csi->slv_addr, CLKRC, ®);
|
||||
ret |= omv_i2c_readb(csi->i2c, csi->slv_addr, CLKRC, ®);
|
||||
int clk_rc;
|
||||
|
||||
if (reg & 0x40) {
|
||||
@ -471,8 +471,8 @@ static int set_auto_exposure(omv_csi_t *csi, int enable, int exposure_us) {
|
||||
__USAT(((exposure_us * ((((OMV_OV7690_CLK_FREQ / clk_rc) * pll_mult) / pll_div) / 1000000)) / t_pclk) /
|
||||
t_line, 16);
|
||||
|
||||
ret |= omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, AECL, ((exposure >> 0) & 0xFF));
|
||||
ret |= omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, AECH, ((exposure >> 8) & 0xFF));
|
||||
ret |= omv_i2c_writeb(csi->i2c, csi->slv_addr, AECL, ((exposure >> 0) & 0xFF));
|
||||
ret |= omv_i2c_writeb(csi->i2c, csi->slv_addr, AECH, ((exposure >> 8) & 0xFF));
|
||||
}
|
||||
|
||||
return ret;
|
||||
@ -482,16 +482,16 @@ static int get_exposure_us(omv_csi_t *csi, int *exposure_us) {
|
||||
uint8_t aec_l, aec_h, reg;
|
||||
int ret = 0;
|
||||
|
||||
ret |= omv_i2c_readb(&csi->i2c_bus, csi->slv_addr, AECL, &aec_l);
|
||||
ret |= omv_i2c_readb(&csi->i2c_bus, csi->slv_addr, AECH, &aec_h);
|
||||
ret |= omv_i2c_readb(csi->i2c, csi->slv_addr, AECL, &aec_l);
|
||||
ret |= omv_i2c_readb(csi->i2c, csi->slv_addr, AECH, &aec_h);
|
||||
|
||||
ret |= omv_i2c_readb(&csi->i2c_bus, csi->slv_addr, REG12, ®);
|
||||
ret |= omv_i2c_readb(csi->i2c, csi->slv_addr, REG12, ®);
|
||||
int t_line = (reg & 0x40) ? (320 + 456) : (640 + 136);
|
||||
|
||||
ret |= omv_i2c_readb(&csi->i2c_bus, csi->slv_addr, REG3E, ®);
|
||||
ret |= omv_i2c_readb(csi->i2c, csi->slv_addr, REG3E, ®);
|
||||
int t_pclk = (reg & 0x10) ? 2 : 1;
|
||||
|
||||
ret |= omv_i2c_readb(&csi->i2c_bus, csi->slv_addr, PLL, ®);
|
||||
ret |= omv_i2c_readb(csi->i2c, csi->slv_addr, PLL, ®);
|
||||
int pll_div = reg >> 6, pll_mult = 1;
|
||||
|
||||
switch ((reg >> 4) & 0x3) {
|
||||
@ -501,7 +501,7 @@ static int get_exposure_us(omv_csi_t *csi, int *exposure_us) {
|
||||
case 3: pll_mult = 8; break;
|
||||
}
|
||||
|
||||
ret |= omv_i2c_readb(&csi->i2c_bus, csi->slv_addr, CLKRC, ®);
|
||||
ret |= omv_i2c_readb(csi->i2c, csi->slv_addr, CLKRC, ®);
|
||||
int clk_rc;
|
||||
|
||||
if (reg & 0x40) {
|
||||
@ -519,8 +519,8 @@ static int get_exposure_us(omv_csi_t *csi, int *exposure_us) {
|
||||
|
||||
static int set_auto_whitebal(omv_csi_t *csi, int enable, float r_gain_db, float g_gain_db, float b_gain_db) {
|
||||
uint8_t reg;
|
||||
int ret = omv_i2c_readb(&csi->i2c_bus, csi->slv_addr, REG13, ®);
|
||||
ret |= omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, REG13, (reg & 0xFD) | ((enable != 0) << 1));
|
||||
int ret = omv_i2c_readb(csi->i2c, csi->slv_addr, REG13, ®);
|
||||
ret |= omv_i2c_writeb(csi->i2c, csi->slv_addr, REG13, (reg & 0xFD) | ((enable != 0) << 1));
|
||||
|
||||
if ((enable == 0) && (!isnanf(r_gain_db)) && (!isnanf(g_gain_db)) && (!isnanf(b_gain_db))
|
||||
&& (!isinff(r_gain_db)) && (!isinff(g_gain_db)) && (!isinff(b_gain_db))) {
|
||||
@ -529,9 +529,9 @@ static int set_auto_whitebal(omv_csi_t *csi, int enable, float r_gain_db, float
|
||||
int g_gain = __USAT(fast_roundf(expf((g_gain_db / 20.0f) * M_LN10)), 8);
|
||||
int b_gain = __USAT(fast_roundf(expf((b_gain_db / 20.0f) * M_LN10)), 8);
|
||||
|
||||
ret |= omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, BGAIN, b_gain);
|
||||
ret |= omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, RGAIN, r_gain);
|
||||
ret |= omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, GGAIN, g_gain);
|
||||
ret |= omv_i2c_writeb(csi->i2c, csi->slv_addr, BGAIN, b_gain);
|
||||
ret |= omv_i2c_writeb(csi->i2c, csi->slv_addr, RGAIN, r_gain);
|
||||
ret |= omv_i2c_writeb(csi->i2c, csi->slv_addr, GGAIN, g_gain);
|
||||
}
|
||||
|
||||
return ret;
|
||||
@ -541,9 +541,9 @@ static int get_rgb_gain_db(omv_csi_t *csi, float *r_gain_db, float *g_gain_db, f
|
||||
uint8_t blue, red, green;
|
||||
int ret = 0;
|
||||
|
||||
ret |= omv_i2c_readb(&csi->i2c_bus, csi->slv_addr, BGAIN, &blue);
|
||||
ret |= omv_i2c_readb(&csi->i2c_bus, csi->slv_addr, RGAIN, &red);
|
||||
ret |= omv_i2c_readb(&csi->i2c_bus, csi->slv_addr, GGAIN, &green);
|
||||
ret |= omv_i2c_readb(csi->i2c, csi->slv_addr, BGAIN, &blue);
|
||||
ret |= omv_i2c_readb(csi->i2c, csi->slv_addr, RGAIN, &red);
|
||||
ret |= omv_i2c_readb(csi->i2c, csi->slv_addr, GGAIN, &green);
|
||||
|
||||
*r_gain_db = 20.0f * log10f(red);
|
||||
*g_gain_db = 20.0f * log10f(green);
|
||||
@ -554,16 +554,16 @@ static int get_rgb_gain_db(omv_csi_t *csi, float *r_gain_db, float *g_gain_db, f
|
||||
|
||||
static int set_hmirror(omv_csi_t *csi, int enable) {
|
||||
uint8_t reg;
|
||||
int ret = omv_i2c_readb(&csi->i2c_bus, csi->slv_addr, REG0C, ®);
|
||||
ret |= omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, REG0C, (reg & 0xBF) | ((enable == 0) << 6));
|
||||
int ret = omv_i2c_readb(csi->i2c, csi->slv_addr, REG0C, ®);
|
||||
ret |= omv_i2c_writeb(csi->i2c, csi->slv_addr, REG0C, (reg & 0xBF) | ((enable == 0) << 6));
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int set_vflip(omv_csi_t *csi, int enable) {
|
||||
uint8_t reg;
|
||||
int ret = omv_i2c_readb(&csi->i2c_bus, csi->slv_addr, REG0C, ®);
|
||||
ret |= omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, REG0C, (reg & 0x7F) | ((enable == 0) << 7));
|
||||
int ret = omv_i2c_readb(csi->i2c, csi->slv_addr, REG0C, ®);
|
||||
ret |= omv_i2c_writeb(csi->i2c, csi->slv_addr, REG0C, (reg & 0x7F) | ((enable == 0) << 7));
|
||||
// Apply new vertical flip setting.
|
||||
ret |= set_framesize(csi, csi->framesize);
|
||||
|
||||
@ -575,10 +575,10 @@ static int set_special_effect(omv_csi_t *csi, omv_csi_sde_t sde) {
|
||||
|
||||
switch (sde) {
|
||||
case OMV_CSI_SDE_NEGATIVE:
|
||||
ret |= omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, 0x28, 0x80);
|
||||
ret |= omv_i2c_writeb(csi->i2c, csi->slv_addr, 0x28, 0x80);
|
||||
break;
|
||||
case OMV_CSI_SDE_NORMAL:
|
||||
ret |= omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, 0x28, 0x00);
|
||||
ret |= omv_i2c_writeb(csi->i2c, csi->slv_addr, 0x28, 0x00);
|
||||
break;
|
||||
default:
|
||||
return -1;
|
||||
@ -590,11 +590,11 @@ static int set_special_effect(omv_csi_t *csi, omv_csi_sde_t sde) {
|
||||
static int set_lens_correction(omv_csi_t *csi, int enable, int radi, int coef) {
|
||||
int ret = 0;
|
||||
|
||||
ret |= omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, LCC0, (enable != 0) << 4);
|
||||
ret |= omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, LCC1, radi);
|
||||
ret |= omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, LCC4, coef);
|
||||
ret |= omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, LCC5, coef);
|
||||
ret |= omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, LCC6, coef);
|
||||
ret |= omv_i2c_writeb(csi->i2c, csi->slv_addr, LCC0, (enable != 0) << 4);
|
||||
ret |= omv_i2c_writeb(csi->i2c, csi->slv_addr, LCC1, radi);
|
||||
ret |= omv_i2c_writeb(csi->i2c, csi->slv_addr, LCC4, coef);
|
||||
ret |= omv_i2c_writeb(csi->i2c, csi->slv_addr, LCC5, coef);
|
||||
ret |= omv_i2c_writeb(csi->i2c, csi->slv_addr, LCC6, coef);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
@ -165,14 +165,14 @@ static const uint8_t saturation_regs[NUM_SATURATION_LEVELS][2] = {
|
||||
|
||||
static int reset(omv_csi_t *csi) {
|
||||
// Reset all registers
|
||||
int ret = omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, COM7, COM7_RESET);
|
||||
int ret = omv_i2c_writeb(csi->i2c, csi->slv_addr, COM7, COM7_RESET);
|
||||
|
||||
// Delay 2 ms
|
||||
mp_hal_delay_ms(2);
|
||||
|
||||
// Write default registers
|
||||
for (int i = 0; default_regs[i][0]; i++) {
|
||||
ret |= omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, default_regs[i][0], default_regs[i][1]);
|
||||
ret |= omv_i2c_writeb(csi->i2c, csi->slv_addr, default_regs[i][0], default_regs[i][1]);
|
||||
}
|
||||
|
||||
// Delay 300 ms
|
||||
@ -185,7 +185,7 @@ static int reset(omv_csi_t *csi) {
|
||||
|
||||
static int sleep(omv_csi_t *csi, int enable) {
|
||||
uint8_t reg;
|
||||
int ret = omv_i2c_readb(&csi->i2c_bus, csi->slv_addr, COM2, ®);
|
||||
int ret = omv_i2c_readb(csi->i2c, csi->slv_addr, COM2, ®);
|
||||
|
||||
if (enable) {
|
||||
reg |= COM2_SOFT_SLEEP;
|
||||
@ -194,45 +194,45 @@ static int sleep(omv_csi_t *csi, int enable) {
|
||||
}
|
||||
|
||||
// Write back register
|
||||
return omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, COM2, reg) | ret;
|
||||
return omv_i2c_writeb(csi->i2c, csi->slv_addr, COM2, reg) | ret;
|
||||
}
|
||||
|
||||
static int read_reg(omv_csi_t *csi, uint16_t reg_addr) {
|
||||
uint8_t reg_data;
|
||||
if (omv_i2c_readb(&csi->i2c_bus, csi->slv_addr, reg_addr, ®_data) != 0) {
|
||||
if (omv_i2c_readb(csi->i2c, csi->slv_addr, reg_addr, ®_data) != 0) {
|
||||
return -1;
|
||||
}
|
||||
return reg_data;
|
||||
}
|
||||
|
||||
static int write_reg(omv_csi_t *csi, uint16_t reg_addr, uint16_t reg_data) {
|
||||
return omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, reg_addr, reg_data);
|
||||
return omv_i2c_writeb(csi->i2c, csi->slv_addr, reg_addr, reg_data);
|
||||
}
|
||||
|
||||
static int set_pixformat(omv_csi_t *csi, pixformat_t pixformat) {
|
||||
uint8_t reg;
|
||||
int ret = omv_i2c_readb(&csi->i2c_bus, csi->slv_addr, COM7, ®);
|
||||
int ret = omv_i2c_readb(csi->i2c, csi->slv_addr, COM7, ®);
|
||||
|
||||
switch (pixformat) {
|
||||
case PIXFORMAT_RGB565:
|
||||
reg = COM7_SET_FMT(reg, COM7_FMT_RGB);
|
||||
ret |= omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, DSP_CTRL4, DSP_CTRL4_YUV_RGB);
|
||||
ret |= omv_i2c_writeb(csi->i2c, csi->slv_addr, DSP_CTRL4, DSP_CTRL4_YUV_RGB);
|
||||
break;
|
||||
case PIXFORMAT_YUV422:
|
||||
case PIXFORMAT_GRAYSCALE:
|
||||
reg = COM7_SET_FMT(reg, COM7_FMT_YUV);
|
||||
ret |= omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, DSP_CTRL4, DSP_CTRL4_YUV_RGB);
|
||||
ret |= omv_i2c_writeb(csi->i2c, csi->slv_addr, DSP_CTRL4, DSP_CTRL4_YUV_RGB);
|
||||
break;
|
||||
case PIXFORMAT_BAYER:
|
||||
reg = COM7_SET_FMT(reg, COM7_FMT_P_BAYER);
|
||||
ret |= omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, DSP_CTRL4, DSP_CTRL4_RAW8);
|
||||
ret |= omv_i2c_writeb(csi->i2c, csi->slv_addr, DSP_CTRL4, DSP_CTRL4_RAW8);
|
||||
break;
|
||||
default:
|
||||
return -1;
|
||||
}
|
||||
|
||||
// Write back register
|
||||
return omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, COM7, reg) | ret;
|
||||
return omv_i2c_writeb(csi->i2c, csi->slv_addr, COM7, reg) | ret;
|
||||
}
|
||||
|
||||
static int set_framesize(omv_csi_t *csi, omv_csi_framesize_t framesize) {
|
||||
@ -247,53 +247,53 @@ static int set_framesize(omv_csi_t *csi, omv_csi_framesize_t framesize) {
|
||||
}
|
||||
|
||||
// Write MSBs
|
||||
ret |= omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, HOUTSIZE, w >> 2);
|
||||
ret |= omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, VOUTSIZE, h >> 1);
|
||||
ret |= omv_i2c_writeb(csi->i2c, csi->slv_addr, HOUTSIZE, w >> 2);
|
||||
ret |= omv_i2c_writeb(csi->i2c, csi->slv_addr, VOUTSIZE, h >> 1);
|
||||
|
||||
// Write LSBs
|
||||
ret |= omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, EXHCH, ((w & 0x3) | ((h & 0x1) << 2)));
|
||||
ret |= omv_i2c_writeb(csi->i2c, csi->slv_addr, EXHCH, ((w & 0x3) | ((h & 0x1) << 2)));
|
||||
|
||||
// Sample VFLIP
|
||||
ret |= omv_i2c_readb(&csi->i2c_bus, csi->slv_addr, COM3, ®);
|
||||
ret |= omv_i2c_readb(csi->i2c, csi->slv_addr, COM3, ®);
|
||||
vflip = reg & COM3_VFLIP;
|
||||
ret |= omv_i2c_readb(&csi->i2c_bus, csi->slv_addr, HREF, ®);
|
||||
ret |= omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, HREF, (reg & 0xBF) | (vflip ? 0x40 : 0x00));
|
||||
ret |= omv_i2c_readb(csi->i2c, csi->slv_addr, HREF, ®);
|
||||
ret |= omv_i2c_writeb(csi->i2c, csi->slv_addr, HREF, (reg & 0xBF) | (vflip ? 0x40 : 0x00));
|
||||
|
||||
if ((w <= 320) && (h <= 240)) {
|
||||
// Set QVGA Resolution
|
||||
uint8_t reg;
|
||||
int ret = omv_i2c_readb(&csi->i2c_bus, csi->slv_addr, COM7, ®);
|
||||
int ret = omv_i2c_readb(csi->i2c, csi->slv_addr, COM7, ®);
|
||||
reg = COM7_SET_RES(reg, COM7_RES_QVGA);
|
||||
ret |= omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, COM7, reg);
|
||||
ret |= omv_i2c_writeb(csi->i2c, csi->slv_addr, COM7, reg);
|
||||
|
||||
// Set QVGA Window Size
|
||||
ret |= omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, HSTART, 0x3F);
|
||||
ret |= omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, HSIZE, 0x50);
|
||||
ret |= omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, VSTART, 0x03 - vflip);
|
||||
ret |= omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, VSIZE, 0x78);
|
||||
ret |= omv_i2c_writeb(csi->i2c, csi->slv_addr, HSTART, 0x3F);
|
||||
ret |= omv_i2c_writeb(csi->i2c, csi->slv_addr, HSIZE, 0x50);
|
||||
ret |= omv_i2c_writeb(csi->i2c, csi->slv_addr, VSTART, 0x03 - vflip);
|
||||
ret |= omv_i2c_writeb(csi->i2c, csi->slv_addr, VSIZE, 0x78);
|
||||
|
||||
// Enable auto-scaling/zooming factors
|
||||
ret |= omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, DSPAUTO, 0xFF);
|
||||
ret |= omv_i2c_writeb(csi->i2c, csi->slv_addr, DSPAUTO, 0xFF);
|
||||
} else {
|
||||
// Set VGA Resolution
|
||||
uint8_t reg;
|
||||
int ret = omv_i2c_readb(&csi->i2c_bus, csi->slv_addr, COM7, ®);
|
||||
int ret = omv_i2c_readb(csi->i2c, csi->slv_addr, COM7, ®);
|
||||
reg = COM7_SET_RES(reg, COM7_RES_VGA);
|
||||
ret |= omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, COM7, reg);
|
||||
ret |= omv_i2c_writeb(csi->i2c, csi->slv_addr, COM7, reg);
|
||||
|
||||
// Set VGA Window Size
|
||||
ret |= omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, HSTART, 0x23);
|
||||
ret |= omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, HSIZE, 0xA0);
|
||||
ret |= omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, VSTART, 0x07 - vflip);
|
||||
ret |= omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, VSIZE, 0xF0);
|
||||
ret |= omv_i2c_writeb(csi->i2c, csi->slv_addr, HSTART, 0x23);
|
||||
ret |= omv_i2c_writeb(csi->i2c, csi->slv_addr, HSIZE, 0xA0);
|
||||
ret |= omv_i2c_writeb(csi->i2c, csi->slv_addr, VSTART, 0x07 - vflip);
|
||||
ret |= omv_i2c_writeb(csi->i2c, csi->slv_addr, VSIZE, 0xF0);
|
||||
|
||||
// Disable auto-scaling/zooming factors
|
||||
ret |= omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, DSPAUTO, 0xF3);
|
||||
ret |= omv_i2c_writeb(csi->i2c, csi->slv_addr, DSPAUTO, 0xF3);
|
||||
|
||||
// Clear auto-scaling/zooming factors
|
||||
ret |= omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, SCAL0, 0x00);
|
||||
ret |= omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, SCAL1, 0x40);
|
||||
ret |= omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, SCAL2, 0x40);
|
||||
ret |= omv_i2c_writeb(csi->i2c, csi->slv_addr, SCAL0, 0x00);
|
||||
ret |= omv_i2c_writeb(csi->i2c, csi->slv_addr, SCAL1, 0x40);
|
||||
ret |= omv_i2c_writeb(csi->i2c, csi->slv_addr, SCAL2, 0x40);
|
||||
}
|
||||
|
||||
return ret;
|
||||
@ -305,7 +305,7 @@ static int set_contrast(omv_csi_t *csi, int level) {
|
||||
return -1;
|
||||
}
|
||||
|
||||
return omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, CONTRAST, contrast_regs[level][0]);
|
||||
return omv_i2c_writeb(csi->i2c, csi->slv_addr, CONTRAST, contrast_regs[level][0]);
|
||||
}
|
||||
|
||||
static int set_brightness(omv_csi_t *csi, int level) {
|
||||
@ -315,8 +315,8 @@ static int set_brightness(omv_csi_t *csi, int level) {
|
||||
return -1;
|
||||
}
|
||||
|
||||
ret |= omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, BRIGHTNESS, brightness_regs[level][0]);
|
||||
ret |= omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, SIGN_BIT, brightness_regs[level][1]);
|
||||
ret |= omv_i2c_writeb(csi->i2c, csi->slv_addr, BRIGHTNESS, brightness_regs[level][0]);
|
||||
ret |= omv_i2c_writeb(csi->i2c, csi->slv_addr, SIGN_BIT, brightness_regs[level][1]);
|
||||
return ret;
|
||||
}
|
||||
|
||||
@ -327,38 +327,38 @@ static int set_saturation(omv_csi_t *csi, int level) {
|
||||
return -1;
|
||||
}
|
||||
|
||||
ret |= omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, USAT, saturation_regs[level][0]);
|
||||
ret |= omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, VSAT, saturation_regs[level][1]);
|
||||
ret |= omv_i2c_writeb(csi->i2c, csi->slv_addr, USAT, saturation_regs[level][0]);
|
||||
ret |= omv_i2c_writeb(csi->i2c, csi->slv_addr, VSAT, saturation_regs[level][1]);
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int set_gainceiling(omv_csi_t *csi, omv_csi_gainceiling_t gainceiling) {
|
||||
uint8_t reg;
|
||||
int ret = omv_i2c_readb(&csi->i2c_bus, csi->slv_addr, COM9, ®);
|
||||
int ret = omv_i2c_readb(csi->i2c, csi->slv_addr, COM9, ®);
|
||||
|
||||
// Set gain ceiling
|
||||
reg = COM9_SET_AGC(reg, gainceiling);
|
||||
return omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, COM9, reg) | ret;
|
||||
return omv_i2c_writeb(csi->i2c, csi->slv_addr, COM9, reg) | ret;
|
||||
}
|
||||
|
||||
static int set_colorbar(omv_csi_t *csi, int enable) {
|
||||
uint8_t reg;
|
||||
int ret = omv_i2c_readb(&csi->i2c_bus, csi->slv_addr, COM3, ®);
|
||||
int ret = omv_i2c_readb(csi->i2c, csi->slv_addr, COM3, ®);
|
||||
|
||||
// Enable colorbar test pattern output
|
||||
reg = COM3_SET_CBAR(reg, enable);
|
||||
ret |= omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, COM3, reg);
|
||||
ret |= omv_i2c_writeb(csi->i2c, csi->slv_addr, COM3, reg);
|
||||
|
||||
// Enable DSP colorbar output
|
||||
ret |= omv_i2c_readb(&csi->i2c_bus, csi->slv_addr, DSP_CTRL3, ®);
|
||||
ret |= omv_i2c_readb(csi->i2c, csi->slv_addr, DSP_CTRL3, ®);
|
||||
reg = DSP_CTRL3_SET_CBAR(reg, enable);
|
||||
return omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, DSP_CTRL3, reg) | ret;
|
||||
return omv_i2c_writeb(csi->i2c, csi->slv_addr, DSP_CTRL3, reg) | ret;
|
||||
}
|
||||
|
||||
static int set_auto_gain(omv_csi_t *csi, int enable, float gain_db, float gain_db_ceiling) {
|
||||
uint8_t reg;
|
||||
int ret = omv_i2c_readb(&csi->i2c_bus, csi->slv_addr, COM8, ®);
|
||||
ret |= omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, COM8, COM8_SET_AGC(reg, (enable != 0)));
|
||||
int ret = omv_i2c_readb(csi->i2c, csi->slv_addr, COM8, ®);
|
||||
ret |= omv_i2c_writeb(csi->i2c, csi->slv_addr, COM8, COM8_SET_AGC(reg, (enable != 0)));
|
||||
|
||||
if ((enable == 0) && (!isnanf(gain_db)) && (!isinff(gain_db))) {
|
||||
float gain = IM_CLAMP(expf((gain_db / 20.0f) * M_LN10), 1.0f, 32.0f);
|
||||
@ -367,13 +367,13 @@ static int set_auto_gain(omv_csi_t *csi, int enable, float gain_db, float gain_d
|
||||
int gain_hi = 0xF >> (4 - gain_temp);
|
||||
int gain_lo = IM_MIN(fast_roundf(((gain / (1 << gain_temp)) - 1.0f) * 16.0f), 15);
|
||||
|
||||
ret |= omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, GAIN, (gain_hi << 4) | (gain_lo << 0));
|
||||
ret |= omv_i2c_writeb(csi->i2c, csi->slv_addr, GAIN, (gain_hi << 4) | (gain_lo << 0));
|
||||
} else if ((enable != 0) && (!isnanf(gain_db_ceiling)) && (!isinff(gain_db_ceiling))) {
|
||||
float gain_ceiling = IM_CLAMP(expf((gain_db_ceiling / 20.0f) * M_LN10), 2.0f, 32.0f);
|
||||
|
||||
ret |= omv_i2c_readb(&csi->i2c_bus, csi->slv_addr, COM9, ®);
|
||||
ret |= omv_i2c_readb(csi->i2c, csi->slv_addr, COM9, ®);
|
||||
ret |=
|
||||
omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, COM9,
|
||||
omv_i2c_writeb(csi->i2c, csi->slv_addr, COM9,
|
||||
(reg & 0x8F) | ((fast_ceilf(logf(gain_ceiling) / M_LN2) - 1) << 4));
|
||||
}
|
||||
|
||||
@ -382,19 +382,19 @@ static int set_auto_gain(omv_csi_t *csi, int enable, float gain_db, float gain_d
|
||||
|
||||
static int get_gain_db(omv_csi_t *csi, float *gain_db) {
|
||||
uint8_t reg, gain;
|
||||
int ret = omv_i2c_readb(&csi->i2c_bus, csi->slv_addr, COM8, ®);
|
||||
int ret = omv_i2c_readb(csi->i2c, csi->slv_addr, COM8, ®);
|
||||
|
||||
// DISABLED
|
||||
// if (reg & COM8_AGC_EN) {
|
||||
// ret |= omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, COM8, COM8_SET_AGC(reg, 0));
|
||||
// ret |= omv_i2c_writeb(csi->i2c, csi->slv_addr, COM8, COM8_SET_AGC(reg, 0));
|
||||
// }
|
||||
// DISABLED
|
||||
|
||||
ret |= omv_i2c_readb(&csi->i2c_bus, csi->slv_addr, GAIN, &gain);
|
||||
ret |= omv_i2c_readb(csi->i2c, csi->slv_addr, GAIN, &gain);
|
||||
|
||||
// DISABLED
|
||||
// if (reg & COM8_AGC_EN) {
|
||||
// ret |= omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, COM8, COM8_SET_AGC(reg, 1));
|
||||
// ret |= omv_i2c_writeb(csi->i2c, csi->slv_addr, COM8, COM8_SET_AGC(reg, 1));
|
||||
// }
|
||||
// DISABLED
|
||||
|
||||
@ -407,16 +407,16 @@ static int get_gain_db(omv_csi_t *csi, float *gain_db) {
|
||||
|
||||
static int set_auto_exposure(omv_csi_t *csi, int enable, int exposure_us) {
|
||||
uint8_t reg;
|
||||
int ret = omv_i2c_readb(&csi->i2c_bus, csi->slv_addr, COM8, ®);
|
||||
ret |= omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, COM8, COM8_SET_AEC(reg, (enable != 0)));
|
||||
int ret = omv_i2c_readb(csi->i2c, csi->slv_addr, COM8, ®);
|
||||
ret |= omv_i2c_writeb(csi->i2c, csi->slv_addr, COM8, COM8_SET_AEC(reg, (enable != 0)));
|
||||
|
||||
if ((enable == 0) && (exposure_us >= 0)) {
|
||||
ret |= omv_i2c_readb(&csi->i2c_bus, csi->slv_addr, COM7, ®);
|
||||
ret |= omv_i2c_readb(csi->i2c, csi->slv_addr, COM7, ®);
|
||||
|
||||
int t_line = (reg & COM7_RES_QVGA) ? (320 + 256) : (640 + 144);
|
||||
int t_pclk = (COM7_GET_FMT(reg) == COM7_FMT_P_BAYER) ? 1 : 2;
|
||||
|
||||
ret |= omv_i2c_readb(&csi->i2c_bus, csi->slv_addr, COM4, ®);
|
||||
ret |= omv_i2c_readb(csi->i2c, csi->slv_addr, COM4, ®);
|
||||
int pll_mult = 0;
|
||||
|
||||
if (COM4_GET_PLL(reg) == COM4_PLL_BYPASS) {
|
||||
@ -432,7 +432,7 @@ static int set_auto_exposure(omv_csi_t *csi, int enable, int exposure_us) {
|
||||
pll_mult = 8;
|
||||
}
|
||||
|
||||
ret |= omv_i2c_readb(&csi->i2c_bus, csi->slv_addr, CLKRC, ®);
|
||||
ret |= omv_i2c_readb(csi->i2c, csi->slv_addr, CLKRC, ®);
|
||||
int clk_rc = 0;
|
||||
|
||||
if (reg & CLKRC_NO_PRESCALE) {
|
||||
@ -444,8 +444,8 @@ static int set_auto_exposure(omv_csi_t *csi, int enable, int exposure_us) {
|
||||
int exposure =
|
||||
__USAT(((exposure_us * (((OMV_CSI_CLK_FREQUENCY / clk_rc) * pll_mult) / 1000000)) / t_pclk) / t_line, 16);
|
||||
|
||||
ret |= omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, AEC, ((exposure >> 0) & 0xFF));
|
||||
ret |= omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, AECH, ((exposure >> 8) & 0xFF));
|
||||
ret |= omv_i2c_writeb(csi->i2c, csi->slv_addr, AEC, ((exposure >> 0) & 0xFF));
|
||||
ret |= omv_i2c_writeb(csi->i2c, csi->slv_addr, AECH, ((exposure >> 8) & 0xFF));
|
||||
}
|
||||
|
||||
return ret;
|
||||
@ -453,29 +453,29 @@ static int set_auto_exposure(omv_csi_t *csi, int enable, int exposure_us) {
|
||||
|
||||
static int get_exposure_us(omv_csi_t *csi, int *exposure_us) {
|
||||
uint8_t reg, aec_l, aec_h;
|
||||
int ret = omv_i2c_readb(&csi->i2c_bus, csi->slv_addr, COM8, ®);
|
||||
int ret = omv_i2c_readb(csi->i2c, csi->slv_addr, COM8, ®);
|
||||
|
||||
// DISABLED
|
||||
// if (reg & COM8_AEC_EN) {
|
||||
// ret |= omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, COM8, COM8_SET_AEC(reg, 0));
|
||||
// ret |= omv_i2c_writeb(csi->i2c, csi->slv_addr, COM8, COM8_SET_AEC(reg, 0));
|
||||
// }
|
||||
// DISABLED
|
||||
|
||||
ret |= omv_i2c_readb(&csi->i2c_bus, csi->slv_addr, AEC, &aec_l);
|
||||
ret |= omv_i2c_readb(&csi->i2c_bus, csi->slv_addr, AECH, &aec_h);
|
||||
ret |= omv_i2c_readb(csi->i2c, csi->slv_addr, AEC, &aec_l);
|
||||
ret |= omv_i2c_readb(csi->i2c, csi->slv_addr, AECH, &aec_h);
|
||||
|
||||
// DISABLED
|
||||
// if (reg & COM8_AEC_EN) {
|
||||
// ret |= omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, COM8, COM8_SET_AEC(reg, 1));
|
||||
// ret |= omv_i2c_writeb(csi->i2c, csi->slv_addr, COM8, COM8_SET_AEC(reg, 1));
|
||||
// }
|
||||
// DISABLED
|
||||
|
||||
ret |= omv_i2c_readb(&csi->i2c_bus, csi->slv_addr, COM7, ®);
|
||||
ret |= omv_i2c_readb(csi->i2c, csi->slv_addr, COM7, ®);
|
||||
|
||||
int t_line = (reg & COM7_RES_QVGA) ? (320 + 256) : (640 + 144);
|
||||
int t_pclk = (COM7_GET_FMT(reg) == COM7_FMT_P_BAYER) ? 1 : 2;
|
||||
|
||||
ret |= omv_i2c_readb(&csi->i2c_bus, csi->slv_addr, COM4, ®);
|
||||
ret |= omv_i2c_readb(csi->i2c, csi->slv_addr, COM4, ®);
|
||||
int pll_mult = 0;
|
||||
|
||||
if (COM4_GET_PLL(reg) == COM4_PLL_BYPASS) {
|
||||
@ -491,7 +491,7 @@ static int get_exposure_us(omv_csi_t *csi, int *exposure_us) {
|
||||
pll_mult = 8;
|
||||
}
|
||||
|
||||
ret |= omv_i2c_readb(&csi->i2c_bus, csi->slv_addr, CLKRC, ®);
|
||||
ret |= omv_i2c_readb(csi->i2c, csi->slv_addr, CLKRC, ®);
|
||||
int clk_rc = 0;
|
||||
|
||||
if (reg & CLKRC_NO_PRESCALE) {
|
||||
@ -508,21 +508,21 @@ static int get_exposure_us(omv_csi_t *csi, int *exposure_us) {
|
||||
|
||||
static int set_auto_whitebal(omv_csi_t *csi, int enable, float r_gain_db, float g_gain_db, float b_gain_db) {
|
||||
uint8_t reg;
|
||||
int ret = omv_i2c_readb(&csi->i2c_bus, csi->slv_addr, COM8, ®);
|
||||
ret |= omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, COM8, COM8_SET_AWB(reg, (enable != 0)));
|
||||
int ret = omv_i2c_readb(csi->i2c, csi->slv_addr, COM8, ®);
|
||||
ret |= omv_i2c_writeb(csi->i2c, csi->slv_addr, COM8, COM8_SET_AWB(reg, (enable != 0)));
|
||||
|
||||
if ((enable == 0) && (!isnanf(r_gain_db)) && (!isnanf(g_gain_db)) && (!isnanf(b_gain_db))
|
||||
&& (!isinff(r_gain_db)) && (!isinff(g_gain_db)) && (!isinff(b_gain_db))) {
|
||||
ret |= omv_i2c_readb(&csi->i2c_bus, csi->slv_addr, AWB_CTRL1, ®);
|
||||
ret |= omv_i2c_readb(csi->i2c, csi->slv_addr, AWB_CTRL1, ®);
|
||||
float gain_div = (reg & 0x2) ? 64.0f : 128.0f;
|
||||
|
||||
int r_gain = __USAT(fast_roundf(expf((r_gain_db / 20.0f) * M_LN10) * gain_div), 8);
|
||||
int g_gain = __USAT(fast_roundf(expf((g_gain_db / 20.0f) * M_LN10) * gain_div), 8);
|
||||
int b_gain = __USAT(fast_roundf(expf((b_gain_db / 20.0f) * M_LN10) * gain_div), 8);
|
||||
|
||||
ret |= omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, BLUE, b_gain);
|
||||
ret |= omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, RED, r_gain);
|
||||
ret |= omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, GREEN, g_gain);
|
||||
ret |= omv_i2c_writeb(csi->i2c, csi->slv_addr, BLUE, b_gain);
|
||||
ret |= omv_i2c_writeb(csi->i2c, csi->slv_addr, RED, r_gain);
|
||||
ret |= omv_i2c_writeb(csi->i2c, csi->slv_addr, GREEN, g_gain);
|
||||
}
|
||||
|
||||
return ret;
|
||||
@ -530,25 +530,25 @@ static int set_auto_whitebal(omv_csi_t *csi, int enable, float r_gain_db, float
|
||||
|
||||
static int get_rgb_gain_db(omv_csi_t *csi, float *r_gain_db, float *g_gain_db, float *b_gain_db) {
|
||||
uint8_t reg, blue, red, green;
|
||||
int ret = omv_i2c_readb(&csi->i2c_bus, csi->slv_addr, COM8, ®);
|
||||
int ret = omv_i2c_readb(csi->i2c, csi->slv_addr, COM8, ®);
|
||||
|
||||
// DISABLED
|
||||
// if (reg & COM8_AWB_EN) {
|
||||
// ret |= omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, COM8, COM8_SET_AWB(reg, 0));
|
||||
// ret |= omv_i2c_writeb(csi->i2c, csi->slv_addr, COM8, COM8_SET_AWB(reg, 0));
|
||||
// }
|
||||
// DISABLED
|
||||
|
||||
ret |= omv_i2c_readb(&csi->i2c_bus, csi->slv_addr, BLUE, &blue);
|
||||
ret |= omv_i2c_readb(&csi->i2c_bus, csi->slv_addr, RED, &red);
|
||||
ret |= omv_i2c_readb(&csi->i2c_bus, csi->slv_addr, GREEN, &green);
|
||||
ret |= omv_i2c_readb(csi->i2c, csi->slv_addr, BLUE, &blue);
|
||||
ret |= omv_i2c_readb(csi->i2c, csi->slv_addr, RED, &red);
|
||||
ret |= omv_i2c_readb(csi->i2c, csi->slv_addr, GREEN, &green);
|
||||
|
||||
// DISABLED
|
||||
// if (reg & COM8_AWB_EN) {
|
||||
// ret |= omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, COM8, COM8_SET_AWB(reg, 1));
|
||||
// ret |= omv_i2c_writeb(csi->i2c, csi->slv_addr, COM8, COM8_SET_AWB(reg, 1));
|
||||
// }
|
||||
// DISABLED
|
||||
|
||||
ret |= omv_i2c_readb(&csi->i2c_bus, csi->slv_addr, AWB_CTRL1, ®);
|
||||
ret |= omv_i2c_readb(csi->i2c, csi->slv_addr, AWB_CTRL1, ®);
|
||||
float gain_div = (reg & 0x2) ? 64.0f : 128.0f;
|
||||
|
||||
*r_gain_db = 20.0f * log10f(red / gain_div);
|
||||
@ -560,12 +560,12 @@ static int get_rgb_gain_db(omv_csi_t *csi, float *r_gain_db, float *g_gain_db, f
|
||||
|
||||
static int set_auto_blc(omv_csi_t *csi, int enable, int *regs) {
|
||||
uint8_t reg;
|
||||
int ret = omv_i2c_readb(&csi->i2c_bus, csi->slv_addr, COM13, ®);
|
||||
ret |= omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, COM13, COM13_SET_BLC(reg, (enable != 0)));
|
||||
int ret = omv_i2c_readb(csi->i2c, csi->slv_addr, COM13, ®);
|
||||
ret |= omv_i2c_writeb(csi->i2c, csi->slv_addr, COM13, COM13_SET_BLC(reg, (enable != 0)));
|
||||
|
||||
if ((enable == 0) && (regs != NULL)) {
|
||||
for (uint32_t i = 0; i < csi->blc_size; i++) {
|
||||
ret |= omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, ADOFF_B + i, regs[i]);
|
||||
ret |= omv_i2c_writeb(csi->i2c, csi->slv_addr, ADOFF_B + i, regs[i]);
|
||||
}
|
||||
}
|
||||
|
||||
@ -577,7 +577,7 @@ static int get_blc_regs(omv_csi_t *csi, int *regs) {
|
||||
|
||||
for (uint32_t i = 0; i < csi->blc_size; i++) {
|
||||
uint8_t reg;
|
||||
ret |= omv_i2c_readb(&csi->i2c_bus, csi->slv_addr, ADOFF_B + i, ®);
|
||||
ret |= omv_i2c_readb(csi->i2c, csi->slv_addr, ADOFF_B + i, ®);
|
||||
regs[i] = reg;
|
||||
}
|
||||
|
||||
@ -586,16 +586,16 @@ static int get_blc_regs(omv_csi_t *csi, int *regs) {
|
||||
|
||||
static int set_hmirror(omv_csi_t *csi, int enable) {
|
||||
uint8_t reg;
|
||||
int ret = omv_i2c_readb(&csi->i2c_bus, csi->slv_addr, COM3, ®);
|
||||
ret |= omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, COM3, COM3_SET_MIRROR(reg, enable));
|
||||
int ret = omv_i2c_readb(csi->i2c, csi->slv_addr, COM3, ®);
|
||||
ret |= omv_i2c_writeb(csi->i2c, csi->slv_addr, COM3, COM3_SET_MIRROR(reg, enable));
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int set_vflip(omv_csi_t *csi, int enable) {
|
||||
uint8_t reg;
|
||||
int ret = omv_i2c_readb(&csi->i2c_bus, csi->slv_addr, COM3, ®);
|
||||
ret |= omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, COM3, COM3_SET_FLIP(reg, enable));
|
||||
int ret = omv_i2c_readb(csi->i2c, csi->slv_addr, COM3, ®);
|
||||
ret |= omv_i2c_writeb(csi->i2c, csi->slv_addr, COM3, COM3_SET_FLIP(reg, enable));
|
||||
// Apply new vertical flip setting.
|
||||
ret |= set_framesize(csi, csi->framesize);
|
||||
|
||||
@ -607,12 +607,12 @@ static int set_special_effect(omv_csi_t *csi, omv_csi_sde_t sde) {
|
||||
|
||||
switch (sde) {
|
||||
case OMV_CSI_SDE_NEGATIVE:
|
||||
ret |= omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, SDE, 0x46);
|
||||
ret |= omv_i2c_writeb(csi->i2c, csi->slv_addr, SDE, 0x46);
|
||||
break;
|
||||
case OMV_CSI_SDE_NORMAL:
|
||||
ret |= omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, SDE, 0x06);
|
||||
ret |= omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, UFIX, 0x80);
|
||||
ret |= omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, VFIX, 0x80);
|
||||
ret |= omv_i2c_writeb(csi->i2c, csi->slv_addr, SDE, 0x06);
|
||||
ret |= omv_i2c_writeb(csi->i2c, csi->slv_addr, UFIX, 0x80);
|
||||
ret |= omv_i2c_writeb(csi->i2c, csi->slv_addr, VFIX, 0x80);
|
||||
break;
|
||||
default:
|
||||
return -1;
|
||||
@ -624,9 +624,9 @@ static int set_special_effect(omv_csi_t *csi, omv_csi_sde_t sde) {
|
||||
static int set_lens_correction(omv_csi_t *csi, int enable, int radi, int coef) {
|
||||
int ret = 0;
|
||||
|
||||
ret |= omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, LC_CTR, (enable & 0x01));
|
||||
ret |= omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, LC_RADI, radi);
|
||||
ret |= omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, LC_COEF, coef);
|
||||
ret |= omv_i2c_writeb(csi->i2c, csi->slv_addr, LC_CTR, (enable & 0x01));
|
||||
ret |= omv_i2c_writeb(csi->i2c, csi->slv_addr, LC_RADI, radi);
|
||||
ret |= omv_i2c_writeb(csi->i2c, csi->slv_addr, LC_COEF, coef);
|
||||
|
||||
return ret;
|
||||
}
|
||||
@ -638,17 +638,17 @@ static int ioctl(omv_csi_t *csi, int request, va_list ap) {
|
||||
switch (request) {
|
||||
case OMV_CSI_IOCTL_SET_NIGHT_MODE: {
|
||||
int enable = va_arg(ap, int);
|
||||
ret = omv_i2c_readb(&csi->i2c_bus, csi->slv_addr, COM5, ®);
|
||||
ret |= omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, COM5, COM5_SET_AFR(reg, (enable != 0)));
|
||||
ret = omv_i2c_readb(csi->i2c, csi->slv_addr, COM5, ®);
|
||||
ret |= omv_i2c_writeb(csi->i2c, csi->slv_addr, COM5, COM5_SET_AFR(reg, (enable != 0)));
|
||||
if (enable == 0) {
|
||||
ret |= omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, ADVFL, 0);
|
||||
ret |= omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, ADVFH, 0);
|
||||
ret |= omv_i2c_writeb(csi->i2c, csi->slv_addr, ADVFL, 0);
|
||||
ret |= omv_i2c_writeb(csi->i2c, csi->slv_addr, ADVFH, 0);
|
||||
}
|
||||
break;
|
||||
}
|
||||
case OMV_CSI_IOCTL_GET_NIGHT_MODE: {
|
||||
int *enable = va_arg(ap, int *);
|
||||
ret = omv_i2c_readb(&csi->i2c_bus, csi->slv_addr, COM5, ®);
|
||||
ret = omv_i2c_readb(csi->i2c, csi->slv_addr, COM5, ®);
|
||||
if (ret >= 0) {
|
||||
*enable = reg & COM5_AFR;
|
||||
}
|
||||
|
||||
@ -222,14 +222,14 @@ static int reset(omv_csi_t *csi) {
|
||||
const uint8_t(*regs)[2] = default_regs;
|
||||
|
||||
/* Reset all registers */
|
||||
omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, REG_COM7, 0x80);
|
||||
omv_i2c_writeb(csi->i2c, csi->slv_addr, REG_COM7, 0x80);
|
||||
|
||||
/* delay n ms */
|
||||
mp_hal_delay_ms(10);
|
||||
|
||||
/* Write initial registers */
|
||||
while (regs[i][0]) {
|
||||
omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, regs[i][0], regs[i][1]);
|
||||
omv_i2c_writeb(csi->i2c, csi->slv_addr, regs[i][0], regs[i][1]);
|
||||
i++;
|
||||
}
|
||||
|
||||
@ -242,7 +242,7 @@ static int set_pixformat(omv_csi_t *csi, pixformat_t pixformat) {
|
||||
uint8_t com7 = 0; /* framesize/RGB */
|
||||
|
||||
/* read pixel format reg */
|
||||
omv_i2c_readb(&csi->i2c_bus, csi->slv_addr, REG_COM7, &com7);
|
||||
omv_i2c_readb(csi->i2c, csi->slv_addr, REG_COM7, &com7);
|
||||
|
||||
switch (pixformat) {
|
||||
case PIXFORMAT_RGB565:
|
||||
@ -262,11 +262,11 @@ static int set_pixformat(omv_csi_t *csi, pixformat_t pixformat) {
|
||||
}
|
||||
|
||||
/* Set pixel format */
|
||||
omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, REG_COM7, com7);
|
||||
omv_i2c_writeb(csi->i2c, csi->slv_addr, REG_COM7, com7);
|
||||
|
||||
/* Write pixel format registers */
|
||||
while (regs[i][0]) {
|
||||
omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, regs[i][0], regs[i][1]);
|
||||
omv_i2c_writeb(csi->i2c, csi->slv_addr, regs[i][0], regs[i][1]);
|
||||
i++;
|
||||
}
|
||||
|
||||
@ -278,7 +278,7 @@ static int set_framesize(omv_csi_t *csi, omv_csi_framesize_t framesize) {
|
||||
uint8_t com1 = 0; /* Skip option */
|
||||
|
||||
/* read COM7 RGB bit */
|
||||
omv_i2c_readb(&csi->i2c_bus, csi->slv_addr, REG_COM7, &com7);
|
||||
omv_i2c_readb(csi->i2c, csi->slv_addr, REG_COM7, &com7);
|
||||
com7 &= REG_COM7_RGB;
|
||||
|
||||
switch (framesize) {
|
||||
@ -298,8 +298,8 @@ static int set_framesize(omv_csi_t *csi, omv_csi_framesize_t framesize) {
|
||||
}
|
||||
|
||||
/* write the frame size registers */
|
||||
omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, REG_COM1, com1);
|
||||
omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, REG_COM7, com7);
|
||||
omv_i2c_writeb(csi->i2c, csi->slv_addr, REG_COM1, com1);
|
||||
omv_i2c_writeb(csi->i2c, csi->slv_addr, REG_COM7, com7);
|
||||
|
||||
return 0;
|
||||
}
|
||||
@ -324,7 +324,7 @@ static int set_brightness(omv_csi_t *csi, int level) {
|
||||
}
|
||||
|
||||
for (i = 0; i < 3; i++) {
|
||||
omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, regs[0][i], regs[level][i]);
|
||||
omv_i2c_writeb(csi->i2c, csi->slv_addr, regs[0][i], regs[level][i]);
|
||||
}
|
||||
|
||||
return 0;
|
||||
@ -332,15 +332,15 @@ static int set_brightness(omv_csi_t *csi, int level) {
|
||||
|
||||
static int set_gainceiling(omv_csi_t *csi, omv_csi_gainceiling_t gainceiling) {
|
||||
/* Write gain ceiling register */
|
||||
omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, REG_COM9, (gainceiling << 4));
|
||||
omv_i2c_writeb(csi->i2c, csi->slv_addr, REG_COM9, (gainceiling << 4));
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int set_auto_gain(omv_csi_t *csi, int enable, float gain_db, float gain_db_ceiling) {
|
||||
uint8_t reg;
|
||||
int ret = omv_i2c_readb(&csi->i2c_bus, csi->slv_addr, REG_COM8, ®);
|
||||
int ret = omv_i2c_readb(csi->i2c, csi->slv_addr, REG_COM8, ®);
|
||||
ret |=
|
||||
omv_i2c_writeb(&csi->i2c_bus,
|
||||
omv_i2c_writeb(csi->i2c,
|
||||
csi->slv_addr,
|
||||
REG_COM8,
|
||||
(reg & (~REG_COM8_AGC)) | ((enable != 0) ? REG_COM8_AGC : 0));
|
||||
@ -352,15 +352,15 @@ static int set_auto_gain(omv_csi_t *csi, int enable, float gain_db, float gain_d
|
||||
int gain_hi = 0x3F >> (6 - gain_temp);
|
||||
int gain_lo = IM_MIN(fast_roundf(((gain / (1 << gain_temp)) - 1.0f) * 16.0f), 15);
|
||||
|
||||
ret |= omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, REG_GAIN, ((gain_hi & 0x0F) << 4) | (gain_lo << 0));
|
||||
ret |= omv_i2c_readb(&csi->i2c_bus, csi->slv_addr, REG_VREF, ®);
|
||||
ret |= omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, REG_VREF, ((gain_hi & 0x30) << 2) | (reg & 0x3F));
|
||||
ret |= omv_i2c_writeb(csi->i2c, csi->slv_addr, REG_GAIN, ((gain_hi & 0x0F) << 4) | (gain_lo << 0));
|
||||
ret |= omv_i2c_readb(csi->i2c, csi->slv_addr, REG_VREF, ®);
|
||||
ret |= omv_i2c_writeb(csi->i2c, csi->slv_addr, REG_VREF, ((gain_hi & 0x30) << 2) | (reg & 0x3F));
|
||||
} else if ((enable != 0) && (!isnanf(gain_db_ceiling)) && (!isinf(gain_db_ceiling))) {
|
||||
float gain_ceiling = IM_CLAMP(expf((gain_db_ceiling / 20.0f) * M_LN10), 2.0f, 128.0f);
|
||||
|
||||
ret |= omv_i2c_readb(&csi->i2c_bus, csi->slv_addr, REG_COM9, ®);
|
||||
ret |= omv_i2c_readb(csi->i2c, csi->slv_addr, REG_COM9, ®);
|
||||
ret |=
|
||||
omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, REG_COM9,
|
||||
omv_i2c_writeb(csi->i2c, csi->slv_addr, REG_COM9,
|
||||
(reg & 0x8F) | ((fast_ceilf(logf(gain_ceiling) / M_LN2) - 1) << 4));
|
||||
}
|
||||
|
||||
@ -369,20 +369,20 @@ static int set_auto_gain(omv_csi_t *csi, int enable, float gain_db, float gain_d
|
||||
|
||||
static int get_gain_db(omv_csi_t *csi, float *gain_db) {
|
||||
uint8_t reg, gain_lo, gain_hi;
|
||||
int ret = omv_i2c_readb(&csi->i2c_bus, csi->slv_addr, REG_COM8, ®);
|
||||
int ret = omv_i2c_readb(csi->i2c, csi->slv_addr, REG_COM8, ®);
|
||||
|
||||
// DISABLED
|
||||
// if (reg & REG_COM8_AGC) {
|
||||
// ret |= omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, REG_COM8, reg & (~REG_COM8_AGC));
|
||||
// ret |= omv_i2c_writeb(csi->i2c, csi->slv_addr, REG_COM8, reg & (~REG_COM8_AGC));
|
||||
// }
|
||||
// DISABLED
|
||||
|
||||
ret |= omv_i2c_readb(&csi->i2c_bus, csi->slv_addr, REG_GAIN, &gain_lo);
|
||||
ret |= omv_i2c_readb(&csi->i2c_bus, csi->slv_addr, REG_VREF, &gain_hi);
|
||||
ret |= omv_i2c_readb(csi->i2c, csi->slv_addr, REG_GAIN, &gain_lo);
|
||||
ret |= omv_i2c_readb(csi->i2c, csi->slv_addr, REG_VREF, &gain_hi);
|
||||
|
||||
// DISABLED
|
||||
// if (reg & REG_COM8_AGC) {
|
||||
// ret |= omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, REG_COM8, reg | REG_COM8_AGC);
|
||||
// ret |= omv_i2c_writeb(csi->i2c, csi->slv_addr, REG_COM8, reg | REG_COM8_AGC);
|
||||
// }
|
||||
// DISABLED
|
||||
|
||||
@ -399,15 +399,15 @@ static int get_gain_db(omv_csi_t *csi, float *gain_db) {
|
||||
|
||||
static int set_auto_exposure(omv_csi_t *csi, int enable, int exposure_us) {
|
||||
uint8_t reg;
|
||||
int ret = omv_i2c_readb(&csi->i2c_bus, csi->slv_addr, REG_COM8, ®);
|
||||
int ret = omv_i2c_readb(csi->i2c, csi->slv_addr, REG_COM8, ®);
|
||||
ret |=
|
||||
omv_i2c_writeb(&csi->i2c_bus,
|
||||
omv_i2c_writeb(csi->i2c,
|
||||
csi->slv_addr,
|
||||
REG_COM8,
|
||||
(reg & (~REG_COM8_AEC)) | ((enable != 0) ? REG_COM8_AEC : 0));
|
||||
|
||||
if ((enable == 0) && (exposure_us >= 0)) {
|
||||
ret |= omv_i2c_readb(&csi->i2c_bus, csi->slv_addr, REG_COM7, ®);
|
||||
ret |= omv_i2c_readb(csi->i2c, csi->slv_addr, REG_COM7, ®);
|
||||
int t_line = 0, t_pclk = (reg & REG_COM7_RGB) ? 2 : 1;
|
||||
|
||||
if (reg & REG_COM7_VGA) {
|
||||
@ -423,21 +423,21 @@ static int set_auto_exposure(omv_csi_t *csi, int enable, int exposure_us) {
|
||||
t_line = 176 + 84;
|
||||
}
|
||||
|
||||
ret |= omv_i2c_readb(&csi->i2c_bus, csi->slv_addr, REG_CLKRC, ®);
|
||||
ret |= omv_i2c_readb(csi->i2c, csi->slv_addr, REG_CLKRC, ®);
|
||||
int pll_mult = (reg & REG_CLKRC_DOUBLE) ? 2 : 1;
|
||||
int clk_rc = ((reg & REG_CLKRC_DIVIDER_MASK) + 1) * 2;
|
||||
|
||||
int exposure =
|
||||
__USAT(((exposure_us * (((OMV_CSI_CLK_FREQUENCY / clk_rc) * pll_mult) / 1000000)) / t_pclk) / t_line, 16);
|
||||
|
||||
ret |= omv_i2c_readb(&csi->i2c_bus, csi->slv_addr, REG_COM1, ®);
|
||||
ret |= omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, REG_COM1, (reg & 0xFC) | ((exposure >> 0) & 0x3));
|
||||
ret |= omv_i2c_readb(csi->i2c, csi->slv_addr, REG_COM1, ®);
|
||||
ret |= omv_i2c_writeb(csi->i2c, csi->slv_addr, REG_COM1, (reg & 0xFC) | ((exposure >> 0) & 0x3));
|
||||
|
||||
ret |= omv_i2c_readb(&csi->i2c_bus, csi->slv_addr, REG_AECH, ®);
|
||||
ret |= omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, REG_AECH, (reg & 0x00) | ((exposure >> 2) & 0xFF));
|
||||
ret |= omv_i2c_readb(csi->i2c, csi->slv_addr, REG_AECH, ®);
|
||||
ret |= omv_i2c_writeb(csi->i2c, csi->slv_addr, REG_AECH, (reg & 0x00) | ((exposure >> 2) & 0xFF));
|
||||
|
||||
ret |= omv_i2c_readb(&csi->i2c_bus, csi->slv_addr, REG_AECHM, ®);
|
||||
ret |= omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, REG_AECHM, (reg & 0xC0) | ((exposure >> 10) & 0x3F));
|
||||
ret |= omv_i2c_readb(csi->i2c, csi->slv_addr, REG_AECHM, ®);
|
||||
ret |= omv_i2c_writeb(csi->i2c, csi->slv_addr, REG_AECHM, (reg & 0xC0) | ((exposure >> 10) & 0x3F));
|
||||
}
|
||||
|
||||
return ret;
|
||||
@ -445,25 +445,25 @@ static int set_auto_exposure(omv_csi_t *csi, int enable, int exposure_us) {
|
||||
|
||||
static int get_exposure_us(omv_csi_t *csi, int *exposure_us) {
|
||||
uint8_t reg, aec_10, aec_92, aec_1510;
|
||||
int ret = omv_i2c_readb(&csi->i2c_bus, csi->slv_addr, REG_COM8, ®);
|
||||
int ret = omv_i2c_readb(csi->i2c, csi->slv_addr, REG_COM8, ®);
|
||||
|
||||
// DISABLED
|
||||
// if (reg & REG_COM8_AEC) {
|
||||
// ret |= omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, REG_COM8, reg & (~REG_COM8_AEC));
|
||||
// ret |= omv_i2c_writeb(csi->i2c, csi->slv_addr, REG_COM8, reg & (~REG_COM8_AEC));
|
||||
// }
|
||||
// DISABLED
|
||||
|
||||
ret |= omv_i2c_readb(&csi->i2c_bus, csi->slv_addr, REG_COM1, &aec_10);
|
||||
ret |= omv_i2c_readb(&csi->i2c_bus, csi->slv_addr, REG_AECH, &aec_92);
|
||||
ret |= omv_i2c_readb(&csi->i2c_bus, csi->slv_addr, REG_AECHM, &aec_1510);
|
||||
ret |= omv_i2c_readb(csi->i2c, csi->slv_addr, REG_COM1, &aec_10);
|
||||
ret |= omv_i2c_readb(csi->i2c, csi->slv_addr, REG_AECH, &aec_92);
|
||||
ret |= omv_i2c_readb(csi->i2c, csi->slv_addr, REG_AECHM, &aec_1510);
|
||||
|
||||
// DISABLED
|
||||
// if (reg & REG_COM8_AEC) {
|
||||
// ret |= omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, REG_COM8, reg | REG_COM8_AEC);
|
||||
// ret |= omv_i2c_writeb(csi->i2c, csi->slv_addr, REG_COM8, reg | REG_COM8_AEC);
|
||||
// }
|
||||
// DISABLED
|
||||
|
||||
ret |= omv_i2c_readb(&csi->i2c_bus, csi->slv_addr, REG_COM7, ®);
|
||||
ret |= omv_i2c_readb(csi->i2c, csi->slv_addr, REG_COM7, ®);
|
||||
int t_line = 0, t_pclk = (reg & REG_COM7_RGB) ? 2 : 1;
|
||||
|
||||
if (reg & REG_COM7_VGA) {
|
||||
@ -479,7 +479,7 @@ static int get_exposure_us(omv_csi_t *csi, int *exposure_us) {
|
||||
t_line = 176 + 84;
|
||||
}
|
||||
|
||||
ret |= omv_i2c_readb(&csi->i2c_bus, csi->slv_addr, REG_CLKRC, ®);
|
||||
ret |= omv_i2c_readb(csi->i2c, csi->slv_addr, REG_CLKRC, ®);
|
||||
int pll_mult = (reg & REG_CLKRC_DOUBLE) ? 2 : 1;
|
||||
int clk_rc = ((reg & REG_CLKRC_DIVIDER_MASK) + 1) * 2;
|
||||
|
||||
@ -491,9 +491,9 @@ static int get_exposure_us(omv_csi_t *csi, int *exposure_us) {
|
||||
|
||||
static int set_auto_whitebal(omv_csi_t *csi, int enable, float r_gain_db, float g_gain_db, float b_gain_db) {
|
||||
uint8_t reg;
|
||||
int ret = omv_i2c_readb(&csi->i2c_bus, csi->slv_addr, REG_COM8, ®);
|
||||
int ret = omv_i2c_readb(csi->i2c, csi->slv_addr, REG_COM8, ®);
|
||||
ret |=
|
||||
omv_i2c_writeb(&csi->i2c_bus,
|
||||
omv_i2c_writeb(csi->i2c,
|
||||
csi->slv_addr,
|
||||
REG_COM8,
|
||||
(reg & (~REG_COM8_AWB)) | ((enable != 0) ? REG_COM8_AWB : 0));
|
||||
@ -503,8 +503,8 @@ static int set_auto_whitebal(omv_csi_t *csi, int enable, float r_gain_db, float
|
||||
int r_gain = __USAT(fast_roundf(expf((r_gain_db / 20.0f) * M_LN10) * 128.0f), 8);
|
||||
int b_gain = __USAT(fast_roundf(expf((b_gain_db / 20.0f) * M_LN10) * 128.0f), 8);
|
||||
|
||||
ret |= omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, REG_BLUE, b_gain);
|
||||
ret |= omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, REG_RED, r_gain);
|
||||
ret |= omv_i2c_writeb(csi->i2c, csi->slv_addr, REG_BLUE, b_gain);
|
||||
ret |= omv_i2c_writeb(csi->i2c, csi->slv_addr, REG_RED, r_gain);
|
||||
}
|
||||
|
||||
return ret;
|
||||
@ -512,20 +512,20 @@ static int set_auto_whitebal(omv_csi_t *csi, int enable, float r_gain_db, float
|
||||
|
||||
static int get_rgb_gain_db(omv_csi_t *csi, float *r_gain_db, float *g_gain_db, float *b_gain_db) {
|
||||
uint8_t reg, blue, red;
|
||||
int ret = omv_i2c_readb(&csi->i2c_bus, csi->slv_addr, REG_COM8, ®);
|
||||
int ret = omv_i2c_readb(csi->i2c, csi->slv_addr, REG_COM8, ®);
|
||||
|
||||
// DISABLED
|
||||
// if (reg & REG_COM8_AWB) {
|
||||
// ret |= omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, REG_COM8, reg & (~REG_COM8_AWB));
|
||||
// ret |= omv_i2c_writeb(csi->i2c, csi->slv_addr, REG_COM8, reg & (~REG_COM8_AWB));
|
||||
// }
|
||||
// DISABLED
|
||||
|
||||
ret |= omv_i2c_readb(&csi->i2c_bus, csi->slv_addr, REG_BLUE, &blue);
|
||||
ret |= omv_i2c_readb(&csi->i2c_bus, csi->slv_addr, REG_RED, &red);
|
||||
ret |= omv_i2c_readb(csi->i2c, csi->slv_addr, REG_BLUE, &blue);
|
||||
ret |= omv_i2c_readb(csi->i2c, csi->slv_addr, REG_RED, &red);
|
||||
|
||||
// DISABLED
|
||||
// if (reg & REG_COM8_AWB) {
|
||||
// ret |= omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, REG_COM8, reg | REG_COM8_AWB);
|
||||
// ret |= omv_i2c_writeb(csi->i2c, csi->slv_addr, REG_COM8, reg | REG_COM8_AWB);
|
||||
// }
|
||||
// DISABLED
|
||||
|
||||
@ -537,9 +537,9 @@ static int get_rgb_gain_db(omv_csi_t *csi, float *r_gain_db, float *g_gain_db, f
|
||||
|
||||
static int set_hmirror(omv_csi_t *csi, int enable) {
|
||||
uint8_t val;
|
||||
int ret = omv_i2c_readb(&csi->i2c_bus, csi->slv_addr, REG_MVFP, &val);
|
||||
int ret = omv_i2c_readb(csi->i2c, csi->slv_addr, REG_MVFP, &val);
|
||||
ret |=
|
||||
omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, REG_MVFP,
|
||||
omv_i2c_writeb(csi->i2c, csi->slv_addr, REG_MVFP,
|
||||
enable ? (val | REG_MVFP_HMIRROR) : (val & (~REG_MVFP_HMIRROR)));
|
||||
|
||||
return ret;
|
||||
@ -547,9 +547,9 @@ static int set_hmirror(omv_csi_t *csi, int enable) {
|
||||
|
||||
static int set_vflip(omv_csi_t *csi, int enable) {
|
||||
uint8_t val;
|
||||
int ret = omv_i2c_readb(&csi->i2c_bus, csi->slv_addr, REG_MVFP, &val);
|
||||
int ret = omv_i2c_readb(csi->i2c, csi->slv_addr, REG_MVFP, &val);
|
||||
ret |=
|
||||
omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, REG_MVFP,
|
||||
omv_i2c_writeb(csi->i2c, csi->slv_addr, REG_MVFP,
|
||||
enable ? (val | REG_MVFP_VFLIP) : (val & (~REG_MVFP_VFLIP)));
|
||||
|
||||
return ret;
|
||||
|
||||
@ -211,7 +211,7 @@ static bool g_f_vflip = false;
|
||||
static int switch_bank(omv_csi_t *csi, uint8_t bank) {
|
||||
if (g_bank_cache != bank) {
|
||||
debug_printf("W Reg: 0x%02X 0x%02X\r\n", REG_BANK, bank);
|
||||
int res = omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, REG_BANK, bank);
|
||||
int res = omv_i2c_writeb(csi->i2c, csi->slv_addr, REG_BANK, bank);
|
||||
if (res) {
|
||||
g_bank_cache = -1; // Encountered an unknown error, clear cache.
|
||||
printf("switch bank failed, res = %d\n", res);
|
||||
@ -234,7 +234,7 @@ static int write_reg_w_bank(omv_csi_t *csi, uint8_t bank, uint8_t addr,
|
||||
}
|
||||
|
||||
debug_printf("W Reg: 0x%02X 0x%02X\r\n", addr, val);
|
||||
return omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, addr, val);
|
||||
return omv_i2c_writeb(csi->i2c, csi->slv_addr, addr, val);
|
||||
}
|
||||
|
||||
static int read_reg_w_bank(omv_csi_t *csi, uint8_t bank, uint8_t addr,
|
||||
@ -245,7 +245,7 @@ static int read_reg_w_bank(omv_csi_t *csi, uint8_t bank, uint8_t addr,
|
||||
}
|
||||
|
||||
debug_printf("R Reg: 0x%02X\r\n", addr);
|
||||
return omv_i2c_readb(&csi->i2c_bus, csi->slv_addr, addr, p_val);
|
||||
return omv_i2c_readb(csi->i2c, csi->slv_addr, addr, p_val);
|
||||
}
|
||||
|
||||
static int init_csi(omv_csi_t *csi) {
|
||||
@ -254,7 +254,7 @@ static int init_csi(omv_csi_t *csi) {
|
||||
#define ta_seq default_regs
|
||||
for (int i = 0; ta_seq[i][0]; i++) {
|
||||
debug_printf("W Reg: 0x%02X 0x%02X\r\n", ta_seq[i][0], ta_seq[i][1]);
|
||||
int res = omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, ta_seq[i][0],
|
||||
int res = omv_i2c_writeb(csi->i2c, csi->slv_addr, ta_seq[i][0],
|
||||
ta_seq[i][1]);
|
||||
if (res) {
|
||||
return res;
|
||||
@ -282,7 +282,7 @@ static int sleep(omv_csi_t *csi, int enable) {
|
||||
|
||||
static int read_reg(omv_csi_t *csi, uint16_t reg_addr) {
|
||||
uint8_t val = 0;
|
||||
if (omv_i2c_readb(&csi->i2c_bus, csi->slv_addr, (uint8_t) reg_addr, &val)) {
|
||||
if (omv_i2c_readb(csi->i2c, csi->slv_addr, (uint8_t) reg_addr, &val)) {
|
||||
return -1;
|
||||
}
|
||||
return val;
|
||||
@ -290,7 +290,7 @@ static int read_reg(omv_csi_t *csi, uint16_t reg_addr) {
|
||||
|
||||
static int write_reg(omv_csi_t *csi, uint16_t reg_addr, uint16_t reg_data) {
|
||||
int ret;
|
||||
ret = omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, (uint8_t) reg_addr,
|
||||
ret = omv_i2c_writeb(csi->i2c, csi->slv_addr, (uint8_t) reg_addr,
|
||||
(uint8_t) reg_data);
|
||||
if (ret == 0 && reg_addr == REG_BANK) {
|
||||
g_bank_cache = (uint8_t) reg_data;
|
||||
|
||||
@ -408,34 +408,34 @@ static int reset(omv_csi_t *csi) {
|
||||
int ret = 0;
|
||||
// Write default registers
|
||||
for (int i = 0; default_regs[i][0] && ret == 0; i++) {
|
||||
ret |= omv_i2c_writeb2(&csi->i2c_bus, csi->slv_addr, default_regs[i][0], default_regs[i][1]);
|
||||
ret |= omv_i2c_writeb2(csi->i2c, csi->slv_addr, default_regs[i][0], default_regs[i][1]);
|
||||
}
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int sleep(omv_csi_t *csi, int enable) {
|
||||
int ret = omv_i2c_writeb2(&csi->i2c_bus, csi->slv_addr, SENSOR_TG_EN, SENSOR_TG_EN_FLAG);
|
||||
ret |= omv_i2c_writeb2(&csi->i2c_bus, csi->slv_addr, SENSOR_OPMODE,
|
||||
int ret = omv_i2c_writeb2(csi->i2c, csi->slv_addr, SENSOR_TG_EN, SENSOR_TG_EN_FLAG);
|
||||
ret |= omv_i2c_writeb2(csi->i2c, csi->slv_addr, SENSOR_OPMODE,
|
||||
enable ? SENSOR_OPMODE_SUSPEND : SENSOR_OPMODE_RUN);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int read_reg(omv_csi_t *csi, uint16_t reg) {
|
||||
uint8_t reg_data;
|
||||
if (omv_i2c_readb2(&csi->i2c_bus, csi->slv_addr, reg, ®_data) != 0) {
|
||||
if (omv_i2c_readb2(csi->i2c, csi->slv_addr, reg, ®_data) != 0) {
|
||||
return -1;
|
||||
}
|
||||
return reg_data;
|
||||
}
|
||||
|
||||
static int write_reg(omv_csi_t *csi, uint16_t reg, uint16_t reg_data) {
|
||||
return omv_i2c_writeb2(&csi->i2c_bus, csi->slv_addr, reg, reg_data);
|
||||
return omv_i2c_writeb2(csi->i2c, csi->slv_addr, reg, reg_data);
|
||||
}
|
||||
|
||||
static int read_reg_seq(omv_csi_t *csi, uint16_t addr, size_t size, uint8_t *buf) {
|
||||
int ret = 0;
|
||||
for (size_t i = 0; i < size; i++) {
|
||||
ret |= omv_i2c_readb2(&csi->i2c_bus, csi->slv_addr, addr + i, &buf[i]);
|
||||
ret |= omv_i2c_readb2(csi->i2c, csi->slv_addr, addr + i, &buf[i]);
|
||||
}
|
||||
return ret;
|
||||
}
|
||||
@ -470,7 +470,7 @@ static int set_framesize(omv_csi_t *csi, omv_csi_framesize_t framesize) {
|
||||
}
|
||||
|
||||
for (int i = 0; regs[i][0] && ret == 0; i++) {
|
||||
ret |= omv_i2c_writeb2(&csi->i2c_bus, csi->slv_addr, regs[i][0], regs[i][1]);
|
||||
ret |= omv_i2c_writeb2(csi->i2c, csi->slv_addr, regs[i][0], regs[i][1]);
|
||||
}
|
||||
|
||||
return ret;
|
||||
@ -496,102 +496,102 @@ static int set_framerate(omv_csi_t *csi, int framerate) {
|
||||
|
||||
int32_t frame_time = FT_CLK / framerate;
|
||||
|
||||
ret |= omv_i2c_readb2(&csi->i2c_bus, csi->slv_addr, FRAME_TIME_20_16, ®);
|
||||
ret |= omv_i2c_writeb2(&csi->i2c_bus, csi->slv_addr, FRAME_TIME_20_16, PAG7936_FRAME_TIME_H(reg, frame_time));
|
||||
ret |= omv_i2c_writeb2(&csi->i2c_bus, csi->slv_addr, FRAME_TIME_15_8, PAG7936_FRAME_TIME_M(frame_time));
|
||||
ret |= omv_i2c_writeb2(&csi->i2c_bus, csi->slv_addr, FRAME_TIME_7_0, PAG7936_FRAME_TIME_L(frame_time));
|
||||
ret |= omv_i2c_readb2(csi->i2c, csi->slv_addr, FRAME_TIME_20_16, ®);
|
||||
ret |= omv_i2c_writeb2(csi->i2c, csi->slv_addr, FRAME_TIME_20_16, PAG7936_FRAME_TIME_H(reg, frame_time));
|
||||
ret |= omv_i2c_writeb2(csi->i2c, csi->slv_addr, FRAME_TIME_15_8, PAG7936_FRAME_TIME_M(frame_time));
|
||||
ret |= omv_i2c_writeb2(csi->i2c, csi->slv_addr, FRAME_TIME_7_0, PAG7936_FRAME_TIME_L(frame_time));
|
||||
|
||||
ret |= omv_i2c_readb2(&csi->i2c_bus, csi->slv_addr, AE_EXPO_MANUAL, ®);
|
||||
ret |= omv_i2c_readb2(csi->i2c, csi->slv_addr, AE_EXPO_MANUAL, ®);
|
||||
|
||||
if (reg & AE_EXPO_MANUAL_AE_MANUAL_EN) {
|
||||
ret |= omv_i2c_readb2(&csi->i2c_bus, csi->slv_addr, AE_EXPO_MANUAL_17_16, &exposure_us_17_16);
|
||||
ret |= omv_i2c_readb2(&csi->i2c_bus, csi->slv_addr, AE_EXPO_MANUAL_15_8, &exposure_us_15_8);
|
||||
ret |= omv_i2c_readb2(&csi->i2c_bus, csi->slv_addr, AE_EXPO_MANUAL_7_0, &exposure_us_7_0);
|
||||
ret |= omv_i2c_readb2(csi->i2c, csi->slv_addr, AE_EXPO_MANUAL_17_16, &exposure_us_17_16);
|
||||
ret |= omv_i2c_readb2(csi->i2c, csi->slv_addr, AE_EXPO_MANUAL_15_8, &exposure_us_15_8);
|
||||
ret |= omv_i2c_readb2(csi->i2c, csi->slv_addr, AE_EXPO_MANUAL_7_0, &exposure_us_7_0);
|
||||
} else {
|
||||
ret |= omv_i2c_readb2(&csi->i2c_bus, csi->slv_addr, AE_MAXEXPO_17_16, &exposure_us_17_16);
|
||||
ret |= omv_i2c_readb2(&csi->i2c_bus, csi->slv_addr, AE_MAXEXPO_15_8, &exposure_us_15_8);
|
||||
ret |= omv_i2c_readb2(&csi->i2c_bus, csi->slv_addr, AE_MAXEXPO_7_0, &exposure_us_7_0);
|
||||
ret |= omv_i2c_readb2(csi->i2c, csi->slv_addr, AE_MAXEXPO_17_16, &exposure_us_17_16);
|
||||
ret |= omv_i2c_readb2(csi->i2c, csi->slv_addr, AE_MAXEXPO_15_8, &exposure_us_15_8);
|
||||
ret |= omv_i2c_readb2(csi->i2c, csi->slv_addr, AE_MAXEXPO_7_0, &exposure_us_7_0);
|
||||
}
|
||||
|
||||
int32_t exposure_us = PAG7936_EXPOSURE(exposure_us_17_16, exposure_us_15_8, exposure_us_7_0);
|
||||
exposure_us = IM_CLAMP(exposure_us, PAG7936_EXP_MIN, (frame_time - PAG7936_EXP_OFFSET)) / PAG7936_EXP_DIV;
|
||||
|
||||
if (reg & AE_EXPO_MANUAL_AE_MANUAL_EN) {
|
||||
ret |= omv_i2c_readb2(&csi->i2c_bus, csi->slv_addr, AE_EXPO_MANUAL_17_16, ®);
|
||||
ret |= omv_i2c_writeb2(&csi->i2c_bus, csi->slv_addr, AE_EXPO_MANUAL_17_16, PAG7936_EXPOSURE_H(reg, exposure_us));
|
||||
ret |= omv_i2c_writeb2(&csi->i2c_bus, csi->slv_addr, AE_EXPO_MANUAL_15_8, PAG7936_EXPOSURE_M(exposure_us));
|
||||
ret |= omv_i2c_writeb2(&csi->i2c_bus, csi->slv_addr, AE_EXPO_MANUAL_7_0, PAG7936_EXPOSURE_L(exposure_us));
|
||||
ret |= omv_i2c_readb2(csi->i2c, csi->slv_addr, AE_EXPO_MANUAL_17_16, ®);
|
||||
ret |= omv_i2c_writeb2(csi->i2c, csi->slv_addr, AE_EXPO_MANUAL_17_16, PAG7936_EXPOSURE_H(reg, exposure_us));
|
||||
ret |= omv_i2c_writeb2(csi->i2c, csi->slv_addr, AE_EXPO_MANUAL_15_8, PAG7936_EXPOSURE_M(exposure_us));
|
||||
ret |= omv_i2c_writeb2(csi->i2c, csi->slv_addr, AE_EXPO_MANUAL_7_0, PAG7936_EXPOSURE_L(exposure_us));
|
||||
} else {
|
||||
ret |= omv_i2c_readb2(&csi->i2c_bus, csi->slv_addr, AE_MAXEXPO_17_16, ®);
|
||||
ret |= omv_i2c_writeb2(&csi->i2c_bus, csi->slv_addr, AE_MAXEXPO_17_16, PAG7936_EXPOSURE_H(reg, exposure_us));
|
||||
ret |= omv_i2c_writeb2(&csi->i2c_bus, csi->slv_addr, AE_MAXEXPO_15_8, PAG7936_EXPOSURE_M(exposure_us));
|
||||
ret |= omv_i2c_writeb2(&csi->i2c_bus, csi->slv_addr, AE_MAXEXPO_7_0, PAG7936_EXPOSURE_L(exposure_us));
|
||||
ret |= omv_i2c_readb2(csi->i2c, csi->slv_addr, AE_MAXEXPO_17_16, ®);
|
||||
ret |= omv_i2c_writeb2(csi->i2c, csi->slv_addr, AE_MAXEXPO_17_16, PAG7936_EXPOSURE_H(reg, exposure_us));
|
||||
ret |= omv_i2c_writeb2(csi->i2c, csi->slv_addr, AE_MAXEXPO_15_8, PAG7936_EXPOSURE_M(exposure_us));
|
||||
ret |= omv_i2c_writeb2(csi->i2c, csi->slv_addr, AE_MAXEXPO_7_0, PAG7936_EXPOSURE_L(exposure_us));
|
||||
}
|
||||
|
||||
ret |= omv_i2c_writeb2(&csi->i2c_bus, csi->slv_addr, SENSOR_UPDATE, SENSOR_UPDATE_FLAG);
|
||||
ret |= omv_i2c_writeb2(csi->i2c, csi->slv_addr, SENSOR_UPDATE, SENSOR_UPDATE_FLAG);
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int set_gainceiling(omv_csi_t *csi, omv_csi_gainceiling_t gainceiling) {
|
||||
uint8_t aec, reg;
|
||||
int ret = omv_i2c_readb2(&csi->i2c_bus, csi->slv_addr, AE_EXPO_MANUAL, &aec);
|
||||
ret |= omv_i2c_writeb2(&csi->i2c_bus, csi->slv_addr, AE_EXPO_MANUAL, aec | AE_EXPO_MANUAL_AE_MANUAL_EN);
|
||||
int ret = omv_i2c_readb2(csi->i2c, csi->slv_addr, AE_EXPO_MANUAL, &aec);
|
||||
ret |= omv_i2c_writeb2(csi->i2c, csi->slv_addr, AE_EXPO_MANUAL, aec | AE_EXPO_MANUAL_AE_MANUAL_EN);
|
||||
|
||||
int new_gainceiling = PAG7936_GAIN_SCALE << (gainceiling + 1);
|
||||
if (new_gainceiling > PAG7936_MAX_AGAIN_REG) {
|
||||
return -1;
|
||||
}
|
||||
|
||||
ret |= omv_i2c_readb2(&csi->i2c_bus, csi->slv_addr, AE_MAXGAIN_10_8, ®);
|
||||
ret |= omv_i2c_writeb2(&csi->i2c_bus, csi->slv_addr, AE_MAXGAIN_10_8, PAG7936_GAIN_H(reg, new_gainceiling));
|
||||
ret |= omv_i2c_writeb2(&csi->i2c_bus, csi->slv_addr, AE_MAXGAIN_7_0, PAG7936_GAIN_L(new_gainceiling));
|
||||
ret |= omv_i2c_readb2(csi->i2c, csi->slv_addr, AE_MAXGAIN_10_8, ®);
|
||||
ret |= omv_i2c_writeb2(csi->i2c, csi->slv_addr, AE_MAXGAIN_10_8, PAG7936_GAIN_H(reg, new_gainceiling));
|
||||
ret |= omv_i2c_writeb2(csi->i2c, csi->slv_addr, AE_MAXGAIN_7_0, PAG7936_GAIN_L(new_gainceiling));
|
||||
|
||||
// Force AEC/AGC to reload the new values.
|
||||
ret |= omv_i2c_writeb2(&csi->i2c_bus, csi->slv_addr, SENSOR_UPDATE, SENSOR_UPDATE_FLAG);
|
||||
ret |= omv_i2c_writeb2(&csi->i2c_bus, csi->slv_addr, AE_EXPO_MANUAL, aec);
|
||||
ret |= omv_i2c_writeb2(&csi->i2c_bus, csi->slv_addr, SENSOR_UPDATE, SENSOR_UPDATE_FLAG);
|
||||
ret |= omv_i2c_writeb2(csi->i2c, csi->slv_addr, SENSOR_UPDATE, SENSOR_UPDATE_FLAG);
|
||||
ret |= omv_i2c_writeb2(csi->i2c, csi->slv_addr, AE_EXPO_MANUAL, aec);
|
||||
ret |= omv_i2c_writeb2(csi->i2c, csi->slv_addr, SENSOR_UPDATE, SENSOR_UPDATE_FLAG);
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int set_colorbar(omv_csi_t *csi, int enable) {
|
||||
uint8_t reg;
|
||||
int ret = omv_i2c_readb2(&csi->i2c_bus, csi->slv_addr, ISP_EN_H, ®);
|
||||
ret |= omv_i2c_writeb2(&csi->i2c_bus, csi->slv_addr, ISP_EN_H,
|
||||
int ret = omv_i2c_readb2(csi->i2c, csi->slv_addr, ISP_EN_H, ®);
|
||||
ret |= omv_i2c_writeb2(csi->i2c, csi->slv_addr, ISP_EN_H,
|
||||
(reg & ~ISP_EN_H_EN) | (enable ? ISP_EN_H_EN : 0));
|
||||
ret |= omv_i2c_readb2(&csi->i2c_bus, csi->slv_addr, ISP_TEST_MODE, ®);
|
||||
ret |= omv_i2c_writeb2(&csi->i2c_bus, csi->slv_addr, ISP_TEST_MODE,
|
||||
ret |= omv_i2c_readb2(csi->i2c, csi->slv_addr, ISP_TEST_MODE, ®);
|
||||
ret |= omv_i2c_writeb2(csi->i2c, csi->slv_addr, ISP_TEST_MODE,
|
||||
(reg & ~ISP_TEST_MODE_RAMP) | (enable ? ISP_TEST_MODE_RAMP : 0));
|
||||
ret |= omv_i2c_writeb2(&csi->i2c_bus, csi->slv_addr, SENSOR_UPDATE, SENSOR_UPDATE_FLAG);
|
||||
ret |= omv_i2c_writeb2(csi->i2c, csi->slv_addr, SENSOR_UPDATE, SENSOR_UPDATE_FLAG);
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int set_auto_gain(omv_csi_t *csi, int enable, float gain_db, float gain_db_ceiling) {
|
||||
uint8_t reg;
|
||||
int ret = omv_i2c_readb2(&csi->i2c_bus, csi->slv_addr, AE_EXPO_MANUAL, ®);
|
||||
ret |= omv_i2c_writeb2(&csi->i2c_bus, csi->slv_addr, AE_EXPO_MANUAL, reg | AE_EXPO_MANUAL_AE_MANUAL_EN);
|
||||
int ret = omv_i2c_readb2(csi->i2c, csi->slv_addr, AE_EXPO_MANUAL, ®);
|
||||
ret |= omv_i2c_writeb2(csi->i2c, csi->slv_addr, AE_EXPO_MANUAL, reg | AE_EXPO_MANUAL_AE_MANUAL_EN);
|
||||
|
||||
if ((enable == 0) && (!isnanf(gain_db)) && (!isinff(gain_db))) {
|
||||
int gain = fast_roundf(expf((gain_db / 20.0f) * M_LN10) * PAG7936_GAIN_SCALE_F);
|
||||
gain = IM_CLAMP(gain, PAG7936_MIN_AGAIN_REG, PAG7936_MAX_AGAIN_REG);
|
||||
|
||||
ret |= omv_i2c_readb2(&csi->i2c_bus, csi->slv_addr, AE_GAIN_MANUAL_10_8, ®);
|
||||
ret |= omv_i2c_writeb2(&csi->i2c_bus, csi->slv_addr, AE_GAIN_MANUAL_10_8, PAG7936_GAIN_H(reg, gain));
|
||||
ret |= omv_i2c_writeb2(&csi->i2c_bus, csi->slv_addr, AE_GAIN_MANUAL_7_0, PAG7936_GAIN_L(gain));
|
||||
ret |= omv_i2c_readb2(csi->i2c, csi->slv_addr, AE_GAIN_MANUAL_10_8, ®);
|
||||
ret |= omv_i2c_writeb2(csi->i2c, csi->slv_addr, AE_GAIN_MANUAL_10_8, PAG7936_GAIN_H(reg, gain));
|
||||
ret |= omv_i2c_writeb2(csi->i2c, csi->slv_addr, AE_GAIN_MANUAL_7_0, PAG7936_GAIN_L(gain));
|
||||
} else if ((enable != 0) && (!isnanf(gain_db_ceiling)) && (!isinff(gain_db_ceiling))) {
|
||||
int gain_ceiling = fast_roundf(expf((gain_db_ceiling / 20.0f) * M_LN10) * PAG7936_GAIN_SCALE_F);
|
||||
gain_ceiling = IM_CLAMP(gain_ceiling, PAG7936_MIN_AGAIN_REG, PAG7936_MAX_AGAIN_REG);
|
||||
|
||||
ret |= omv_i2c_readb2(&csi->i2c_bus, csi->slv_addr, AE_MAXGAIN_10_8, ®);
|
||||
ret |= omv_i2c_writeb2(&csi->i2c_bus, csi->slv_addr, AE_MAXGAIN_10_8, PAG7936_GAIN_H(reg, gain_ceiling));
|
||||
ret |= omv_i2c_writeb2(&csi->i2c_bus, csi->slv_addr, AE_MAXGAIN_7_0, PAG7936_GAIN_L(gain_ceiling));
|
||||
ret |= omv_i2c_readb2(csi->i2c, csi->slv_addr, AE_MAXGAIN_10_8, ®);
|
||||
ret |= omv_i2c_writeb2(csi->i2c, csi->slv_addr, AE_MAXGAIN_10_8, PAG7936_GAIN_H(reg, gain_ceiling));
|
||||
ret |= omv_i2c_writeb2(csi->i2c, csi->slv_addr, AE_MAXGAIN_7_0, PAG7936_GAIN_L(gain_ceiling));
|
||||
}
|
||||
|
||||
// Force AEC/AGC to reload the new values.
|
||||
ret |= omv_i2c_writeb2(&csi->i2c_bus, csi->slv_addr, SENSOR_UPDATE, SENSOR_UPDATE_FLAG);
|
||||
ret |= omv_i2c_readb2(&csi->i2c_bus, csi->slv_addr, AE_EXPO_MANUAL, ®);
|
||||
ret |= omv_i2c_writeb2(&csi->i2c_bus, csi->slv_addr, AE_EXPO_MANUAL,
|
||||
ret |= omv_i2c_writeb2(csi->i2c, csi->slv_addr, SENSOR_UPDATE, SENSOR_UPDATE_FLAG);
|
||||
ret |= omv_i2c_readb2(csi->i2c, csi->slv_addr, AE_EXPO_MANUAL, ®);
|
||||
ret |= omv_i2c_writeb2(csi->i2c, csi->slv_addr, AE_EXPO_MANUAL,
|
||||
(reg & ~AE_EXPO_MANUAL_AE_MANUAL_EN) | (enable ? 0 : AE_EXPO_MANUAL_AE_MANUAL_EN));
|
||||
ret |= omv_i2c_writeb2(&csi->i2c_bus, csi->slv_addr, SENSOR_UPDATE, SENSOR_UPDATE_FLAG);
|
||||
ret |= omv_i2c_writeb2(csi->i2c, csi->slv_addr, SENSOR_UPDATE, SENSOR_UPDATE_FLAG);
|
||||
return ret;
|
||||
}
|
||||
|
||||
@ -599,8 +599,8 @@ static int get_gain_db(omv_csi_t *csi, float *gain_db) {
|
||||
uint8_t gainh, gainl;
|
||||
int ret = 0;
|
||||
|
||||
ret |= omv_i2c_readb2(&csi->i2c_bus, csi->slv_addr, TOTAL_GAIN_10_8, &gainh);
|
||||
ret |= omv_i2c_readb2(&csi->i2c_bus, csi->slv_addr, TOTAL_GAIN_7_0, &gainl);
|
||||
ret |= omv_i2c_readb2(csi->i2c, csi->slv_addr, TOTAL_GAIN_10_8, &gainh);
|
||||
ret |= omv_i2c_readb2(csi->i2c, csi->slv_addr, TOTAL_GAIN_7_0, &gainl);
|
||||
|
||||
*gain_db = 20.0f * log10f(PAG7936_GAIN(gainh, gainl) / PAG7936_GAIN_SCALE_F);
|
||||
|
||||
@ -609,34 +609,34 @@ static int get_gain_db(omv_csi_t *csi, float *gain_db) {
|
||||
|
||||
static int set_auto_exposure(omv_csi_t *csi, int enable, int exposure_us) {
|
||||
uint8_t reg, frame_time_20_16, frame_time_15_8, frame_time_7_0;
|
||||
int ret = omv_i2c_readb2(&csi->i2c_bus, csi->slv_addr, AE_EXPO_MANUAL, ®);
|
||||
ret |= omv_i2c_writeb2(&csi->i2c_bus, csi->slv_addr, AE_EXPO_MANUAL, reg | AE_EXPO_MANUAL_AE_MANUAL_EN);
|
||||
int ret = omv_i2c_readb2(csi->i2c, csi->slv_addr, AE_EXPO_MANUAL, ®);
|
||||
ret |= omv_i2c_writeb2(csi->i2c, csi->slv_addr, AE_EXPO_MANUAL, reg | AE_EXPO_MANUAL_AE_MANUAL_EN);
|
||||
|
||||
ret |= omv_i2c_readb2(&csi->i2c_bus, csi->slv_addr, FRAME_TIME_20_16, &frame_time_20_16);
|
||||
ret |= omv_i2c_readb2(&csi->i2c_bus, csi->slv_addr, FRAME_TIME_15_8, &frame_time_15_8);
|
||||
ret |= omv_i2c_readb2(&csi->i2c_bus, csi->slv_addr, FRAME_TIME_7_0, &frame_time_7_0);
|
||||
ret |= omv_i2c_readb2(csi->i2c, csi->slv_addr, FRAME_TIME_20_16, &frame_time_20_16);
|
||||
ret |= omv_i2c_readb2(csi->i2c, csi->slv_addr, FRAME_TIME_15_8, &frame_time_15_8);
|
||||
ret |= omv_i2c_readb2(csi->i2c, csi->slv_addr, FRAME_TIME_7_0, &frame_time_7_0);
|
||||
|
||||
int32_t frame_time_us = PAG7936_FRAME_TIME(frame_time_20_16, frame_time_15_8, frame_time_7_0);
|
||||
exposure_us = IM_CLAMP(exposure_us, PAG7936_EXP_MIN, (frame_time_us - PAG7936_EXP_OFFSET)) / PAG7936_EXP_DIV;
|
||||
|
||||
if ((enable == 0) && (exposure_us >= 0)) {
|
||||
ret |= omv_i2c_readb2(&csi->i2c_bus, csi->slv_addr, AE_EXPO_MANUAL_17_16, ®);
|
||||
ret |= omv_i2c_writeb2(&csi->i2c_bus, csi->slv_addr, AE_EXPO_MANUAL_17_16, PAG7936_EXPOSURE_H(reg, exposure_us));
|
||||
ret |= omv_i2c_writeb2(&csi->i2c_bus, csi->slv_addr, AE_EXPO_MANUAL_15_8, PAG7936_EXPOSURE_M(exposure_us));
|
||||
ret |= omv_i2c_writeb2(&csi->i2c_bus, csi->slv_addr, AE_EXPO_MANUAL_7_0, PAG7936_EXPOSURE_L(exposure_us));
|
||||
ret |= omv_i2c_readb2(csi->i2c, csi->slv_addr, AE_EXPO_MANUAL_17_16, ®);
|
||||
ret |= omv_i2c_writeb2(csi->i2c, csi->slv_addr, AE_EXPO_MANUAL_17_16, PAG7936_EXPOSURE_H(reg, exposure_us));
|
||||
ret |= omv_i2c_writeb2(csi->i2c, csi->slv_addr, AE_EXPO_MANUAL_15_8, PAG7936_EXPOSURE_M(exposure_us));
|
||||
ret |= omv_i2c_writeb2(csi->i2c, csi->slv_addr, AE_EXPO_MANUAL_7_0, PAG7936_EXPOSURE_L(exposure_us));
|
||||
} else if ((enable != 0) && (exposure_us >= 0)) {
|
||||
ret |= omv_i2c_readb2(&csi->i2c_bus, csi->slv_addr, AE_MAXEXPO_17_16, ®);
|
||||
ret |= omv_i2c_writeb2(&csi->i2c_bus, csi->slv_addr, AE_MAXEXPO_17_16, PAG7936_EXPOSURE_H(reg, exposure_us));
|
||||
ret |= omv_i2c_writeb2(&csi->i2c_bus, csi->slv_addr, AE_MAXEXPO_15_8, PAG7936_EXPOSURE_M(exposure_us));
|
||||
ret |= omv_i2c_writeb2(&csi->i2c_bus, csi->slv_addr, AE_MAXEXPO_7_0, PAG7936_EXPOSURE_L(exposure_us));
|
||||
ret |= omv_i2c_readb2(csi->i2c, csi->slv_addr, AE_MAXEXPO_17_16, ®);
|
||||
ret |= omv_i2c_writeb2(csi->i2c, csi->slv_addr, AE_MAXEXPO_17_16, PAG7936_EXPOSURE_H(reg, exposure_us));
|
||||
ret |= omv_i2c_writeb2(csi->i2c, csi->slv_addr, AE_MAXEXPO_15_8, PAG7936_EXPOSURE_M(exposure_us));
|
||||
ret |= omv_i2c_writeb2(csi->i2c, csi->slv_addr, AE_MAXEXPO_7_0, PAG7936_EXPOSURE_L(exposure_us));
|
||||
}
|
||||
|
||||
// Force AEC/AGC to reload the new values.
|
||||
ret |= omv_i2c_writeb2(&csi->i2c_bus, csi->slv_addr, SENSOR_UPDATE, SENSOR_UPDATE_FLAG);
|
||||
ret |= omv_i2c_readb2(&csi->i2c_bus, csi->slv_addr, AE_EXPO_MANUAL, ®);
|
||||
ret |= omv_i2c_writeb2(&csi->i2c_bus, csi->slv_addr, AE_EXPO_MANUAL,
|
||||
ret |= omv_i2c_writeb2(csi->i2c, csi->slv_addr, SENSOR_UPDATE, SENSOR_UPDATE_FLAG);
|
||||
ret |= omv_i2c_readb2(csi->i2c, csi->slv_addr, AE_EXPO_MANUAL, ®);
|
||||
ret |= omv_i2c_writeb2(csi->i2c, csi->slv_addr, AE_EXPO_MANUAL,
|
||||
(reg & ~AE_EXPO_MANUAL_AE_MANUAL_EN) | (enable ? 0 : AE_EXPO_MANUAL_AE_MANUAL_EN));
|
||||
ret |= omv_i2c_writeb2(&csi->i2c_bus, csi->slv_addr, SENSOR_UPDATE, SENSOR_UPDATE_FLAG);
|
||||
ret |= omv_i2c_writeb2(csi->i2c, csi->slv_addr, SENSOR_UPDATE, SENSOR_UPDATE_FLAG);
|
||||
return ret;
|
||||
}
|
||||
|
||||
@ -644,9 +644,9 @@ static int get_exposure_us(omv_csi_t *csi, int *exposure_us) {
|
||||
uint8_t exposure_us_17_16, exposure_us_15_8, exposure_us_7_0;
|
||||
int ret = 0;
|
||||
|
||||
ret |= omv_i2c_readb2(&csi->i2c_bus, csi->slv_addr, AE_EXP_LINE_NUM_17_16, &exposure_us_17_16);
|
||||
ret |= omv_i2c_readb2(&csi->i2c_bus, csi->slv_addr, AE_EXP_LINE_NUM_15_8, &exposure_us_15_8);
|
||||
ret |= omv_i2c_readb2(&csi->i2c_bus, csi->slv_addr, AE_EXP_LINE_NUM_7_0, &exposure_us_7_0);
|
||||
ret |= omv_i2c_readb2(csi->i2c, csi->slv_addr, AE_EXP_LINE_NUM_17_16, &exposure_us_17_16);
|
||||
ret |= omv_i2c_readb2(csi->i2c, csi->slv_addr, AE_EXP_LINE_NUM_15_8, &exposure_us_15_8);
|
||||
ret |= omv_i2c_readb2(csi->i2c, csi->slv_addr, AE_EXP_LINE_NUM_7_0, &exposure_us_7_0);
|
||||
|
||||
*exposure_us = PAG7936_EXPOSURE(exposure_us_17_16, exposure_us_15_8, exposure_us_7_0);
|
||||
|
||||
@ -655,17 +655,17 @@ static int get_exposure_us(omv_csi_t *csi, int *exposure_us) {
|
||||
|
||||
static int set_hmirror(omv_csi_t *csi, int enable) {
|
||||
uint8_t reg;
|
||||
int ret = omv_i2c_readb2(&csi->i2c_bus, csi->slv_addr, TG_FLIP, ®);
|
||||
ret |= omv_i2c_writeb2(&csi->i2c_bus, csi->slv_addr, TG_FLIP, TG_FLIP_SET_HFLIP(reg, enable));
|
||||
ret |= omv_i2c_writeb2(&csi->i2c_bus, csi->slv_addr, SENSOR_UPDATE, SENSOR_UPDATE_FLAG);
|
||||
int ret = omv_i2c_readb2(csi->i2c, csi->slv_addr, TG_FLIP, ®);
|
||||
ret |= omv_i2c_writeb2(csi->i2c, csi->slv_addr, TG_FLIP, TG_FLIP_SET_HFLIP(reg, enable));
|
||||
ret |= omv_i2c_writeb2(csi->i2c, csi->slv_addr, SENSOR_UPDATE, SENSOR_UPDATE_FLAG);
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int set_vflip(omv_csi_t *csi, int enable) {
|
||||
uint8_t reg;
|
||||
int ret = omv_i2c_readb2(&csi->i2c_bus, csi->slv_addr, TG_FLIP, ®);
|
||||
ret |= omv_i2c_writeb2(&csi->i2c_bus, csi->slv_addr, TG_FLIP, TG_FLIP_SET_VFLIP(reg, enable));
|
||||
ret |= omv_i2c_writeb2(&csi->i2c_bus, csi->slv_addr, SENSOR_UPDATE, SENSOR_UPDATE_FLAG);
|
||||
int ret = omv_i2c_readb2(csi->i2c, csi->slv_addr, TG_FLIP, ®);
|
||||
ret |= omv_i2c_writeb2(csi->i2c, csi->slv_addr, TG_FLIP, TG_FLIP_SET_VFLIP(reg, enable));
|
||||
ret |= omv_i2c_writeb2(csi->i2c, csi->slv_addr, SENSOR_UPDATE, SENSOR_UPDATE_FLAG);
|
||||
return ret;
|
||||
}
|
||||
|
||||
@ -678,8 +678,8 @@ static int ioctl(omv_csi_t *csi, int request, va_list ap) {
|
||||
case OMV_CSI_IOCTL_GET_RGB_STATS: {
|
||||
uint32_t rgb_stats[4];
|
||||
uint8_t buf[] = {(RGB_STAT_B_VS >> 8), RGB_STAT_B_VS & 0xFF };
|
||||
ret |= omv_i2c_write_bytes(&csi->i2c_bus, csi->slv_addr, buf, 2, OMV_I2C_XFER_NO_STOP);
|
||||
ret |= omv_i2c_read_bytes(&csi->i2c_bus, csi->slv_addr, (uint8_t *) rgb_stats, sizeof(rgb_stats), 0);
|
||||
ret |= omv_i2c_write_bytes(csi->i2c, csi->slv_addr, buf, 2, OMV_I2C_XFER_NO_STOP);
|
||||
ret |= omv_i2c_read_bytes(csi->i2c, csi->slv_addr, (uint8_t *) rgb_stats, sizeof(rgb_stats), 0);
|
||||
|
||||
*va_arg(ap, uint32_t *) = rgb_stats[2];
|
||||
*va_arg(ap, uint32_t *) = rgb_stats[1];
|
||||
|
||||
@ -1149,20 +1149,20 @@ static int reset(omv_csi_t *csi) {
|
||||
aec_exposure = PS5520_DEF_EXP;
|
||||
aec_exposure_ceiling = PS5520_DEF_EXP_CEILING;
|
||||
|
||||
ret |= omv_i2c_readb(&csi->i2c_bus, csi->slv_addr, CMD_LPF_H, &exposure_line_h);
|
||||
ret |= omv_i2c_readb(&csi->i2c_bus, csi->slv_addr, CMD_LPF_L, &exposure_line_l);
|
||||
ret |= omv_i2c_readb(csi->i2c, csi->slv_addr, CMD_LPF_H, &exposure_line_h);
|
||||
ret |= omv_i2c_readb(csi->i2c, csi->slv_addr, CMD_LPF_L, &exposure_line_l);
|
||||
lpf = (exposure_line_h << 8) + exposure_line_l; // Cmd_Lpf
|
||||
|
||||
ret |= omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, REG_BANK, 0x01);
|
||||
ret |= omv_i2c_writeb(csi->i2c, csi->slv_addr, REG_BANK, 0x01);
|
||||
|
||||
// Set default gain
|
||||
ret |= omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, CMD_GAIN_IDX, agc_gain);
|
||||
ret |= omv_i2c_writeb(csi->i2c, csi->slv_addr, CMD_GAIN_IDX, agc_gain);
|
||||
|
||||
// Set default exposure
|
||||
ret |= omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, CMD_OFFNY1_H, (lpf - 1 - aec_exposure) >> 8);
|
||||
ret |= omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, CMD_OFFNY1_L, (lpf - 1 - aec_exposure) & 0xFF);
|
||||
ret |= omv_i2c_writeb(csi->i2c, csi->slv_addr, CMD_OFFNY1_H, (lpf - 1 - aec_exposure) >> 8);
|
||||
ret |= omv_i2c_writeb(csi->i2c, csi->slv_addr, CMD_OFFNY1_L, (lpf - 1 - aec_exposure) & 0xFF);
|
||||
|
||||
ret |= omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, SENSOR_UPDATE, 0x01);
|
||||
ret |= omv_i2c_writeb(csi->i2c, csi->slv_addr, SENSOR_UPDATE, 0x01);
|
||||
|
||||
return ret;
|
||||
}
|
||||
@ -1173,14 +1173,14 @@ static int sleep(omv_csi_t *csi, int enable) {
|
||||
|
||||
static int read_reg(omv_csi_t *csi, uint16_t reg) {
|
||||
uint8_t reg_data;
|
||||
if (omv_i2c_readb(&csi->i2c_bus, csi->slv_addr, reg, ®_data) != 0) {
|
||||
if (omv_i2c_readb(csi->i2c, csi->slv_addr, reg, ®_data) != 0) {
|
||||
return -1;
|
||||
}
|
||||
return reg_data;
|
||||
}
|
||||
|
||||
static int write_reg(omv_csi_t *csi, uint16_t reg, uint16_t reg_data) {
|
||||
return omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, reg, reg_data);
|
||||
return omv_i2c_writeb(csi->i2c, csi->slv_addr, reg, reg_data);
|
||||
}
|
||||
|
||||
static int write_registers(omv_csi_t *csi, const uint8_t(*regs)[2]) {
|
||||
@ -1303,23 +1303,23 @@ static int set_framerate(omv_csi_t *csi, int framerate) {
|
||||
|
||||
exposure_line = IM_CLAMP(exposure_line, PS5520_MIN_INT, (lpf - 2));
|
||||
|
||||
ret |= omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, REG_BANK, 0x01);
|
||||
ret |= omv_i2c_writeb(csi->i2c, csi->slv_addr, REG_BANK, 0x01);
|
||||
|
||||
ret |= omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, CMD_LPF_H, lpf >> 8);
|
||||
ret |= omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, CMD_LPF_L, lpf & 0xFF);
|
||||
ret |= omv_i2c_writeb(csi->i2c, csi->slv_addr, CMD_LPF_H, lpf >> 8);
|
||||
ret |= omv_i2c_writeb(csi->i2c, csi->slv_addr, CMD_LPF_L, lpf & 0xFF);
|
||||
|
||||
ret |= omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, CMD_OFFNY1_H, (lpf - exposure_line) >> 8);
|
||||
ret |= omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, CMD_OFFNY1_L, (lpf - exposure_line) & 0xFF);
|
||||
ret |= omv_i2c_writeb(csi->i2c, csi->slv_addr, CMD_OFFNY1_H, (lpf - exposure_line) >> 8);
|
||||
ret |= omv_i2c_writeb(csi->i2c, csi->slv_addr, CMD_OFFNY1_L, (lpf - exposure_line) & 0xFF);
|
||||
|
||||
ret |= omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, CMD_NP, np & 0xFF);
|
||||
ret |= omv_i2c_writeb(csi->i2c, csi->slv_addr, CMD_NP, np & 0xFF);
|
||||
|
||||
ret |= omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, SENSOR_UPDATE, 0x01);
|
||||
ret |= omv_i2c_writeb(csi->i2c, csi->slv_addr, SENSOR_UPDATE, 0x01);
|
||||
|
||||
if (flg_stall == 1) {
|
||||
ret |= omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, REG_BANK, 0x05);
|
||||
ret |= omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, 0x25, 0x01);
|
||||
ret |= omv_i2c_writeb(csi->i2c, csi->slv_addr, REG_BANK, 0x05);
|
||||
ret |= omv_i2c_writeb(csi->i2c, csi->slv_addr, 0x25, 0x01);
|
||||
mp_hal_delay_ms(35 * g_div); // delay over 1 frame time
|
||||
ret |= omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, 0x25, 0x00);
|
||||
ret |= omv_i2c_writeb(csi->i2c, csi->slv_addr, 0x25, 0x00);
|
||||
}
|
||||
|
||||
return ret;
|
||||
@ -1335,17 +1335,17 @@ static int set_colorbar(omv_csi_t *csi, int enable) {
|
||||
int ret = 0;
|
||||
uint8_t reg;
|
||||
|
||||
ret |= omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, REG_BANK, 0x00);
|
||||
ret |= omv_i2c_readb(&csi->i2c_bus, csi->slv_addr, CMD_OUTGEN, ®);
|
||||
ret |= omv_i2c_writeb(csi->i2c, csi->slv_addr, REG_BANK, 0x00);
|
||||
ret |= omv_i2c_readb(csi->i2c, csi->slv_addr, CMD_OUTGEN, ®);
|
||||
|
||||
reg = enable ? (reg | 0x60) : (reg & 0x8F);
|
||||
ret |= omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, CMD_OUTGEN, reg);
|
||||
ret |= omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, REG_BANK, 0x01);
|
||||
ret |= omv_i2c_readb(&csi->i2c_bus, csi->slv_addr, R_ISP_TESTMODE, ®);
|
||||
ret |= omv_i2c_writeb(csi->i2c, csi->slv_addr, CMD_OUTGEN, reg);
|
||||
ret |= omv_i2c_writeb(csi->i2c, csi->slv_addr, REG_BANK, 0x01);
|
||||
ret |= omv_i2c_readb(csi->i2c, csi->slv_addr, R_ISP_TESTMODE, ®);
|
||||
|
||||
reg = enable ? (reg | 0x06) : (reg & 0xE0);
|
||||
ret |= omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, R_ISP_TESTMODE, reg);
|
||||
ret |= omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, SENSOR_UPDATE, 0x01);
|
||||
ret |= omv_i2c_writeb(csi->i2c, csi->slv_addr, R_ISP_TESTMODE, reg);
|
||||
ret |= omv_i2c_writeb(csi->i2c, csi->slv_addr, SENSOR_UPDATE, 0x01);
|
||||
|
||||
return ret;
|
||||
}
|
||||
@ -1365,9 +1365,9 @@ static int set_auto_gain(omv_csi_t *csi, int enable, float gain_db, float gain_d
|
||||
|
||||
agc_gain = ((idx - 1) << 4) + ((gain >> (idx - 1)) & 0x0F);
|
||||
|
||||
ret |= omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, REG_BANK, 0x01);
|
||||
ret |= omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, CMD_GAIN_IDX, agc_gain);
|
||||
ret |= omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, SENSOR_UPDATE, 0x01);
|
||||
ret |= omv_i2c_writeb(csi->i2c, csi->slv_addr, REG_BANK, 0x01);
|
||||
ret |= omv_i2c_writeb(csi->i2c, csi->slv_addr, CMD_GAIN_IDX, agc_gain);
|
||||
ret |= omv_i2c_writeb(csi->i2c, csi->slv_addr, SENSOR_UPDATE, 0x01);
|
||||
} else if ((enable != 0) && (!isnanf(gain_db_ceiling)) && (!isinff(gain_db_ceiling))) {
|
||||
int gain = fast_roundf(expf((gain_db_ceiling / 20.0f) * M_LN10) * PS5520_GAIN_SCALE_F);
|
||||
gain = IM_CLAMP(gain, PS5520_MIN_AGAIN_REG, PS5520_MAX_AGAIN_REG);
|
||||
@ -1383,9 +1383,9 @@ static int set_auto_gain(omv_csi_t *csi, int enable, float gain_db, float gain_d
|
||||
|
||||
static int get_gain_db(omv_csi_t *csi, float *gain_db) {
|
||||
uint8_t gain;
|
||||
int ret = omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, REG_BANK, 0x01);
|
||||
int ret = omv_i2c_writeb(csi->i2c, csi->slv_addr, REG_BANK, 0x01);
|
||||
|
||||
ret |= omv_i2c_readb(&csi->i2c_bus, csi->slv_addr, CMD_GAIN_IDX, &gain);
|
||||
ret |= omv_i2c_readb(csi->i2c, csi->slv_addr, CMD_GAIN_IDX, &gain);
|
||||
|
||||
*gain_db = 20.0f * log10f(PS5520_GAIN((int) gain) / PS5520_GAIN_SCALE_F);
|
||||
|
||||
@ -1401,19 +1401,19 @@ static int set_auto_exposure(omv_csi_t *csi, int enable, int exposure_us) {
|
||||
enable_aec = enable;
|
||||
|
||||
if ((enable == 0) && (exposure_us >= 0)) {
|
||||
ret |= omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, REG_BANK, 0x01);
|
||||
ret |= omv_i2c_writeb(csi->i2c, csi->slv_addr, REG_BANK, 0x01);
|
||||
|
||||
ret |= omv_i2c_readb(&csi->i2c_bus, csi->slv_addr, CMD_LPF_H, &exposure_line_h);
|
||||
ret |= omv_i2c_readb(&csi->i2c_bus, csi->slv_addr, CMD_LPF_L, &exposure_line_l);
|
||||
ret |= omv_i2c_readb(csi->i2c, csi->slv_addr, CMD_LPF_H, &exposure_line_h);
|
||||
ret |= omv_i2c_readb(csi->i2c, csi->slv_addr, CMD_LPF_L, &exposure_line_l);
|
||||
lpf = (exposure_line_h << 8) + exposure_line_l; // Cmd_Lpf
|
||||
|
||||
int32_t exposure_line = ConvertT2L(exposure_us);
|
||||
aec_exposure = IM_CLAMP(exposure_line, PS5520_MIN_INT, (lpf - 2));
|
||||
|
||||
ret |= omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, CMD_OFFNY1_H, (lpf - aec_exposure) >> 8);
|
||||
ret |= omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, CMD_OFFNY1_L, (lpf - aec_exposure) & 0xFF);
|
||||
ret |= omv_i2c_writeb(csi->i2c, csi->slv_addr, CMD_OFFNY1_H, (lpf - aec_exposure) >> 8);
|
||||
ret |= omv_i2c_writeb(csi->i2c, csi->slv_addr, CMD_OFFNY1_L, (lpf - aec_exposure) & 0xFF);
|
||||
|
||||
ret |= omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, SENSOR_UPDATE, 0x01);
|
||||
ret |= omv_i2c_writeb(csi->i2c, csi->slv_addr, SENSOR_UPDATE, 0x01);
|
||||
} else if ((enable != 0) && (exposure_us >= 0)) {
|
||||
aec_exposure_ceiling = ConvertT2LineBase(exposure_us);
|
||||
aec_exposure_ceiling = IM_CLAMP(aec_exposure_ceiling, PS5520_MIN_INT, PS5520_MAX_INT);
|
||||
@ -1428,14 +1428,14 @@ static int get_exposure_us(omv_csi_t *csi, int *exposure_us) {
|
||||
uint8_t exposure_line_h;
|
||||
uint8_t exposure_line_l;
|
||||
|
||||
ret |= omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, REG_BANK, 0x01);
|
||||
ret |= omv_i2c_writeb(csi->i2c, csi->slv_addr, REG_BANK, 0x01);
|
||||
|
||||
ret |= omv_i2c_readb(&csi->i2c_bus, csi->slv_addr, CMD_LPF_H, &exposure_line_h);
|
||||
ret |= omv_i2c_readb(&csi->i2c_bus, csi->slv_addr, CMD_LPF_L, &exposure_line_l);
|
||||
ret |= omv_i2c_readb(csi->i2c, csi->slv_addr, CMD_LPF_H, &exposure_line_h);
|
||||
ret |= omv_i2c_readb(csi->i2c, csi->slv_addr, CMD_LPF_L, &exposure_line_l);
|
||||
lpf = (exposure_line_h << 8) + exposure_line_l; // Cmd_Lpf
|
||||
|
||||
ret |= omv_i2c_readb(&csi->i2c_bus, csi->slv_addr, CMD_OFFNY1_H, &exposure_line_h);
|
||||
ret |= omv_i2c_readb(&csi->i2c_bus, csi->slv_addr, CMD_OFFNY1_L, &exposure_line_l);
|
||||
ret |= omv_i2c_readb(csi->i2c, csi->slv_addr, CMD_OFFNY1_H, &exposure_line_h);
|
||||
ret |= omv_i2c_readb(csi->i2c, csi->slv_addr, CMD_OFFNY1_L, &exposure_line_l);
|
||||
|
||||
int16_t exposure_line = lpf - ((exposure_line_h << 8) + exposure_line_l);
|
||||
*exposure_us = ConvertL2T(exposure_line);
|
||||
@ -1447,16 +1447,16 @@ static int set_hmirror(omv_csi_t *csi, int enable) {
|
||||
uint8_t reg1, reg2;
|
||||
uint16_t hsize;
|
||||
|
||||
int ret = omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, REG_BANK, 0x01);
|
||||
ret |= omv_i2c_readb(&csi->i2c_bus, csi->slv_addr, CMD_HFLIP, ®1);
|
||||
ret |= omv_i2c_readb(&csi->i2c_bus, csi->slv_addr, CMD_HSIZE_E1, ®2);
|
||||
int ret = omv_i2c_writeb(csi->i2c, csi->slv_addr, REG_BANK, 0x01);
|
||||
ret |= omv_i2c_readb(csi->i2c, csi->slv_addr, CMD_HFLIP, ®1);
|
||||
ret |= omv_i2c_readb(csi->i2c, csi->slv_addr, CMD_HSIZE_E1, ®2);
|
||||
|
||||
hsize = ((reg1 & 0x7F) << 8) + reg2 - (reg1 >> 7) + (enable?0x7FFF:0);
|
||||
reg1 = hsize >> 8;
|
||||
reg2 = hsize & 0xFF;
|
||||
ret |= omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, CMD_HFLIP, reg1);
|
||||
ret |= omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, CMD_HSIZE_E1, reg2);
|
||||
ret |= omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, SENSOR_UPDATE, 0x01);
|
||||
ret |= omv_i2c_writeb(csi->i2c, csi->slv_addr, CMD_HFLIP, reg1);
|
||||
ret |= omv_i2c_writeb(csi->i2c, csi->slv_addr, CMD_HSIZE_E1, reg2);
|
||||
ret |= omv_i2c_writeb(csi->i2c, csi->slv_addr, SENSOR_UPDATE, 0x01);
|
||||
|
||||
return ret;
|
||||
}
|
||||
@ -1464,11 +1464,11 @@ static int set_hmirror(omv_csi_t *csi, int enable) {
|
||||
static int set_vflip(omv_csi_t *csi, int enable) {
|
||||
uint8_t reg1;
|
||||
|
||||
int ret = omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, REG_BANK, 0x01);
|
||||
ret |= omv_i2c_readb(&csi->i2c_bus, csi->slv_addr, CMD_VFLIP, ®1);
|
||||
int ret = omv_i2c_writeb(csi->i2c, csi->slv_addr, REG_BANK, 0x01);
|
||||
ret |= omv_i2c_readb(csi->i2c, csi->slv_addr, CMD_VFLIP, ®1);
|
||||
|
||||
ret |= omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, CMD_VFLIP, (reg1 & 0x7F) | ((enable & 0x01) << 7));
|
||||
ret |= omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, SENSOR_UPDATE, 0x01);
|
||||
ret |= omv_i2c_writeb(csi->i2c, csi->slv_addr, CMD_VFLIP, (reg1 & 0x7F) | ((enable & 0x01) << 7));
|
||||
ret |= omv_i2c_writeb(csi->i2c, csi->slv_addr, SENSOR_UPDATE, 0x01);
|
||||
|
||||
return ret;
|
||||
}
|
||||
@ -1481,7 +1481,7 @@ static int update_agc_aec(omv_csi_t *csi, int luminance) {
|
||||
bool aec_exposure_in = ((diff > 0) && (aec_exposure < aec_exposure_ceiling)) ||
|
||||
((diff < 0) && (agc_gain <= PS5520_MIN_GAIN_IDX));
|
||||
|
||||
ret |= omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, REG_BANK, 0x01);
|
||||
ret |= omv_i2c_writeb(csi->i2c, csi->slv_addr, REG_BANK, 0x01);
|
||||
|
||||
if (enable_aec && aec_exposure_in) {
|
||||
// Long exposure first for better SNR
|
||||
@ -1515,35 +1515,35 @@ static int update_agc_aec(omv_csi_t *csi, int luminance) {
|
||||
g_div = gu16ExpTbl[cnt].div;
|
||||
flg_stall = 1;
|
||||
}
|
||||
ret |= omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, CMD_NP, np & 0xFF);
|
||||
ret |= omv_i2c_writeb(csi->i2c, csi->slv_addr, CMD_NP, np & 0xFF);
|
||||
|
||||
} else {
|
||||
lpf = VTS_5M_30 - 1;
|
||||
exposure_line = aec_exposure;
|
||||
exposure_line = IM_CLAMP(exposure_line, PS5520_MIN_INT, (lpf - 2));
|
||||
}
|
||||
ret |= omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, CMD_LPF_H, lpf >> 8);
|
||||
ret |= omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, CMD_LPF_L, lpf & 0xFF);
|
||||
ret |= omv_i2c_writeb(csi->i2c, csi->slv_addr, CMD_LPF_H, lpf >> 8);
|
||||
ret |= omv_i2c_writeb(csi->i2c, csi->slv_addr, CMD_LPF_L, lpf & 0xFF);
|
||||
|
||||
ret |= omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, CMD_OFFNY1_H, (lpf - exposure_line) >> 8);
|
||||
ret |= omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, CMD_OFFNY1_L, (lpf - exposure_line) & 0xFF);
|
||||
ret |= omv_i2c_writeb(csi->i2c, csi->slv_addr, CMD_OFFNY1_H, (lpf - exposure_line) >> 8);
|
||||
ret |= omv_i2c_writeb(csi->i2c, csi->slv_addr, CMD_OFFNY1_L, (lpf - exposure_line) & 0xFF);
|
||||
|
||||
ret |= omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, SENSOR_UPDATE, 0x01);
|
||||
ret |= omv_i2c_writeb(csi->i2c, csi->slv_addr, SENSOR_UPDATE, 0x01);
|
||||
|
||||
if (flg_stall == 1) {
|
||||
ret |= omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, REG_BANK, 0x05);
|
||||
ret |= omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, 0x25, 0x01);
|
||||
ret |= omv_i2c_writeb(csi->i2c, csi->slv_addr, REG_BANK, 0x05);
|
||||
ret |= omv_i2c_writeb(csi->i2c, csi->slv_addr, 0x25, 0x01);
|
||||
mp_hal_delay_ms(35 * g_div); // delay over 1 frame time
|
||||
ret |= omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, 0x25, 0x00);
|
||||
ret |= omv_i2c_writeb(csi->i2c, csi->slv_addr, 0x25, 0x00);
|
||||
}
|
||||
|
||||
} else if (enable_agc) {
|
||||
agc_gain += diff / PS5520_L_AGC_DIFF_DIV;
|
||||
agc_gain = IM_CLAMP(agc_gain, PS5520_MIN_GAIN_IDX, agc_gain_ceiling);
|
||||
|
||||
//ret |= omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, REG_BANK, 0x01);
|
||||
ret |= omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, CMD_GAIN_IDX, agc_gain);
|
||||
ret |= omv_i2c_writeb(&csi->i2c_bus, csi->slv_addr, SENSOR_UPDATE, 0x01);
|
||||
//ret |= omv_i2c_writeb(csi->i2c, csi->slv_addr, REG_BANK, 0x01);
|
||||
ret |= omv_i2c_writeb(csi->i2c, csi->slv_addr, CMD_GAIN_IDX, agc_gain);
|
||||
ret |= omv_i2c_writeb(csi->i2c, csi->slv_addr, SENSOR_UPDATE, 0x01);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
@ -80,10 +80,10 @@ void omv_csi_init0() {
|
||||
|
||||
// Re-init I2C to reset the bus state after soft reset, which
|
||||
// could have interrupted the bus in the middle of a transfer.
|
||||
if (csi.i2c_bus.initialized) {
|
||||
if (csi.i2c->initialized) {
|
||||
// Reinitialize the bus using the last used id and speed.
|
||||
// TODO: Causes Alif's I3C to lock up.
|
||||
//omv_i2c_init(&csi.i2c_bus, csi.i2c_bus.id, csi.i2c_bus.speed);
|
||||
//omv_i2c_init(csi.i2c, csi.i2c->id, csi.i2c->speed);
|
||||
}
|
||||
|
||||
csi.disable_delays = false;
|
||||
@ -416,6 +416,9 @@ int omv_csi_init() {
|
||||
// Set default framebuffer
|
||||
csi.fb = framebuffer_get(0);
|
||||
|
||||
// Set I2C bus
|
||||
csi.i2c = &csi_i2c;
|
||||
|
||||
// Set default snapshot function.
|
||||
csi.snapshot = omv_csi_snapshot;
|
||||
|
||||
|
||||
@ -59,9 +59,9 @@ void omv_csi_init0() {
|
||||
|
||||
// Re-init I2C to reset the bus state after soft reset, which
|
||||
// could have interrupted the bus in the middle of a transfer.
|
||||
if (csi.i2c_bus.initialized) {
|
||||
if (csi.i2c->initialized) {
|
||||
// Reinitialize the bus using the last used id and speed.
|
||||
omv_i2c_init(&csi.i2c_bus, csi.i2c_bus.id, csi.i2c_bus.speed);
|
||||
omv_i2c_init(csi.i2c, csi.i2c->id, csi.i2c->speed);
|
||||
}
|
||||
|
||||
csi.disable_delays = false;
|
||||
@ -551,6 +551,9 @@ int omv_csi_init() {
|
||||
// Set default framebuffer
|
||||
csi.fb = framebuffer_get(0);
|
||||
|
||||
// Set I2C bus
|
||||
csi.i2c = &csi_i2c;
|
||||
|
||||
// Set default snapshot function.
|
||||
// Some sensors need to call snapshot from init.
|
||||
csi.snapshot = omv_csi_snapshot;
|
||||
|
||||
@ -225,6 +225,9 @@ int omv_csi_init() {
|
||||
// Set default framebuffer
|
||||
csi.fb = framebuffer_get(0);
|
||||
|
||||
// Set I2C bus
|
||||
csi.i2c = &csi_i2c;
|
||||
|
||||
// Set default snapshot function.
|
||||
csi.snapshot = omv_csi_snapshot;
|
||||
|
||||
|
||||
@ -231,6 +231,9 @@ int omv_csi_init() {
|
||||
// Set default framebuffer
|
||||
csi.fb = framebuffer_get(0);
|
||||
|
||||
// Set I2C bus
|
||||
csi.i2c = &csi_i2c;
|
||||
|
||||
// Set default snapshot function.
|
||||
csi.snapshot = omv_csi_snapshot;
|
||||
|
||||
|
||||
@ -106,9 +106,9 @@ void omv_csi_init0() {
|
||||
|
||||
// Re-init i2c bus to reset the bus state after soft reset, which
|
||||
// could have interrupted the bus in the middle of a transfer.
|
||||
if (csi.i2c_bus.initialized) {
|
||||
if (csi.i2c->initialized) {
|
||||
// Reinitialize the bus using the last used id and speed.
|
||||
omv_i2c_init(&csi.i2c_bus, csi.i2c_bus.id, csi.i2c_bus.speed);
|
||||
omv_i2c_init(csi.i2c, csi.i2c->id, csi.i2c->speed);
|
||||
}
|
||||
}
|
||||
|
||||
@ -1105,6 +1105,9 @@ int omv_csi_init() {
|
||||
// Set default framebuffer
|
||||
csi.fb = framebuffer_get(0);
|
||||
|
||||
// Set I2C bus
|
||||
csi.i2c = &csi_i2c;
|
||||
|
||||
// Set default snapshot function.
|
||||
csi.snapshot = omv_csi_snapshot;
|
||||
|
||||
@ -1119,7 +1122,7 @@ int omv_csi_init() {
|
||||
if ((init_ret = omv_csi_probe_init(id, speed)) == 0) {
|
||||
break;
|
||||
}
|
||||
omv_i2c_deinit(&csi.i2c_bus);
|
||||
omv_i2c_deinit(csi.i2c);
|
||||
// Scan the next bus or fail if this is the last one.
|
||||
if ((i + 1) == n_buses) {
|
||||
return init_ret;
|
||||
|
||||
Loading…
Reference in New Issue
Block a user