diff --git a/src/drivers/pixart/src/pixspi.c b/src/drivers/pixart/src/pixspi.c index 3f23224b1..451858183 100644 --- a/src/drivers/pixart/src/pixspi.c +++ b/src/drivers/pixart/src/pixspi.c @@ -10,95 +10,107 @@ * Pixart SPI driver. */ #include "omv_boardconfig.h" -#ifdef ISC_SPI +#ifdef ISC_SPI_ID #include #include #include -#include STM32_HAL_H #include "common.h" #include "omv_gpio.h" +#include "omv_spi.h" #include "pixspi.h" -#define SPI_TIMEOUT (5000) // in ms +#define SPI_BUS_TIMEOUT (5000) // in ms +#ifdef PIXART_SPI_DEBUG +#define debug_printf(...) printf(__VA_ARGS__) +#else +#define debug_printf(...) +#endif -extern SPI_HandleTypeDef ISC_SPIHandle; +static omv_spi_t spi_bus; -static bool spi_send(uint8_t *data, uint16_t len) +static bool spi_send(uint8_t *txbuf, uint16_t len) { - HAL_StatusTypeDef status = HAL_OK; - omv_gpio_write(ISC_SPI_SSEL_PIN, 0); - // mp_uint_t atomic_state = MICROPY_BEGIN_ATOMIC_SECTION(); - status = HAL_SPI_Transmit( - &ISC_SPIHandle, data, len, SPI_TIMEOUT); - // MICROPY_END_ATOMIC_SECTION(atomic_state); - omv_gpio_write(ISC_SPI_SSEL_PIN, 1); + int ret = 0; - return (status == HAL_OK); + omv_spi_transfer_t spi_xfer = { + .txbuf = txbuf, + .rxbuf = NULL, + .size = len, + .timeout = SPI_BUS_TIMEOUT, + .flags = OMV_SPI_XFER_BLOCKING, + .callback = NULL, + .userdata = NULL, + }; + + omv_gpio_write(spi_bus.cs, 0); + ret = omv_spi_transfer_start(&spi_bus, &spi_xfer); + omv_gpio_write(spi_bus.cs, 1); + + return ret; } -static bool spi_send_recv(uint8_t *txData, uint8_t *rxData, uint16_t len) +static bool spi_send_recv(uint8_t *txbuf, uint8_t *rxbuf, uint16_t len) { - omv_gpio_write(ISC_SPI_SSEL_PIN, 0); - // mp_uint_t atomic_state = MICROPY_BEGIN_ATOMIC_SECTION(); - bool res = (HAL_SPI_Transmit(&ISC_SPIHandle, txData, 1, SPI_TIMEOUT) == HAL_OK); - res = (HAL_SPI_Receive(&ISC_SPIHandle, rxData, len, SPI_TIMEOUT) == HAL_OK); - // MICROPY_END_ATOMIC_SECTION(atomic_state); - omv_gpio_write(ISC_SPI_SSEL_PIN, 1); - return res; + int ret = 0; + + omv_spi_transfer_t spi_xfer = { + .timeout = SPI_BUS_TIMEOUT, + .flags = OMV_SPI_XFER_BLOCKING, + .callback = NULL, + .userdata = NULL, + }; + + omv_gpio_write(spi_bus.cs, 0); + + spi_xfer.size = 1; + spi_xfer.txbuf = txbuf; + spi_xfer.rxbuf = NULL; + ret |= omv_spi_transfer_start(&spi_bus, &spi_xfer); + + spi_xfer.size = len; + spi_xfer.txbuf = NULL; + spi_xfer.rxbuf = rxbuf; + ret |= omv_spi_transfer_start(&spi_bus, &spi_xfer); + + omv_gpio_write(spi_bus.cs, 1); + return ret; } bool pixspi_init() { // Init SPI - memset(&ISC_SPIHandle, 0, sizeof(ISC_SPIHandle)); - ISC_SPIHandle.Instance = ISC_SPI; - ISC_SPIHandle.Init.Mode = SPI_MODE_MASTER; - ISC_SPIHandle.Init.Direction = SPI_DIRECTION_2LINES; - ISC_SPIHandle.Init.DataSize = SPI_DATASIZE_8BIT; - ISC_SPIHandle.Init.CLKPolarity = SPI_POLARITY_HIGH; - ISC_SPIHandle.Init.CLKPhase = SPI_PHASE_2EDGE; - ISC_SPIHandle.Init.NSS = SPI_NSS_SOFT; - ISC_SPIHandle.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_32 ; - ISC_SPIHandle.Init.FirstBit = SPI_FIRSTBIT_MSB; - ISC_SPIHandle.Init.TIMode = SPI_TIMODE_DISABLED; - ISC_SPIHandle.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLED; - ISC_SPIHandle.Init.CRCPolynomial = 0; + omv_spi_config_t spi_config; + omv_spi_default_config(&spi_config, ISC_SPI_ID); - if (HAL_SPI_Init(&ISC_SPIHandle) != HAL_OK) { - // Initialization Error + spi_config.baudrate = 5000000; + spi_config.nss_enable = false; // Soft NSS + spi_config.clk_pol = OMV_SPI_CPOL_HIGH; + spi_config.clk_pha = OMV_SPI_CPHA_2EDGE; + + if (omv_spi_init(&spi_bus, &spi_config) != 0) { return false; } - - // Re-Init GPIO for SPI SS(CS) pin, software control. - omv_gpio_config(ISC_SPI_SSEL_PIN, OMV_GPIO_MODE_OUTPUT, OMV_GPIO_PULL_UP, OMV_GPIO_SPEED_LOW, -1); - - // Default high. - omv_gpio_write(ISC_SPI_SSEL_PIN, 1); return true; } void pixspi_release() { - omv_gpio_write(ISC_SPI_SSEL_PIN, 0); - HAL_SPI_DeInit(&ISC_SPIHandle); + omv_gpio_write(spi_bus.cs, 1); + omv_spi_deinit(&spi_bus); } int pixspi_regs_read(uint8_t addr, uint8_t * data, uint16_t length) { if ((addr & 0x80)) { - #ifdef DEBUG - printf("pixspi_regs_read() address (0x%x) overflow.\n", addr); - #endif + debug_printf("pixspi_regs_read() address (0x%x) overflow.\n", addr); return -1; } addr |= 0x80; if (!spi_send_recv(&addr, data, length)) { - #ifdef DEBUG - printf("spi_send_recv() failed.\n"); - #endif + debug_printf("spi_send_recv() failed.\n"); return -1; } return 0; @@ -108,9 +120,7 @@ int pixspi_regs_write(uint8_t addr, const uint8_t * data, uint16_t length) { uint8_t buff[64] = {}; if ((addr & 0x80) == 0x80) { - #ifdef DEBUG - printf("pixspi_regs_read() address (0x%x) overflow.\n", addr); - #endif + debug_printf("pixspi_regs_read() address (0x%x) overflow.\n", addr); return -1; } int32_t remaining = length; @@ -122,9 +132,7 @@ int pixspi_regs_write(uint8_t addr, const uint8_t * data, uint16_t length) memcpy(buff+1, data, len); bool res = spi_send(buff, len + 1); if (!res) { - #ifdef DEBUG - printf("spi_send() failed.\n"); - #endif + debug_printf("spi_send() failed.\n"); return -1; } remaining = remaining - MAX_LENGTH; diff --git a/src/omv/boards/OPENMV4/omv_boardconfig.h b/src/omv/boards/OPENMV4/omv_boardconfig.h index 1626115b6..918f22323 100644 --- a/src/omv/boards/OPENMV4/omv_boardconfig.h +++ b/src/omv/boards/OPENMV4/omv_boardconfig.h @@ -62,7 +62,7 @@ #define OMV_ENABLE_MT9V0XX (1) #define OMV_ENABLE_LEPTON (1) #define OMV_ENABLE_HM01B0 (0) -#define OMV_ENABLE_PAJ6100 (0) +#define OMV_ENABLE_PAJ6100 (1) #define OMV_ENABLE_FROGEYE2020 (1) #define OMV_ENABLE_FIR_MLX90621 (1) #define OMV_ENABLE_FIR_MLX90640 (1) @@ -163,7 +163,7 @@ #define OMV_FB_SIZE (400K) // FB memory: header + VGA/GS image #define OMV_FB_ALLOC_SIZE (100K) // minimum fb alloc size #define OMV_STACK_SIZE (64K) -#define OMV_HEAP_SIZE (229K) +#define OMV_HEAP_SIZE (228K) #define OMV_LINE_BUF_SIZE (5 * 1024) // Image line buffer. #define OMV_MSC_BUF_SIZE (2K) // USB MSC bot data diff --git a/src/omv/boards/OPENMV4P/omv_boardconfig.h b/src/omv/boards/OPENMV4P/omv_boardconfig.h index 7204485e9..1ebb5ffce 100644 --- a/src/omv/boards/OPENMV4P/omv_boardconfig.h +++ b/src/omv/boards/OPENMV4P/omv_boardconfig.h @@ -61,7 +61,7 @@ #define OMV_ENABLE_MT9V0XX (1) #define OMV_ENABLE_LEPTON (1) #define OMV_ENABLE_HM01B0 (0) -#define OMV_ENABLE_PAJ6100 (0) +#define OMV_ENABLE_PAJ6100 (1) #define OMV_ENABLE_FROGEYE2020 (1) #define OMV_ENABLE_FIR_MLX90621 (1) #define OMV_ENABLE_FIR_MLX90640 (1)