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boards/all: Add TIM clock sleep enable macro.
Signed-off-by: iabdalkader <i.abdalkader@gmail.com>
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@ -213,6 +213,7 @@
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#define OMV_CSI_TIM_CHANNEL (TIM_CHANNEL_3)
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#define OMV_CSI_TIM_CLK_ENABLE() __TIM1_CLK_ENABLE()
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#define OMV_CSI_TIM_CLK_DISABLE() __TIM1_CLK_DISABLE()
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#define OMV_CSI_TIM_CLK_SLEEP_ENABLE() __TIM1_CLK_SLEEP_ENABLE()
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#define OMV_CSI_TIM_PCLK_FREQ() HAL_RCC_GetPCLK2Freq()
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#define OMV_CSI_DMA_MEMCPY_ENABLE (1)
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#define OMV_CSI_HW_CROP_ENABLE (1)
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@ -210,6 +210,7 @@
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#define OMV_CSI_TIM_CHANNEL (TIM_CHANNEL_2)
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#define OMV_CSI_TIM_CLK_ENABLE() __TIM3_CLK_ENABLE()
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#define OMV_CSI_TIM_CLK_DISABLE() __TIM3_CLK_DISABLE()
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#define OMV_CSI_TIM_CLK_SLEEP_ENABLE() __TIM3_CLK_SLEEP_ENABLE()
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#define OMV_CSI_TIM_PCLK_FREQ() HAL_RCC_GetPCLK1Freq()
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#define OMV_CSI_DMA_MEMCPY_ENABLE (1)
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#define OMV_CSI_HW_CROP_ENABLE (1)
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@ -222,6 +222,7 @@
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#define OMV_CSI_TIM_CHANNEL (TIM_CHANNEL_1)
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#define OMV_CSI_TIM_CLK_ENABLE() __TIM1_CLK_ENABLE()
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#define OMV_CSI_TIM_CLK_DISABLE() __TIM1_CLK_DISABLE()
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#define OMV_CSI_TIM_CLK_SLEEP_ENABLE() __TIM1_CLK_SLEEP_ENABLE()
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#define OMV_CSI_TIM_PCLK_FREQ() HAL_RCC_GetPCLK2Freq()
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#define OMV_CSI_DMA_MEMCPY_ENABLE (1)
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#define OMV_CSI_HW_CROP_ENABLE (1)
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@ -86,6 +86,7 @@
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#define OMV_CSI_TIM_CHANNEL (TIM_CHANNEL_1)
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#define OMV_CSI_TIM_CLK_ENABLE() __TIM1_CLK_ENABLE()
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#define OMV_CSI_TIM_CLK_DISABLE() __TIM1_CLK_DISABLE()
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#define OMV_CSI_TIM_CLK_SLEEP_ENABLE() __TIM1_CLK_SLEEP_ENABLE()
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#define OMV_CSI_HW_CROP_ENABLE (1)
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#define OMV_CSI_RESET_PIN (GPIO_PIN_10)
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@ -140,6 +140,7 @@
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#define OMV_CSI_TIM_CHANNEL (TIM_CHANNEL_1)
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#define OMV_CSI_TIM_CLK_ENABLE() __TIM1_CLK_ENABLE()
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#define OMV_CSI_TIM_CLK_DISABLE() __TIM1_CLK_DISABLE()
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#define OMV_CSI_TIM_CLK_SLEEP_ENABLE() __TIM1_CLK_SLEEP_ENABLE()
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#define OMV_CSI_TIM_PCLK_FREQ() HAL_RCC_GetPCLK2Freq()
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#define OMV_CSI_HW_CROP_ENABLE (1)
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@ -139,6 +139,7 @@
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#define OMV_CSI_TIM_CHANNEL (TIM_CHANNEL_1)
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#define OMV_CSI_TIM_CLK_ENABLE() __TIM1_CLK_ENABLE()
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#define OMV_CSI_TIM_CLK_DISABLE() __TIM1_CLK_DISABLE()
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#define OMV_CSI_TIM_CLK_SLEEP_ENABLE() __TIM1_CLK_SLEEP_ENABLE()
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#define OMV_CSI_TIM_PCLK_FREQ() HAL_RCC_GetPCLK2Freq()
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#define OMV_CSI_HW_CROP_ENABLE (1)
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@ -213,6 +213,7 @@
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#define OMV_CSI_TIM_CHANNEL (TIM_CHANNEL_1)
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#define OMV_CSI_TIM_CLK_ENABLE() __TIM1_CLK_ENABLE()
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#define OMV_CSI_TIM_CLK_DISABLE() __TIM1_CLK_DISABLE()
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#define OMV_CSI_TIM_CLK_SLEEP_ENABLE() __TIM1_CLK_SLEEP_ENABLE()
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#define OMV_CSI_TIM_PCLK_FREQ() HAL_RCC_GetPCLK2Freq()
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#define OMV_CSI_DMA_MEMCPY_ENABLE (1)
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#define OMV_CSI_HW_CROP_ENABLE (1)
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@ -214,6 +214,7 @@
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#define OMV_CSI_TIM_CHANNEL (TIM_CHANNEL_1)
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#define OMV_CSI_TIM_CLK_ENABLE() __TIM1_CLK_ENABLE()
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#define OMV_CSI_TIM_CLK_DISABLE() __TIM1_CLK_DISABLE()
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#define OMV_CSI_TIM_CLK_SLEEP_ENABLE() __TIM1_CLK_SLEEP_ENABLE()
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#define OMV_CSI_TIM_PCLK_FREQ() HAL_RCC_GetPCLK2Freq()
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#define OMV_CSI_DMA_MEMCPY_ENABLE (1)
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#define OMV_CSI_HW_CROP_ENABLE (1)
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@ -206,6 +206,7 @@
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#define OMV_CSI_TIM_CHANNEL (TIM_CHANNEL_1)
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#define OMV_CSI_TIM_CLK_ENABLE() __TIM1_CLK_ENABLE()
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#define OMV_CSI_TIM_CLK_DISABLE() __TIM1_CLK_DISABLE()
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#define OMV_CSI_TIM_CLK_SLEEP_ENABLE() __TIM1_CLK_SLEEP_ENABLE()
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#define OMV_CSI_TIM_PCLK_FREQ() HAL_RCC_GetPCLK2Freq()
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#define OMV_CSI_DMA_MEMCPY_ENABLE (1)
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#define OMV_CSI_HW_CROP_ENABLE (1)
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