From 309779337018aefa3a3bfc2635a7cf3fad0b439d Mon Sep 17 00:00:00 2001 From: "Kwabena W. Agyeman" Date: Mon, 10 Feb 2020 23:25:50 -0800 Subject: [PATCH] Add IMU driver --- src/Makefile | 6 + src/omv/Makefile | 1 + src/omv/boards/OPENMV4/omv_boardconfig.h | 27 + src/omv/py/py_imu.c | 300 + src/omv/py/py_imu.h | 16 + src/omv/py/qstrdefsomv.h | 8 + src/omv/stm32fxxx_hal_msp.c | 26 + src/st/Makefile | 25 + src/st/include/lsm6ds3_reg.h | 1669 ++++++ src/st/include/lsm6ds3tr_c_reg.h | 1893 ++++++ src/st/src/lsm6ds3_reg.c | 5910 +++++++++++++++++++ src/st/src/lsm6ds3tr_c_reg.c | 6805 ++++++++++++++++++++++ 12 files changed, 16686 insertions(+) create mode 100644 src/omv/py/py_imu.c create mode 100644 src/omv/py/py_imu.h create mode 100644 src/st/Makefile create mode 100644 src/st/include/lsm6ds3_reg.h create mode 100644 src/st/include/lsm6ds3tr_c_reg.h create mode 100644 src/st/src/lsm6ds3_reg.c create mode 100644 src/st/src/lsm6ds3tr_c_reg.c diff --git a/src/Makefile b/src/Makefile index 716fb532f..54cfb2a6d 100755 --- a/src/Makefile +++ b/src/Makefile @@ -52,6 +52,7 @@ MICROPY_DIR=micropython OMV_DIR=omv LEPTON_DIR=lepton MLX_DIR=mlx +ST_DIR=st TENSORFLOW_DIR=libtf WINC1500_DIR=winc1500 BOOTLDR_DIR=bootloader @@ -126,6 +127,7 @@ OMV_CFLAGS += -I$(TOP_DIR)/$(OMV_DIR)/img/ OMV_CFLAGS += -I$(OMV_BOARD_CONFIG_DIR) OMV_CFLAGS += -I$(TOP_DIR)/$(LEPTON_DIR)/include/ OMV_CFLAGS += -I$(TOP_DIR)/$(MLX_DIR)/include/ +OMV_CFLAGS += -I$(TOP_DIR)/$(ST_DIR)/include/ OMV_CFLAGS += -I$(TOP_DIR)/$(TENSORFLOW_DIR)/$(CPU)/ OMV_CFLAGS += -I$(TOP_DIR)/$(WINC1500_DIR)/include/ @@ -169,6 +171,7 @@ endif FIRM_OBJ += $(wildcard $(BUILD)/$(STHAL_DIR)/src/*.o) FIRM_OBJ += $(wildcard $(BUILD)/$(LEPTON_DIR)/src/*.o) FIRM_OBJ += $(wildcard $(BUILD)/$(MLX_DIR)/src/*.o) +FIRM_OBJ += $(wildcard $(BUILD)/$(ST_DIR)/src/*.o) ifeq ($(MICROPY_PY_WINC1500), 1) FIRM_OBJ += $(wildcard $(BUILD)/$(WINC1500_DIR)/src/*.o) endif @@ -273,6 +276,7 @@ FIRM_OBJ += $(addprefix $(BUILD)/$(OMV_DIR)/py/, \ py_cpufreq.o \ py_nn.o \ py_tf.o \ + py_imu.o \ ) @@ -532,6 +536,7 @@ UVC_OBJ += $(addprefix $(BUILD)/$(OMV_DIR)/img/,\ UVC_OBJ += $(wildcard $(BUILD)/$(LEPTON_DIR)/src/*.o) UVC_OBJ += $(wildcard $(BUILD)/$(MLX_DIR)/src/*.o) +UVC_OBJ += $(wildcard $(BUILD)/$(ST_DIR)/src/*.o) ################################################### #Export Variables @@ -567,6 +572,7 @@ FIRMWARE_OBJS: | $(BUILD) $(FW_DIR) $(MAKE) -C $(MICROPY_DIR)/ports/stm32 BUILD=$(BUILD)/$(MICROPY_DIR) BOARD=$(TARGET) DEBUG=$(DEBUG) QSTR_DEFS="$(OMV_QSTR_DEFS)" $(MAKE) -C $(LEPTON_DIR) BUILD=$(BUILD)/$(LEPTON_DIR) CFLAGS="$(CFLAGS) -MMD" $(MAKE) -C $(MLX_DIR) BUILD=$(BUILD)/$(MLX_DIR) CFLAGS="$(CFLAGS) -MMD" + $(MAKE) -C $(ST_DIR) BUILD=$(BUILD)/$(ST_DIR) CFLAGS="$(CFLAGS) -MMD" ifeq ($(MICROPY_PY_WINC1500), 1) $(MAKE) -C $(WINC1500_DIR) BUILD=$(BUILD)/$(WINC1500_DIR) CFLAGS="$(CFLAGS) -MMD" endif diff --git a/src/omv/Makefile b/src/omv/Makefile index 5a300bb74..3a4f8a41e 100644 --- a/src/omv/Makefile +++ b/src/omv/Makefile @@ -107,6 +107,7 @@ SRCS += $(addprefix py/, \ py_cpufreq.c \ py_nn.c \ py_tf.c \ + py_imu.c \ ) OBJS = $(addprefix $(BUILD)/, $(SRCS:.c=.o)) diff --git a/src/omv/boards/OPENMV4/omv_boardconfig.h b/src/omv/boards/OPENMV4/omv_boardconfig.h index ac365f670..f5f83c9ce 100644 --- a/src/omv/boards/OPENMV4/omv_boardconfig.h +++ b/src/omv/boards/OPENMV4/omv_boardconfig.h @@ -49,6 +49,9 @@ #define OMV_ENABLE_MT9V034 (1) #define OMV_ENABLE_LEPTON (1) +// Enable IMU sensor +#define OMV_ENABLE_IMU (1) + // Enable WiFi debug #define OMV_ENABLE_WIFIDBG (1) @@ -241,4 +244,28 @@ #define LEPTON_SPI_MOSI_PORT (GPIOB) #define LEPTON_SPI_SSEL_PORT (GPIOA) +// The IMU sensor is on the same SPI bus pins as the camera module interface +// SPI bus. While the buses overlap both devices will never be in-use at once. + +#define IMU_SPI (SPI1) +#define IMU_SPI_AF (GPIO_AF5_SPI1) +// SPI1/2/3 clock source is PLL2 (160MHz/16 == 10MHz). +#define IMU_SPI_PRESCALER (SPI_BAUDRATEPRESCALER_16) + +#define IMU_SPI_RESET() __HAL_RCC_SPI1_FORCE_RESET() +#define IMU_SPI_RELEASE() __HAL_RCC_SPI1_RELEASE_RESET() + +#define IMU_SPI_CLK_ENABLE() __HAL_RCC_SPI1_CLK_ENABLE() +#define IMU_SPI_CLK_DISABLE() __HAL_RCC_SPI1_CLK_DISABLE() + +#define IMU_SPI_SCLK_PIN (GPIO_PIN_3) +#define IMU_SPI_MISO_PIN (GPIO_PIN_4) +#define IMU_SPI_MOSI_PIN (GPIO_PIN_5) +#define IMU_SPI_SSEL_PIN (GPIO_PIN_15) + +#define IMU_SPI_SCLK_PORT (GPIOB) +#define IMU_SPI_MISO_PORT (GPIOB) +#define IMU_SPI_MOSI_PORT (GPIOB) +#define IMU_SPI_SSEL_PORT (GPIOA) + #endif //__OMV_BOARDCONFIG_H__ diff --git a/src/omv/py/py_imu.c b/src/omv/py/py_imu.c new file mode 100644 index 000000000..61a292e1d --- /dev/null +++ b/src/omv/py/py_imu.c @@ -0,0 +1,300 @@ +/* + * This file is part of the OpenMV project. + * + * Copyright (c) 2013-2020 Ibrahim Abdelkader + * Copyright (c) 2013-2020 Kwabena W. Agyeman + * + * This work is licensed under the MIT license, see the file LICENSE for details. + * + * IMU Python module. + */ +#include STM32_HAL_H +#include "lsm6ds3tr_c_reg.h" +#include "omv_boardconfig.h" +#include "py_helper.h" +#include "py_imu.h" + +#if defined(OMV_ENABLE_IMU) + +typedef union { + int16_t i16bit[3]; + uint8_t u8bit[6]; +} axis3bit16_t; + +typedef union { + int16_t i16bit; + uint8_t u8bit[2]; +} axis1bit16_t; + +STATIC int32_t platform_write(void *handle, uint8_t Reg, uint8_t *Bufp, + uint16_t len) +{ + HAL_GPIO_WritePin(IMU_SPI_SSEL_PORT, IMU_SPI_SSEL_PIN, GPIO_PIN_RESET); + HAL_SPI_Transmit(handle, &Reg, 1, HAL_MAX_DELAY); + HAL_SPI_Transmit(handle, Bufp, len, HAL_MAX_DELAY); + HAL_GPIO_WritePin(IMU_SPI_SSEL_PORT, IMU_SPI_SSEL_PIN, GPIO_PIN_SET); + return 0; +} + +STATIC int32_t platform_read(void *handle, uint8_t Reg, uint8_t *Bufp, + uint16_t len) +{ + Reg |= 0x80; + HAL_GPIO_WritePin(IMU_SPI_SSEL_PORT, IMU_SPI_SSEL_PIN, GPIO_PIN_RESET); + HAL_SPI_Transmit(handle, &Reg, 1, HAL_MAX_DELAY); + HAL_SPI_Receive(handle, Bufp, len, HAL_MAX_DELAY); + HAL_GPIO_WritePin(IMU_SPI_SSEL_PORT, IMU_SPI_SSEL_PIN, GPIO_PIN_SET); + return 0; +} + +STATIC SPI_HandleTypeDef SPIHandle = { + .Instance = IMU_SPI, + .Init.Mode = SPI_MODE_MASTER, + .Init.Direction = SPI_DIRECTION_2LINES, + .Init.DataSize = SPI_DATASIZE_8BIT, + .Init.CLKPolarity = SPI_POLARITY_HIGH, + .Init.CLKPhase = SPI_PHASE_2EDGE, + .Init.NSS = SPI_NSS_SOFT, + .Init.BaudRatePrescaler = IMU_SPI_PRESCALER, + .Init.FirstBit = SPI_FIRSTBIT_MSB, +}; + +STATIC stmdev_ctx_t dev_ctx = { + .write_reg = platform_write, + .read_reg = platform_read, + .handle = &SPIHandle +}; + +STATIC bool test_not_ready() +{ + return HAL_SPI_GetState(&SPIHandle) != HAL_SPI_STATE_READY; +} + +STATIC void error_on_not_ready() +{ + if (test_not_ready()) nlr_raise(mp_obj_new_exception_msg(&mp_type_OSError, "IMU Not Ready!")); +} + +STATIC mp_obj_t py_imu_tuple(float x, float y, float z) +{ + return mp_obj_new_tuple(3, (mp_obj_t [3]) {mp_obj_new_float(x), + mp_obj_new_float(y), + mp_obj_new_float(z)}); +} + +// For when the camera board is lying on a table face up. + +// X points to the right of the camera sensor +// Y points down below the camera sensor +// Z points in the reverse direction of the camera sensor + +// Thus (https://www.nxp.com/docs/en/application-note/AN3461.pdf): +// +// Roll = atan2(Y, Z) +// Pitch = atan2(-X, sqrt(Y^2, + Z^2)) -> assume Y=0 -> atan2(-X, Z) + +// For when the camera board is standing right-side up. + +// X points to the right of the camera sensor (still X) +// Y points down below the camera sensor (now Z) +// Z points in the reverse direction of the camera sensor (now -Y) + +// So: +// +// Roll = atan2(-X, sqrt(Z^2, + Y^2)) -> assume Z=0 -> atan2(-X, Y) +// Pitch = atan2(Z, -Y) + +STATIC float py_imu_get_roll() +{ + axis3bit16_t data_raw_acceleration = {}; + lsm6ds3tr_c_acceleration_raw_get(&dev_ctx, data_raw_acceleration.u8bit); + float x = lsm6ds3tr_c_from_fs8g_to_mg(data_raw_acceleration.i16bit[0]); + float y = lsm6ds3tr_c_from_fs8g_to_mg(data_raw_acceleration.i16bit[1]); + return fmodf((IM_RAD2DEG(fast_atan2f(-x, y)) + 180), 360); // rotate 180 +} + +STATIC float py_imu_get_pitch() +{ + axis3bit16_t data_raw_acceleration = {}; + lsm6ds3tr_c_acceleration_raw_get(&dev_ctx, data_raw_acceleration.u8bit); + float y = lsm6ds3tr_c_from_fs8g_to_mg(data_raw_acceleration.i16bit[1]); + float z = lsm6ds3tr_c_from_fs8g_to_mg(data_raw_acceleration.i16bit[2]); + return IM_RAD2DEG(fast_atan2f(z, -y)); +} + +STATIC mp_obj_t py_imu_acceleration_mg() +{ + error_on_not_ready(); + + axis3bit16_t data_raw_acceleration = {}; + lsm6ds3tr_c_acceleration_raw_get(&dev_ctx, data_raw_acceleration.u8bit); + return py_imu_tuple(lsm6ds3tr_c_from_fs8g_to_mg(data_raw_acceleration.i16bit[0]), + lsm6ds3tr_c_from_fs8g_to_mg(data_raw_acceleration.i16bit[1]), + lsm6ds3tr_c_from_fs8g_to_mg(data_raw_acceleration.i16bit[2])); +} +STATIC MP_DEFINE_CONST_FUN_OBJ_0(py_imu_acceleration_mg_obj, py_imu_acceleration_mg); + +STATIC mp_obj_t py_imu_angular_rate_mdps() +{ + error_on_not_ready(); + + axis3bit16_t data_raw_angular_rate = {}; + lsm6ds3tr_c_angular_rate_raw_get(&dev_ctx, data_raw_angular_rate.u8bit); + return py_imu_tuple(lsm6ds3tr_c_from_fs2000dps_to_mdps(data_raw_angular_rate.i16bit[0]), + lsm6ds3tr_c_from_fs2000dps_to_mdps(data_raw_angular_rate.i16bit[1]), + lsm6ds3tr_c_from_fs2000dps_to_mdps(data_raw_angular_rate.i16bit[2])); +} +STATIC MP_DEFINE_CONST_FUN_OBJ_0(py_imu_angular_rate_mdps_obj, py_imu_angular_rate_mdps); + +STATIC mp_obj_t py_imu_temperature_c() +{ + error_on_not_ready(); + + axis1bit16_t data_raw_temperature = {}; + lsm6ds3tr_c_temperature_raw_get(&dev_ctx, data_raw_temperature.u8bit); + return mp_obj_new_float(lsm6ds3tr_c_from_lsb_to_celsius(data_raw_temperature.i16bit)); +} +STATIC MP_DEFINE_CONST_FUN_OBJ_0(py_imu_temperature_c_obj, py_imu_temperature_c); + +STATIC mp_obj_t py_imu_roll() +{ + error_on_not_ready(); + + return mp_obj_new_float(py_imu_get_roll()); +} +STATIC MP_DEFINE_CONST_FUN_OBJ_0(py_imu_roll_obj, py_imu_roll); + +STATIC mp_obj_t py_imu_pitch() +{ + error_on_not_ready(); + + return mp_obj_new_float(py_imu_get_pitch()); +} +STATIC MP_DEFINE_CONST_FUN_OBJ_0(py_imu_pitch_obj, py_imu_pitch); + +STATIC mp_obj_t py_imu_sleep(mp_obj_t enable) +{ + error_on_not_ready(); + + bool en = mp_obj_get_int(enable); + lsm6ds3tr_c_xl_data_rate_set(&dev_ctx, en ? LSM6DS3TR_C_XL_ODR_OFF : LSM6DS3TR_C_XL_ODR_52Hz); + lsm6ds3tr_c_gy_data_rate_set(&dev_ctx, en ? LSM6DS3TR_C_GY_ODR_OFF : LSM6DS3TR_C_GY_ODR_52Hz); + return mp_const_none; +} +STATIC MP_DEFINE_CONST_FUN_OBJ_1(py_imu_sleep_obj, py_imu_sleep); + +STATIC mp_obj_t py_imu_write_reg(mp_obj_t addr, mp_obj_t val) +{ + error_on_not_ready(); + + uint8_t v = mp_obj_get_int(val); + lsm6ds3tr_c_write_reg(&dev_ctx, mp_obj_get_int(addr), &v, sizeof(v)); + return mp_const_none; +} +STATIC MP_DEFINE_CONST_FUN_OBJ_2(py_imu_write_reg_obj, py_imu_write_reg); + +STATIC mp_obj_t py_imu_read_reg(mp_obj_t addr) +{ + error_on_not_ready(); + + uint8_t v; + lsm6ds3tr_c_read_reg(&dev_ctx, mp_obj_get_int(addr), &v, sizeof(v)); + return mp_obj_new_int(v); +} +STATIC MP_DEFINE_CONST_FUN_OBJ_1(py_imu_read_reg_obj, py_imu_read_reg); + +#endif + +STATIC const mp_rom_map_elem_t globals_dict_table[] = { + { MP_ROM_QSTR(MP_QSTR___name__), MP_OBJ_NEW_QSTR(MP_QSTR_imu) }, +#if defined(OMV_ENABLE_IMU) + { MP_ROM_QSTR(MP_QSTR_acceleration_mg), MP_ROM_PTR(&py_imu_acceleration_mg_obj) }, + { MP_ROM_QSTR(MP_QSTR_angular_rate_mdps), MP_ROM_PTR(&py_imu_angular_rate_mdps_obj) }, + { MP_ROM_QSTR(MP_QSTR_temperature_c), MP_ROM_PTR(&py_imu_temperature_c_obj) }, + { MP_ROM_QSTR(MP_QSTR_roll), MP_ROM_PTR(&py_imu_roll_obj) }, + { MP_ROM_QSTR(MP_QSTR_pitch), MP_ROM_PTR(&py_imu_pitch_obj) }, + { MP_ROM_QSTR(MP_QSTR_sleep), MP_ROM_PTR(&py_imu_sleep_obj) }, + { MP_ROM_QSTR(MP_QSTR___write_reg), MP_ROM_PTR(&py_imu_write_reg_obj) }, + { MP_ROM_QSTR(MP_QSTR___read_reg), MP_ROM_PTR(&py_imu_read_reg_obj) }, +#else + { MP_ROM_QSTR(MP_QSTR_acceleration_mg), MP_ROM_PTR(&py_func_unavailable_obj) }, + { MP_ROM_QSTR(MP_QSTR_angular_rate_mdps), MP_ROM_PTR(&py_func_unavailable_obj) }, + { MP_ROM_QSTR(MP_QSTR_temperature_c), MP_ROM_PTR(&py_func_unavailable_obj) }, + { MP_ROM_QSTR(MP_QSTR_roll), MP_ROM_PTR(&py_func_unavailable_obj) }, + { MP_ROM_QSTR(MP_QSTR_pitch), MP_ROM_PTR(&py_func_unavailable_obj) }, + { MP_ROM_QSTR(MP_QSTR_sleep), MP_ROM_PTR(&py_func_unavailable_obj) }, + { MP_ROM_QSTR(MP_QSTR___write_reg), MP_ROM_PTR(&py_func_unavailable_obj) }, + { MP_ROM_QSTR(MP_QSTR___read_reg), MP_ROM_PTR(&py_func_unavailable_obj) }, +#endif +}; + +STATIC MP_DEFINE_CONST_DICT(globals_dict, globals_dict_table); + +const mp_obj_module_t imu_module = { + .base = { &mp_type_module }, + .globals = (mp_obj_t) &globals_dict +}; + +void py_imu_init() +{ +#if defined(OMV_ENABLE_IMU) + HAL_SPI_Init(&SPIHandle); + + uint8_t whoamI = 0, rst = 1; + + // Try to read device id... + for (int i = 0; (i < 10) && (whoamI != LSM6DS3TR_C_ID); i++) { + lsm6ds3tr_c_device_id_get(&dev_ctx, &whoamI); + } + + if (whoamI != LSM6DS3TR_C_ID) { + HAL_SPI_DeInit(&SPIHandle); + return; + } + + lsm6ds3tr_c_reset_set(&dev_ctx, PROPERTY_ENABLE); + + for (int i = 0; (i < 10000) && rst; i++) { + lsm6ds3tr_c_reset_get(&dev_ctx, &rst); + } + + if (rst) { + HAL_SPI_DeInit(&SPIHandle); + return; + } + + lsm6ds3tr_c_block_data_update_set(&dev_ctx, PROPERTY_ENABLE); + + lsm6ds3tr_c_xl_data_rate_set(&dev_ctx, LSM6DS3TR_C_XL_ODR_52Hz); + lsm6ds3tr_c_gy_data_rate_set(&dev_ctx, LSM6DS3TR_C_GY_ODR_52Hz); + + lsm6ds3tr_c_xl_full_scale_set(&dev_ctx, LSM6DS3TR_C_8g); + lsm6ds3tr_c_gy_full_scale_set(&dev_ctx, LSM6DS3TR_C_2000dps); +#endif +} + +float py_imu_roll_rotation() +{ +#if defined(OMV_ENABLE_IMU) + if (test_not_ready()) { + return 0; // output when the camera is mounted upright + } + + return py_imu_get_roll(); +#else + return 0; // output when the camera is mounted upright +#endif +} + +float py_imu_pitch_rotation() +{ +#if defined(OMV_ENABLE_IMU) + if (test_not_ready()) { + return 0; // output when the camera is mounted upright + } + + return py_imu_get_pitch(); +#else + return 0; // output when the camera is mounted upright +#endif +} diff --git a/src/omv/py/py_imu.h b/src/omv/py/py_imu.h new file mode 100644 index 000000000..11ed1ae59 --- /dev/null +++ b/src/omv/py/py_imu.h @@ -0,0 +1,16 @@ +/* + * This file is part of the OpenMV project. + * + * Copyright (c) 2013-2020 Ibrahim Abdelkader + * Copyright (c) 2013-2020 Kwabena W. Agyeman + * + * This work is licensed under the MIT license, see the file LICENSE for details. + * + * IMU Python module. + */ +#ifndef __PY_IMU_H__ +#define __PY_IMU_H__ +void py_imu_init(); +float py_imu_roll_rotation(); // in degrees +float py_imu_pitch_rotation(); // in degrees +#endif // __PY_IMU_H__ diff --git a/src/omv/py/qstrdefsomv.h b/src/omv/py/qstrdefsomv.h index c443df67a..e8634bd38 100644 --- a/src/omv/py/qstrdefsomv.h +++ b/src/omv/py/qstrdefsomv.h @@ -1215,3 +1215,11 @@ Q(output) // Segment // duplicate Q(segment) // duplicate Q(roi) + +// IMU Module +Q(imu) +Q(acceleration_mg) +Q(angular_rate_mdps) +Q(temperature_c) +Q(roll) +Q(pitch) diff --git a/src/omv/stm32fxxx_hal_msp.c b/src/omv/stm32fxxx_hal_msp.c index 8fd76ffce..6c461f83e 100644 --- a/src/omv/stm32fxxx_hal_msp.c +++ b/src/omv/stm32fxxx_hal_msp.c @@ -216,6 +216,32 @@ void HAL_DCMI_MspInit(DCMI_HandleTypeDef* hdcmi) void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi) { + #if defined(IMU_SPI) + if (hspi->Instance == IMU_SPI) { + IMU_SPI_CLK_ENABLE(); + + GPIO_InitTypeDef GPIO_InitStructure; + GPIO_InitStructure.Pull = GPIO_PULLUP; + GPIO_InitStructure.Mode = GPIO_MODE_AF_PP; + GPIO_InitStructure.Alternate = IMU_SPI_AF; + GPIO_InitStructure.Speed = GPIO_SPEED_FREQ_LOW; + + GPIO_InitStructure.Pin = IMU_SPI_SCLK_PIN; + HAL_GPIO_Init(IMU_SPI_SCLK_PORT, &GPIO_InitStructure); + + GPIO_InitStructure.Pin = IMU_SPI_MISO_PIN; + HAL_GPIO_Init(IMU_SPI_MISO_PORT, &GPIO_InitStructure); + + GPIO_InitStructure.Pin = IMU_SPI_MOSI_PIN; + HAL_GPIO_Init(IMU_SPI_MOSI_PORT, &GPIO_InitStructure); + + GPIO_InitStructure.Mode = GPIO_MODE_OUTPUT_PP; + + GPIO_InitStructure.Pin = IMU_SPI_SSEL_PIN; + HAL_GPIO_Init(IMU_SPI_SSEL_PORT, &GPIO_InitStructure); + } + #endif + #if defined(LEPTON_SPI) if (hspi->Instance == LEPTON_SPI) { LEPTON_SPI_CLK_ENABLE(); diff --git a/src/st/Makefile b/src/st/Makefile new file mode 100644 index 000000000..baf2fc2ac --- /dev/null +++ b/src/st/Makefile @@ -0,0 +1,25 @@ +# This file is part of the OpenMV project. +# +# Copyright (c) 2013-2020 Ibrahim Abdelkader +# Copyright (c) 2013-2020 Kwabena W. Agyeman +# +# This work is licensed under the MIT license, see the file LICENSE for details. +# +# ST Makefile +SRCS = $(wildcard src/*.c) +OBJS = $(addprefix $(BUILD)/, $(SRCS:.c=.o)) +OBJ_DIRS = $(sort $(dir $(OBJS))) + +all: | $(OBJ_DIRS) $(OBJS) +$(OBJ_DIRS): + $(MKDIR) -p $@ + +$(BUILD)/%.o : %.c + $(ECHO) "CC $<" + $(CC) $(CFLAGS) -c -o $@ $< + +$(BUILD)/%.o : %.s + $(ECHO) "AS $<" + $(AS) $(AFLAGS) $< -o $@ + +-include $(OBJS:%.o=%.d) diff --git a/src/st/include/lsm6ds3_reg.h b/src/st/include/lsm6ds3_reg.h new file mode 100644 index 000000000..17e926a51 --- /dev/null +++ b/src/st/include/lsm6ds3_reg.h @@ -0,0 +1,1669 @@ +/* + ****************************************************************************** + * @file lsm6ds3_reg.h + * @author Sensors Software Solution Team + * @brief This file contains all the functions prototypes for the + * lsm6ds3_reg.c driver. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2019 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef LSM6DS3_REGS_H +#define LSM6DS3_REGS_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include +#include + +/** @addtogroup LSM6DS3 + * @{ + * + */ + +/** @defgroup STMicroelectronics sensors common types + * @{ + * + */ + +#ifndef MEMS_SHARED_TYPES +#define MEMS_SHARED_TYPES + +typedef struct{ + uint8_t bit0 : 1; + uint8_t bit1 : 1; + uint8_t bit2 : 1; + uint8_t bit3 : 1; + uint8_t bit4 : 1; + uint8_t bit5 : 1; + uint8_t bit6 : 1; + uint8_t bit7 : 1; +} bitwise_t; + +#define PROPERTY_DISABLE (0U) +#define PROPERTY_ENABLE (1U) + +/** @addtogroup Interfaces_Functions + * @brief This section provide a set of functions used to read and + * write a generic register of the device. + * MANDATORY: return 0 -> no Error. + * @{ + * + */ + +typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, uint8_t*, uint16_t); +typedef int32_t (*stmdev_read_ptr) (void *, uint8_t, uint8_t*, uint16_t); + +typedef struct { + /** Component mandatory fields **/ + stmdev_write_ptr write_reg; + stmdev_read_ptr read_reg; + /** Customizable optional pointer **/ + void *handle; +} stmdev_ctx_t; + +/** + * @} + * + */ + +#endif /* MEMS_SHARED_TYPES */ + +#ifndef MEMS_UCF_SHARED_TYPES +#define MEMS_UCF_SHARED_TYPES + +/** @defgroup Generic address-data structure definition + * @brief This structure is useful to load a predefined configuration + * of a sensor. + * You can create a sensor configuration by your own or using + * Unico / Unicleo tools available on STMicroelectronics + * web site. + * + * @{ + * + */ + +typedef struct { + uint8_t address; + uint8_t data; +} ucf_line_t; + +/** + * @} + * + */ + +#endif /* MEMS_UCF_SHARED_TYPES */ + +/** + * @} + * + */ + +/** @defgroup LSM6DS3_Infos + * @{ + * + */ + +/** I2C Device Address 8 bit format if SA0=0 -> 0xD5 if SA0=1 -> 0xD7 **/ +#define LSM6DS3_I2C_ADD_L 0xD5U +#define LSM6DS3_I2C_ADD_H 0xD7U +/** Device Identification (Who am I) **/ +#define LSM6DS3_ID 0x69U + +/** + * @} + * + */ + +#define LSM6DS3_FUNC_CFG_ACCESS 0x01U +typedef struct { + uint8_t not_used_01 : 7; + uint8_t func_cfg_en : 1; +} lsm6ds3_func_cfg_access_t; + +#define LSM6DS3_SENSOR_SYNC_TIME_FRAME 0x04U +typedef struct { + uint8_t tph : 8; +} lsm6ds3_sensor_sync_time_frame_t; + +#define LSM6DS3_FIFO_CTRL1 0x06U +typedef struct { + uint8_t fth : 8; +} lsm6ds3_fifo_ctrl1_t; + +#define LSM6DS3_FIFO_CTRL2 0x07U +typedef struct { + uint8_t fth : 4; + uint8_t not_used_01 : 2; + uint8_t timer_pedo_fifo_drdy : 1; + uint8_t timer_pedo_fifo_en : 1; +} lsm6ds3_fifo_ctrl2_t; + +#define LSM6DS3_FIFO_CTRL3 0x08U +typedef struct { + uint8_t dec_fifo_xl : 3; + uint8_t dec_fifo_gyro : 3; + uint8_t not_used_01 : 2; +} lsm6ds3_fifo_ctrl3_t; + +#define LSM6DS3_FIFO_CTRL4 0x09U +typedef struct { + uint8_t dec_ds3_fifo : 3; + uint8_t dec_ds4_fifo : 3; + uint8_t only_high_data : 1; + uint8_t not_used_01 : 1; +} lsm6ds3_fifo_ctrl4_t; + +#define LSM6DS3_FIFO_CTRL5 0x0AU +typedef struct { + uint8_t fifo_mode : 3; + uint8_t odr_fifo : 4; + uint8_t not_used_01 : 1; +} lsm6ds3_fifo_ctrl5_t; + +#define LSM6DS3_ORIENT_CFG_G 0x0BU +typedef struct { + uint8_t orient : 3; + uint8_t sign_g : 3; /* SignX_G) + SignY_G + SignZ_G */ + uint8_t not_used_01 : 2; +} lsm6ds3_orient_cfg_g_t; + +#define LSM6DS3_INT1_CTRL 0x0DU +typedef struct { + uint8_t int1_drdy_xl : 1; + uint8_t int1_drdy_g : 1; + uint8_t int1_boot : 1; + uint8_t int1_fth : 1; + uint8_t int1_fifo_ovr : 1; + uint8_t int1_full_flag : 1; + uint8_t int1_sign_mot : 1; + uint8_t int1_step_detector : 1; +} lsm6ds3_int1_ctrl_t; + +#define LSM6DS3_INT2_CTRL 0x0EU +typedef struct { + uint8_t int2_drdy_xl : 1; + uint8_t int2_drdy_g : 1; + uint8_t int2_drdy_temp : 1; + uint8_t int2_fth : 1; + uint8_t int2_fifo_ovr : 1; + uint8_t int2_full_flag : 1; + uint8_t int2_step_count_ov : 1; + uint8_t int2_step_delta : 1; +} lsm6ds3_int2_ctrl_t; + +#define LSM6DS3_WHO_AM_I 0x0FU +#define LSM6DS3_CTRL1_XL 0x10U +typedef struct { + uint8_t bw_xl : 2; + uint8_t fs_xl : 2; + uint8_t odr_xl : 4; +} lsm6ds3_ctrl1_xl_t; + +#define LSM6DS3_CTRL2_G 0x11U +typedef struct { + uint8_t not_used_01 : 1; + uint8_t fs_g : 3; /* FS_G + FS_125 */ + uint8_t odr_g : 4; +} lsm6ds3_ctrl2_g_t; + +#define LSM6DS3_CTRL3_C 0x12U +typedef struct { + uint8_t sw_reset : 1; + uint8_t ble : 1; + uint8_t if_inc : 1; + uint8_t sim : 1; + uint8_t pp_od : 1; + uint8_t h_lactive : 1; + uint8_t bdu : 1; + uint8_t boot : 1; +} lsm6ds3_ctrl3_c_t; + +#define LSM6DS3_CTRL4_C 0x13U +typedef struct { + uint8_t stop_on_fth : 1; + uint8_t not_used_01 : 1; + uint8_t i2c_disable : 1; + uint8_t drdy_mask : 1; + uint8_t fifo_temp_en : 1; + uint8_t int2_on_int1 : 1; + uint8_t sleep_g : 1; + uint8_t xl_bw_scal_odr : 1; +} lsm6ds3_ctrl4_c_t; + +#define LSM6DS3_CTRL5_C 0x14U +typedef struct { + uint8_t st_xl : 2; + uint8_t st_g : 2; + uint8_t not_used_01 : 1; + uint8_t rounding : 3; +} lsm6ds3_ctrl5_c_t; + +#define LSM6DS3_CTRL6_C 0x15U +typedef struct { + uint8_t not_used_01 : 4; + uint8_t xl_hm_mode : 1; + uint8_t den_mode : 3; /* trig_en + lvl1_en + lvl2_en */ +} lsm6ds3_ctrl6_c_t; + +#define LSM6DS3_CTRL7_G 0x16U +typedef struct { + uint8_t not_used_01 : 2; + uint8_t rounding_status : 1; + uint8_t hpcf_g : 2; + uint8_t hp_g_rst : 1; + uint8_t hp_g_en : 1; + uint8_t g_hm_mode : 1; +} lsm6ds3_ctrl7_g_t; + +#define LSM6DS3_CTRL8_XL 0x17U +typedef struct { + uint8_t low_pass_on_6d : 1; + uint8_t not_used_01 : 1; + uint8_t hp_slope_xl_en : 1; + uint8_t not_used_02 : 2; + uint8_t hpcf_xl : 2; + uint8_t lpf2_xl_en : 1; +} lsm6ds3_ctrl8_xl_t; + +#define LSM6DS3_CTRL9_XL 0x18U +typedef struct { + uint8_t not_used_01 : 2; + uint8_t soft_en : 1; + uint8_t xen_xl : 1; + uint8_t yen_xl : 1; + uint8_t zen_xl : 1; + uint8_t not_used_02 : 2; +} lsm6ds3_ctrl9_xl_t; + +#define LSM6DS3_CTRL10_C 0x19U +typedef struct { + uint8_t sign_motion_en : 1; + uint8_t pedo_rst_step : 1; + uint8_t func_en : 1; + uint8_t xen_g : 1; + uint8_t yen_g : 1; + uint8_t zen_g : 1; + uint8_t not_used_01 : 2; +} lsm6ds3_ctrl10_c_t; + +#define LSM6DS3_MASTER_CONFIG 0x1AU +typedef struct { + uint8_t master_on : 1; + uint8_t iron_en : 1; + uint8_t pass_through_mode : 1; + uint8_t pull_up_en : 1; + uint8_t start_config : 1; + uint8_t not_used_01 : 1; + uint8_t data_valid_sel_fifo : 1; + uint8_t drdy_on_int1 : 1; +} lsm6ds3_master_config_t; + +#define LSM6DS3_WAKE_UP_SRC 0x1BU +typedef struct { + uint8_t z_wu : 1; + uint8_t y_wu : 1; + uint8_t x_wu : 1; + uint8_t wu_ia : 1; + uint8_t sleep_state_ia : 1; + uint8_t ff_ia : 1; + uint8_t not_used_01 : 2; +} lsm6ds3_wake_up_src_t; + +#define LSM6DS3_TAP_SRC 0x1CU +typedef struct { + uint8_t z_tap : 1; + uint8_t y_tap : 1; + uint8_t x_tap : 1; + uint8_t tap_sign : 1; + uint8_t double_tap : 1; + uint8_t single_tap : 1; + uint8_t tap_ia : 1; + uint8_t not_used_01 : 1; +} lsm6ds3_tap_src_t; + +#define LSM6DS3_D6D_SRC 0x1DU +typedef struct { + uint8_t xl : 1; + uint8_t xh : 1; + uint8_t yl : 1; + uint8_t yh : 1; + uint8_t zl : 1; + uint8_t zh : 1; + uint8_t d6d_ia : 1; + uint8_t not_used_01 : 1; +} lsm6ds3_d6d_src_t; + +#define LSM6DS3_STATUS_REG 0x1EU +typedef struct { + uint8_t xlda : 1; + uint8_t gda : 1; + uint8_t tda : 1; + uint8_t not_used_01 : 5; +} lsm6ds3_status_reg_t; + +#define LSM6DS3_OUT_TEMP_L 0x20U +#define LSM6DS3_OUT_TEMP_H 0x21U +#define LSM6DS3_OUTX_L_G 0x22U +#define LSM6DS3_OUTX_H_G 0x23U +#define LSM6DS3_OUTY_L_G 0x24U +#define LSM6DS3_OUTY_H_G 0x25U +#define LSM6DS3_OUTZ_L_G 0x26U +#define LSM6DS3_OUTZ_H_G 0x27U +#define LSM6DS3_OUTX_L_XL 0x28U +#define LSM6DS3_OUTX_H_XL 0x29U +#define LSM6DS3_OUTY_L_XL 0x2AU +#define LSM6DS3_OUTY_H_XL 0x2BU +#define LSM6DS3_OUTZ_L_XL 0x2CU +#define LSM6DS3_OUTZ_H_XL 0x2DU +#define LSM6DS3_SENSORHUB1_REG 0x2EU +typedef struct { + uint8_t shub1_0 : 1; + uint8_t shub1_1 : 1; + uint8_t shub1_2 : 1; + uint8_t shub1_3 : 1; + uint8_t shub1_4 : 1; + uint8_t shub1_5 : 1; + uint8_t shub1_6 : 1; + uint8_t shub1_7 : 1; +} lsm6ds3_sensorhub1_reg_t; + +#define LSM6DS3_SENSORHUB2_REG 0x2FU +typedef struct { + uint8_t shub2_0 : 1; + uint8_t shub2_1 : 1; + uint8_t shub2_2 : 1; + uint8_t shub2_3 : 1; + uint8_t shub2_4 : 1; + uint8_t shub2_5 : 1; + uint8_t shub2_6 : 1; + uint8_t shub2_7 : 1; +} lsm6ds3_sensorhub2_reg_t; + +#define LSM6DS3_SENSORHUB3_REG 0x30U +typedef struct { + uint8_t shub3_0 : 1; + uint8_t shub3_1 : 1; + uint8_t shub3_2 : 1; + uint8_t shub3_3 : 1; + uint8_t shub3_4 : 1; + uint8_t shub3_5 : 1; + uint8_t shub3_6 : 1; + uint8_t shub3_7 : 1; +} lsm6ds3_sensorhub3_reg_t; + +#define LSM6DS3_SENSORHUB4_REG 0x31U +typedef struct { + uint8_t shub4_0 : 1; + uint8_t shub4_1 : 1; + uint8_t shub4_2 : 1; + uint8_t shub4_3 : 1; + uint8_t shub4_4 : 1; + uint8_t shub4_5 : 1; + uint8_t shub4_6 : 1; + uint8_t shub4_7 : 1; +} lsm6ds3_sensorhub4_reg_t; + +#define LSM6DS3_SENSORHUB5_REG 0x32U +typedef struct { + uint8_t shub5_0 : 1; + uint8_t shub5_1 : 1; + uint8_t shub5_2 : 1; + uint8_t shub5_3 : 1; + uint8_t shub5_4 : 1; + uint8_t shub5_5 : 1; + uint8_t shub5_6 : 1; + uint8_t shub5_7 : 1; +} lsm6ds3_sensorhub5_reg_t; + +#define LSM6DS3_SENSORHUB6_REG 0x33U +typedef struct { + uint8_t shub6_0 : 1; + uint8_t shub6_1 : 1; + uint8_t shub6_2 : 1; + uint8_t shub6_3 : 1; + uint8_t shub6_4 : 1; + uint8_t shub6_5 : 1; + uint8_t shub6_6 : 1; + uint8_t shub6_7 : 1; +} lsm6ds3_sensorhub6_reg_t; + +#define LSM6DS3_SENSORHUB7_REG 0x34U +typedef struct { + uint8_t shub7_0 : 1; + uint8_t shub7_1 : 1; + uint8_t shub7_2 : 1; + uint8_t shub7_3 : 1; + uint8_t shub7_4 : 1; + uint8_t shub7_5 : 1; + uint8_t shub7_6 : 1; + uint8_t shub7_7 : 1; +} lsm6ds3_sensorhub7_reg_t; + +#define LSM6DS3_SENSORHUB8_REG 0x35U +typedef struct { + uint8_t shub8_0 : 1; + uint8_t shub8_1 : 1; + uint8_t shub8_2 : 1; + uint8_t shub8_3 : 1; + uint8_t shub8_4 : 1; + uint8_t shub8_5 : 1; + uint8_t shub8_6 : 1; + uint8_t shub8_7 : 1; +} lsm6ds3_sensorhub8_reg_t; + +#define LSM6DS3_SENSORHUB9_REG 0x36U +typedef struct { + uint8_t shub9_0 : 1; + uint8_t shub9_1 : 1; + uint8_t shub9_2 : 1; + uint8_t shub9_3 : 1; + uint8_t shub9_4 : 1; + uint8_t shub9_5 : 1; + uint8_t shub9_6 : 1; + uint8_t shub9_7 : 1; +} lsm6ds3_sensorhub9_reg_t; + +#define LSM6DS3_SENSORHUB10_REG 0x37U +typedef struct { + uint8_t shub10_0 : 1; + uint8_t shub10_1 : 1; + uint8_t shub10_2 : 1; + uint8_t shub10_3 : 1; + uint8_t shub10_4 : 1; + uint8_t shub10_5 : 1; + uint8_t shub10_6 : 1; + uint8_t shub10_7 : 1; +} lsm6ds3_sensorhub10_reg_t; + +#define LSM6DS3_SENSORHUB11_REG 0x38U +typedef struct { + uint8_t shub11_0 : 1; + uint8_t shub11_1 : 1; + uint8_t shub11_2 : 1; + uint8_t shub11_3 : 1; + uint8_t shub11_4 : 1; + uint8_t shub11_5 : 1; + uint8_t shub11_6 : 1; + uint8_t shub11_7 : 1; +} lsm6ds3_sensorhub11_reg_t; + +#define LSM6DS3_SENSORHUB12_REG 0x39U +typedef struct { + uint8_t shub12_0 : 1; + uint8_t shub12_1 : 1; + uint8_t shub12_2 : 1; + uint8_t shub12_3 : 1; + uint8_t shub12_4 : 1; + uint8_t shub12_5 : 1; + uint8_t shub12_6 : 1; + uint8_t shub12_7 : 1; +} lsm6ds3_sensorhub12_reg_t; + +#define LSM6DS3_FIFO_STATUS1 0x3AU +typedef struct { + uint8_t diff_fifo : 8; +} lsm6ds3_fifo_status1_t; + +#define LSM6DS3_FIFO_STATUS2 0x3BU +typedef struct { + uint8_t diff_fifo : 4; + uint8_t fifo_empty : 1; + uint8_t fifo_full : 1; + uint8_t fifo_over_run : 1; + uint8_t fth : 1; +} lsm6ds3_fifo_status2_t; + +#define LSM6DS3_FIFO_STATUS3 0x3CU +typedef struct { + uint8_t fifo_pattern : 8; +} lsm6ds3_fifo_status3_t; + +#define LSM6DS3_FIFO_STATUS4 0x3DU +typedef struct { + uint8_t fifo_pattern : 2; + uint8_t not_used_01 : 6; +} lsm6ds3_fifo_status4_t; + +#define LSM6DS3_FIFO_DATA_OUT_L 0x3EU +#define LSM6DS3_FIFO_DATA_OUT_H 0x3FU +#define LSM6DS3_TIMESTAMP0_REG 0x40U +#define LSM6DS3_TIMESTAMP1_REG 0x41U +#define LSM6DS3_TIMESTAMP2_REG 0x42U +#define LSM6DS3_STEP_TIMESTAMP_L 0x49U +#define LSM6DS3_STEP_TIMESTAMP_H 0x4AU +#define LSM6DS3_STEP_COUNTER_L 0x4BU +#define LSM6DS3_STEP_COUNTER_H 0x4CU +#define LSM6DS3_SENSORHUB13_REG 0x4DU +typedef struct { + uint8_t shub13_0 : 1; + uint8_t shub13_1 : 1; + uint8_t shub13_2 : 1; + uint8_t shub13_3 : 1; + uint8_t shub13_4 : 1; + uint8_t shub13_5 : 1; + uint8_t shub13_6 : 1; + uint8_t shub13_7 : 1; +} lsm6ds3_sensorhub13_reg_t; + +#define LSM6DS3_SENSORHUB14_REG 0x4EU +typedef struct { + uint8_t shub14_0 : 1; + uint8_t shub14_1 : 1; + uint8_t shub14_2 : 1; + uint8_t shub14_3 : 1; + uint8_t shub14_4 : 1; + uint8_t shub14_5 : 1; + uint8_t shub14_6 : 1; + uint8_t shub14_7 : 1; +} lsm6ds3_sensorhub14_reg_t; + +#define LSM6DS3_SENSORHUB15_REG 0x4FU +typedef struct { + uint8_t shub15_0 : 1; + uint8_t shub15_1 : 1; + uint8_t shub15_2 : 1; + uint8_t shub15_3 : 1; + uint8_t shub15_4 : 1; + uint8_t shub15_5 : 1; + uint8_t shub15_6 : 1; + uint8_t shub15_7 : 1; +} lsm6ds3_sensorhub15_reg_t; + +#define LSM6DS3_SENSORHUB16_REG 0x50U +typedef struct { + uint8_t shub16_0 : 1; + uint8_t shub16_1 : 1; + uint8_t shub16_2 : 1; + uint8_t shub16_3 : 1; + uint8_t shub16_4 : 1; + uint8_t shub16_5 : 1; + uint8_t shub16_6 : 1; + uint8_t shub16_7 : 1; +} lsm6ds3_sensorhub16_reg_t; + +#define LSM6DS3_SENSORHUB17_REG 0x51U +typedef struct { + uint8_t shub17_0 : 1; + uint8_t shub17_1 : 1; + uint8_t shub17_2 : 1; + uint8_t shub17_3 : 1; + uint8_t shub17_4 : 1; + uint8_t shub17_5 : 1; + uint8_t shub17_6 : 1; + uint8_t shub17_7 : 1; +} lsm6ds3_sensorhub17_reg_t; + +#define LSM6DS3_SENSORHUB18_REG 0x52U +typedef struct { + uint8_t shub18_0 : 1; + uint8_t shub18_1 : 1; + uint8_t shub18_2 : 1; + uint8_t shub18_3 : 1; + uint8_t shub18_4 : 1; + uint8_t shub18_5 : 1; + uint8_t shub18_6 : 1; + uint8_t shub18_7 : 1; +} lsm6ds3_sensorhub18_reg_t; + +#define LSM6DS3_FUNC_SRC 0x53U +typedef struct { + uint8_t sensor_hub_end_op : 1; + uint8_t si_end_op : 1; + uint8_t not_used_01 : 1; + uint8_t step_overflow : 1; + uint8_t step_detected : 1; + uint8_t tilt_ia : 1; + uint8_t sign_motion_ia : 1; + uint8_t step_count_delta_ia : 1; +} lsm6ds3_func_src_t; + +#define LSM6DS3_TAP_CFG 0x58U +typedef struct { + uint8_t lir : 1; + uint8_t tap_z_en : 1; + uint8_t tap_y_en : 1; + uint8_t tap_x_en : 1; + uint8_t slope_fds : 1; + uint8_t tilt_en : 1; + uint8_t pedo_en : 1; + uint8_t timer_en : 1; +} lsm6ds3_tap_cfg_t; + +#define LSM6DS3_TAP_THS_6D 0x59U +typedef struct { + uint8_t tap_ths : 5; + uint8_t sixd_ths : 2; + uint8_t d4d_en : 1; +} lsm6ds3_tap_ths_6d_t; + +#define LSM6DS3_INT_DUR2 0x5AU +typedef struct { + uint8_t shock : 2; + uint8_t quiet : 2; + uint8_t dur : 4; +} lsm6ds3_int_dur2_t; + +#define LSM6DS3_WAKE_UP_THS 0x5BU +typedef struct { + uint8_t wk_ths : 6; + uint8_t inactivity : 1; + uint8_t single_double_tap : 1; +} lsm6ds3_wake_up_ths_t; + +#define LSM6DS3_WAKE_UP_DUR 0x5CU +typedef struct { + uint8_t sleep_dur : 4; + uint8_t timer_hr : 1; + uint8_t wake_dur : 2; + uint8_t ff_dur : 1; +} lsm6ds3_wake_up_dur_t; + +#define LSM6DS3_FREE_FALL 0x5DU +typedef struct { + uint8_t ff_ths : 3; + uint8_t ff_dur : 5; +} lsm6ds3_free_fall_t; + +#define LSM6DS3_MD1_CFG 0x5EU +typedef struct { + uint8_t int1_timer : 1; + uint8_t int1_tilt : 1; + uint8_t int1_6d : 1; + uint8_t int1_double_tap : 1; + uint8_t int1_ff : 1; + uint8_t int1_wu : 1; + uint8_t int1_single_tap : 1; + uint8_t int1_inact_state : 1; +} lsm6ds3_md1_cfg_t; + +#define LSM6DS3_MD2_CFG 0x5FU +typedef struct { + uint8_t int2_iron : 1; + uint8_t int2_tilt : 1; + uint8_t int2_6d : 1; + uint8_t int2_double_tap : 1; + uint8_t int2_ff : 1; + uint8_t int2_wu : 1; + uint8_t int2_single_tap : 1; + uint8_t int2_inact_state : 1; +} lsm6ds3_md2_cfg_t; + +#define LSM6DS3_OUT_MAG_RAW_X_L 0x66U +#define LSM6DS3_OUT_MAG_RAW_X_H 0x67U +#define LSM6DS3_OUT_MAG_RAW_Y_L 0x68U +#define LSM6DS3_OUT_MAG_RAW_Y_H 0x69U +#define LSM6DS3_OUT_MAG_RAW_Z_L 0x6AU +#define LSM6DS3_OUT_MAG_RAW_Z_H 0x6BU +#define LSM6DS3_SLV0_ADD 0x02U +typedef struct { + uint8_t rw_0 : 1; + uint8_t slave0_add : 7; +} lsm6ds3_slv0_add_t; + +#define LSM6DS3_SLV0_SUBADD 0x03U +typedef struct { + uint8_t slave0_reg : 8; +} lsm6ds3_slv0_subadd_t; + +#define LSM6DS3_SLAVE0_CONFIG 0x04U +typedef struct { + uint8_t slave0_numop : 3; + uint8_t src_mode : 1; + uint8_t aux_sens_on : 2; + uint8_t slave0_rate : 2; +} lsm6ds3_slave0_config_t; + +#define LSM6DS3_SLV1_ADD 0x05U +typedef struct { + uint8_t r_1 : 1; + uint8_t slave1_add : 7; +} lsm6ds3_slv1_add_t; + +#define LSM6DS3_SLV1_SUBADD 0x06U +typedef struct { + uint8_t slave1_reg : 8; +} lsm6ds3_slv1_subadd_t; + +#define LSM6DS3_SLAVE1_CONFIG 0x07U +typedef struct { + uint8_t slave1_numop : 3; + uint8_t not_used_01 : 3; + uint8_t slave1_rate : 2; +} lsm6ds3_slave1_config_t; + +#define LSM6DS3_SLV2_ADD 0x08U +typedef struct { + uint8_t r_2 : 1; + uint8_t slave2_add : 7; +} lsm6ds3_slv2_add_t; + +#define LSM6DS3_SLV2_SUBADD 0x09U +typedef struct { + uint8_t slave2_reg : 8; +} lsm6ds3_slv2_subadd_t; + +#define LSM6DS3_SLAVE2_CONFIG 0x0AU +typedef struct { + uint8_t slave2_numop : 3; + uint8_t not_used_01 : 3; + uint8_t slave2_rate : 2; +} lsm6ds3_slave2_config_t; + +#define LSM6DS3_SLV3_ADD 0x0BU +typedef struct { + uint8_t r_3 : 1; + uint8_t slave3_add : 7; +} lsm6ds3_slv3_add_t; + +#define LSM6DS3_SLV3_SUBADD 0x0CU +typedef struct { + uint8_t slave3_reg : 8; +} lsm6ds3_slv3_subadd_t; + +#define LSM6DS3_SLAVE3_CONFIG 0x0DU +typedef struct { + uint8_t slave3_numop : 3; + uint8_t not_used_01 : 3; + uint8_t slave3_rate : 2; +} lsm6ds3_slave3_config_t; + +#define LSM6DS3_DATAWRITE_SRC_MODE_SUB_SLV0 0x0EU +typedef struct { + uint8_t slave_dataw : 8; +} lsm6ds3_datawrite_src_mode_sub_slv0_t; + +#define LSM6DS3_PEDO_THS_REG 0x0FU +typedef struct { + uint8_t ths_min : 5; + uint8_t not_used_01 : 2; + uint8_t pedo_4g : 1; +} lsm6ds3_pedo_ths_reg_t; + +#define LSM6DS3_SM_THS 0x13U +typedef struct { + uint8_t sm_ths : 8; +} lsm6ds3_sm_ths_t; + +#define LSM6DS3_PEDO_DEB_REG 0x14U +typedef struct { + uint8_t deb_step : 3; + uint8_t deb_time : 5; +} lsm6ds3_pedo_deb_reg_t; + +#define LSM6DS3_STEP_COUNT_DELTA 0x15U +typedef struct { + uint8_t sc_delta : 8; +} lsm6ds3_step_count_delta_t; + +#define LSM6DS3_MAG_SI_XX 0x24U +#define LSM6DS3_MAG_SI_XY 0x25U +#define LSM6DS3_MAG_SI_XZ 0x26U +#define LSM6DS3_MAG_SI_YX 0x27U +#define LSM6DS3_MAG_SI_YY 0x28U +#define LSM6DS3_MAG_SI_YZ 0x29U +#define LSM6DS3_MAG_SI_ZX 0x2AU +#define LSM6DS3_MAG_SI_ZY 0x2BU +#define LSM6DS3_MAG_SI_ZZ 0x2CU +#define LSM6DS3_MAG_OFFX_L 0x2DU +#define LSM6DS3_MAG_OFFX_H 0x2EU +#define LSM6DS3_MAG_OFFY_L 0x2FU +#define LSM6DS3_MAG_OFFY_H 0x30U +#define LSM6DS3_MAG_OFFZ_L 0x31U +#define LSM6DS3_MAG_OFFZ_H 0x32U + +/** + * @defgroup LSM6DS3_Register_Union + * @brief This union group all the registers that has a bit-field + * description. + * This union is useful but not need by the driver. + * + * REMOVING this union you are compliant with: + * MISRA-C 2012 [Rule 19.2] -> " Union are not allowed " + * + * @{ + * + */ + +typedef union{ + lsm6ds3_func_cfg_access_t func_cfg_access; + lsm6ds3_sensor_sync_time_frame_t sensor_sync_time_frame; + lsm6ds3_fifo_ctrl1_t fifo_ctrl1; + lsm6ds3_fifo_ctrl2_t fifo_ctrl2; + lsm6ds3_fifo_ctrl3_t fifo_ctrl3; + lsm6ds3_fifo_ctrl4_t fifo_ctrl4; + lsm6ds3_fifo_ctrl5_t fifo_ctrl5; + lsm6ds3_orient_cfg_g_t orient_cfg_g; + lsm6ds3_int1_ctrl_t int1_ctrl; + lsm6ds3_int2_ctrl_t int2_ctrl; + lsm6ds3_ctrl1_xl_t ctrl1_xl; + lsm6ds3_ctrl2_g_t ctrl2_g; + lsm6ds3_ctrl3_c_t ctrl3_c; + lsm6ds3_ctrl4_c_t ctrl4_c; + lsm6ds3_ctrl5_c_t ctrl5_c; + lsm6ds3_ctrl6_c_t ctrl6_c; + lsm6ds3_ctrl7_g_t ctrl7_g; + lsm6ds3_ctrl8_xl_t ctrl8_xl; + lsm6ds3_ctrl9_xl_t ctrl9_xl; + lsm6ds3_ctrl10_c_t ctrl10_c; + lsm6ds3_master_config_t master_config; + lsm6ds3_wake_up_src_t wake_up_src; + lsm6ds3_tap_src_t tap_src; + lsm6ds3_d6d_src_t d6d_src; + lsm6ds3_status_reg_t status_reg; + lsm6ds3_sensorhub1_reg_t sensorhub1_reg; + lsm6ds3_sensorhub2_reg_t sensorhub2_reg; + lsm6ds3_sensorhub3_reg_t sensorhub3_reg; + lsm6ds3_sensorhub4_reg_t sensorhub4_reg; + lsm6ds3_sensorhub5_reg_t sensorhub5_reg; + lsm6ds3_sensorhub6_reg_t sensorhub6_reg; + lsm6ds3_sensorhub7_reg_t sensorhub7_reg; + lsm6ds3_sensorhub8_reg_t sensorhub8_reg; + lsm6ds3_sensorhub9_reg_t sensorhub9_reg; + lsm6ds3_sensorhub10_reg_t sensorhub10_reg; + lsm6ds3_sensorhub11_reg_t sensorhub11_reg; + lsm6ds3_sensorhub12_reg_t sensorhub12_reg; + lsm6ds3_fifo_status1_t fifo_status1; + lsm6ds3_fifo_status2_t fifo_status2; + lsm6ds3_fifo_status3_t fifo_status3; + lsm6ds3_fifo_status4_t fifo_status4; + lsm6ds3_sensorhub13_reg_t sensorhub13_reg; + lsm6ds3_sensorhub14_reg_t sensorhub14_reg; + lsm6ds3_sensorhub15_reg_t sensorhub15_reg; + lsm6ds3_sensorhub16_reg_t sensorhub16_reg; + lsm6ds3_sensorhub17_reg_t sensorhub17_reg; + lsm6ds3_sensorhub18_reg_t sensorhub18_reg; + lsm6ds3_func_src_t func_src; + lsm6ds3_tap_cfg_t tap_cfg; + lsm6ds3_tap_ths_6d_t tap_ths_6d; + lsm6ds3_int_dur2_t int_dur2; + lsm6ds3_wake_up_ths_t wake_up_ths; + lsm6ds3_wake_up_dur_t wake_up_dur; + lsm6ds3_free_fall_t free_fall; + lsm6ds3_md1_cfg_t md1_cfg; + lsm6ds3_md2_cfg_t md2_cfg; + lsm6ds3_slv0_add_t slv0_add; + lsm6ds3_slv0_subadd_t slv0_subadd; + lsm6ds3_slave0_config_t slave0_config; + lsm6ds3_slv1_add_t slv1_add; + lsm6ds3_slv1_subadd_t slv1_subadd; + lsm6ds3_slave1_config_t slave1_config; + lsm6ds3_slv2_add_t slv2_add; + lsm6ds3_slv2_subadd_t slv2_subadd; + lsm6ds3_slave2_config_t slave2_config; + lsm6ds3_slv3_add_t slv3_add; + lsm6ds3_slv3_subadd_t slv3_subadd; + lsm6ds3_slave3_config_t slave3_config; + lsm6ds3_datawrite_src_mode_sub_slv0_t datawrite_src_mode_sub_slv0; + lsm6ds3_pedo_ths_reg_t pedo_ths_reg; + lsm6ds3_sm_ths_t sm_ths; + lsm6ds3_pedo_deb_reg_t pedo_deb_reg; + lsm6ds3_step_count_delta_t step_count_delta; + bitwise_t bitwise; + uint8_t byte; +} lsm6ds3_reg_t; + +/** + * @} + * + */ + +int32_t lsm6ds3_read_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t* data, + uint16_t len); +int32_t lsm6ds3_write_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t* data, + uint16_t len); + +extern float_t lsm6ds3_from_fs2g_to_mg(int16_t lsb); +extern float_t lsm6ds3_from_fs4g_to_mg(int16_t lsb); +extern float_t lsm6ds3_from_fs8g_to_mg(int16_t lsb); +extern float_t lsm6ds3_from_fs16g_to_mg(int16_t lsb); + +extern float_t lsm6ds3_from_fs125dps_to_mdps(int16_t lsb); +extern float_t lsm6ds3_from_fs250dps_to_mdps(int16_t lsb); +extern float_t lsm6ds3_from_fs500dps_to_mdps(int16_t lsb); +extern float_t lsm6ds3_from_fs1000dps_to_mdps(int16_t lsb); +extern float_t lsm6ds3_from_fs2000dps_to_mdps(int16_t lsb); + +extern float_t lsm6ds3_from_lsb_to_celsius(int16_t lsb); + +typedef enum { + LSM6DS3_GY_ORIENT_XYZ = 0, + LSM6DS3_GY_ORIENT_XZY = 1, + LSM6DS3_GY_ORIENT_YXZ = 2, + LSM6DS3_GY_ORIENT_YZX = 3, + LSM6DS3_GY_ORIENT_ZXY = 4, + LSM6DS3_GY_ORIENT_ZYX = 5, +} lsm6ds3_gy_orient_t; +int32_t lsm6ds3_gy_data_orient_set(stmdev_ctx_t *ctx, + lsm6ds3_gy_orient_t val); +int32_t lsm6ds3_gy_data_orient_get(stmdev_ctx_t *ctx, + lsm6ds3_gy_orient_t *val); + +typedef enum { + LSM6DS3_GY_SIGN_PPP = 0, + LSM6DS3_GY_SIGN_PPN = 1, + LSM6DS3_GY_SIGN_PNP = 2, + LSM6DS3_GY_SIGN_NPP = 4, + LSM6DS3_GY_SIGN_NNP = 6, + LSM6DS3_GY_SIGN_NPN = 5, + LSM6DS3_GY_SIGN_PNN = 3, + LSM6DS3_GY_SIGN_NNN = 7, +} lsm6ds3_gy_sgn_t; +int32_t lsm6ds3_gy_data_sign_set(stmdev_ctx_t *ctx, lsm6ds3_gy_sgn_t val); +int32_t lsm6ds3_gy_data_sign_get(stmdev_ctx_t *ctx, lsm6ds3_gy_sgn_t *val); + +typedef enum { + LSM6DS3_2g = 0, + LSM6DS3_16g = 1, + LSM6DS3_4g = 2, + LSM6DS3_8g = 3, +} lsm6ds3_xl_fs_t; +int32_t lsm6ds3_xl_full_scale_set(stmdev_ctx_t *ctx, lsm6ds3_xl_fs_t val); +int32_t lsm6ds3_xl_full_scale_get(stmdev_ctx_t *ctx, lsm6ds3_xl_fs_t *val); + +typedef enum { + LSM6DS3_XL_ODR_OFF = 0, + LSM6DS3_XL_ODR_12Hz5 = 1, + LSM6DS3_XL_ODR_26Hz = 2, + LSM6DS3_XL_ODR_52Hz = 3, + LSM6DS3_XL_ODR_104Hz = 4, + LSM6DS3_XL_ODR_208Hz = 5, + LSM6DS3_XL_ODR_416Hz = 6, + LSM6DS3_XL_ODR_833Hz = 7, + LSM6DS3_XL_ODR_1k66Hz = 8, + LSM6DS3_XL_ODR_3k33Hz = 9, + LSM6DS3_XL_ODR_6k66Hz = 10, +} lsm6ds3_odr_xl_t; +int32_t lsm6ds3_xl_data_rate_set(stmdev_ctx_t *ctx, lsm6ds3_odr_xl_t val); +int32_t lsm6ds3_xl_data_rate_get(stmdev_ctx_t *ctx, lsm6ds3_odr_xl_t *val); + +typedef enum { + LSM6DS3_250dps = 0, + LSM6DS3_125dps = 1, + LSM6DS3_500dps = 2, + LSM6DS3_1000dps = 4, + LSM6DS3_2000dps = 6, +} lsm6ds3_fs_g_t; +int32_t lsm6ds3_gy_full_scale_set(stmdev_ctx_t *ctx, lsm6ds3_fs_g_t val); +int32_t lsm6ds3_gy_full_scale_get(stmdev_ctx_t *ctx, lsm6ds3_fs_g_t *val); + +typedef enum { + LSM6DS3_GY_ODR_OFF = 0, + LSM6DS3_GY_ODR_12Hz5 = 1, + LSM6DS3_GY_ODR_26Hz = 2, + LSM6DS3_GY_ODR_52Hz = 3, + LSM6DS3_GY_ODR_104Hz = 4, + LSM6DS3_GY_ODR_208Hz = 5, + LSM6DS3_GY_ODR_416Hz = 6, + LSM6DS3_GY_ODR_833Hz = 7, + LSM6DS3_GY_ODR_1k66Hz = 8, +} lsm6ds3_odr_g_t; +int32_t lsm6ds3_gy_data_rate_set(stmdev_ctx_t *ctx, lsm6ds3_odr_g_t val); +int32_t lsm6ds3_gy_data_rate_get(stmdev_ctx_t *ctx, lsm6ds3_odr_g_t *val); + +int32_t lsm6ds3_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6ds3_block_data_update_get(stmdev_ctx_t *ctx, uint8_t *val); + +typedef enum { + LSM6DS3_XL_HIGH_PERFORMANCE = 0, + LSM6DS3_XL_NORMAL = 1, +} lsm6ds3_xl_hm_mode_t; +int32_t lsm6ds3_xl_power_mode_set(stmdev_ctx_t *ctx, + lsm6ds3_xl_hm_mode_t val); +int32_t lsm6ds3_xl_power_mode_get(stmdev_ctx_t *ctx, + lsm6ds3_xl_hm_mode_t *val); + +typedef enum { + LSM6DS3_STAT_RND_DISABLE = 0, + LSM6DS3_STAT_RND_ENABLE = 1, +} lsm6ds3_rnd_stat_t; +int32_t lsm6ds3_rounding_on_status_set(stmdev_ctx_t *ctx, + lsm6ds3_rnd_stat_t val); +int32_t lsm6ds3_rounding_on_status_get(stmdev_ctx_t *ctx, + lsm6ds3_rnd_stat_t *val); + +typedef enum { + LSM6DS3_GY_HIGH_PERFORMANCE = 0, + LSM6DS3_GY_NORMAL = 1, +} lsm6ds3_g_hm_mode_t; +int32_t lsm6ds3_gy_power_mode_set(stmdev_ctx_t *ctx, + lsm6ds3_g_hm_mode_t val); +int32_t lsm6ds3_gy_power_mode_get(stmdev_ctx_t *ctx, + lsm6ds3_g_hm_mode_t *val); + +int32_t lsm6ds3_xl_axis_x_data_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6ds3_xl_axis_x_data_get(stmdev_ctx_t *ctx, uint8_t *val); + +int32_t lsm6ds3_xl_axis_y_data_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6ds3_xl_axis_y_data_get(stmdev_ctx_t *ctx, uint8_t *val); + +int32_t lsm6ds3_xl_axis_z_data_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6ds3_xl_axis_z_data_get(stmdev_ctx_t *ctx, uint8_t *val); + +int32_t lsm6ds3_gy_axis_x_data_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6ds3_gy_axis_x_data_get(stmdev_ctx_t *ctx, uint8_t *val); + +int32_t lsm6ds3_gy_axis_y_data_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6ds3_gy_axis_y_data_get(stmdev_ctx_t *ctx, uint8_t *val); + +int32_t lsm6ds3_gy_axis_z_data_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6ds3_gy_axis_z_data_get(stmdev_ctx_t *ctx, uint8_t *val); + +typedef struct { + lsm6ds3_wake_up_src_t wake_up_src; + lsm6ds3_tap_src_t tap_src; + lsm6ds3_d6d_src_t d6d_src; + lsm6ds3_func_src_t func_src; +} lsm6ds3_all_src_t; +int32_t lsm6ds3_all_sources_get(stmdev_ctx_t *ctx, lsm6ds3_all_src_t *val); + +int32_t lsm6ds3_status_reg_get(stmdev_ctx_t *ctx, lsm6ds3_status_reg_t *val); + +int32_t lsm6ds3_xl_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val); + +int32_t lsm6ds3_gy_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val); + +int32_t lsm6ds3_temp_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val); + +int32_t lsm6ds3_timestamp_raw_get(stmdev_ctx_t *ctx, uint8_t *buff); + +int32_t lsm6ds3_timestamp_rst_set(stmdev_ctx_t *ctx); + +int32_t lsm6ds3_timestamp_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6ds3_timestamp_get(stmdev_ctx_t *ctx, uint8_t *val); +typedef enum { + LSM6DS3_LSB_6ms4 = 0, + LSM6DS3_LSB_25us = 1, +} lsm6ds3_ts_res_t; +int32_t lsm6ds3_timestamp_res_set(stmdev_ctx_t *ctx, lsm6ds3_ts_res_t val); +int32_t lsm6ds3_timestamp_res_get(stmdev_ctx_t *ctx, lsm6ds3_ts_res_t *val); + +typedef enum { + LSM6DS3_ROUND_DISABLE = 0, + LSM6DS3_ROUND_XL = 1, + LSM6DS3_ROUND_GY = 2, + LSM6DS3_ROUND_GY_XL = 3, + LSM6DS3_ROUND_SH1_TO_SH6 = 4, + LSM6DS3_ROUND_XL_SH1_TO_SH6 = 5, + LSM6DS3_ROUND_GY_XL_SH1_TO_SH12 = 6, + LSM6DS3_ROUND_GY_XL_SH1_TO_SH6 = 7, +} lsm6ds3_rounding_t; +int32_t lsm6ds3_rounding_mode_set(stmdev_ctx_t *ctx, + lsm6ds3_rounding_t val); +int32_t lsm6ds3_rounding_mode_get(stmdev_ctx_t *ctx, + lsm6ds3_rounding_t *val); + +int32_t lsm6ds3_temperature_raw_get(stmdev_ctx_t *ctx, uint8_t *buff); + +int32_t lsm6ds3_angular_rate_raw_get(stmdev_ctx_t *ctx, uint8_t *buff); + +int32_t lsm6ds3_acceleration_raw_get(stmdev_ctx_t *ctx, uint8_t *buff); + +int32_t lsm6ds3_fifo_raw_data_get(stmdev_ctx_t *ctx, uint8_t *buffer, uint8_t len); + +int32_t lsm6ds3_number_of_steps_get(stmdev_ctx_t *ctx, uint8_t *buff); + +int32_t lsm6ds3_mag_calibrated_raw_get(stmdev_ctx_t *ctx, uint8_t *buff); + +typedef enum { + LSM6DS3_USER_BANK = 0, + LSM6DS3_EMBEDDED_FUNC_BANK = 1, +} lsm6ds3_func_cfg_en_t; +int32_t lsm6ds3_mem_bank_set(stmdev_ctx_t *ctx, lsm6ds3_func_cfg_en_t val); +int32_t lsm6ds3_mem_bank_get(stmdev_ctx_t *ctx, lsm6ds3_func_cfg_en_t *val); + +int32_t lsm6ds3_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff); + +int32_t lsm6ds3_reset_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6ds3_reset_get(stmdev_ctx_t *ctx, uint8_t *val); + +typedef enum { + LSM6DS3_LSB_AT_LOW_ADD = 0, + LSM6DS3_MSB_AT_LOW_ADD = 1, +} lsm6ds3_ble_t; +int32_t lsm6ds3_data_format_set(stmdev_ctx_t *ctx, lsm6ds3_ble_t val); +int32_t lsm6ds3_data_format_get(stmdev_ctx_t *ctx, lsm6ds3_ble_t *val); + +int32_t lsm6ds3_auto_increment_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6ds3_auto_increment_get(stmdev_ctx_t *ctx, uint8_t *val); + +int32_t lsm6ds3_boot_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6ds3_boot_get(stmdev_ctx_t *ctx, uint8_t *val); + +typedef enum { + LSM6DS3_XL_ST_DISABLE = 0, + LSM6DS3_XL_ST_POSITIVE = 1, + LSM6DS3_XL_ST_NEGATIVE = 2, +} lsm6ds3_st_xl_t; +int32_t lsm6ds3_xl_self_test_set(stmdev_ctx_t *ctx, lsm6ds3_st_xl_t val); +int32_t lsm6ds3_xl_self_test_get(stmdev_ctx_t *ctx, lsm6ds3_st_xl_t *val); + +typedef enum { + LSM6DS3_GY_ST_DISABLE = 0, + LSM6DS3_GY_ST_POSITIVE = 1, + LSM6DS3_GY_ST_NEGATIVE = 3, +} lsm6ds3_st_g_t; +int32_t lsm6ds3_gy_self_test_set(stmdev_ctx_t *ctx, lsm6ds3_st_g_t val); +int32_t lsm6ds3_gy_self_test_get(stmdev_ctx_t *ctx, lsm6ds3_st_g_t *val); + +int32_t lsm6ds3_filter_settling_mask_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6ds3_filter_settling_mask_get(stmdev_ctx_t *ctx, uint8_t *val); + +typedef enum { + LSM6DS3_HP_CUT_OFF_8mHz1 = 0, + LSM6DS3_HP_CUT_OFF_32mHz4 = 1, + LSM6DS3_HP_CUT_OFF_2Hz07 = 2, + LSM6DS3_HP_CUT_OFF_16Hz32 = 3, +} lsm6ds3_hpcf_g_t; +int32_t lsm6ds3_gy_hp_bandwidth_set(stmdev_ctx_t *ctx, lsm6ds3_hpcf_g_t val); +int32_t lsm6ds3_gy_hp_bandwidth_get(stmdev_ctx_t *ctx, lsm6ds3_hpcf_g_t *val); + +int32_t lsm6ds3_gy_hp_reset_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6ds3_gy_hp_reset_get(stmdev_ctx_t *ctx, uint8_t *val); + +typedef enum { + LSM6DS3_XL_HP_ODR_DIV_4 = 0, + LSM6DS3_XL_HP_ODR_DIV_100 = 1, + LSM6DS3_XL_HP_ODR_DIV_9 = 2, + LSM6DS3_XL_HP_ODR_DIV_400 = 3, +} lsm6ds3_hp_bw_t; +int32_t lsm6ds3_xl_hp_bandwidth_set(stmdev_ctx_t *ctx, lsm6ds3_hp_bw_t val); +int32_t lsm6ds3_xl_hp_bandwidth_get(stmdev_ctx_t *ctx, lsm6ds3_hp_bw_t *val); + +typedef enum { + LSM6DS3_XL_LP_ODR_DIV_50 = 0, + LSM6DS3_XL_LP_ODR_DIV_100 = 1, + LSM6DS3_XL_LP_ODR_DIV_9 = 2, + LSM6DS3_XL_LP_ODR_DIV_400 = 3, +} lsm6ds3_lp_bw_t; +int32_t lsm6ds3_xl_lp2_bandwidth_set(stmdev_ctx_t *ctx, lsm6ds3_lp_bw_t val); +int32_t lsm6ds3_xl_lp2_bandwidth_get(stmdev_ctx_t *ctx, lsm6ds3_lp_bw_t *val); + +typedef enum { + LSM6DS3_ANTI_ALIASING_400Hz = 0, + LSM6DS3_ANTI_ALIASING_200Hz = 1, + LSM6DS3_ANTI_ALIASING_100Hz = 2, + LSM6DS3_ANTI_ALIASING_50Hz = 3, +} lsm6ds3_bw_xl_t; +int32_t lsm6ds3_xl_filter_analog_set(stmdev_ctx_t *ctx, lsm6ds3_bw_xl_t val); +int32_t lsm6ds3_xl_filter_analog_get(stmdev_ctx_t *ctx, lsm6ds3_bw_xl_t *val); + +typedef enum { + LSM6DS3_SPI_4_WIRE = 0, + LSM6DS3_SPI_3_WIRE = 1, +} lsm6ds3_sim_t; +int32_t lsm6ds3_spi_mode_set(stmdev_ctx_t *ctx, lsm6ds3_sim_t val); +int32_t lsm6ds3_spi_mode_get(stmdev_ctx_t *ctx, lsm6ds3_sim_t *val); + +typedef enum { + LSM6DS3_I2C_ENABLE = 0, + LSM6DS3_I2C_DISABLE = 1, +} lsm6ds3_i2c_dis_t; +int32_t lsm6ds3_i2c_interface_set(stmdev_ctx_t *ctx, lsm6ds3_i2c_dis_t val); +int32_t lsm6ds3_i2c_interface_get(stmdev_ctx_t *ctx, lsm6ds3_i2c_dis_t *val); + +typedef struct { + uint8_t int1_drdy_xl : 1; + uint8_t int1_drdy_g : 1; + uint8_t int1_boot : 1; + uint8_t int1_fth : 1; + uint8_t int1_fifo_ovr : 1; + uint8_t int1_full_flag : 1; + uint8_t int1_sign_mot : 1; + uint8_t int1_step_detector : 1; + uint8_t int1_timer : 1; + uint8_t int1_tilt : 1; + uint8_t int1_6d : 1; + uint8_t int1_double_tap : 1; + uint8_t int1_ff : 1; + uint8_t int1_wu : 1; + uint8_t int1_single_tap : 1; + uint8_t int1_inact_state : 1; + uint8_t drdy_on_int1 : 1; +} lsm6ds3_int1_route_t; +int32_t lsm6ds3_pin_int1_route_set(stmdev_ctx_t *ctx, + lsm6ds3_int1_route_t *val); +int32_t lsm6ds3_pin_int1_route_get(stmdev_ctx_t *ctx, + lsm6ds3_int1_route_t *val); + +typedef struct { + uint8_t int2_drdy_xl : 1; + uint8_t int2_drdy_g : 1; + uint8_t int2_drdy_temp : 1; + uint8_t int2_fth : 1; + uint8_t int2_fifo_ovr : 1; + uint8_t int2_full_flag : 1; + uint8_t int2_step_count_ov : 1; + uint8_t int2_step_delta : 1; + uint8_t int2_iron : 1; + uint8_t int2_tilt : 1; + uint8_t int2_6d : 1; + uint8_t int2_double_tap : 1; + uint8_t int2_ff : 1; + uint8_t int2_wu : 1; + uint8_t int2_single_tap : 1; + uint8_t int2_inact_state : 1; + uint8_t start_config : 1; +} lsm6ds3_int2_route_t; +int32_t lsm6ds3_pin_int2_route_set(stmdev_ctx_t *ctx, lsm6ds3_int2_route_t *val); +int32_t lsm6ds3_pin_int2_route_get(stmdev_ctx_t *ctx, lsm6ds3_int2_route_t *val); + +typedef enum { + LSM6DS3_PUSH_PULL = 0, + LSM6DS3_OPEN_DRAIN = 1, +} lsm6ds3_pp_od_t; +int32_t lsm6ds3_pin_mode_set(stmdev_ctx_t *ctx, lsm6ds3_pp_od_t val); +int32_t lsm6ds3_pin_mode_get(stmdev_ctx_t *ctx, lsm6ds3_pp_od_t *val); + +typedef enum { + LSM6DS3_ACTIVE_HIGH = 0, + LSM6DS3_ACTIVE_LOW = 1, +} lsm6ds3_pin_pol_t; +int32_t lsm6ds3_pin_polarity_set(stmdev_ctx_t *ctx, lsm6ds3_pin_pol_t val); +int32_t lsm6ds3_pin_polarity_get(stmdev_ctx_t *ctx, lsm6ds3_pin_pol_t *val); + +int32_t lsm6ds3_all_on_int1_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6ds3_all_on_int1_get(stmdev_ctx_t *ctx, uint8_t *val); + +typedef enum { + LSM6DS3_INT_PULSED = 0, + LSM6DS3_INT_LATCHED = 1, +} lsm6ds3_lir_t; +int32_t lsm6ds3_int_notification_set(stmdev_ctx_t *ctx, lsm6ds3_lir_t val); +int32_t lsm6ds3_int_notification_get(stmdev_ctx_t *ctx, lsm6ds3_lir_t *val); + +int32_t lsm6ds3_wkup_src_get(stmdev_ctx_t *ctx, lsm6ds3_wake_up_src_t *val); + +int32_t lsm6ds3_wkup_threshold_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6ds3_wkup_threshold_get(stmdev_ctx_t *ctx, uint8_t *val); + +int32_t lsm6ds3_wkup_dur_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6ds3_wkup_dur_get(stmdev_ctx_t *ctx, uint8_t *val); + +int32_t lsm6ds3_gy_sleep_mode_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6ds3_gy_sleep_mode_get(stmdev_ctx_t *ctx, uint8_t *val); + +int32_t lsm6ds3_act_mode_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6ds3_act_mode_get(stmdev_ctx_t *ctx, uint8_t *val); + +int32_t lsm6ds3_act_sleep_dur_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6ds3_act_sleep_dur_get(stmdev_ctx_t *ctx, uint8_t *val); + +int32_t lsm6ds3_tap_src_get(stmdev_ctx_t *ctx, lsm6ds3_tap_src_t *val); + +int32_t lsm6ds3_tap_detection_on_z_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6ds3_tap_detection_on_z_get(stmdev_ctx_t *ctx, uint8_t *val); + +int32_t lsm6ds3_tap_detection_on_y_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6ds3_tap_detection_on_y_get(stmdev_ctx_t *ctx, uint8_t *val); + +int32_t lsm6ds3_tap_detection_on_x_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6ds3_tap_detection_on_x_get(stmdev_ctx_t *ctx, uint8_t *val); + +int32_t lsm6ds3_tap_threshold_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6ds3_tap_threshold_get(stmdev_ctx_t *ctx, uint8_t *val); + +int32_t lsm6ds3_tap_shock_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6ds3_tap_shock_get(stmdev_ctx_t *ctx, uint8_t *val); + +int32_t lsm6ds3_tap_quiet_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6ds3_tap_quiet_get(stmdev_ctx_t *ctx, uint8_t *val); + +int32_t lsm6ds3_tap_dur_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6ds3_tap_dur_get(stmdev_ctx_t *ctx, uint8_t *val); + +typedef enum { + LSM6DS3_ONLY_DOUBLE = 1, + LSM6DS3_SINGLE_DOUBLE = 0, +} lsm6ds3_tap_md_t; +int32_t lsm6ds3_tap_mode_set(stmdev_ctx_t *ctx, lsm6ds3_tap_md_t val); +int32_t lsm6ds3_tap_mode_get(stmdev_ctx_t *ctx, lsm6ds3_tap_md_t *val); + +typedef enum { + LSM6DS3_ODR_DIV_2_FEED = 0, + LSM6DS3_LPF2_FEED = 1, +} lsm6ds3_low_pass_on_6d_t; +int32_t lsm6ds3_6d_feed_data_set(stmdev_ctx_t *ctx, + lsm6ds3_low_pass_on_6d_t val); +int32_t lsm6ds3_6d_feed_data_get(stmdev_ctx_t *ctx, + lsm6ds3_low_pass_on_6d_t *val); + +int32_t lsm6ds3_6d_src_get(stmdev_ctx_t *ctx, lsm6ds3_d6d_src_t *val); + +typedef enum { + LSM6DS3_DEG_80 = 0, + LSM6DS3_DEG_70 = 1, + LSM6DS3_DEG_60 = 2, + LSM6DS3_DEG_50 = 3, +} lsm6ds3_sixd_ths_t; +int32_t lsm6ds3_6d_threshold_set(stmdev_ctx_t *ctx, lsm6ds3_sixd_ths_t val); +int32_t lsm6ds3_6d_threshold_get(stmdev_ctx_t *ctx, lsm6ds3_sixd_ths_t *val); + +int32_t lsm6ds3_4d_mode_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6ds3_4d_mode_get(stmdev_ctx_t *ctx, uint8_t *val); + +typedef enum { + LSM6DS3_156_mg = 0, + LSM6DS3_219_mg = 1, + LSM6DS3_250_mg = 2, + LSM6DS3_312_mg = 3, + LSM6DS3_344_mg = 4, + LSM6DS3_406_mg = 5, + LSM6DS3_469_mg = 6, + LSM6DS3_500_mg = 7, +} lsm6ds3_ff_ths_t; +int32_t lsm6ds3_ff_threshold_set(stmdev_ctx_t *ctx, lsm6ds3_ff_ths_t val); +int32_t lsm6ds3_ff_threshold_get(stmdev_ctx_t *ctx, lsm6ds3_ff_ths_t *val); + +int32_t lsm6ds3_ff_dur_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6ds3_ff_dur_get(stmdev_ctx_t *ctx, uint8_t *val); + +int32_t lsm6ds3_fifo_watermark_set(stmdev_ctx_t *ctx, uint16_t val); +int32_t lsm6ds3_fifo_watermark_get(stmdev_ctx_t *ctx, uint16_t *val); + +typedef enum { + LSM6DS3_TRG_XL_GY_DRDY = 0, + LSM6DS3_TRG_STEP_DETECT = 1, +} lsm6ds3_tmr_ped_fifo_drdy_t; +int32_t lsm6ds3_fifo_write_trigger_set(stmdev_ctx_t *ctx, + lsm6ds3_tmr_ped_fifo_drdy_t val); +int32_t lsm6ds3_fifo_write_trigger_get(stmdev_ctx_t *ctx, + lsm6ds3_tmr_ped_fifo_drdy_t *val); + +int32_t lsm6ds3_fifo_pedo_batch_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6ds3_fifo_pedo_batch_get(stmdev_ctx_t *ctx, uint8_t *val); + +typedef enum { + LSM6DS3_FIFO_XL_DISABLE = 0, + LSM6DS3_FIFO_XL_NO_DEC = 1, + LSM6DS3_FIFO_XL_DEC_2 = 2, + LSM6DS3_FIFO_XL_DEC_3 = 3, + LSM6DS3_FIFO_XL_DEC_4 = 4, + LSM6DS3_FIFO_XL_DEC_8 = 5, + LSM6DS3_FIFO_XL_DEC_16 = 6, + LSM6DS3_FIFO_XL_DEC_32 = 7, +} lsm6ds3_dec_fifo_xl_t; +int32_t lsm6ds3_fifo_xl_batch_set(stmdev_ctx_t *ctx, + lsm6ds3_dec_fifo_xl_t val); +int32_t lsm6ds3_fifo_xl_batch_get(stmdev_ctx_t *ctx, + lsm6ds3_dec_fifo_xl_t *val); + +typedef enum { + LSM6DS3_FIFO_GY_DISABLE = 0, + LSM6DS3_FIFO_GY_NO_DEC = 1, + LSM6DS3_FIFO_GY_DEC_2 = 2, + LSM6DS3_FIFO_GY_DEC_3 = 3, + LSM6DS3_FIFO_GY_DEC_4 = 4, + LSM6DS3_FIFO_GY_DEC_8 = 5, + LSM6DS3_FIFO_GY_DEC_16 = 6, + LSM6DS3_FIFO_GY_DEC_32 = 7, +} lsm6ds3_dec_fifo_gyro_t; +int32_t lsm6ds3_fifo_gy_batch_set(stmdev_ctx_t *ctx, + lsm6ds3_dec_fifo_gyro_t val); +int32_t lsm6ds3_fifo_gy_batch_get(stmdev_ctx_t *ctx, + lsm6ds3_dec_fifo_gyro_t *val); + +typedef enum { + LSM6DS3_FIFO_DS3_DISABLE = 0, + LSM6DS3_FIFO_DS3_NO_DEC = 1, + LSM6DS3_FIFO_DS3_DEC_2 = 2, + LSM6DS3_FIFO_DS3_DEC_3 = 3, + LSM6DS3_FIFO_DS3_DEC_4 = 4, + LSM6DS3_FIFO_DS3_DEC_8 = 5, + LSM6DS3_FIFO_DS3_DEC_16 = 6, + LSM6DS3_FIFO_DS3_DEC_32 = 7, +} lsm6ds3_dec_ds3_fifo_t; +int32_t lsm6ds3_fifo_dataset_3_batch_set(stmdev_ctx_t *ctx, + lsm6ds3_dec_ds3_fifo_t val); +int32_t lsm6ds3_fifo_dataset_3_batch_get(stmdev_ctx_t *ctx, + lsm6ds3_dec_ds3_fifo_t *val); + +typedef enum { + LSM6DS3_FIFO_DS4_DISABLE = 0, + LSM6DS3_FIFO_DS4_NO_DEC = 1, + LSM6DS3_FIFO_DS4_DEC_2 = 2, + LSM6DS3_FIFO_DS4_DEC_3 = 3, + LSM6DS3_FIFO_DS4_DEC_4 = 4, + LSM6DS3_FIFO_DS4_DEC_8 = 5, + LSM6DS3_FIFO_DS4_DEC_16 = 6, + LSM6DS3_FIFO_DS4_DEC_32 = 7, +} lsm6ds3_dec_ds4_fifo_t; +int32_t lsm6ds3_fifo_dataset_4_batch_set(stmdev_ctx_t *ctx, + lsm6ds3_dec_ds4_fifo_t val); +int32_t lsm6ds3_fifo_dataset_4_batch_get(stmdev_ctx_t *ctx, + lsm6ds3_dec_ds4_fifo_t *val); + +int32_t lsm6ds3_fifo_xl_gy_8bit_format_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6ds3_fifo_xl_gy_8bit_format_get(stmdev_ctx_t *ctx, uint8_t *val); + +typedef enum { + LSM6DS3_BYPASS_MODE = 0, + LSM6DS3_FIFO_MODE = 1, + LSM6DS3_STREAM_TO_FIFO_MODE = 3, + LSM6DS3_BYPASS_TO_STREAM_MODE = 4, + LSM6DS3_STREAM_MODE = 6, +} lsm6ds3_fifo_md_t; +int32_t lsm6ds3_fifo_mode_set(stmdev_ctx_t *ctx, lsm6ds3_fifo_md_t val); +int32_t lsm6ds3_fifo_mode_get(stmdev_ctx_t *ctx, lsm6ds3_fifo_md_t *val); + +typedef enum { + LSM6DS3_FIFO_DISABLE = 0, + LSM6DS3_FIFO_12Hz5 = 1, + LSM6DS3_FIFO_26Hz = 2, + LSM6DS3_FIFO_52Hz = 3, + LSM6DS3_FIFO_104Hz = 4, + LSM6DS3_FIFO_208Hz = 5, + LSM6DS3_FIFO_416Hz = 6, + LSM6DS3_FIFO_833Hz = 7, + LSM6DS3_FIFO_1k66Hz = 8, + LSM6DS3_FIFO_3k33Hz = 9, + LSM6DS3_FIFO_6k66Hz = 10, +} lsm6ds3_odr_fifo_t; +int32_t lsm6ds3_fifo_data_rate_set(stmdev_ctx_t *ctx, + lsm6ds3_odr_fifo_t val); +int32_t lsm6ds3_fifo_data_rate_get(stmdev_ctx_t *ctx, + lsm6ds3_odr_fifo_t *val); + +int32_t lsm6ds3_fifo_stop_on_wtm_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6ds3_fifo_stop_on_wtm_get(stmdev_ctx_t *ctx, uint8_t *val); + +int32_t lsm6ds3_fifo_temp_batch_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6ds3_fifo_temp_batch_get(stmdev_ctx_t *ctx, uint8_t *val); + +int32_t lsm6ds3_fifo_data_level_get(stmdev_ctx_t *ctx, uint16_t *val); + +int32_t lsm6ds3_fifo_full_flag_get(stmdev_ctx_t *ctx, uint8_t *val); + +int32_t lsm6ds3_fifo_ovr_flag_get(stmdev_ctx_t *ctx, uint8_t *val); + +int32_t lsm6ds3_fifo_wtm_flag_get(stmdev_ctx_t *ctx, uint8_t *val); + +int32_t lsm6ds3_fifo_pattern_get(stmdev_ctx_t *ctx, uint16_t *val); + +typedef enum { + LSM6DS3_DEN_DISABLE = 0, + LSM6DS3_LEVEL_FIFO = 6, + LSM6DS3_LEVEL_LETCHED = 3, + LSM6DS3_LEVEL_TRIGGER = 2, + LSM6DS3_EDGE_TRIGGER = 4, +} lsm6ds3_den_mode_t; +int32_t lsm6ds3_den_mode_set(stmdev_ctx_t *ctx, lsm6ds3_den_mode_t val); +int32_t lsm6ds3_den_mode_get(stmdev_ctx_t *ctx, lsm6ds3_den_mode_t *val); + +int32_t lsm6ds3_pedo_step_reset_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6ds3_pedo_step_reset_get(stmdev_ctx_t *ctx, uint8_t *val); + +int32_t lsm6ds3_pedo_timestamp_raw_get(stmdev_ctx_t *ctx, uint8_t *buff); + +int32_t lsm6ds3_pedo_step_detect_flag_get(stmdev_ctx_t *ctx, uint8_t *val); + +int32_t lsm6ds3_pedo_sens_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6ds3_pedo_sens_get(stmdev_ctx_t *ctx, uint8_t *val); + +int32_t lsm6ds3_pedo_threshold_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6ds3_pedo_threshold_get(stmdev_ctx_t *ctx, uint8_t *val); + +typedef enum { + LSM6DS3_PEDO_AT_2g = 0, + LSM6DS3_PEDO_AT_4g = 1, +} lsm6ds3_pedo_fs_t; +int32_t lsm6ds3_pedo_full_scale_set(stmdev_ctx_t *ctx, + lsm6ds3_pedo_fs_t val); +int32_t lsm6ds3_pedo_full_scale_get(stmdev_ctx_t *ctx, + lsm6ds3_pedo_fs_t *val); + +int32_t lsm6ds3_pedo_debounce_steps_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6ds3_pedo_debounce_steps_get(stmdev_ctx_t *ctx, uint8_t *val); + +int32_t lsm6ds3_pedo_timeout_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6ds3_pedo_timeout_get(stmdev_ctx_t *ctx, uint8_t *val); + +int32_t lsm6ds3_motion_sens_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6ds3_motion_sens_get(stmdev_ctx_t *ctx, uint8_t *val); + +int32_t lsm6ds3_motion_event_flag_get(stmdev_ctx_t *ctx, uint8_t *val); + +int32_t lsm6ds3_motion_threshold_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6ds3_motion_threshold_get(stmdev_ctx_t *ctx, uint8_t *val); + +int32_t lsm6ds3_sc_delta_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6ds3_sc_delta_get(stmdev_ctx_t *ctx, uint8_t *val); + +int32_t lsm6ds3_tilt_event_flag_get(stmdev_ctx_t *ctx, uint8_t *val); + +int32_t lsm6ds3_tilt_sens_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6ds3_tilt_sens_get(stmdev_ctx_t *ctx, uint8_t *val); + +int32_t lsm6ds3_mag_soft_iron_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6ds3_mag_soft_iron_get(stmdev_ctx_t *ctx, uint8_t *val); + +int32_t lsm6ds3_mag_hard_iron_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6ds3_mag_hard_iron_get(stmdev_ctx_t *ctx, uint8_t *val); + +int32_t lsm6ds3_mag_soft_iron_end_op_flag_get(stmdev_ctx_t *ctx, + uint8_t *val); + +int32_t lsm6ds3_mag_soft_iron_coeff_set(stmdev_ctx_t *ctx, uint8_t *buff); +int32_t lsm6ds3_mag_soft_iron_coeff_get(stmdev_ctx_t *ctx, uint8_t *buff); + +int32_t lsm6ds3_mag_offset_set(stmdev_ctx_t *ctx, uint8_t *buff); +int32_t lsm6ds3_mag_offset_get(stmdev_ctx_t *ctx, uint8_t *buff); + +int32_t lsm6ds3_sh_sync_sens_frame_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6ds3_sh_sync_sens_frame_get(stmdev_ctx_t *ctx, uint8_t *val); + +int32_t lsm6ds3_sh_master_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6ds3_sh_master_get(stmdev_ctx_t *ctx, uint8_t *val); + +int32_t lsm6ds3_sh_pass_through_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6ds3_sh_pass_through_get(stmdev_ctx_t *ctx, uint8_t *val); + +typedef enum { + LSM6DS3_EXT_PULL_UP = 0, + LSM6DS3_INTERNAL_PULL_UP = 1, +} lsm6ds3_sh_pin_md_t; +int32_t lsm6ds3_sh_pin_mode_set(stmdev_ctx_t *ctx, lsm6ds3_sh_pin_md_t val); +int32_t lsm6ds3_sh_pin_mode_get(stmdev_ctx_t *ctx, lsm6ds3_sh_pin_md_t *val); + +typedef enum { + LSM6DS3_XL_GY_DRDY = 0, + LSM6DS3_EXT_ON_INT2_PIN = 1, +} lsm6ds3_start_cfg_t; +int32_t lsm6ds3_sh_syncro_mode_set(stmdev_ctx_t *ctx, + lsm6ds3_start_cfg_t val); +int32_t lsm6ds3_sh_syncro_mode_get(stmdev_ctx_t *ctx, + lsm6ds3_start_cfg_t *val); + +typedef struct { + lsm6ds3_sensorhub1_reg_t sh_byte_1; + lsm6ds3_sensorhub2_reg_t sh_byte_2; + lsm6ds3_sensorhub3_reg_t sh_byte_3; + lsm6ds3_sensorhub4_reg_t sh_byte_4; + lsm6ds3_sensorhub5_reg_t sh_byte_5; + lsm6ds3_sensorhub6_reg_t sh_byte_6; + lsm6ds3_sensorhub7_reg_t sh_byte_7; + lsm6ds3_sensorhub8_reg_t sh_byte_8; + lsm6ds3_sensorhub9_reg_t sh_byte_9; + lsm6ds3_sensorhub10_reg_t sh_byte_10; + lsm6ds3_sensorhub11_reg_t sh_byte_11; + lsm6ds3_sensorhub12_reg_t sh_byte_12; + lsm6ds3_sensorhub13_reg_t sh_byte_13; + lsm6ds3_sensorhub14_reg_t sh_byte_14; + lsm6ds3_sensorhub15_reg_t sh_byte_15; + lsm6ds3_sensorhub16_reg_t sh_byte_16; + lsm6ds3_sensorhub17_reg_t sh_byte_17; + lsm6ds3_sensorhub18_reg_t sh_byte_18; +} lsm6ds3_sh_read_t; +int32_t lsm6ds3_sh_read_data_raw_get(stmdev_ctx_t *ctx, + lsm6ds3_sh_read_t *buff); + +typedef enum { + LSM6DS3_SLV_0 = 0, + LSM6DS3_SLV_0_1 = 1, + LSM6DS3_SLV_0_1_2 = 2, + LSM6DS3_SLV_0_1_2_3 = 3, +} lsm6ds3_aux_sens_on_t; +int32_t lsm6ds3_sh_num_of_dev_connected_set(stmdev_ctx_t *ctx, + lsm6ds3_aux_sens_on_t val); +int32_t lsm6ds3_sh_num_of_dev_connected_get(stmdev_ctx_t *ctx, + lsm6ds3_aux_sens_on_t *val); + +typedef struct{ + uint8_t slv0_add; + uint8_t slv0_subadd; + uint8_t slv0_data; +} lsm6ds3_sh_cfg_write_t; +int32_t lsm6ds3_sh_cfg_write(stmdev_ctx_t *ctx, lsm6ds3_sh_cfg_write_t *val); + +typedef struct{ + uint8_t slv_add; + uint8_t slv_subadd; + uint8_t slv_len; +} lsm6ds3_sh_cfg_read_t; +int32_t lsm6ds3_sh_slv0_cfg_read(stmdev_ctx_t *ctx, + lsm6ds3_sh_cfg_read_t *val); +int32_t lsm6ds3_sh_slv1_cfg_read(stmdev_ctx_t *ctx, + lsm6ds3_sh_cfg_read_t *val); +int32_t lsm6ds3_sh_slv2_cfg_read(stmdev_ctx_t *ctx, + lsm6ds3_sh_cfg_read_t *val); +int32_t lsm6ds3_sh_slv3_cfg_read(stmdev_ctx_t *ctx, + lsm6ds3_sh_cfg_read_t *val); + +int32_t lsm6ds3_sh_end_op_flag_get(stmdev_ctx_t *ctx, uint8_t *val); + +typedef enum { + LSM6DS3_USE_SLOPE = 0, + LSM6DS3_USE_HPF = 1, +} lsm6ds3_slope_fds_t; +int32_t lsm6ds3_xl_hp_path_internal_set(stmdev_ctx_t *ctx, + lsm6ds3_slope_fds_t val); +int32_t lsm6ds3_xl_hp_path_internal_get(stmdev_ctx_t *ctx, + lsm6ds3_slope_fds_t *val); + +/** + *@} + * + */ + +#ifdef __cplusplus +} +#endif + +#endif /* LSM6DS3_REGS_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/st/include/lsm6ds3tr_c_reg.h b/src/st/include/lsm6ds3tr_c_reg.h new file mode 100644 index 000000000..9ea4569cd --- /dev/null +++ b/src/st/include/lsm6ds3tr_c_reg.h @@ -0,0 +1,1893 @@ +/* + ****************************************************************************** + * @file lsm6ds3tr_c_reg.h + * @author Sensors Software Solution Team + * @brief This file contains all the functions prototypes for the + * lsm6ds3tr_c_reg.c driver. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2019 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef LSM6DS3TR_C_DRIVER_H +#define LSM6DS3TR_C_DRIVER_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include +#include + +/** @addtogroup LSM6DS3TR_C + * @{ + * + */ + +/** @defgroup STMicroelectronics sensors common types + * @{ + * + */ + +#ifndef MEMS_SHARED_TYPES +#define MEMS_SHARED_TYPES + +typedef struct{ + uint8_t bit0 : 1; + uint8_t bit1 : 1; + uint8_t bit2 : 1; + uint8_t bit3 : 1; + uint8_t bit4 : 1; + uint8_t bit5 : 1; + uint8_t bit6 : 1; + uint8_t bit7 : 1; +} bitwise_t; + +#define PROPERTY_DISABLE (0U) +#define PROPERTY_ENABLE (1U) + +/** @addtogroup Interfaces_Functions + * @brief This section provide a set of functions used to read and + * write a generic register of the device. + * MANDATORY: return 0 -> no Error. + * @{ + * + */ + +typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, uint8_t*, uint16_t); +typedef int32_t (*stmdev_read_ptr) (void *, uint8_t, uint8_t*, uint16_t); + +typedef struct { + /** Component mandatory fields **/ + stmdev_write_ptr write_reg; + stmdev_read_ptr read_reg; + /** Customizable optional pointer **/ + void *handle; +} stmdev_ctx_t; + +/** + * @} + * + */ + +#endif /* MEMS_SHARED_TYPES */ + +#ifndef MEMS_UCF_SHARED_TYPES +#define MEMS_UCF_SHARED_TYPES + +/** @defgroup Generic address-data structure definition + * @brief This structure is useful to load a predefined configuration + * of a sensor. + * You can create a sensor configuration by your own or using + * Unico / Unicleo tools available on STMicroelectronics + * web site. + * + * @{ + * + */ + +typedef struct { + uint8_t address; + uint8_t data; +} ucf_line_t; + +/** + * @} + * + */ + +#endif /* MEMS_UCF_SHARED_TYPES */ + +/** + * @} + * + */ + +/** @defgroup LSM6DS3TR_C_Infos + * @{ + * + */ + +/** I2C Device Address 8 bit format if SA0=0 -> D5 if SA0=1 -> D7 **/ +#define LSM6DS3TR_C_I2C_ADD_L 0xD5U +#define LSM6DS3TR_C_I2C_ADD_H 0xD7U + +/** Device Identification (Who am I) **/ +#define LSM6DS3TR_C_ID 0x6AU + +/** + * @} + * + */ + +#define LSM6DS3TR_C_FUNC_CFG_ACCESS 0x01U +typedef struct { + uint8_t not_used_01 : 5; + uint8_t func_cfg_en : 3; /* func_cfg_en + func_cfg_en_b */ +} lsm6ds3tr_c_func_cfg_access_t; + +#define LSM6DS3TR_C_SENSOR_SYNC_TIME_FRAME 0x04U +typedef struct { + uint8_t tph : 4; + uint8_t not_used_01 : 4; +} lsm6ds3tr_c_sensor_sync_time_frame_t; + +#define LSM6DS3TR_C_SENSOR_SYNC_RES_RATIO 0x05U +typedef struct { + uint8_t rr : 2; + uint8_t not_used_01 : 6; +} lsm6ds3tr_c_sensor_sync_res_ratio_t; + +#define LSM6DS3TR_C_FIFO_CTRL1 0x06U +typedef struct { + uint8_t fth : 8; /* + FIFO_CTRL2(fth) */ +} lsm6ds3tr_c_fifo_ctrl1_t; + +#define LSM6DS3TR_C_FIFO_CTRL2 0x07U +typedef struct { + uint8_t fth : 3; /* + FIFO_CTRL1(fth) */ + uint8_t fifo_temp_en : 1; + uint8_t not_used_01 : 2; + uint8_t timer_pedo_fifo_drdy : 1; + uint8_t timer_pedo_fifo_en : 1; +} lsm6ds3tr_c_fifo_ctrl2_t; + +#define LSM6DS3TR_C_FIFO_CTRL3 0x08U +typedef struct { + uint8_t dec_fifo_xl : 3; + uint8_t dec_fifo_gyro : 3; + uint8_t not_used_01 : 2; +} lsm6ds3tr_c_fifo_ctrl3_t; + +#define LSM6DS3TR_C_FIFO_CTRL4 0x09U +typedef struct { + uint8_t dec_ds3_fifo : 3; + uint8_t dec_ds4_fifo : 3; + uint8_t only_high_data : 1; + uint8_t stop_on_fth : 1; +} lsm6ds3tr_c_fifo_ctrl4_t; + +#define LSM6DS3TR_C_FIFO_CTRL5 0x0AU +typedef struct { + uint8_t fifo_mode : 3; + uint8_t odr_fifo : 4; + uint8_t not_used_01 : 1; +} lsm6ds3tr_c_fifo_ctrl5_t; + +#define LSM6DS3TR_C_DRDY_PULSE_CFG_G 0x0BU +typedef struct { + uint8_t int2_wrist_tilt : 1; + uint8_t not_used_01 : 6; + uint8_t drdy_pulsed : 1; +} lsm6ds3tr_c_drdy_pulse_cfg_g_t; + +#define LSM6DS3TR_C_INT1_CTRL 0x0DU +typedef struct { + uint8_t int1_drdy_xl : 1; + uint8_t int1_drdy_g : 1; + uint8_t int1_boot : 1; + uint8_t int1_fth : 1; + uint8_t int1_fifo_ovr : 1; + uint8_t int1_full_flag : 1; + uint8_t int1_sign_mot : 1; + uint8_t int1_step_detector : 1; +} lsm6ds3tr_c_int1_ctrl_t; + +#define LSM6DS3TR_C_INT2_CTRL 0x0EU +typedef struct { + uint8_t int2_drdy_xl : 1; + uint8_t int2_drdy_g : 1; + uint8_t int2_drdy_temp : 1; + uint8_t int2_fth : 1; + uint8_t int2_fifo_ovr : 1; + uint8_t int2_full_flag : 1; + uint8_t int2_step_count_ov : 1; + uint8_t int2_step_delta : 1; +} lsm6ds3tr_c_int2_ctrl_t; + +#define LSM6DS3TR_C_WHO_AM_I 0x0FU +#define LSM6DS3TR_C_CTRL1_XL 0x10U +typedef struct { + uint8_t bw0_xl : 1; + uint8_t lpf1_bw_sel : 1; + uint8_t fs_xl : 2; + uint8_t odr_xl : 4; +} lsm6ds3tr_c_ctrl1_xl_t; + +#define LSM6DS3TR_C_CTRL2_G 0x11U +typedef struct { + uint8_t not_used_01 : 1; + uint8_t fs_g : 3; /* fs_g + fs_125 */ + uint8_t odr_g : 4; +} lsm6ds3tr_c_ctrl2_g_t; + +#define LSM6DS3TR_C_CTRL3_C 0x12U +typedef struct { + uint8_t sw_reset : 1; + uint8_t ble : 1; + uint8_t if_inc : 1; + uint8_t sim : 1; + uint8_t pp_od : 1; + uint8_t h_lactive : 1; + uint8_t bdu : 1; + uint8_t boot : 1; +} lsm6ds3tr_c_ctrl3_c_t; + +#define LSM6DS3TR_C_CTRL4_C 0x13U +typedef struct { + uint8_t not_used_01 : 1; + uint8_t lpf1_sel_g : 1; + uint8_t i2c_disable : 1; + uint8_t drdy_mask : 1; + uint8_t den_drdy_int1 : 1; + uint8_t int2_on_int1 : 1; + uint8_t sleep : 1; + uint8_t den_xl_en : 1; +} lsm6ds3tr_c_ctrl4_c_t; + +#define LSM6DS3TR_C_CTRL5_C 0x14U +typedef struct { + uint8_t st_xl : 2; + uint8_t st_g : 2; + uint8_t den_lh : 1; + uint8_t rounding : 3; +} lsm6ds3tr_c_ctrl5_c_t; + +#define LSM6DS3TR_C_CTRL6_C 0x15U +typedef struct { + uint8_t ftype : 2; + uint8_t not_used_01 : 1; + uint8_t usr_off_w : 1; + uint8_t xl_hm_mode : 1; + uint8_t den_mode : 3; /* trig_en + lvl_en + lvl2_en */ +} lsm6ds3tr_c_ctrl6_c_t; + +#define LSM6DS3TR_C_CTRL7_G 0x16U +typedef struct { + uint8_t not_used_01 : 2; + uint8_t rounding_status : 1; + uint8_t not_used_02 : 1; + uint8_t hpm_g : 2; + uint8_t hp_en_g : 1; + uint8_t g_hm_mode : 1; +} lsm6ds3tr_c_ctrl7_g_t; + +#define LSM6DS3TR_C_CTRL8_XL 0x17U +typedef struct { + uint8_t low_pass_on_6d : 1; + uint8_t not_used_01 : 1; + uint8_t hp_slope_xl_en : 1; + uint8_t input_composite : 1; + uint8_t hp_ref_mode : 1; + uint8_t hpcf_xl : 2; + uint8_t lpf2_xl_en : 1; +} lsm6ds3tr_c_ctrl8_xl_t; + +#define LSM6DS3TR_C_CTRL9_XL 0x18U +typedef struct { + uint8_t not_used_01 : 2; + uint8_t soft_en : 1; + uint8_t not_used_02 : 1; + uint8_t den_xl_g : 1; + uint8_t den_z : 1; + uint8_t den_y : 1; + uint8_t den_x : 1; +} lsm6ds3tr_c_ctrl9_xl_t; + +#define LSM6DS3TR_C_CTRL10_C 0x19U +typedef struct { + uint8_t sign_motion_en : 1; + uint8_t pedo_rst_step : 1; + uint8_t func_en : 1; + uint8_t tilt_en : 1; + uint8_t pedo_en : 1; + uint8_t timer_en : 1; + uint8_t not_used_01 : 1; + uint8_t wrist_tilt_en : 1; +} lsm6ds3tr_c_ctrl10_c_t; + +#define LSM6DS3TR_C_MASTER_CONFIG 0x1AU +typedef struct { + uint8_t master_on : 1; + uint8_t iron_en : 1; + uint8_t pass_through_mode : 1; + uint8_t pull_up_en : 1; + uint8_t start_config : 1; + uint8_t not_used_01 : 1; + uint8_t data_valid_sel_fifo : 1; + uint8_t drdy_on_int1 : 1; +} lsm6ds3tr_c_master_config_t; + +#define LSM6DS3TR_C_WAKE_UP_SRC 0x1BU +typedef struct { + uint8_t z_wu : 1; + uint8_t y_wu : 1; + uint8_t x_wu : 1; + uint8_t wu_ia : 1; + uint8_t sleep_state_ia : 1; + uint8_t ff_ia : 1; + uint8_t not_used_01 : 2; +} lsm6ds3tr_c_wake_up_src_t; + +#define LSM6DS3TR_C_TAP_SRC 0x1CU +typedef struct { + uint8_t z_tap : 1; + uint8_t y_tap : 1; + uint8_t x_tap : 1; + uint8_t tap_sign : 1; + uint8_t double_tap : 1; + uint8_t single_tap : 1; + uint8_t tap_ia : 1; + uint8_t not_used_01 : 1; +} lsm6ds3tr_c_tap_src_t; + +#define LSM6DS3TR_C_D6D_SRC 0x1DU +typedef struct { + uint8_t xl : 1; + uint8_t xh : 1; + uint8_t yl : 1; + uint8_t yh : 1; + uint8_t zl : 1; + uint8_t zh : 1; + uint8_t d6d_ia : 1; + uint8_t den_drdy : 1; +} lsm6ds3tr_c_d6d_src_t; + +#define LSM6DS3TR_C_STATUS_REG 0x1EU +typedef struct { + uint8_t xlda : 1; + uint8_t gda : 1; + uint8_t tda : 1; + uint8_t not_used_01 : 5; +} lsm6ds3tr_c_status_reg_t; + +#define LSM6DS3TR_C_OUT_TEMP_L 0x20U +#define LSM6DS3TR_C_OUT_TEMP_H 0x21U +#define LSM6DS3TR_C_OUTX_L_G 0x22U +#define LSM6DS3TR_C_OUTX_H_G 0x23U +#define LSM6DS3TR_C_OUTY_L_G 0x24U +#define LSM6DS3TR_C_OUTY_H_G 0x25U +#define LSM6DS3TR_C_OUTZ_L_G 0x26U +#define LSM6DS3TR_C_OUTZ_H_G 0x27U +#define LSM6DS3TR_C_OUTX_L_XL 0x28U +#define LSM6DS3TR_C_OUTX_H_XL 0x29U +#define LSM6DS3TR_C_OUTY_L_XL 0x2AU +#define LSM6DS3TR_C_OUTY_H_XL 0x2BU +#define LSM6DS3TR_C_OUTZ_L_XL 0x2CU +#define LSM6DS3TR_C_OUTZ_H_XL 0x2DU +#define LSM6DS3TR_C_SENSORHUB1_REG 0x2EU +typedef struct { + uint8_t bit0 : 1; + uint8_t bit1 : 1; + uint8_t bit2 : 1; + uint8_t bit3 : 1; + uint8_t bit4 : 1; + uint8_t bit5 : 1; + uint8_t bit6 : 1; + uint8_t bit7 : 1; +} lsm6ds3tr_c_sensorhub1_reg_t; + +#define LSM6DS3TR_C_SENSORHUB2_REG 0x2FU +typedef struct { + uint8_t bit0 : 1; + uint8_t bit1 : 1; + uint8_t bit2 : 1; + uint8_t bit3 : 1; + uint8_t bit4 : 1; + uint8_t bit5 : 1; + uint8_t bit6 : 1; + uint8_t bit7 : 1; +} lsm6ds3tr_c_sensorhub2_reg_t; + +#define LSM6DS3TR_C_SENSORHUB3_REG 0x30U +typedef struct { + uint8_t bit0 : 1; + uint8_t bit1 : 1; + uint8_t bit2 : 1; + uint8_t bit3 : 1; + uint8_t bit4 : 1; + uint8_t bit5 : 1; + uint8_t bit6 : 1; + uint8_t bit7 : 1; +} lsm6ds3tr_c_sensorhub3_reg_t; + +#define LSM6DS3TR_C_SENSORHUB4_REG 0x31U +typedef struct { + uint8_t bit0 : 1; + uint8_t bit1 : 1; + uint8_t bit2 : 1; + uint8_t bit3 : 1; + uint8_t bit4 : 1; + uint8_t bit5 : 1; + uint8_t bit6 : 1; + uint8_t bit7 : 1; +} lsm6ds3tr_c_sensorhub4_reg_t; + +#define LSM6DS3TR_C_SENSORHUB5_REG 0x32U +typedef struct { + uint8_t bit0 : 1; + uint8_t bit1 : 1; + uint8_t bit2 : 1; + uint8_t bit3 : 1; + uint8_t bit4 : 1; + uint8_t bit5 : 1; + uint8_t bit6 : 1; + uint8_t bit7 : 1; +} lsm6ds3tr_c_sensorhub5_reg_t; + +#define LSM6DS3TR_C_SENSORHUB6_REG 0x33U +typedef struct { + uint8_t bit0 : 1; + uint8_t bit1 : 1; + uint8_t bit2 : 1; + uint8_t bit3 : 1; + uint8_t bit4 : 1; + uint8_t bit5 : 1; + uint8_t bit6 : 1; + uint8_t bit7 : 1; +} lsm6ds3tr_c_sensorhub6_reg_t; + +#define LSM6DS3TR_C_SENSORHUB7_REG 0x34U +typedef struct { + uint8_t bit0 : 1; + uint8_t bit1 : 1; + uint8_t bit2 : 1; + uint8_t bit3 : 1; + uint8_t bit4 : 1; + uint8_t bit5 : 1; + uint8_t bit6 : 1; + uint8_t bit7 : 1; +} lsm6ds3tr_c_sensorhub7_reg_t; + +#define LSM6DS3TR_C_SENSORHUB8_REG 0x35U +typedef struct { + uint8_t bit0 : 1; + uint8_t bit1 : 1; + uint8_t bit2 : 1; + uint8_t bit3 : 1; + uint8_t bit4 : 1; + uint8_t bit5 : 1; + uint8_t bit6 : 1; + uint8_t bit7 : 1; +} lsm6ds3tr_c_sensorhub8_reg_t; + +#define LSM6DS3TR_C_SENSORHUB9_REG 0x36U +typedef struct { + uint8_t bit0 : 1; + uint8_t bit1 : 1; + uint8_t bit2 : 1; + uint8_t bit3 : 1; + uint8_t bit4 : 1; + uint8_t bit5 : 1; + uint8_t bit6 : 1; + uint8_t bit7 : 1; +} lsm6ds3tr_c_sensorhub9_reg_t; + +#define LSM6DS3TR_C_SENSORHUB10_REG 0x37U +typedef struct { + uint8_t bit0 : 1; + uint8_t bit1 : 1; + uint8_t bit2 : 1; + uint8_t bit3 : 1; + uint8_t bit4 : 1; + uint8_t bit5 : 1; + uint8_t bit6 : 1; + uint8_t bit7 : 1; +} lsm6ds3tr_c_sensorhub10_reg_t; + +#define LSM6DS3TR_C_SENSORHUB11_REG 0x38U +typedef struct { + uint8_t bit0 : 1; + uint8_t bit1 : 1; + uint8_t bit2 : 1; + uint8_t bit3 : 1; + uint8_t bit4 : 1; + uint8_t bit5 : 1; + uint8_t bit6 : 1; + uint8_t bit7 : 1; +} lsm6ds3tr_c_sensorhub11_reg_t; + +#define LSM6DS3TR_C_SENSORHUB12_REG 0x39U +typedef struct { + uint8_t bit0 : 1; + uint8_t bit1 : 1; + uint8_t bit2 : 1; + uint8_t bit3 : 1; + uint8_t bit4 : 1; + uint8_t bit5 : 1; + uint8_t bit6 : 1; + uint8_t bit7 : 1; +} lsm6ds3tr_c_sensorhub12_reg_t; + +#define LSM6DS3TR_C_FIFO_STATUS1 0x3AU +typedef struct { + uint8_t diff_fifo : 8; /* + FIFO_STATUS2(diff_fifo) */ +} lsm6ds3tr_c_fifo_status1_t; + +#define LSM6DS3TR_C_FIFO_STATUS2 0x3BU +typedef struct { + uint8_t diff_fifo : 3; /* + FIFO_STATUS1(diff_fifo) */ + uint8_t not_used_01 : 1; + uint8_t fifo_empty : 1; + uint8_t fifo_full_smart : 1; + uint8_t over_run : 1; + uint8_t waterm : 1; +} lsm6ds3tr_c_fifo_status2_t; + +#define LSM6DS3TR_C_FIFO_STATUS3 0x3CU +typedef struct { + uint8_t fifo_pattern : 8; /* + FIFO_STATUS4(fifo_pattern) */ +} lsm6ds3tr_c_fifo_status3_t; + +#define LSM6DS3TR_C_FIFO_STATUS4 0x3DU +typedef struct { + uint8_t fifo_pattern : 2; /* + FIFO_STATUS3(fifo_pattern) */ + uint8_t not_used_01 : 6; +} lsm6ds3tr_c_fifo_status4_t; + +#define LSM6DS3TR_C_FIFO_DATA_OUT_L 0x3EU +#define LSM6DS3TR_C_FIFO_DATA_OUT_H 0x3FU +#define LSM6DS3TR_C_TIMESTAMP0_REG 0x40U +#define LSM6DS3TR_C_TIMESTAMP1_REG 0x41U +#define LSM6DS3TR_C_TIMESTAMP2_REG 0x42U +#define LSM6DS3TR_C_STEP_TIMESTAMP_L 0x49U +#define LSM6DS3TR_C_STEP_TIMESTAMP_H 0x4AU +#define LSM6DS3TR_C_STEP_COUNTER_L 0x4BU +#define LSM6DS3TR_C_STEP_COUNTER_H 0x4CU + +#define LSM6DS3TR_C_SENSORHUB13_REG 0x4DU +typedef struct { + uint8_t bit0 : 1; + uint8_t bit1 : 1; + uint8_t bit2 : 1; + uint8_t bit3 : 1; + uint8_t bit4 : 1; + uint8_t bit5 : 1; + uint8_t bit6 : 1; + uint8_t bit7 : 1; +} lsm6ds3tr_c_sensorhub13_reg_t; + +#define LSM6DS3TR_C_SENSORHUB14_REG 0x4EU +typedef struct { + uint8_t bit0 : 1; + uint8_t bit1 : 1; + uint8_t bit2 : 1; + uint8_t bit3 : 1; + uint8_t bit4 : 1; + uint8_t bit5 : 1; + uint8_t bit6 : 1; + uint8_t bit7 : 1; +} lsm6ds3tr_c_sensorhub14_reg_t; + +#define LSM6DS3TR_C_SENSORHUB15_REG 0x4FU +typedef struct { + uint8_t bit0 : 1; + uint8_t bit1 : 1; + uint8_t bit2 : 1; + uint8_t bit3 : 1; + uint8_t bit4 : 1; + uint8_t bit5 : 1; + uint8_t bit6 : 1; + uint8_t bit7 : 1; +} lsm6ds3tr_c_sensorhub15_reg_t; + +#define LSM6DS3TR_C_SENSORHUB16_REG 0x50U +typedef struct { + uint8_t bit0 : 1; + uint8_t bit1 : 1; + uint8_t bit2 : 1; + uint8_t bit3 : 1; + uint8_t bit4 : 1; + uint8_t bit5 : 1; + uint8_t bit6 : 1; + uint8_t bit7 : 1; +} lsm6ds3tr_c_sensorhub16_reg_t; + +#define LSM6DS3TR_C_SENSORHUB17_REG 0x51U +typedef struct { + uint8_t bit0 : 1; + uint8_t bit1 : 1; + uint8_t bit2 : 1; + uint8_t bit3 : 1; + uint8_t bit4 : 1; + uint8_t bit5 : 1; + uint8_t bit6 : 1; + uint8_t bit7 : 1; +} lsm6ds3tr_c_sensorhub17_reg_t; + +#define LSM6DS3TR_C_SENSORHUB18_REG 0x52U +typedef struct { + uint8_t bit0 : 1; + uint8_t bit1 : 1; + uint8_t bit2 : 1; + uint8_t bit3 : 1; + uint8_t bit4 : 1; + uint8_t bit5 : 1; + uint8_t bit6 : 1; + uint8_t bit7 : 1; +} lsm6ds3tr_c_sensorhub18_reg_t; + +#define LSM6DS3TR_C_FUNC_SRC1 0x53U +typedef struct { + uint8_t sensorhub_end_op : 1; + uint8_t si_end_op : 1; + uint8_t hi_fail : 1; + uint8_t step_overflow : 1; + uint8_t step_detected : 1; + uint8_t tilt_ia : 1; + uint8_t sign_motion_ia : 1; + uint8_t step_count_delta_ia : 1; +} lsm6ds3tr_c_func_src1_t; + +#define LSM6DS3TR_C_FUNC_SRC2 0x54U +typedef struct { + uint8_t wrist_tilt_ia : 1; + uint8_t not_used_01 : 2; + uint8_t slave0_nack : 1; + uint8_t slave1_nack : 1; + uint8_t slave2_nack : 1; + uint8_t slave3_nack : 1; + uint8_t not_used_02 : 1; +} lsm6ds3tr_c_func_src2_t; + +#define LSM6DS3TR_C_WRIST_TILT_IA 0x55U +typedef struct { + uint8_t not_used_01 : 2; + uint8_t wrist_tilt_ia_zneg : 1; + uint8_t wrist_tilt_ia_zpos : 1; + uint8_t wrist_tilt_ia_yneg : 1; + uint8_t wrist_tilt_ia_ypos : 1; + uint8_t wrist_tilt_ia_xneg : 1; + uint8_t wrist_tilt_ia_xpos : 1; +} lsm6ds3tr_c_wrist_tilt_ia_t; + +#define LSM6DS3TR_C_TAP_CFG 0x58U +typedef struct { + uint8_t lir : 1; + uint8_t tap_z_en : 1; + uint8_t tap_y_en : 1; + uint8_t tap_x_en : 1; + uint8_t slope_fds : 1; + uint8_t inact_en : 2; + uint8_t interrupts_enable : 1; +} lsm6ds3tr_c_tap_cfg_t; + +#define LSM6DS3TR_C_TAP_THS_6D 0x59U +typedef struct { + uint8_t tap_ths : 5; + uint8_t sixd_ths : 2; + uint8_t d4d_en : 1; +} lsm6ds3tr_c_tap_ths_6d_t; + +#define LSM6DS3TR_C_INT_DUR2 0x5AU +typedef struct { + uint8_t shock : 2; + uint8_t quiet : 2; + uint8_t dur : 4; +} lsm6ds3tr_c_int_dur2_t; + +#define LSM6DS3TR_C_WAKE_UP_THS 0x5BU +typedef struct { + uint8_t wk_ths : 6; + uint8_t not_used_01 : 1; + uint8_t single_double_tap : 1; +} lsm6ds3tr_c_wake_up_ths_t; + +#define LSM6DS3TR_C_WAKE_UP_DUR 0x5CU +typedef struct { + uint8_t sleep_dur : 4; + uint8_t timer_hr : 1; + uint8_t wake_dur : 2; + uint8_t ff_dur : 1; +} lsm6ds3tr_c_wake_up_dur_t; + +#define LSM6DS3TR_C_FREE_FALL 0x5DU +typedef struct { + uint8_t ff_ths : 3; + uint8_t ff_dur : 5; +} lsm6ds3tr_c_free_fall_t; + +#define LSM6DS3TR_C_MD1_CFG 0x5EU +typedef struct { + uint8_t int1_timer : 1; + uint8_t int1_tilt : 1; + uint8_t int1_6d : 1; + uint8_t int1_double_tap : 1; + uint8_t int1_ff : 1; + uint8_t int1_wu : 1; + uint8_t int1_single_tap : 1; + uint8_t int1_inact_state : 1; +} lsm6ds3tr_c_md1_cfg_t; + +#define LSM6DS3TR_C_MD2_CFG 0x5FU +typedef struct { + uint8_t int2_iron : 1; + uint8_t int2_tilt : 1; + uint8_t int2_6d : 1; + uint8_t int2_double_tap : 1; + uint8_t int2_ff : 1; + uint8_t int2_wu : 1; + uint8_t int2_single_tap : 1; + uint8_t int2_inact_state : 1; +} lsm6ds3tr_c_md2_cfg_t; + +#define LSM6DS3TR_C_MASTER_CMD_CODE 0x60U +typedef struct { + uint8_t master_cmd_code : 8; +} lsm6ds3tr_c_master_cmd_code_t; + +#define LSM6DS3TR_C_SENS_SYNC_SPI_ERROR_CODE 0x61U +typedef struct { + uint8_t error_code : 8; +} lsm6ds3tr_c_sens_sync_spi_error_code_t; + +#define LSM6DS3TR_C_OUT_MAG_RAW_X_L 0x66U +#define LSM6DS3TR_C_OUT_MAG_RAW_X_H 0x67U +#define LSM6DS3TR_C_OUT_MAG_RAW_Y_L 0x68U +#define LSM6DS3TR_C_OUT_MAG_RAW_Y_H 0x69U +#define LSM6DS3TR_C_OUT_MAG_RAW_Z_L 0x6AU +#define LSM6DS3TR_C_OUT_MAG_RAW_Z_H 0x6BU +#define LSM6DS3TR_C_X_OFS_USR 0x73U +#define LSM6DS3TR_C_Y_OFS_USR 0x74U +#define LSM6DS3TR_C_Z_OFS_USR 0x75U +#define LSM6DS3TR_C_SLV0_ADD 0x02U +typedef struct { + uint8_t rw_0 : 1; + uint8_t slave0_add : 7; +} lsm6ds3tr_c_slv0_add_t; + +#define LSM6DS3TR_C_SLV0_SUBADD 0x03U +typedef struct { + uint8_t slave0_reg : 8; +} lsm6ds3tr_c_slv0_subadd_t; + +#define LSM6DS3TR_C_SLAVE0_CONFIG 0x04U +typedef struct { + uint8_t slave0_numop : 3; + uint8_t src_mode : 1; + uint8_t aux_sens_on : 2; + uint8_t slave0_rate : 2; +} lsm6ds3tr_c_slave0_config_t; + +#define LSM6DS3TR_C_SLV1_ADD 0x05U +typedef struct { + uint8_t r_1 : 1; + uint8_t slave1_add : 7; +} lsm6ds3tr_c_slv1_add_t; + +#define LSM6DS3TR_C_SLV1_SUBADD 0x06U +typedef struct { + uint8_t slave1_reg : 8; +} lsm6ds3tr_c_slv1_subadd_t; + +#define LSM6DS3TR_C_SLAVE1_CONFIG 0x07U +typedef struct { + uint8_t slave1_numop : 3; + uint8_t not_used_01 : 2; + uint8_t write_once : 1; + uint8_t slave1_rate : 2; +} lsm6ds3tr_c_slave1_config_t; + +#define LSM6DS3TR_C_SLV2_ADD 0x08U +typedef struct { + uint8_t r_2 : 1; + uint8_t slave2_add : 7; +} lsm6ds3tr_c_slv2_add_t; + +#define LSM6DS3TR_C_SLV2_SUBADD 0x09U +typedef struct { + uint8_t slave2_reg : 8; +} lsm6ds3tr_c_slv2_subadd_t; + +#define LSM6DS3TR_C_SLAVE2_CONFIG 0x0AU +typedef struct { + uint8_t slave2_numop : 3; + uint8_t not_used_01 : 3; + uint8_t slave2_rate : 2; +} lsm6ds3tr_c_slave2_config_t; + +#define LSM6DS3TR_C_SLV3_ADD 0x0BU +typedef struct { + uint8_t r_3 : 1; + uint8_t slave3_add : 7; +} lsm6ds3tr_c_slv3_add_t; + +#define LSM6DS3TR_C_SLV3_SUBADD 0x0CU +typedef struct { + uint8_t slave3_reg : 8; +} lsm6ds3tr_c_slv3_subadd_t; + +#define LSM6DS3TR_C_SLAVE3_CONFIG 0x0DU +typedef struct { + uint8_t slave3_numop : 3; + uint8_t not_used_01 : 3; + uint8_t slave3_rate : 2; +} lsm6ds3tr_c_slave3_config_t; + +#define LSM6DS3TR_C_DATAWRITE_SRC_MODE_SUB_SLV0 0x0EU +typedef struct { + uint8_t slave_dataw : 8; +} lsm6ds3tr_c_datawrite_src_mode_sub_slv0_t; + +#define LSM6DS3TR_C_CONFIG_PEDO_THS_MIN 0x0FU +typedef struct { + uint8_t ths_min : 5; + uint8_t not_used_01 : 2; + uint8_t pedo_fs : 1; +} lsm6ds3tr_c_config_pedo_ths_min_t; + +#define LSM6DS3TR_C_SM_THS 0x13U +#define LSM6DS3TR_C_PEDO_DEB_REG 0x14U +typedef struct { + uint8_t deb_step : 3; + uint8_t deb_time : 5; +} lsm6ds3tr_c_pedo_deb_reg_t; + +#define LSM6DS3TR_C_STEP_COUNT_DELTA 0x15U +#define LSM6DS3TR_C_MAG_SI_XX 0x24U +#define LSM6DS3TR_C_MAG_SI_XY 0x25U +#define LSM6DS3TR_C_MAG_SI_XZ 0x26U +#define LSM6DS3TR_C_MAG_SI_YX 0x27U +#define LSM6DS3TR_C_MAG_SI_YY 0x28U +#define LSM6DS3TR_C_MAG_SI_YZ 0x29U +#define LSM6DS3TR_C_MAG_SI_ZX 0x2AU +#define LSM6DS3TR_C_MAG_SI_ZY 0x2BU +#define LSM6DS3TR_C_MAG_SI_ZZ 0x2CU +#define LSM6DS3TR_C_MAG_OFFX_L 0x2DU +#define LSM6DS3TR_C_MAG_OFFX_H 0x2EU +#define LSM6DS3TR_C_MAG_OFFY_L 0x2FU +#define LSM6DS3TR_C_MAG_OFFY_H 0x30U +#define LSM6DS3TR_C_MAG_OFFZ_L 0x31U +#define LSM6DS3TR_C_MAG_OFFZ_H 0x32U +#define LSM6DS3TR_C_A_WRIST_TILT_LAT 0x50U +#define LSM6DS3TR_C_A_WRIST_TILT_THS 0x54U +#define LSM6DS3TR_C_A_WRIST_TILT_MASK 0x59U +typedef struct { + uint8_t not_used_01 : 2; + uint8_t wrist_tilt_mask_zneg : 1; + uint8_t wrist_tilt_mask_zpos : 1; + uint8_t wrist_tilt_mask_yneg : 1; + uint8_t wrist_tilt_mask_ypos : 1; + uint8_t wrist_tilt_mask_xneg : 1; + uint8_t wrist_tilt_mask_xpos : 1; +} lsm6ds3tr_c_a_wrist_tilt_mask_t; + +/** + * @defgroup LSM6DS3TR_C_Register_Union + * @brief This union group all the registers that has a bit-field + * description. + * This union is useful but not need by the driver. + * + * REMOVING this union you are compliant with: + * MISRA-C 2012 [Rule 19.2] -> " Union are not allowed " + * + * @{ + * + */ +typedef union{ + lsm6ds3tr_c_func_cfg_access_t func_cfg_access; + lsm6ds3tr_c_sensor_sync_time_frame_t sensor_sync_time_frame; + lsm6ds3tr_c_sensor_sync_res_ratio_t sensor_sync_res_ratio; + lsm6ds3tr_c_fifo_ctrl1_t fifo_ctrl1; + lsm6ds3tr_c_fifo_ctrl2_t fifo_ctrl2; + lsm6ds3tr_c_fifo_ctrl3_t fifo_ctrl3; + lsm6ds3tr_c_fifo_ctrl4_t fifo_ctrl4; + lsm6ds3tr_c_fifo_ctrl5_t fifo_ctrl5; + lsm6ds3tr_c_drdy_pulse_cfg_g_t drdy_pulse_cfg_g; + lsm6ds3tr_c_int1_ctrl_t int1_ctrl; + lsm6ds3tr_c_int2_ctrl_t int2_ctrl; + lsm6ds3tr_c_ctrl1_xl_t ctrl1_xl; + lsm6ds3tr_c_ctrl2_g_t ctrl2_g; + lsm6ds3tr_c_ctrl3_c_t ctrl3_c; + lsm6ds3tr_c_ctrl4_c_t ctrl4_c; + lsm6ds3tr_c_ctrl5_c_t ctrl5_c; + lsm6ds3tr_c_ctrl6_c_t ctrl6_c; + lsm6ds3tr_c_ctrl7_g_t ctrl7_g; + lsm6ds3tr_c_ctrl8_xl_t ctrl8_xl; + lsm6ds3tr_c_ctrl9_xl_t ctrl9_xl; + lsm6ds3tr_c_ctrl10_c_t ctrl10_c; + lsm6ds3tr_c_master_config_t master_config; + lsm6ds3tr_c_wake_up_src_t wake_up_src; + lsm6ds3tr_c_tap_src_t tap_src; + lsm6ds3tr_c_d6d_src_t d6d_src; + lsm6ds3tr_c_status_reg_t status_reg; + lsm6ds3tr_c_sensorhub1_reg_t sensorhub1_reg; + lsm6ds3tr_c_sensorhub2_reg_t sensorhub2_reg; + lsm6ds3tr_c_sensorhub3_reg_t sensorhub3_reg; + lsm6ds3tr_c_sensorhub4_reg_t sensorhub4_reg; + lsm6ds3tr_c_sensorhub5_reg_t sensorhub5_reg; + lsm6ds3tr_c_sensorhub6_reg_t sensorhub6_reg; + lsm6ds3tr_c_sensorhub7_reg_t sensorhub7_reg; + lsm6ds3tr_c_sensorhub8_reg_t sensorhub8_reg; + lsm6ds3tr_c_sensorhub9_reg_t sensorhub9_reg; + lsm6ds3tr_c_sensorhub10_reg_t sensorhub10_reg; + lsm6ds3tr_c_sensorhub11_reg_t sensorhub11_reg; + lsm6ds3tr_c_sensorhub12_reg_t sensorhub12_reg; + lsm6ds3tr_c_fifo_status1_t fifo_status1; + lsm6ds3tr_c_fifo_status2_t fifo_status2; + lsm6ds3tr_c_fifo_status3_t fifo_status3; + lsm6ds3tr_c_fifo_status4_t fifo_status4; + lsm6ds3tr_c_sensorhub13_reg_t sensorhub13_reg; + lsm6ds3tr_c_sensorhub14_reg_t sensorhub14_reg; + lsm6ds3tr_c_sensorhub15_reg_t sensorhub15_reg; + lsm6ds3tr_c_sensorhub16_reg_t sensorhub16_reg; + lsm6ds3tr_c_sensorhub17_reg_t sensorhub17_reg; + lsm6ds3tr_c_sensorhub18_reg_t sensorhub18_reg; + lsm6ds3tr_c_func_src1_t func_src1; + lsm6ds3tr_c_func_src2_t func_src2; + lsm6ds3tr_c_wrist_tilt_ia_t wrist_tilt_ia; + lsm6ds3tr_c_tap_cfg_t tap_cfg; + lsm6ds3tr_c_tap_ths_6d_t tap_ths_6d; + lsm6ds3tr_c_int_dur2_t int_dur2; + lsm6ds3tr_c_wake_up_ths_t wake_up_ths; + lsm6ds3tr_c_wake_up_dur_t wake_up_dur; + lsm6ds3tr_c_free_fall_t free_fall; + lsm6ds3tr_c_md1_cfg_t md1_cfg; + lsm6ds3tr_c_md2_cfg_t md2_cfg; + lsm6ds3tr_c_master_cmd_code_t master_cmd_code; + lsm6ds3tr_c_sens_sync_spi_error_code_t sens_sync_spi_error_code; + lsm6ds3tr_c_slv0_add_t slv0_add; + lsm6ds3tr_c_slv0_subadd_t slv0_subadd; + lsm6ds3tr_c_slave0_config_t slave0_config; + lsm6ds3tr_c_slv1_add_t slv1_add; + lsm6ds3tr_c_slv1_subadd_t slv1_subadd; + lsm6ds3tr_c_slave1_config_t slave1_config; + lsm6ds3tr_c_slv2_add_t slv2_add; + lsm6ds3tr_c_slv2_subadd_t slv2_subadd; + lsm6ds3tr_c_slave2_config_t slave2_config; + lsm6ds3tr_c_slv3_add_t slv3_add; + lsm6ds3tr_c_slv3_subadd_t slv3_subadd; + lsm6ds3tr_c_slave3_config_t slave3_config; + lsm6ds3tr_c_datawrite_src_mode_sub_slv0_t datawrite_src_mode_sub_slv0; + lsm6ds3tr_c_config_pedo_ths_min_t config_pedo_ths_min; + lsm6ds3tr_c_pedo_deb_reg_t pedo_deb_reg; + lsm6ds3tr_c_a_wrist_tilt_mask_t a_wrist_tilt_mask; + bitwise_t bitwise; + uint8_t byte; +} lsm6ds3tr_c_reg_t; + +/** + * @} + * + */ + +int32_t lsm6ds3tr_c_read_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t* data, + uint16_t len); +int32_t lsm6ds3tr_c_write_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t* data, + uint16_t len); + +extern float_t lsm6ds3tr_c_from_fs2g_to_mg(int16_t lsb); +extern float_t lsm6ds3tr_c_from_fs4g_to_mg(int16_t lsb); +extern float_t lsm6ds3tr_c_from_fs8g_to_mg(int16_t lsb); +extern float_t lsm6ds3tr_c_from_fs16g_to_mg(int16_t lsb); + +extern float_t lsm6ds3tr_c_from_fs125dps_to_mdps(int16_t lsb); +extern float_t lsm6ds3tr_c_from_fs250dps_to_mdps(int16_t lsb); +extern float_t lsm6ds3tr_c_from_fs500dps_to_mdps(int16_t lsb); +extern float_t lsm6ds3tr_c_from_fs1000dps_to_mdps(int16_t lsb); +extern float_t lsm6ds3tr_c_from_fs2000dps_to_mdps(int16_t lsb); + +extern float_t lsm6ds3tr_c_from_lsb_to_celsius(int16_t lsb); + +typedef enum { + LSM6DS3TR_C_2g = 0, + LSM6DS3TR_C_16g = 1, + LSM6DS3TR_C_4g = 2, + LSM6DS3TR_C_8g = 3, + LSM6DS3TR_C_XL_FS_ND = 4, /* ERROR CODE */ +} lsm6ds3tr_c_fs_xl_t; +int32_t lsm6ds3tr_c_xl_full_scale_set(stmdev_ctx_t *ctx, lsm6ds3tr_c_fs_xl_t val); +int32_t lsm6ds3tr_c_xl_full_scale_get(stmdev_ctx_t *ctx, lsm6ds3tr_c_fs_xl_t *val); + +typedef enum { + LSM6DS3TR_C_XL_ODR_OFF = 0, + LSM6DS3TR_C_XL_ODR_12Hz5 = 1, + LSM6DS3TR_C_XL_ODR_26Hz = 2, + LSM6DS3TR_C_XL_ODR_52Hz = 3, + LSM6DS3TR_C_XL_ODR_104Hz = 4, + LSM6DS3TR_C_XL_ODR_208Hz = 5, + LSM6DS3TR_C_XL_ODR_416Hz = 6, + LSM6DS3TR_C_XL_ODR_833Hz = 7, + LSM6DS3TR_C_XL_ODR_1k66Hz = 8, + LSM6DS3TR_C_XL_ODR_3k33Hz = 9, + LSM6DS3TR_C_XL_ODR_6k66Hz = 10, + LSM6DS3TR_C_XL_ODR_1Hz6 = 11, + LSM6DS3TR_C_XL_ODR_ND = 12, /* ERROR CODE */ +} lsm6ds3tr_c_odr_xl_t; +int32_t lsm6ds3tr_c_xl_data_rate_set(stmdev_ctx_t *ctx, lsm6ds3tr_c_odr_xl_t val); +int32_t lsm6ds3tr_c_xl_data_rate_get(stmdev_ctx_t *ctx, lsm6ds3tr_c_odr_xl_t *val); + +typedef enum { + LSM6DS3TR_C_250dps = 0, + LSM6DS3TR_C_125dps = 1, + LSM6DS3TR_C_500dps = 2, + LSM6DS3TR_C_1000dps = 4, + LSM6DS3TR_C_2000dps = 6, + LSM6DS3TR_C_GY_FS_ND = 7, /* ERROR CODE */ +} lsm6ds3tr_c_fs_g_t; +int32_t lsm6ds3tr_c_gy_full_scale_set(stmdev_ctx_t *ctx, lsm6ds3tr_c_fs_g_t val); +int32_t lsm6ds3tr_c_gy_full_scale_get(stmdev_ctx_t *ctx, lsm6ds3tr_c_fs_g_t *val); + +typedef enum { + LSM6DS3TR_C_GY_ODR_OFF = 0, + LSM6DS3TR_C_GY_ODR_12Hz5 = 1, + LSM6DS3TR_C_GY_ODR_26Hz = 2, + LSM6DS3TR_C_GY_ODR_52Hz = 3, + LSM6DS3TR_C_GY_ODR_104Hz = 4, + LSM6DS3TR_C_GY_ODR_208Hz = 5, + LSM6DS3TR_C_GY_ODR_416Hz = 6, + LSM6DS3TR_C_GY_ODR_833Hz = 7, + LSM6DS3TR_C_GY_ODR_1k66Hz = 8, + LSM6DS3TR_C_GY_ODR_3k33Hz = 9, + LSM6DS3TR_C_GY_ODR_6k66Hz = 10, + LSM6DS3TR_C_GY_ODR_ND = 11, /* ERROR CODE */ +} lsm6ds3tr_c_odr_g_t; +int32_t lsm6ds3tr_c_gy_data_rate_set(stmdev_ctx_t *ctx, lsm6ds3tr_c_odr_g_t val); +int32_t lsm6ds3tr_c_gy_data_rate_get(stmdev_ctx_t *ctx, lsm6ds3tr_c_odr_g_t *val); + +int32_t lsm6ds3tr_c_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6ds3tr_c_block_data_update_get(stmdev_ctx_t *ctx, uint8_t *val); + +typedef enum { + LSM6DS3TR_C_LSb_1mg = 0, + LSM6DS3TR_C_LSb_16mg = 1, + LSM6DS3TR_C_WEIGHT_ND = 2, +} lsm6ds3tr_c_usr_off_w_t; +int32_t lsm6ds3tr_c_xl_offset_weight_set(stmdev_ctx_t *ctx, + lsm6ds3tr_c_usr_off_w_t val); +int32_t lsm6ds3tr_c_xl_offset_weight_get(stmdev_ctx_t *ctx, + lsm6ds3tr_c_usr_off_w_t *val); + +typedef enum { + LSM6DS3TR_C_XL_HIGH_PERFORMANCE = 0, + LSM6DS3TR_C_XL_NORMAL = 1, + LSM6DS3TR_C_XL_PW_MODE_ND = 2, /* ERROR CODE */ +} lsm6ds3tr_c_xl_hm_mode_t; +int32_t lsm6ds3tr_c_xl_power_mode_set(stmdev_ctx_t *ctx, + lsm6ds3tr_c_xl_hm_mode_t val); +int32_t lsm6ds3tr_c_xl_power_mode_get(stmdev_ctx_t *ctx, + lsm6ds3tr_c_xl_hm_mode_t *val); + +typedef enum { + LSM6DS3TR_C_STAT_RND_DISABLE = 0, + LSM6DS3TR_C_STAT_RND_ENABLE = 1, + LSM6DS3TR_C_STAT_RND_ND = 2, /* ERROR CODE */ +} lsm6ds3tr_c_rounding_status_t; +int32_t lsm6ds3tr_c_rounding_on_status_set(stmdev_ctx_t *ctx, + lsm6ds3tr_c_rounding_status_t val); +int32_t lsm6ds3tr_c_rounding_on_status_get(stmdev_ctx_t *ctx, + lsm6ds3tr_c_rounding_status_t *val); + +typedef enum { + LSM6DS3TR_C_GY_HIGH_PERFORMANCE = 0, + LSM6DS3TR_C_GY_NORMAL = 1, + LSM6DS3TR_C_GY_PW_MODE_ND = 2, /* ERROR CODE */ +} lsm6ds3tr_c_g_hm_mode_t; +int32_t lsm6ds3tr_c_gy_power_mode_set(stmdev_ctx_t *ctx, + lsm6ds3tr_c_g_hm_mode_t val); +int32_t lsm6ds3tr_c_gy_power_mode_get(stmdev_ctx_t *ctx, + lsm6ds3tr_c_g_hm_mode_t *val); + +typedef struct { + lsm6ds3tr_c_wake_up_src_t wake_up_src; + lsm6ds3tr_c_tap_src_t tap_src; + lsm6ds3tr_c_d6d_src_t d6d_src; + lsm6ds3tr_c_status_reg_t status_reg; + lsm6ds3tr_c_func_src1_t func_src1; + lsm6ds3tr_c_func_src2_t func_src2; + lsm6ds3tr_c_wrist_tilt_ia_t wrist_tilt_ia; + lsm6ds3tr_c_a_wrist_tilt_mask_t a_wrist_tilt_mask; +} lsm6ds3tr_c_all_sources_t; +int32_t lsm6ds3tr_c_all_sources_get(stmdev_ctx_t *ctx, + lsm6ds3tr_c_all_sources_t *val); + +int32_t lsm6ds3tr_c_status_reg_get(stmdev_ctx_t *ctx, lsm6ds3tr_c_status_reg_t *val); + +int32_t lsm6ds3tr_c_xl_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val); + +int32_t lsm6ds3tr_c_gy_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val); + +int32_t lsm6ds3tr_c_temp_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val); + +int32_t lsm6ds3tr_c_xl_usr_offset_set(stmdev_ctx_t *ctx, uint8_t *buff); +int32_t lsm6ds3tr_c_xl_usr_offset_get(stmdev_ctx_t *ctx, uint8_t *buff); +int32_t lsm6ds3tr_c_timestamp_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6ds3tr_c_timestamp_get(stmdev_ctx_t *ctx, uint8_t *val); + +typedef enum { + LSM6DS3TR_C_LSB_6ms4 = 0, + LSM6DS3TR_C_LSB_25us = 1, + LSM6DS3TR_C_TS_RES_ND = 2, /* ERROR CODE */ +} lsm6ds3tr_c_timer_hr_t; +int32_t lsm6ds3tr_c_timestamp_res_set(stmdev_ctx_t *ctx, lsm6ds3tr_c_timer_hr_t val); +int32_t lsm6ds3tr_c_timestamp_res_get(stmdev_ctx_t *ctx, lsm6ds3tr_c_timer_hr_t *val); + +typedef enum { + LSM6DS3TR_C_ROUND_DISABLE = 0, + LSM6DS3TR_C_ROUND_XL = 1, + LSM6DS3TR_C_ROUND_GY = 2, + LSM6DS3TR_C_ROUND_GY_XL = 3, + LSM6DS3TR_C_ROUND_SH1_TO_SH6 = 4, + LSM6DS3TR_C_ROUND_XL_SH1_TO_SH6 = 5, + LSM6DS3TR_C_ROUND_GY_XL_SH1_TO_SH12 = 6, + LSM6DS3TR_C_ROUND_GY_XL_SH1_TO_SH6 = 7, + LSM6DS3TR_C_ROUND_OUT_ND = 8, /* ERROR CODE */ +} lsm6ds3tr_c_rounding_t; +int32_t lsm6ds3tr_c_rounding_mode_set(stmdev_ctx_t *ctx, lsm6ds3tr_c_rounding_t val); +int32_t lsm6ds3tr_c_rounding_mode_get(stmdev_ctx_t *ctx, lsm6ds3tr_c_rounding_t *val); + +int32_t lsm6ds3tr_c_temperature_raw_get(stmdev_ctx_t *ctx, uint8_t *buff); +int32_t lsm6ds3tr_c_angular_rate_raw_get(stmdev_ctx_t *ctx, uint8_t *buff); +int32_t lsm6ds3tr_c_acceleration_raw_get(stmdev_ctx_t *ctx, uint8_t *buff); + +int32_t lsm6ds3tr_c_mag_calibrated_raw_get(stmdev_ctx_t *ctx, uint8_t *buff); + +int32_t lsm6ds3tr_c_fifo_raw_data_get(stmdev_ctx_t *ctx, uint8_t *buffer, + uint8_t len); + +typedef enum { + LSM6DS3TR_C_USER_BANK = 0, + LSM6DS3TR_C_BANK_A = 4, + LSM6DS3TR_C_BANK_B = 5, + LSM6DS3TR_C_BANK_ND = 6, /* ERROR CODE */ +} lsm6ds3tr_c_func_cfg_en_t; +int32_t lsm6ds3tr_c_mem_bank_set(stmdev_ctx_t *ctx, lsm6ds3tr_c_func_cfg_en_t val); +int32_t lsm6ds3tr_c_mem_bank_get(stmdev_ctx_t *ctx, lsm6ds3tr_c_func_cfg_en_t *val); + +typedef enum { + LSM6DS3TR_C_DRDY_LATCHED = 0, + LSM6DS3TR_C_DRDY_PULSED = 1, + LSM6DS3TR_C_DRDY_ND = 2, /* ERROR CODE */ +} lsm6ds3tr_c_drdy_pulsed_g_t; +int32_t lsm6ds3tr_c_data_ready_mode_set(stmdev_ctx_t *ctx, + lsm6ds3tr_c_drdy_pulsed_g_t val); +int32_t lsm6ds3tr_c_data_ready_mode_get(stmdev_ctx_t *ctx, + lsm6ds3tr_c_drdy_pulsed_g_t *val); + +int32_t lsm6ds3tr_c_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff); +int32_t lsm6ds3tr_c_reset_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6ds3tr_c_reset_get(stmdev_ctx_t *ctx, uint8_t *val); + +typedef enum { + LSM6DS3TR_C_LSB_AT_LOW_ADD = 0, + LSM6DS3TR_C_MSB_AT_LOW_ADD = 1, + LSM6DS3TR_C_DATA_FMT_ND = 2, /* ERROR CODE */ +} lsm6ds3tr_c_ble_t; +int32_t lsm6ds3tr_c_data_format_set(stmdev_ctx_t *ctx, lsm6ds3tr_c_ble_t val); +int32_t lsm6ds3tr_c_data_format_get(stmdev_ctx_t *ctx, lsm6ds3tr_c_ble_t *val); + +int32_t lsm6ds3tr_c_auto_increment_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6ds3tr_c_auto_increment_get(stmdev_ctx_t *ctx, uint8_t *val); + +int32_t lsm6ds3tr_c_boot_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6ds3tr_c_boot_get(stmdev_ctx_t *ctx, uint8_t *val); + +typedef enum { + LSM6DS3TR_C_XL_ST_DISABLE = 0, + LSM6DS3TR_C_XL_ST_POSITIVE = 1, + LSM6DS3TR_C_XL_ST_NEGATIVE = 2, + LSM6DS3TR_C_XL_ST_ND = 3, /* ERROR CODE */ +} lsm6ds3tr_c_st_xl_t; +int32_t lsm6ds3tr_c_xl_self_test_set(stmdev_ctx_t *ctx, lsm6ds3tr_c_st_xl_t val); +int32_t lsm6ds3tr_c_xl_self_test_get(stmdev_ctx_t *ctx, lsm6ds3tr_c_st_xl_t *val); + +typedef enum { + LSM6DS3TR_C_GY_ST_DISABLE = 0, + LSM6DS3TR_C_GY_ST_POSITIVE = 1, + LSM6DS3TR_C_GY_ST_NEGATIVE = 3, + LSM6DS3TR_C_GY_ST_ND = 4, /* ERROR CODE */ +} lsm6ds3tr_c_st_g_t; +int32_t lsm6ds3tr_c_gy_self_test_set(stmdev_ctx_t *ctx, lsm6ds3tr_c_st_g_t val); +int32_t lsm6ds3tr_c_gy_self_test_get(stmdev_ctx_t *ctx, lsm6ds3tr_c_st_g_t *val); + +int32_t lsm6ds3tr_c_filter_settling_mask_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6ds3tr_c_filter_settling_mask_get(stmdev_ctx_t *ctx, uint8_t *val); + +typedef enum { + LSM6DS3TR_C_USE_SLOPE = 0, + LSM6DS3TR_C_USE_HPF = 1, + LSM6DS3TR_C_HP_PATH_ND = 2, /* ERROR CODE */ +} lsm6ds3tr_c_slope_fds_t; +int32_t lsm6ds3tr_c_xl_hp_path_internal_set(stmdev_ctx_t *ctx, + lsm6ds3tr_c_slope_fds_t val); +int32_t lsm6ds3tr_c_xl_hp_path_internal_get(stmdev_ctx_t *ctx, + lsm6ds3tr_c_slope_fds_t *val); + +typedef enum { + LSM6DS3TR_C_XL_ANA_BW_1k5Hz = 0, + LSM6DS3TR_C_XL_ANA_BW_400Hz = 1, + LSM6DS3TR_C_XL_ANA_BW_ND = 2, /* ERROR CODE */ +} lsm6ds3tr_c_bw0_xl_t; +int32_t lsm6ds3tr_c_xl_filter_analog_set(stmdev_ctx_t *ctx, + lsm6ds3tr_c_bw0_xl_t val); +int32_t lsm6ds3tr_c_xl_filter_analog_get(stmdev_ctx_t *ctx, + lsm6ds3tr_c_bw0_xl_t *val); + +typedef enum { + LSM6DS3TR_C_XL_LP1_ODR_DIV_2 = 0, + LSM6DS3TR_C_XL_LP1_ODR_DIV_4 = 1, + LSM6DS3TR_C_XL_LP1_NA = 2, /* ERROR CODE */ +} lsm6ds3tr_c_lpf1_bw_sel_t; +int32_t lsm6ds3tr_c_xl_lp1_bandwidth_set(stmdev_ctx_t *ctx, + lsm6ds3tr_c_lpf1_bw_sel_t val); +int32_t lsm6ds3tr_c_xl_lp1_bandwidth_get(stmdev_ctx_t *ctx, + lsm6ds3tr_c_lpf1_bw_sel_t *val); + +typedef enum { + LSM6DS3TR_C_XL_LOW_LAT_LP_ODR_DIV_50 = 0x00, + LSM6DS3TR_C_XL_LOW_LAT_LP_ODR_DIV_100 = 0x01, + LSM6DS3TR_C_XL_LOW_LAT_LP_ODR_DIV_9 = 0x02, + LSM6DS3TR_C_XL_LOW_LAT_LP_ODR_DIV_400 = 0x03, + LSM6DS3TR_C_XL_LOW_NOISE_LP_ODR_DIV_50 = 0x10, + LSM6DS3TR_C_XL_LOW_NOISE_LP_ODR_DIV_100 = 0x11, + LSM6DS3TR_C_XL_LOW_NOISE_LP_ODR_DIV_9 = 0x12, + LSM6DS3TR_C_XL_LOW_NOISE_LP_ODR_DIV_400 = 0x13, + LSM6DS3TR_C_XL_LP_NA = 0x20, /* ERROR CODE */ +} lsm6ds3tr_c_input_composite_t; +int32_t lsm6ds3tr_c_xl_lp2_bandwidth_set(stmdev_ctx_t *ctx, + lsm6ds3tr_c_input_composite_t val); +int32_t lsm6ds3tr_c_xl_lp2_bandwidth_get(stmdev_ctx_t *ctx, + lsm6ds3tr_c_input_composite_t *val); + +int32_t lsm6ds3tr_c_xl_reference_mode_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6ds3tr_c_xl_reference_mode_get(stmdev_ctx_t *ctx, uint8_t *val); + +typedef enum { + LSM6DS3TR_C_XL_HP_ODR_DIV_4 = 0x00, /* Slope filter */ + LSM6DS3TR_C_XL_HP_ODR_DIV_100 = 0x01, + LSM6DS3TR_C_XL_HP_ODR_DIV_9 = 0x02, + LSM6DS3TR_C_XL_HP_ODR_DIV_400 = 0x03, + LSM6DS3TR_C_XL_HP_NA = 0x10, /* ERROR CODE */ +} lsm6ds3tr_c_hpcf_xl_t; +int32_t lsm6ds3tr_c_xl_hp_bandwidth_set(stmdev_ctx_t *ctx, + lsm6ds3tr_c_hpcf_xl_t val); +int32_t lsm6ds3tr_c_xl_hp_bandwidth_get(stmdev_ctx_t *ctx, + lsm6ds3tr_c_hpcf_xl_t *val); + +typedef enum { + LSM6DS3TR_C_LP2_ONLY = 0x00, + + LSM6DS3TR_C_HP_16mHz_LP2 = 0x80, + LSM6DS3TR_C_HP_65mHz_LP2 = 0x90, + LSM6DS3TR_C_HP_260mHz_LP2 = 0xA0, + LSM6DS3TR_C_HP_1Hz04_LP2 = 0xB0, + + LSM6DS3TR_C_HP_DISABLE_LP1_LIGHT = 0x0A, + LSM6DS3TR_C_HP_DISABLE_LP1_NORMAL = 0x09, + LSM6DS3TR_C_HP_DISABLE_LP_STRONG = 0x08, + LSM6DS3TR_C_HP_DISABLE_LP1_AGGRESSIVE = 0x0B, + + LSM6DS3TR_C_HP_16mHz_LP1_LIGHT = 0x8A, + LSM6DS3TR_C_HP_65mHz_LP1_NORMAL = 0x99, + LSM6DS3TR_C_HP_260mHz_LP1_STRONG = 0xA8, + LSM6DS3TR_C_HP_1Hz04_LP1_AGGRESSIVE = 0xBB, + + LSM6DS3TR_C_HP_GY_BAND_NA = 0xFF, /* ERROR CODE */ +} lsm6ds3tr_c_lpf1_sel_g_t; +int32_t lsm6ds3tr_c_gy_band_pass_set(stmdev_ctx_t *ctx, + lsm6ds3tr_c_lpf1_sel_g_t val); +int32_t lsm6ds3tr_c_gy_band_pass_get(stmdev_ctx_t *ctx, + lsm6ds3tr_c_lpf1_sel_g_t *val); + +typedef enum { + LSM6DS3TR_C_SPI_4_WIRE = 0, + LSM6DS3TR_C_SPI_3_WIRE = 1, + LSM6DS3TR_C_SPI_MODE_ND = 2, /* ERROR CODE */ +} lsm6ds3tr_c_sim_t; +int32_t lsm6ds3tr_c_spi_mode_set(stmdev_ctx_t *ctx, lsm6ds3tr_c_sim_t val); +int32_t lsm6ds3tr_c_spi_mode_get(stmdev_ctx_t *ctx, lsm6ds3tr_c_sim_t *val); + +typedef enum { + LSM6DS3TR_C_I2C_ENABLE = 0, + LSM6DS3TR_C_I2C_DISABLE = 1, + LSM6DS3TR_C_I2C_MODE_ND = 2, /* ERROR CODE */ +} lsm6ds3tr_c_i2c_disable_t; +int32_t lsm6ds3tr_c_i2c_interface_set(stmdev_ctx_t *ctx, + lsm6ds3tr_c_i2c_disable_t val); +int32_t lsm6ds3tr_c_i2c_interface_get(stmdev_ctx_t *ctx, + lsm6ds3tr_c_i2c_disable_t *val); + +typedef struct { + uint8_t int1_drdy_xl : 1; + uint8_t int1_drdy_g : 1; + uint8_t int1_boot : 1; + uint8_t int1_fth : 1; + uint8_t int1_fifo_ovr : 1; + uint8_t int1_full_flag : 1; + uint8_t int1_sign_mot : 1; + uint8_t int1_step_detector : 1; + uint8_t int1_timer : 1; + uint8_t int1_tilt : 1; + uint8_t int1_6d : 1; + uint8_t int1_double_tap : 1; + uint8_t int1_ff : 1; + uint8_t int1_wu : 1; + uint8_t int1_single_tap : 1; + uint8_t int1_inact_state : 1; + uint8_t den_drdy_int1 : 1; + uint8_t drdy_on_int1 : 1; +} lsm6ds3tr_c_int1_route_t; +int32_t lsm6ds3tr_c_pin_int1_route_set(stmdev_ctx_t *ctx, + lsm6ds3tr_c_int1_route_t val); +int32_t lsm6ds3tr_c_pin_int1_route_get(stmdev_ctx_t *ctx, + lsm6ds3tr_c_int1_route_t *val); + +typedef struct{ + uint8_t int2_drdy_xl : 1; + uint8_t int2_drdy_g : 1; + uint8_t int2_drdy_temp : 1; + uint8_t int2_fth : 1; + uint8_t int2_fifo_ovr : 1; + uint8_t int2_full_flag : 1; + uint8_t int2_step_count_ov : 1; + uint8_t int2_step_delta : 1; + uint8_t int2_iron : 1; + uint8_t int2_tilt : 1; + uint8_t int2_6d : 1; + uint8_t int2_double_tap : 1; + uint8_t int2_ff : 1; + uint8_t int2_wu : 1; + uint8_t int2_single_tap : 1; + uint8_t int2_inact_state : 1; + uint8_t int2_wrist_tilt : 1; +} lsm6ds3tr_c_int2_route_t; +int32_t lsm6ds3tr_c_pin_int2_route_set(stmdev_ctx_t *ctx, + lsm6ds3tr_c_int2_route_t val); +int32_t lsm6ds3tr_c_pin_int2_route_get(stmdev_ctx_t *ctx, + lsm6ds3tr_c_int2_route_t *val); + +typedef enum { + LSM6DS3TR_C_PUSH_PULL = 0, + LSM6DS3TR_C_OPEN_DRAIN = 1, + LSM6DS3TR_C_PIN_MODE_ND = 2, /* ERROR CODE */ +} lsm6ds3tr_c_pp_od_t; +int32_t lsm6ds3tr_c_pin_mode_set(stmdev_ctx_t *ctx, lsm6ds3tr_c_pp_od_t val); +int32_t lsm6ds3tr_c_pin_mode_get(stmdev_ctx_t *ctx, lsm6ds3tr_c_pp_od_t *val); + +typedef enum { + LSM6DS3TR_C_ACTIVE_HIGH = 0, + LSM6DS3TR_C_ACTIVE_LOW = 1, + LSM6DS3TR_C_POLARITY_ND = 2, /* ERROR CODE */ +} lsm6ds3tr_c_h_lactive_t; +int32_t lsm6ds3tr_c_pin_polarity_set(stmdev_ctx_t *ctx, lsm6ds3tr_c_h_lactive_t val); +int32_t lsm6ds3tr_c_pin_polarity_get(stmdev_ctx_t *ctx, lsm6ds3tr_c_h_lactive_t *val); + +int32_t lsm6ds3tr_c_all_on_int1_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6ds3tr_c_all_on_int1_get(stmdev_ctx_t *ctx, uint8_t *val); + +typedef enum { + LSM6DS3TR_C_INT_PULSED = 0, + LSM6DS3TR_C_INT_LATCHED = 1, + LSM6DS3TR_C_INT_MODE = 2, /* ERROR CODE */ +} lsm6ds3tr_c_lir_t; +int32_t lsm6ds3tr_c_int_notification_set(stmdev_ctx_t *ctx, lsm6ds3tr_c_lir_t val); +int32_t lsm6ds3tr_c_int_notification_get(stmdev_ctx_t *ctx, lsm6ds3tr_c_lir_t *val); + +int32_t lsm6ds3tr_c_wkup_threshold_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6ds3tr_c_wkup_threshold_get(stmdev_ctx_t *ctx, uint8_t *val); + +int32_t lsm6ds3tr_c_wkup_dur_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6ds3tr_c_wkup_dur_get(stmdev_ctx_t *ctx, uint8_t *val); + +int32_t lsm6ds3tr_c_gy_sleep_mode_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6ds3tr_c_gy_sleep_mode_get(stmdev_ctx_t *ctx, uint8_t *val); + +typedef enum { + LSM6DS3TR_C_PROPERTY_DISABLE = 0, + LSM6DS3TR_C_XL_12Hz5_GY_NOT_AFFECTED = 1, + LSM6DS3TR_C_XL_12Hz5_GY_SLEEP = 2, + LSM6DS3TR_C_XL_12Hz5_GY_PD = 3, + LSM6DS3TR_C_ACT_MODE_ND = 4, /* ERROR CODE */ +} lsm6ds3tr_c_inact_en_t; +int32_t lsm6ds3tr_c_act_mode_set(stmdev_ctx_t *ctx, lsm6ds3tr_c_inact_en_t val); +int32_t lsm6ds3tr_c_act_mode_get(stmdev_ctx_t *ctx, lsm6ds3tr_c_inact_en_t *val); + +int32_t lsm6ds3tr_c_act_sleep_dur_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6ds3tr_c_act_sleep_dur_get(stmdev_ctx_t *ctx, uint8_t *val); + +int32_t lsm6ds3tr_c_tap_src_get(stmdev_ctx_t *ctx, lsm6ds3tr_c_tap_src_t *val); + +int32_t lsm6ds3tr_c_tap_detection_on_z_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6ds3tr_c_tap_detection_on_z_get(stmdev_ctx_t *ctx, uint8_t *val); + +int32_t lsm6ds3tr_c_tap_detection_on_y_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6ds3tr_c_tap_detection_on_y_get(stmdev_ctx_t *ctx, uint8_t *val); + +int32_t lsm6ds3tr_c_tap_detection_on_x_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6ds3tr_c_tap_detection_on_x_get(stmdev_ctx_t *ctx, uint8_t *val); + +int32_t lsm6ds3tr_c_tap_threshold_x_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6ds3tr_c_tap_threshold_x_get(stmdev_ctx_t *ctx, uint8_t *val); + +int32_t lsm6ds3tr_c_tap_shock_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6ds3tr_c_tap_shock_get(stmdev_ctx_t *ctx, uint8_t *val); + +int32_t lsm6ds3tr_c_tap_quiet_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6ds3tr_c_tap_quiet_get(stmdev_ctx_t *ctx, uint8_t *val); + +int32_t lsm6ds3tr_c_tap_dur_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6ds3tr_c_tap_dur_get(stmdev_ctx_t *ctx, uint8_t *val); + +typedef enum { + LSM6DS3TR_C_ONLY_SINGLE = 0, + LSM6DS3TR_C_BOTH_SINGLE_DOUBLE = 1, + LSM6DS3TR_C_TAP_MODE_ND = 2, /* ERROR CODE */ +} lsm6ds3tr_c_single_double_tap_t; +int32_t lsm6ds3tr_c_tap_mode_set(stmdev_ctx_t *ctx, + lsm6ds3tr_c_single_double_tap_t val); +int32_t lsm6ds3tr_c_tap_mode_get(stmdev_ctx_t *ctx, + lsm6ds3tr_c_single_double_tap_t *val); + +typedef enum { + LSM6DS3TR_C_ODR_DIV_2_FEED = 0, + LSM6DS3TR_C_LPF2_FEED = 1, + LSM6DS3TR_C_6D_FEED_ND = 2, /* ERROR CODE */ +} lsm6ds3tr_c_low_pass_on_6d_t; +int32_t lsm6ds3tr_c_6d_feed_data_set(stmdev_ctx_t *ctx, + lsm6ds3tr_c_low_pass_on_6d_t val); +int32_t lsm6ds3tr_c_6d_feed_data_get(stmdev_ctx_t *ctx, + lsm6ds3tr_c_low_pass_on_6d_t *val); + +typedef enum { + LSM6DS3TR_C_DEG_80 = 0, + LSM6DS3TR_C_DEG_70 = 1, + LSM6DS3TR_C_DEG_60 = 2, + LSM6DS3TR_C_DEG_50 = 3, + LSM6DS3TR_C_6D_TH_ND = 4, /* ERROR CODE */ +} lsm6ds3tr_c_sixd_ths_t; +int32_t lsm6ds3tr_c_6d_threshold_set(stmdev_ctx_t *ctx, lsm6ds3tr_c_sixd_ths_t val); +int32_t lsm6ds3tr_c_6d_threshold_get(stmdev_ctx_t *ctx, lsm6ds3tr_c_sixd_ths_t *val); + +int32_t lsm6ds3tr_c_4d_mode_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6ds3tr_c_4d_mode_get(stmdev_ctx_t *ctx, uint8_t *val); + +int32_t lsm6ds3tr_c_ff_dur_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6ds3tr_c_ff_dur_get(stmdev_ctx_t *ctx, uint8_t *val); + +typedef enum { + LSM6DS3TR_C_FF_TSH_156mg = 0, + LSM6DS3TR_C_FF_TSH_219mg = 1, + LSM6DS3TR_C_FF_TSH_250mg = 2, + LSM6DS3TR_C_FF_TSH_312mg = 3, + LSM6DS3TR_C_FF_TSH_344mg = 4, + LSM6DS3TR_C_FF_TSH_406mg = 5, + LSM6DS3TR_C_FF_TSH_469mg = 6, + LSM6DS3TR_C_FF_TSH_500mg = 7, + LSM6DS3TR_C_FF_TSH_ND = 8, /* ERROR CODE */ +} lsm6ds3tr_c_ff_ths_t; +int32_t lsm6ds3tr_c_ff_threshold_set(stmdev_ctx_t *ctx, lsm6ds3tr_c_ff_ths_t val); +int32_t lsm6ds3tr_c_ff_threshold_get(stmdev_ctx_t *ctx, lsm6ds3tr_c_ff_ths_t *val); + +int32_t lsm6ds3tr_c_fifo_watermark_set(stmdev_ctx_t *ctx, uint16_t val); +int32_t lsm6ds3tr_c_fifo_watermark_get(stmdev_ctx_t *ctx, uint16_t *val); + +int32_t lsm6ds3tr_c_fifo_data_level_get(stmdev_ctx_t *ctx, uint16_t *val); + +int32_t lsm6ds3tr_c_fifo_wtm_flag_get(stmdev_ctx_t *ctx, uint8_t *val); + +int32_t lsm6ds3tr_c_fifo_pattern_get(stmdev_ctx_t *ctx, uint16_t *val); + +int32_t lsm6ds3tr_c_fifo_temp_batch_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6ds3tr_c_fifo_temp_batch_get(stmdev_ctx_t *ctx, uint8_t *val); + +typedef enum { + LSM6DS3TR_C_TRG_XL_GY_DRDY = 0, + LSM6DS3TR_C_TRG_STEP_DETECT = 1, + LSM6DS3TR_C_TRG_SH_DRDY = 2, + LSM6DS3TR_C_TRG_SH_ND = 3, /* ERROR CODE */ +} lsm6ds3tr_c_trigger_fifo_t; +int32_t lsm6ds3tr_c_fifo_write_trigger_set(stmdev_ctx_t *ctx, + lsm6ds3tr_c_trigger_fifo_t val); +int32_t lsm6ds3tr_c_fifo_write_trigger_get(stmdev_ctx_t *ctx, + lsm6ds3tr_c_trigger_fifo_t *val); + +int32_t lsm6ds3tr_c_fifo_pedo_and_timestamp_batch_set(stmdev_ctx_t *ctx, + uint8_t val); +int32_t lsm6ds3tr_c_fifo_pedo_and_timestamp_batch_get(stmdev_ctx_t *ctx, + uint8_t *val); + +typedef enum { + LSM6DS3TR_C_FIFO_XL_DISABLE = 0, + LSM6DS3TR_C_FIFO_XL_NO_DEC = 1, + LSM6DS3TR_C_FIFO_XL_DEC_2 = 2, + LSM6DS3TR_C_FIFO_XL_DEC_3 = 3, + LSM6DS3TR_C_FIFO_XL_DEC_4 = 4, + LSM6DS3TR_C_FIFO_XL_DEC_8 = 5, + LSM6DS3TR_C_FIFO_XL_DEC_16 = 6, + LSM6DS3TR_C_FIFO_XL_DEC_32 = 7, + LSM6DS3TR_C_FIFO_XL_DEC_ND = 8, /* ERROR CODE */ +} lsm6ds3tr_c_dec_fifo_xl_t; +int32_t lsm6ds3tr_c_fifo_xl_batch_set(stmdev_ctx_t *ctx, + lsm6ds3tr_c_dec_fifo_xl_t val); +int32_t lsm6ds3tr_c_fifo_xl_batch_get(stmdev_ctx_t *ctx, + lsm6ds3tr_c_dec_fifo_xl_t *val); + +typedef enum { + LSM6DS3TR_C_FIFO_GY_DISABLE = 0, + LSM6DS3TR_C_FIFO_GY_NO_DEC = 1, + LSM6DS3TR_C_FIFO_GY_DEC_2 = 2, + LSM6DS3TR_C_FIFO_GY_DEC_3 = 3, + LSM6DS3TR_C_FIFO_GY_DEC_4 = 4, + LSM6DS3TR_C_FIFO_GY_DEC_8 = 5, + LSM6DS3TR_C_FIFO_GY_DEC_16 = 6, + LSM6DS3TR_C_FIFO_GY_DEC_32 = 7, + LSM6DS3TR_C_FIFO_GY_DEC_ND = 8, /* ERROR CODE */ +} lsm6ds3tr_c_dec_fifo_gyro_t; +int32_t lsm6ds3tr_c_fifo_gy_batch_set(stmdev_ctx_t *ctx, + lsm6ds3tr_c_dec_fifo_gyro_t val); +int32_t lsm6ds3tr_c_fifo_gy_batch_get(stmdev_ctx_t *ctx, + lsm6ds3tr_c_dec_fifo_gyro_t *val); + +typedef enum { + LSM6DS3TR_C_FIFO_DS3_DISABLE = 0, + LSM6DS3TR_C_FIFO_DS3_NO_DEC = 1, + LSM6DS3TR_C_FIFO_DS3_DEC_2 = 2, + LSM6DS3TR_C_FIFO_DS3_DEC_3 = 3, + LSM6DS3TR_C_FIFO_DS3_DEC_4 = 4, + LSM6DS3TR_C_FIFO_DS3_DEC_8 = 5, + LSM6DS3TR_C_FIFO_DS3_DEC_16 = 6, + LSM6DS3TR_C_FIFO_DS3_DEC_32 = 7, + LSM6DS3TR_C_FIFO_DS3_DEC_ND = 8, /* ERROR CODE */ +} lsm6ds3tr_c_dec_ds3_fifo_t; +int32_t lsm6ds3tr_c_fifo_dataset_3_batch_set(stmdev_ctx_t *ctx, + lsm6ds3tr_c_dec_ds3_fifo_t val); +int32_t lsm6ds3tr_c_fifo_dataset_3_batch_get(stmdev_ctx_t *ctx, + lsm6ds3tr_c_dec_ds3_fifo_t *val); + +typedef enum { + LSM6DS3TR_C_FIFO_DS4_DISABLE = 0, + LSM6DS3TR_C_FIFO_DS4_NO_DEC = 1, + LSM6DS3TR_C_FIFO_DS4_DEC_2 = 2, + LSM6DS3TR_C_FIFO_DS4_DEC_3 = 3, + LSM6DS3TR_C_FIFO_DS4_DEC_4 = 4, + LSM6DS3TR_C_FIFO_DS4_DEC_8 = 5, + LSM6DS3TR_C_FIFO_DS4_DEC_16 = 6, + LSM6DS3TR_C_FIFO_DS4_DEC_32 = 7, + LSM6DS3TR_C_FIFO_DS4_DEC_ND = 8, /* ERROR CODE */ +} lsm6ds3tr_c_dec_ds4_fifo_t; +int32_t lsm6ds3tr_c_fifo_dataset_4_batch_set(stmdev_ctx_t *ctx, + lsm6ds3tr_c_dec_ds4_fifo_t val); +int32_t lsm6ds3tr_c_fifo_dataset_4_batch_get(stmdev_ctx_t *ctx, + lsm6ds3tr_c_dec_ds4_fifo_t *val); + +int32_t lsm6ds3tr_c_fifo_xl_gy_8bit_format_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6ds3tr_c_fifo_xl_gy_8bit_format_get(stmdev_ctx_t *ctx, uint8_t *val); + +int32_t lsm6ds3tr_c_fifo_stop_on_wtm_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6ds3tr_c_fifo_stop_on_wtm_get(stmdev_ctx_t *ctx, uint8_t *val); + +typedef enum { + LSM6DS3TR_C_BYPASS_MODE = 0, + LSM6DS3TR_C_FIFO_MODE = 1, + LSM6DS3TR_C_STREAM_TO_FIFO_MODE = 3, + LSM6DS3TR_C_BYPASS_TO_STREAM_MODE = 4, + LSM6DS3TR_C_STREAM_MODE = 6, + LSM6DS3TR_C_FIFO_MODE_ND = 8, /* ERROR CODE */ +} lsm6ds3tr_c_fifo_mode_t; +int32_t lsm6ds3tr_c_fifo_mode_set(stmdev_ctx_t *ctx, lsm6ds3tr_c_fifo_mode_t val); +int32_t lsm6ds3tr_c_fifo_mode_get(stmdev_ctx_t *ctx, lsm6ds3tr_c_fifo_mode_t *val); + +typedef enum { + LSM6DS3TR_C_FIFO_DISABLE = 0, + LSM6DS3TR_C_FIFO_12Hz5 = 1, + LSM6DS3TR_C_FIFO_26Hz = 2, + LSM6DS3TR_C_FIFO_52Hz = 3, + LSM6DS3TR_C_FIFO_104Hz = 4, + LSM6DS3TR_C_FIFO_208Hz = 5, + LSM6DS3TR_C_FIFO_416Hz = 6, + LSM6DS3TR_C_FIFO_833Hz = 7, + LSM6DS3TR_C_FIFO_1k66Hz = 8, + LSM6DS3TR_C_FIFO_3k33Hz = 9, + LSM6DS3TR_C_FIFO_6k66Hz = 10, + LSM6DS3TR_C_FIFO_RATE_ND = 11, /* ERROR CODE */ +} lsm6ds3tr_c_odr_fifo_t; +int32_t lsm6ds3tr_c_fifo_data_rate_set(stmdev_ctx_t *ctx, + lsm6ds3tr_c_odr_fifo_t val); +int32_t lsm6ds3tr_c_fifo_data_rate_get(stmdev_ctx_t *ctx, + lsm6ds3tr_c_odr_fifo_t *val); + +typedef enum { + LSM6DS3TR_C_DEN_ACT_LOW = 0, + LSM6DS3TR_C_DEN_ACT_HIGH = 1, + LSM6DS3TR_C_DEN_POL_ND = 2, /* ERROR CODE */ +} lsm6ds3tr_c_den_lh_t; +int32_t lsm6ds3tr_c_den_polarity_set(stmdev_ctx_t *ctx, lsm6ds3tr_c_den_lh_t val); +int32_t lsm6ds3tr_c_den_polarity_get(stmdev_ctx_t *ctx, lsm6ds3tr_c_den_lh_t *val); + +typedef enum { + LSM6DS3TR_C_DEN_DISABLE = 0, + LSM6DS3TR_C_LEVEL_FIFO = 6, + LSM6DS3TR_C_LEVEL_LETCHED = 3, + LSM6DS3TR_C_LEVEL_TRIGGER = 2, + LSM6DS3TR_C_EDGE_TRIGGER = 4, + LSM6DS3TR_C_DEN_MODE_ND = 5, /* ERROR CODE */ +} lsm6ds3tr_c_den_mode_t; +int32_t lsm6ds3tr_c_den_mode_set(stmdev_ctx_t *ctx, lsm6ds3tr_c_den_mode_t val); +int32_t lsm6ds3tr_c_den_mode_get(stmdev_ctx_t *ctx, lsm6ds3tr_c_den_mode_t *val); + +typedef enum { + LSM6DS3TR_C_STAMP_IN_GY_DATA = 0, + LSM6DS3TR_C_STAMP_IN_XL_DATA = 1, + LSM6DS3TR_C_STAMP_IN_GY_XL_DATA = 2, + LSM6DS3TR_C_DEN_STAMP_ND = 3, /* ERROR CODE */ +} lsm6ds3tr_c_den_xl_en_t; +int32_t lsm6ds3tr_c_den_enable_set(stmdev_ctx_t *ctx, lsm6ds3tr_c_den_xl_en_t val); +int32_t lsm6ds3tr_c_den_enable_get(stmdev_ctx_t *ctx, lsm6ds3tr_c_den_xl_en_t *val); + +int32_t lsm6ds3tr_c_den_mark_axis_z_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6ds3tr_c_den_mark_axis_z_get(stmdev_ctx_t *ctx, uint8_t *val); + +int32_t lsm6ds3tr_c_den_mark_axis_y_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6ds3tr_c_den_mark_axis_y_get(stmdev_ctx_t *ctx, uint8_t *val); + +int32_t lsm6ds3tr_c_den_mark_axis_x_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6ds3tr_c_den_mark_axis_x_get(stmdev_ctx_t *ctx, uint8_t *val); + +int32_t lsm6ds3tr_c_pedo_step_reset_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6ds3tr_c_pedo_step_reset_get(stmdev_ctx_t *ctx, uint8_t *val); + +int32_t lsm6ds3tr_c_pedo_sens_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6ds3tr_c_pedo_sens_get(stmdev_ctx_t *ctx, uint8_t *val); + +int32_t lsm6ds3tr_c_pedo_threshold_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6ds3tr_c_pedo_threshold_get(stmdev_ctx_t *ctx, uint8_t *val); + +typedef enum { + LSM6DS3TR_C_PEDO_AT_2g = 0, + LSM6DS3TR_C_PEDO_AT_4g = 1, + LSM6DS3TR_C_PEDO_FS_ND = 2, /* ERROR CODE */ +} lsm6ds3tr_c_pedo_fs_t; +int32_t lsm6ds3tr_c_pedo_full_scale_set(stmdev_ctx_t *ctx, + lsm6ds3tr_c_pedo_fs_t val); +int32_t lsm6ds3tr_c_pedo_full_scale_get(stmdev_ctx_t *ctx, + lsm6ds3tr_c_pedo_fs_t *val); + +int32_t lsm6ds3tr_c_pedo_debounce_steps_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6ds3tr_c_pedo_debounce_steps_get(stmdev_ctx_t *ctx, uint8_t *val); + +int32_t lsm6ds3tr_c_pedo_timeout_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6ds3tr_c_pedo_timeout_get(stmdev_ctx_t *ctx, uint8_t *val); + +int32_t lsm6ds3tr_c_pedo_steps_period_set(stmdev_ctx_t *ctx, uint8_t *buff); +int32_t lsm6ds3tr_c_pedo_steps_period_get(stmdev_ctx_t *ctx, uint8_t *buff); + +int32_t lsm6ds3tr_c_motion_sens_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6ds3tr_c_motion_sens_get(stmdev_ctx_t *ctx, uint8_t *val); + +int32_t lsm6ds3tr_c_motion_threshold_set(stmdev_ctx_t *ctx, uint8_t *buff); +int32_t lsm6ds3tr_c_motion_threshold_get(stmdev_ctx_t *ctx, uint8_t *buff); + +int32_t lsm6ds3tr_c_tilt_sens_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6ds3tr_c_tilt_sens_get(stmdev_ctx_t *ctx, uint8_t *val); + +int32_t lsm6ds3tr_c_wrist_tilt_sens_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6ds3tr_c_wrist_tilt_sens_get(stmdev_ctx_t *ctx, uint8_t *val); + +int32_t lsm6ds3tr_c_tilt_latency_set(stmdev_ctx_t *ctx, uint8_t *buff); +int32_t lsm6ds3tr_c_tilt_latency_get(stmdev_ctx_t *ctx, uint8_t *buff); + +int32_t lsm6ds3tr_c_tilt_threshold_set(stmdev_ctx_t *ctx, uint8_t *buff); +int32_t lsm6ds3tr_c_tilt_threshold_get(stmdev_ctx_t *ctx, uint8_t *buff); + +int32_t lsm6ds3tr_c_tilt_src_set(stmdev_ctx_t *ctx, + lsm6ds3tr_c_a_wrist_tilt_mask_t *val); +int32_t lsm6ds3tr_c_tilt_src_get(stmdev_ctx_t *ctx, + lsm6ds3tr_c_a_wrist_tilt_mask_t *val); + +int32_t lsm6ds3tr_c_mag_soft_iron_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6ds3tr_c_mag_soft_iron_get(stmdev_ctx_t *ctx, uint8_t *val); + +int32_t lsm6ds3tr_c_mag_hard_iron_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6ds3tr_c_mag_hard_iron_get(stmdev_ctx_t *ctx, uint8_t *val); + +int32_t lsm6ds3tr_c_mag_soft_iron_mat_set(stmdev_ctx_t *ctx, uint8_t *buff); +int32_t lsm6ds3tr_c_mag_soft_iron_mat_get(stmdev_ctx_t *ctx, uint8_t *buff); + +int32_t lsm6ds3tr_c_mag_offset_set(stmdev_ctx_t *ctx, uint8_t *buff); +int32_t lsm6ds3tr_c_mag_offset_get(stmdev_ctx_t *ctx, uint8_t *buff); + +int32_t lsm6ds3tr_c_func_en_set(stmdev_ctx_t *ctx, uint8_t val); + +int32_t lsm6ds3tr_c_sh_sync_sens_frame_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6ds3tr_c_sh_sync_sens_frame_get(stmdev_ctx_t *ctx, uint8_t *val); + +typedef enum { + LSM6DS3TR_C_RES_RATIO_2_11 = 0, + LSM6DS3TR_C_RES_RATIO_2_12 = 1, + LSM6DS3TR_C_RES_RATIO_2_13 = 2, + LSM6DS3TR_C_RES_RATIO_2_14 = 3, + LSM6DS3TR_C_RES_RATIO_ND = 4, /* ERROR CODE */ +} lsm6ds3tr_c_rr_t; +int32_t lsm6ds3tr_c_sh_sync_sens_ratio_set(stmdev_ctx_t *ctx, lsm6ds3tr_c_rr_t val); +int32_t lsm6ds3tr_c_sh_sync_sens_ratio_get(stmdev_ctx_t *ctx, lsm6ds3tr_c_rr_t *val); + +int32_t lsm6ds3tr_c_sh_master_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6ds3tr_c_sh_master_get(stmdev_ctx_t *ctx, uint8_t *val); + +int32_t lsm6ds3tr_c_sh_pass_through_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6ds3tr_c_sh_pass_through_get(stmdev_ctx_t *ctx, uint8_t *val); + +typedef enum { + LSM6DS3TR_C_EXT_PULL_UP = 0, + LSM6DS3TR_C_INTERNAL_PULL_UP = 1, + LSM6DS3TR_C_SH_PIN_MODE = 2, /* ERROR CODE */ +} lsm6ds3tr_c_pull_up_en_t; +int32_t lsm6ds3tr_c_sh_pin_mode_set(stmdev_ctx_t *ctx, lsm6ds3tr_c_pull_up_en_t val); +int32_t lsm6ds3tr_c_sh_pin_mode_get(stmdev_ctx_t *ctx, lsm6ds3tr_c_pull_up_en_t *val); + +typedef enum { + LSM6DS3TR_C_XL_GY_DRDY = 0, + LSM6DS3TR_C_EXT_ON_INT2_PIN = 1, + LSM6DS3TR_C_SH_SYNCRO_ND = 2, /* ERROR CODE */ +} lsm6ds3tr_c_start_config_t; +int32_t lsm6ds3tr_c_sh_syncro_mode_set(stmdev_ctx_t *ctx, + lsm6ds3tr_c_start_config_t val); +int32_t lsm6ds3tr_c_sh_syncro_mode_get(stmdev_ctx_t *ctx, + lsm6ds3tr_c_start_config_t *val); + +int32_t lsm6ds3tr_c_sh_drdy_on_int1_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6ds3tr_c_sh_drdy_on_int1_get(stmdev_ctx_t *ctx, uint8_t *val); + +typedef struct { + lsm6ds3tr_c_sensorhub1_reg_t sh_byte_1; + lsm6ds3tr_c_sensorhub2_reg_t sh_byte_2; + lsm6ds3tr_c_sensorhub3_reg_t sh_byte_3; + lsm6ds3tr_c_sensorhub4_reg_t sh_byte_4; + lsm6ds3tr_c_sensorhub5_reg_t sh_byte_5; + lsm6ds3tr_c_sensorhub6_reg_t sh_byte_6; + lsm6ds3tr_c_sensorhub7_reg_t sh_byte_7; + lsm6ds3tr_c_sensorhub8_reg_t sh_byte_8; + lsm6ds3tr_c_sensorhub9_reg_t sh_byte_9; + lsm6ds3tr_c_sensorhub10_reg_t sh_byte_10; + lsm6ds3tr_c_sensorhub11_reg_t sh_byte_11; + lsm6ds3tr_c_sensorhub12_reg_t sh_byte_12; + lsm6ds3tr_c_sensorhub13_reg_t sh_byte_13; + lsm6ds3tr_c_sensorhub14_reg_t sh_byte_14; + lsm6ds3tr_c_sensorhub15_reg_t sh_byte_15; + lsm6ds3tr_c_sensorhub16_reg_t sh_byte_16; + lsm6ds3tr_c_sensorhub17_reg_t sh_byte_17; + lsm6ds3tr_c_sensorhub18_reg_t sh_byte_18; +} lsm6ds3tr_c_emb_sh_read_t; +int32_t lsm6ds3tr_c_sh_read_data_raw_get(stmdev_ctx_t *ctx, + lsm6ds3tr_c_emb_sh_read_t *val); + +int32_t lsm6ds3tr_c_sh_cmd_sens_sync_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6ds3tr_c_sh_cmd_sens_sync_get(stmdev_ctx_t *ctx, uint8_t *val); + +int32_t lsm6ds3tr_c_sh_spi_sync_error_set(stmdev_ctx_t *ctx, uint8_t val); +int32_t lsm6ds3tr_c_sh_spi_sync_error_get(stmdev_ctx_t *ctx, uint8_t *val); + +typedef enum { + LSM6DS3TR_C_SLV_0 = 0, + LSM6DS3TR_C_SLV_0_1 = 1, + LSM6DS3TR_C_SLV_0_1_2 = 2, + LSM6DS3TR_C_SLV_0_1_2_3 = 3, + LSM6DS3TR_C_SLV_EN_ND = 4, /* ERROR CODE */ +} lsm6ds3tr_c_aux_sens_on_t; +int32_t lsm6ds3tr_c_sh_num_of_dev_connected_set(stmdev_ctx_t *ctx, + lsm6ds3tr_c_aux_sens_on_t val); +int32_t lsm6ds3tr_c_sh_num_of_dev_connected_get(stmdev_ctx_t *ctx, + lsm6ds3tr_c_aux_sens_on_t *val); + +typedef struct{ + uint8_t slv0_add; + uint8_t slv0_subadd; + uint8_t slv0_data; +} lsm6ds3tr_c_sh_cfg_write_t; +int32_t lsm6ds3tr_c_sh_cfg_write(stmdev_ctx_t *ctx, lsm6ds3tr_c_sh_cfg_write_t *val); + +typedef struct{ + uint8_t slv_add; + uint8_t slv_subadd; + uint8_t slv_len; +} lsm6ds3tr_c_sh_cfg_read_t; +int32_t lsm6ds3tr_c_sh_slv0_cfg_read(stmdev_ctx_t *ctx, + lsm6ds3tr_c_sh_cfg_read_t *val); +int32_t lsm6ds3tr_c_sh_slv1_cfg_read(stmdev_ctx_t *ctx, + lsm6ds3tr_c_sh_cfg_read_t *val); +int32_t lsm6ds3tr_c_sh_slv2_cfg_read(stmdev_ctx_t *ctx, + lsm6ds3tr_c_sh_cfg_read_t *val); +int32_t lsm6ds3tr_c_sh_slv3_cfg_read(stmdev_ctx_t *ctx, + lsm6ds3tr_c_sh_cfg_read_t *val); + +typedef enum { + LSM6DS3TR_C_SL0_NO_DEC = 0, + LSM6DS3TR_C_SL0_DEC_2 = 1, + LSM6DS3TR_C_SL0_DEC_4 = 2, + LSM6DS3TR_C_SL0_DEC_8 = 3, + LSM6DS3TR_C_SL0_DEC_ND = 4, /* ERROR CODE */ +} lsm6ds3tr_c_slave0_rate_t; +int32_t lsm6ds3tr_c_sh_slave_0_dec_set(stmdev_ctx_t *ctx, + lsm6ds3tr_c_slave0_rate_t val); +int32_t lsm6ds3tr_c_sh_slave_0_dec_get(stmdev_ctx_t *ctx, + lsm6ds3tr_c_slave0_rate_t *val); + +typedef enum { + LSM6DS3TR_C_EACH_SH_CYCLE = 0, + LSM6DS3TR_C_ONLY_FIRST_CYCLE = 1, + LSM6DS3TR_C_SH_WR_MODE_ND = 2, /* ERROR CODE */ +} lsm6ds3tr_c_write_once_t; +int32_t lsm6ds3tr_c_sh_write_mode_set(stmdev_ctx_t *ctx, + lsm6ds3tr_c_write_once_t val); +int32_t lsm6ds3tr_c_sh_write_mode_get(stmdev_ctx_t *ctx, + lsm6ds3tr_c_write_once_t *val); + +typedef enum { + LSM6DS3TR_C_SL1_NO_DEC = 0, + LSM6DS3TR_C_SL1_DEC_2 = 1, + LSM6DS3TR_C_SL1_DEC_4 = 2, + LSM6DS3TR_C_SL1_DEC_8 = 3, + LSM6DS3TR_C_SL1_DEC_ND = 4, /* ERROR CODE */ +} lsm6ds3tr_c_slave1_rate_t; +int32_t lsm6ds3tr_c_sh_slave_1_dec_set(stmdev_ctx_t *ctx, + lsm6ds3tr_c_slave1_rate_t val); +int32_t lsm6ds3tr_c_sh_slave_1_dec_get(stmdev_ctx_t *ctx, + lsm6ds3tr_c_slave1_rate_t *val); + +typedef enum { + LSM6DS3TR_C_SL2_NO_DEC = 0, + LSM6DS3TR_C_SL2_DEC_2 = 1, + LSM6DS3TR_C_SL2_DEC_4 = 2, + LSM6DS3TR_C_SL2_DEC_8 = 3, + LSM6DS3TR_C_SL2_DEC_ND = 4, /* ERROR CODE */ +} lsm6ds3tr_c_slave2_rate_t; +int32_t lsm6ds3tr_c_sh_slave_2_dec_set(stmdev_ctx_t *ctx, + lsm6ds3tr_c_slave2_rate_t val); +int32_t lsm6ds3tr_c_sh_slave_2_dec_get(stmdev_ctx_t *ctx, + lsm6ds3tr_c_slave2_rate_t *val); + +typedef enum { + LSM6DS3TR_C_SL3_NO_DEC = 0, + LSM6DS3TR_C_SL3_DEC_2 = 1, + LSM6DS3TR_C_SL3_DEC_4 = 2, + LSM6DS3TR_C_SL3_DEC_8 = 3, + LSM6DS3TR_C_SL3_DEC_ND = 4, /* ERROR CODE */ +} lsm6ds3tr_c_slave3_rate_t; +int32_t lsm6ds3tr_c_sh_slave_3_dec_set(stmdev_ctx_t *ctx, + lsm6ds3tr_c_slave3_rate_t val); +int32_t lsm6ds3tr_c_sh_slave_3_dec_get(stmdev_ctx_t *ctx, + lsm6ds3tr_c_slave3_rate_t *val); + +/** + * @} + * + */ + +#ifdef __cplusplus +} +#endif + +#endif /* LSM6DS3TR_C_DRIVER_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/st/src/lsm6ds3_reg.c b/src/st/src/lsm6ds3_reg.c new file mode 100644 index 000000000..a86c03bc8 --- /dev/null +++ b/src/st/src/lsm6ds3_reg.c @@ -0,0 +1,5910 @@ +/* + ****************************************************************************** + * @file lsm6ds3_reg.c + * @author Sensors Software Solution Team + * @brief LSM6DS3 driver file + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2019 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ +#include "lsm6ds3_reg.h" + +/** + * @defgroup LSM6DS3 + * @brief This file provides a set of functions needed to drive the + * lsm6ds3 enhanced inertial module. + * @{ + * + */ + +/** + * @defgroup LSM6DS3_Interfaces_Functions + * @brief This section provide a set of functions used to read and + * write a generic register of the device. + * MANDATORY: return 0 -> no Error. + * @{ + * + */ + +/** + * @brief Read generic device register + * + * @param ctx read / write interface definitions(ptr) + * @param reg register to read + * @param data pointer to buffer that store the data read(ptr) + * @param len number of consecutive register to read + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6ds3_read_reg(stmdev_ctx_t* ctx, uint8_t reg, uint8_t* data, + uint16_t len) +{ + int32_t ret; + ret = ctx->read_reg(ctx->handle, reg, data, len); + return ret; +} + +/** + * @brief Write generic device register + * + * @param ctx read / write interface definitions(ptr) + * @param reg register to write + * @param data pointer to data to write in register reg(ptr) + * @param len number of consecutive register to write + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6ds3_write_reg(stmdev_ctx_t* ctx, uint8_t reg, uint8_t* data, + uint16_t len) +{ + int32_t ret; + ret = ctx->write_reg(ctx->handle, reg, data, len); + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup LSM6DS3_Sensitivity + * @brief These functions convert raw-data into engineering units. + * @{ + * + */ + +float_t lsm6ds3_from_fs2g_to_mg(int16_t lsb) +{ + return ((float_t)lsb * 61.0f / 1000.0f); +} + +float_t lsm6ds3_from_fs4g_to_mg(int16_t lsb) +{ + return ((float_t)lsb * 122.0f / 1000.0f); +} + +float_t lsm6ds3_from_fs8g_to_mg(int16_t lsb) +{ + return ((float_t)lsb * 244.0f / 1000.0f); +} + +float_t lsm6ds3_from_fs16g_to_mg(int16_t lsb) +{ + return ((float_t)lsb * 488.0f / 1000.0f); +} + +float_t lsm6ds3_from_fs125dps_to_mdps(int16_t lsb) +{ + return ((float_t)lsb * 4375.0f / 1000.0f); +} + +float_t lsm6ds3_from_fs250dps_to_mdps(int16_t lsb) +{ + return ((float_t)lsb * 8750.0f / 1000.0f); +} + +float_t lsm6ds3_from_fs500dps_to_mdps(int16_t lsb) +{ + return ((float_t)lsb * 1750.0f / 100.0f); +} + +float_t lsm6ds3_from_fs1000dps_to_mdps(int16_t lsb) +{ + return ((float_t)lsb * 35.0f); +} + +float_t lsm6ds3_from_fs2000dps_to_mdps(int16_t lsb) +{ + return ((float_t)lsb * 70.0f); +} + +float_t lsm6ds3_from_lsb_to_celsius(int16_t lsb) +{ + return ((float_t)lsb / 16.0f + 25.0f ); +} + +/** + * @} + * + */ + +/** + * @defgroup LSM6DS3_Data_generation + * @brief This section groups all the functions concerning + * data generation + * @{ + * + */ + +/** + * @brief Gyroscope directional user-orientation selection.[set] + * + * @param ctx read / write interface definitions(ptr) + * @param val change the values of orient in reg LSM6DS3 + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6ds3_gy_data_orient_set(stmdev_ctx_t *ctx, lsm6ds3_gy_orient_t val) +{ + lsm6ds3_orient_cfg_g_t orient_cfg_g; + int32_t ret; + + ret = lsm6ds3_read_reg(ctx, LSM6DS3_ORIENT_CFG_G, + (uint8_t*)&orient_cfg_g, 1); + if(ret == 0){ + orient_cfg_g.orient = (uint8_t)val; + ret = lsm6ds3_write_reg(ctx, LSM6DS3_ORIENT_CFG_G, + (uint8_t*)&orient_cfg_g, 1); + } + return ret; +} + +/** + * @brief Gyroscope directional user-orientation selection.[get] + * + * @param ctx read / write interface definitions(ptr) + * @param val get the values of orient in reg ORIENT_CFG_G + * + */ +int32_t lsm6ds3_gy_data_orient_get(stmdev_ctx_t *ctx, + lsm6ds3_gy_orient_t *val) +{ + lsm6ds3_orient_cfg_g_t orient_cfg_g; + int32_t ret; + + ret = lsm6ds3_read_reg(ctx, LSM6DS3_ORIENT_CFG_G, + (uint8_t*)&orient_cfg_g, 1); + + switch (orient_cfg_g.orient) + { + case LSM6DS3_GY_ORIENT_XYZ: + *val = LSM6DS3_GY_ORIENT_XYZ; + break; + case LSM6DS3_GY_ORIENT_XZY: + *val = LSM6DS3_GY_ORIENT_XZY; + break; + case LSM6DS3_GY_ORIENT_YXZ: + *val = LSM6DS3_GY_ORIENT_YXZ; + break; + case LSM6DS3_GY_ORIENT_YZX: + *val = LSM6DS3_GY_ORIENT_YZX; + break; + case LSM6DS3_GY_ORIENT_ZXY: + *val = LSM6DS3_GY_ORIENT_ZXY; + break; + case LSM6DS3_GY_ORIENT_ZYX: + *val = LSM6DS3_GY_ORIENT_ZYX; + break; + default: + *val = LSM6DS3_GY_ORIENT_XYZ; + break; + } + return ret; +} + +/** + * @brief angular rate sign.[set] + * + * @param ctx read / write interface definitions(ptr) + * @param val change the values of sign_g in reg LSM6DS3 + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6ds3_gy_data_sign_set(stmdev_ctx_t *ctx, lsm6ds3_gy_sgn_t val) +{ + lsm6ds3_orient_cfg_g_t orient_cfg_g; + int32_t ret; + + ret = lsm6ds3_read_reg(ctx, LSM6DS3_ORIENT_CFG_G, + (uint8_t*)&orient_cfg_g, 1); + if(ret == 0){ + orient_cfg_g.sign_g = (uint8_t)val; + ret = lsm6ds3_write_reg(ctx, LSM6DS3_ORIENT_CFG_G, + (uint8_t*)&orient_cfg_g, 1); + } + return ret; +} + +/** + * @brief angularratesign.[get] + * + * @param ctx read / write interface definitions(ptr) + * @param val get the values of sign_g in reg ORIENT_CFG_G + * + */ +int32_t lsm6ds3_gy_data_sign_get(stmdev_ctx_t *ctx, lsm6ds3_gy_sgn_t *val) +{ + lsm6ds3_orient_cfg_g_t orient_cfg_g; + int32_t ret; + + ret = lsm6ds3_read_reg(ctx, LSM6DS3_ORIENT_CFG_G, + (uint8_t*)&orient_cfg_g, 1); + + switch (orient_cfg_g.sign_g) + { + case LSM6DS3_GY_SIGN_PPP: + *val =LSM6DS3_GY_SIGN_PPP; + break; + case LSM6DS3_GY_SIGN_PPN: + *val = LSM6DS3_GY_SIGN_PPN; + break; + case LSM6DS3_GY_SIGN_PNP: + *val = LSM6DS3_GY_SIGN_PNP; + break; + case LSM6DS3_GY_SIGN_NPP: + *val = LSM6DS3_GY_SIGN_NPP; + break; + case LSM6DS3_GY_SIGN_NNP: + *val = LSM6DS3_GY_SIGN_NNP; + break; + case LSM6DS3_GY_SIGN_NPN: + *val = LSM6DS3_GY_SIGN_NPN; + break; + case LSM6DS3_GY_SIGN_PNN: + *val = LSM6DS3_GY_SIGN_PNN; + break; + case LSM6DS3_GY_SIGN_NNN: + *val = LSM6DS3_GY_SIGN_NNN; + break; + default: + *val = LSM6DS3_GY_SIGN_PPP; + break; + } + return ret; +} + +/** + * @brief Accelerometer full-scale selection.[set] + * + * @param ctx read / write interface definitions(ptr) + * @param val change the values of fs_xl in reg LSM6DS3 + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6ds3_xl_full_scale_set(stmdev_ctx_t *ctx, lsm6ds3_xl_fs_t val) +{ + lsm6ds3_ctrl1_xl_t ctrl1_xl; + int32_t ret; + + ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL1_XL, (uint8_t*)&ctrl1_xl, 1); + if(ret == 0){ + ctrl1_xl.fs_xl = (uint8_t)val; + ret = lsm6ds3_write_reg(ctx, LSM6DS3_CTRL1_XL, (uint8_t*)&ctrl1_xl, 1); + } + return ret; +} + +/** + * @brief Accelerometer full-scale selection.[get] + * + * @param ctx read / write interface definitions(ptr) + * @param val get the values of fs_xl in reg CTRL1_XL + * + */ +int32_t lsm6ds3_xl_full_scale_get(stmdev_ctx_t *ctx, lsm6ds3_xl_fs_t *val) +{ + lsm6ds3_ctrl1_xl_t ctrl1_xl; + int32_t ret; + + ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL1_XL, (uint8_t*)&ctrl1_xl, 1); + + switch (ctrl1_xl.fs_xl) + { + case LSM6DS3_2g: + *val = LSM6DS3_2g; + break; + case LSM6DS3_16g: + *val = LSM6DS3_16g; + break; + case LSM6DS3_4g: + *val = LSM6DS3_4g; + break; + case LSM6DS3_8g: + *val = LSM6DS3_8g; + break; + default: + *val = LSM6DS3_2g; + break; + } + return ret; +} + +/** + * @brief Accelerometer data rate selection.[set] + * + * @param ctx read / write interface definitions(ptr) + * @param val change the values of odr_xl in reg LSM6DS3 + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6ds3_xl_data_rate_set(stmdev_ctx_t *ctx, lsm6ds3_odr_xl_t val) +{ + lsm6ds3_ctrl1_xl_t ctrl1_xl; + int32_t ret; + + ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL1_XL, (uint8_t*)&ctrl1_xl, 1); + if(ret == 0){ + ctrl1_xl.odr_xl = (uint8_t)val; + ret = lsm6ds3_write_reg(ctx, LSM6DS3_CTRL1_XL, (uint8_t*)&ctrl1_xl, 1); + } + return ret; +} + +/** + * @brief Accelerometer data rate selection.[get] + * + * @param ctx read / write interface definitions(ptr) + * @param val get the values of odr_xl in reg CTRL1_XL + * + */ +int32_t lsm6ds3_xl_data_rate_get(stmdev_ctx_t *ctx, lsm6ds3_odr_xl_t *val) +{ + lsm6ds3_ctrl1_xl_t ctrl1_xl; + int32_t ret; + + ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL1_XL, (uint8_t*)&ctrl1_xl, 1); + + switch (ctrl1_xl.odr_xl) + { + case LSM6DS3_XL_ODR_OFF: + *val = LSM6DS3_XL_ODR_OFF; + break; + case LSM6DS3_XL_ODR_12Hz5: + *val = LSM6DS3_XL_ODR_12Hz5; + break; + case LSM6DS3_XL_ODR_26Hz: + *val = LSM6DS3_XL_ODR_26Hz; + break; + case LSM6DS3_XL_ODR_52Hz: + *val = LSM6DS3_XL_ODR_52Hz; + break; + case LSM6DS3_XL_ODR_104Hz: + *val = LSM6DS3_XL_ODR_104Hz; + break; + case LSM6DS3_XL_ODR_208Hz: + *val = LSM6DS3_XL_ODR_208Hz; + break; + case LSM6DS3_XL_ODR_416Hz: + *val = LSM6DS3_XL_ODR_416Hz; + break; + case LSM6DS3_XL_ODR_833Hz: + *val = LSM6DS3_XL_ODR_833Hz; + break; + case LSM6DS3_XL_ODR_1k66Hz: + *val = LSM6DS3_XL_ODR_1k66Hz; + break; + case LSM6DS3_XL_ODR_3k33Hz: + *val = LSM6DS3_XL_ODR_3k33Hz; + break; + case LSM6DS3_XL_ODR_6k66Hz: + *val = LSM6DS3_XL_ODR_6k66Hz; + break; + default: + *val = LSM6DS3_XL_ODR_OFF; + break; + } + return ret; +} + +/** + * @brief Gyroscope UI chain full-scale selection.[set] + * + * @param ctx read / write interface definitions(ptr) + * @param val change the values of fs_g in reg LSM6DS3 + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6ds3_gy_full_scale_set(stmdev_ctx_t *ctx, lsm6ds3_fs_g_t val) +{ + lsm6ds3_ctrl2_g_t ctrl2_g; + int32_t ret; + + ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL2_G, (uint8_t*)&ctrl2_g, 1); + if(ret == 0){ + ctrl2_g.fs_g = (uint8_t)val; + ret = lsm6ds3_write_reg(ctx, LSM6DS3_CTRL2_G, (uint8_t*)&ctrl2_g, 1); + } + return ret; +} + +/** + * @brief Gyroscope UI chain full-scale selection.[get] + * + * @param ctx read / write interface definitions(ptr) + * @param val get the values of fs_g in reg CTRL2_G + * + */ +int32_t lsm6ds3_gy_full_scale_get(stmdev_ctx_t *ctx, lsm6ds3_fs_g_t *val) +{ + lsm6ds3_ctrl2_g_t ctrl2_g; + int32_t ret; + + ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL2_G, (uint8_t*)&ctrl2_g, 1); + + switch (ctrl2_g.fs_g) + { + case LSM6DS3_250dps: + *val = LSM6DS3_250dps; + break; + case LSM6DS3_125dps: + *val = LSM6DS3_125dps; + break; + case LSM6DS3_500dps: + *val = LSM6DS3_500dps; + break; + case LSM6DS3_1000dps: + *val = LSM6DS3_1000dps; + break; + case LSM6DS3_2000dps: + *val = LSM6DS3_2000dps; + break; + default: + *val = LSM6DS3_250dps; + break; + } + return ret; +} + +/** + * @brief Gyroscope UI data rate selection.[set] + * + * @param ctx read / write interface definitions(ptr) + * @param val change the values of odr_g in reg LSM6DS3 + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6ds3_gy_data_rate_set(stmdev_ctx_t *ctx, lsm6ds3_odr_g_t val) +{ + lsm6ds3_ctrl2_g_t ctrl2_g; + int32_t ret; + + ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL2_G, (uint8_t*)&ctrl2_g, 1); + if(ret == 0){ + ctrl2_g.odr_g = (uint8_t)val; + ret = lsm6ds3_write_reg(ctx, LSM6DS3_CTRL2_G, (uint8_t*)&ctrl2_g, 1); + } + return ret; +} + +/** + * @brief Gyroscope UI data rate selection.[get] + * + * @param ctx read / write interface definitions(ptr) + * @param val get the values of odr_g in reg CTRL2_G + * + */ +int32_t lsm6ds3_gy_data_rate_get(stmdev_ctx_t *ctx, lsm6ds3_odr_g_t *val) +{ + lsm6ds3_ctrl2_g_t ctrl2_g; + int32_t ret; + + ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL2_G, (uint8_t*)&ctrl2_g, 1); + + switch (ctrl2_g.odr_g) + { + case LSM6DS3_GY_ODR_OFF: + *val = LSM6DS3_GY_ODR_OFF; + break; + case LSM6DS3_GY_ODR_12Hz5: + *val = LSM6DS3_GY_ODR_12Hz5; + break; + case LSM6DS3_GY_ODR_26Hz: + *val = LSM6DS3_GY_ODR_26Hz; + break; + case LSM6DS3_GY_ODR_52Hz: + *val = LSM6DS3_GY_ODR_52Hz; + break; + case LSM6DS3_GY_ODR_104Hz: + *val = LSM6DS3_GY_ODR_104Hz; + break; + case LSM6DS3_GY_ODR_208Hz: + *val = LSM6DS3_GY_ODR_208Hz; + break; + case LSM6DS3_GY_ODR_416Hz: + *val = LSM6DS3_GY_ODR_416Hz; + break; + case LSM6DS3_GY_ODR_833Hz: + *val = LSM6DS3_GY_ODR_833Hz; + break; + case LSM6DS3_GY_ODR_1k66Hz: + *val = LSM6DS3_GY_ODR_1k66Hz; + break; + default: + *val = LSM6DS3_GY_ODR_OFF; + break; + } + return ret; +} + +/** + * @brief Blockdataupdate.[set] + * + * @param ctx read / write interface definitions(ptr) + * @param val change the values of bdu in reg CTRL3_C + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6ds3_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6ds3_ctrl3_c_t ctrl3_c; + int32_t ret; + + ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL3_C, (uint8_t*)&ctrl3_c, 1); + if(ret == 0){ + ctrl3_c.bdu = (uint8_t)val; + ret = lsm6ds3_write_reg(ctx, LSM6DS3_CTRL3_C, (uint8_t*)&ctrl3_c, 1); + } + return ret; +} + +/** + * @brief Blockdataupdate.[get] + * + * @param ctx read / write interface definitions(ptr) + * @param val get the values of bdu in reg CTRL3_C + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6ds3_block_data_update_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6ds3_ctrl3_c_t ctrl3_c; + int32_t ret; + + ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL3_C, (uint8_t*)&ctrl3_c, 1); + *val = (uint8_t)ctrl3_c.bdu; + + return ret; +} + +/** + * @brief High-performance operating mode for accelerometer.[set] + * + * @param ctx read / write interface definitions(ptr) + * @param val change the values of xl_hm_mode in reg LSM6DS3 + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6ds3_xl_power_mode_set(stmdev_ctx_t *ctx, lsm6ds3_xl_hm_mode_t val) +{ + lsm6ds3_ctrl6_c_t ctrl6_c; + int32_t ret; + + ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL6_C, (uint8_t*)&ctrl6_c, 1); + if(ret == 0){ + ctrl6_c.xl_hm_mode = (uint8_t)val; + ret = lsm6ds3_write_reg(ctx, LSM6DS3_CTRL6_C, (uint8_t*)&ctrl6_c, 1); + } + return ret; +} + +/** + * @brief High-performance operating mode for accelerometer.[get] + * + * @param ctx read / write interface definitions(ptr) + * @param val get the values of xl_hm_mode in reg CTRL6_C + * + */ +int32_t lsm6ds3_xl_power_mode_get(stmdev_ctx_t *ctx, + lsm6ds3_xl_hm_mode_t *val) +{ + lsm6ds3_ctrl6_c_t ctrl6_c; + int32_t ret; + + ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL6_C, (uint8_t*)&ctrl6_c, 1); + + switch (ctrl6_c.xl_hm_mode) + { + case LSM6DS3_XL_HIGH_PERFORMANCE: + *val = LSM6DS3_XL_HIGH_PERFORMANCE; + break; + case LSM6DS3_XL_NORMAL: + *val = LSM6DS3_XL_NORMAL; + break; + default: + *val = LSM6DS3_XL_HIGH_PERFORMANCE; + break; + } + return ret; +} + +/** + * @brief Source register rounding function on ADD HERE ROUNDING REGISTERS.[set] + * + * @param ctx read / write interface definitions(ptr) + * @param val change the values of rounding_status in reg LSM6DS3 + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6ds3_rounding_on_status_set(stmdev_ctx_t *ctx, lsm6ds3_rnd_stat_t val) +{ + lsm6ds3_ctrl7_g_t ctrl7_g; + int32_t ret; + + ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL7_G, (uint8_t*)&ctrl7_g, 1); + if(ret == 0){ + ctrl7_g.rounding_status = (uint8_t)val; + ret = lsm6ds3_write_reg(ctx, LSM6DS3_CTRL7_G, (uint8_t*)&ctrl7_g, 1); + } + return ret; +} + +/** + * @brief Source register rounding function on ADD HERE ROUNDING REGISTERS.[get] + * + * @param ctx read / write interface definitions(ptr) + * @param val get the values of rounding_status in reg CTRL7_G + * + */ +int32_t lsm6ds3_rounding_on_status_get(stmdev_ctx_t *ctx, + lsm6ds3_rnd_stat_t *val) +{ + lsm6ds3_ctrl7_g_t ctrl7_g; + int32_t ret; + + ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL7_G, (uint8_t*)&ctrl7_g, 1); + + switch (ctrl7_g.rounding_status) + { + case LSM6DS3_STAT_RND_DISABLE: + *val = LSM6DS3_STAT_RND_DISABLE; + break; + case LSM6DS3_STAT_RND_ENABLE: + *val = LSM6DS3_STAT_RND_ENABLE; + break; + default: + *val = LSM6DS3_STAT_RND_DISABLE; + break; + } + return ret; +} + +/** + * @brief High-performance operating mode disable for gyroscope.[set] + * + * @param ctx read / write interface definitions(ptr) + * @param val change the values of g_hm_mode in reg LSM6DS3 + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6ds3_gy_power_mode_set(stmdev_ctx_t *ctx, lsm6ds3_g_hm_mode_t val) +{ + lsm6ds3_ctrl7_g_t ctrl7_g; + int32_t ret; + + ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL7_G, (uint8_t*)&ctrl7_g, 1); + if(ret == 0){ + ctrl7_g.g_hm_mode = (uint8_t)val; + ret = lsm6ds3_write_reg(ctx, LSM6DS3_CTRL7_G, (uint8_t*)&ctrl7_g, 1); + } + return ret; +} + +/** + * @brief High-performance operating mode disable for gyroscope.[get] + * + * @param ctx read / write interface definitions(ptr) + * @param val get the values of g_hm_mode in reg CTRL7_G + * + */ +int32_t lsm6ds3_gy_power_mode_get(stmdev_ctx_t *ctx, lsm6ds3_g_hm_mode_t *val) +{ + lsm6ds3_ctrl7_g_t ctrl7_g; + int32_t ret; + + ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL7_G, (uint8_t*)&ctrl7_g, 1); + + switch (ctrl7_g.g_hm_mode) + { + case LSM6DS3_GY_HIGH_PERFORMANCE: + *val = LSM6DS3_GY_HIGH_PERFORMANCE; + break; + case LSM6DS3_GY_NORMAL: + *val = LSM6DS3_GY_NORMAL; + break; + default: + *val = LSM6DS3_GY_HIGH_PERFORMANCE; + break; + } + return ret; +} + +/** + * @brief Accelerometer X-axis output enable/disable.[set] + * + * @param ctx read / write interface definitions(ptr) + * @param val change the values of xen_xl in reg CTRL9_XL + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6ds3_xl_axis_x_data_set(stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6ds3_ctrl9_xl_t ctrl9_xl; + int32_t ret; + + ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL9_XL, (uint8_t*)&ctrl9_xl, 1); + if(ret == 0){ + ctrl9_xl.xen_xl = (uint8_t)val; + ret = lsm6ds3_write_reg(ctx, LSM6DS3_CTRL9_XL, (uint8_t*)&ctrl9_xl, 1); + } + return ret; +} + +/** + * @brief Accelerometer X-axis output enable/disable.[get] + * + * @param ctx read / write interface definitions(ptr) + * @param val get the values of xen_xl in reg CTRL9_XL + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6ds3_xl_axis_x_data_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6ds3_ctrl9_xl_t ctrl9_xl; + int32_t ret; + + ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL9_XL, (uint8_t*)&ctrl9_xl, 1); + *val = (uint8_t)ctrl9_xl.xen_xl; + + return ret; +} + +/** + * @brief Accelerometer Y-axis output enable/disable.[set] + * + * @param ctx read / write interface definitions(ptr) + * @param val change the values of yen_xl in reg CTRL9_XL + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6ds3_xl_axis_y_data_set(stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6ds3_ctrl9_xl_t ctrl9_xl; + int32_t ret; + + ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL9_XL, (uint8_t*)&ctrl9_xl, 1); + if(ret == 0){ + ctrl9_xl.yen_xl = (uint8_t)val; + ret = lsm6ds3_write_reg(ctx, LSM6DS3_CTRL9_XL, (uint8_t*)&ctrl9_xl, 1); + } + return ret; +} + +/** + * @brief Accelerometer Y-axis output enable/disable.[get] + * + * @param ctx read / write interface definitions(ptr) + * @param val get the values of yen_xl in reg CTRL9_XL + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6ds3_xl_axis_y_data_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6ds3_ctrl9_xl_t ctrl9_xl; + int32_t ret; + + ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL9_XL, (uint8_t*)&ctrl9_xl, 1); + *val = (uint8_t)ctrl9_xl.yen_xl; + + return ret; +} + +/** + * @brief Accelerometer Z-axis output enable/disable.[set] + * + * @param ctx read / write interface definitions(ptr) + * @param val change the values of zen_xl in reg CTRL9_XL + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6ds3_xl_axis_z_data_set(stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6ds3_ctrl9_xl_t ctrl9_xl; + int32_t ret; + + ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL9_XL, (uint8_t*)&ctrl9_xl, 1); + if(ret == 0){ + ctrl9_xl.zen_xl = (uint8_t)val; + ret = lsm6ds3_write_reg(ctx, LSM6DS3_CTRL9_XL, (uint8_t*)&ctrl9_xl, 1); + } + return ret; +} + +/** + * @brief Accelerometer Z-axis output enable/disable.[get] + * + * @param ctx read / write interface definitions(ptr) + * @param val get the values of zen_xl in reg CTRL9_XL + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6ds3_xl_axis_z_data_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6ds3_ctrl9_xl_t ctrl9_xl; + int32_t ret; + + ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL9_XL, (uint8_t*)&ctrl9_xl, 1); + *val = (uint8_t)ctrl9_xl.zen_xl; + + return ret; +} + +/** + * @brief Gyroscope pitch axis (X) output enable/disable.[set] + * + * @param ctx read / write interface definitions(ptr) + * @param val change the values of xen_g in reg CTRL10_C + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6ds3_gy_axis_x_data_set(stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6ds3_ctrl10_c_t ctrl10_c; + int32_t ret; + + ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL10_C, (uint8_t*)&ctrl10_c, 1); + if(ret == 0){ + ctrl10_c.xen_g = (uint8_t)val; + ret = lsm6ds3_write_reg(ctx, LSM6DS3_CTRL10_C, (uint8_t*)&ctrl10_c, 1); + } + return ret; +} + +/** + * @brief Gyroscope pitch axis (X) output enable/disable.[get] + * + * @param ctx read / write interface definitions(ptr) + * @param val get the values of xen_g in reg CTRL10_C + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6ds3_gy_axis_x_data_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6ds3_ctrl10_c_t ctrl10_c; + int32_t ret; + + ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL10_C, (uint8_t*)&ctrl10_c, 1); + *val = (uint8_t)ctrl10_c.xen_g; + + return ret; +} + +/** + * @brief Gyroscope pitch axis (Y) output enable/disable.[set] + * + * @param ctx read / write interface definitions(ptr) + * @param val change the values of yen_g in reg CTRL10_C + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6ds3_gy_axis_y_data_set(stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6ds3_ctrl10_c_t ctrl10_c; + int32_t ret; + + ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL10_C, (uint8_t*)&ctrl10_c, 1); + if(ret == 0){ + ctrl10_c.yen_g = (uint8_t)val; + ret = lsm6ds3_write_reg(ctx, LSM6DS3_CTRL10_C, (uint8_t*)&ctrl10_c, 1); + } + return ret; +} + +/** + * @brief Gyroscope pitch axis (Y) output enable/disable.[get] + * + * @param ctx read / write interface definitions(ptr) + * @param val get the values of yen_g in reg CTRL10_C + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6ds3_gy_axis_y_data_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6ds3_ctrl10_c_t ctrl10_c; + int32_t ret; + + ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL10_C, (uint8_t*)&ctrl10_c, 1); + *val = (uint8_t)ctrl10_c.yen_g; + + return ret; +} + +/** + * @brief Gyroscope pitch axis (Z) output enable/disable.[set] + * + * @param ctx read / write interface definitions(ptr) + * @param val change the values of zen_g in reg CTRL10_C + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6ds3_gy_axis_z_data_set(stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6ds3_ctrl10_c_t ctrl10_c; + int32_t ret; + + ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL10_C, (uint8_t*)&ctrl10_c, 1); + if(ret == 0){ + ctrl10_c.zen_g = (uint8_t)val; + ret = lsm6ds3_write_reg(ctx, LSM6DS3_CTRL10_C, (uint8_t*)&ctrl10_c, 1); + } + return ret; +} + +/** + * @brief Gyroscope pitch axis (Z) output enable/disable.[get] + * + * @param ctx read / write interface definitions(ptr) + * @param val get the values of zen_g in reg CTRL10_C + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6ds3_gy_axis_z_data_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6ds3_ctrl10_c_t ctrl10_c; + int32_t ret; + + ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL10_C, (uint8_t*)&ctrl10_c, 1); + *val = (uint8_t)ctrl10_c.zen_g; + + return ret; +} + +/** + * @brief Read all the interrupt/status flag of the device. ELENCA I REGISTRI[get] + * + * @param ctx read / write interface definitions(ptr) + * @param val Read all the interrupt flag of the device: + * WAKE_UP_SRC, TAP_SRC, D6D_SRC, FUNC_SRC. + * + */ +int32_t lsm6ds3_all_sources_get(stmdev_ctx_t *ctx, lsm6ds3_all_src_t *val) +{ + int32_t ret; + + ret = lsm6ds3_read_reg(ctx, LSM6DS3_WAKE_UP_SRC, + (uint8_t*)&(val->wake_up_src), 1); + if(ret == 0) { + ret = lsm6ds3_read_reg(ctx, LSM6DS3_TAP_SRC, + (uint8_t*)&(val->tap_src), 1); + } + if(ret == 0) { + ret = lsm6ds3_read_reg(ctx, LSM6DS3_D6D_SRC, + (uint8_t*)&(val->d6d_src), 1); + } + if(ret == 0) { + ret = lsm6ds3_read_reg(ctx, LSM6DS3_FUNC_SRC, + (uint8_t*)&(val->func_src), 1); + } + return ret; +} + +/** + * @brief The STATUS_REG register of the device.[get] + * + * @param ctx read / write interface definitions(ptr) + * @param val The STATUS_REG register of the device. + * + */ +int32_t lsm6ds3_status_reg_get(stmdev_ctx_t *ctx, lsm6ds3_status_reg_t *val) +{ + int32_t ret; + + ret = lsm6ds3_read_reg(ctx, LSM6DS3_STATUS_REG, (uint8_t*)&val, 1); + + return ret; +} + +/** + * @brief Accelerometer new data available.[get] + * + * @param ctx read / write interface definitions(ptr) + * @param val get the values of xlda in reg STATUS_REG + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6ds3_xl_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6ds3_status_reg_t status_reg; + int32_t ret; + + ret = lsm6ds3_read_reg(ctx, LSM6DS3_STATUS_REG, (uint8_t*)&status_reg, 1); + *val = (uint8_t)status_reg.xlda; + + return ret; +} + +/** + * @brief Gyroscope new data available.[get] + * + * @param ctx read / write interface definitions(ptr) + * @param val get the values of gda in reg STATUS_REG + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6ds3_gy_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6ds3_status_reg_t status_reg; + int32_t ret; + + ret = lsm6ds3_read_reg(ctx, LSM6DS3_STATUS_REG, (uint8_t*)&status_reg, 1); + *val = (uint8_t)status_reg.gda; + + return ret; +} + +/** + * @brief Temperature new data available.[get] + * + * @param ctx read / write interface definitions(ptr) + * @param val get the values of tda in reg STATUS_REG + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6ds3_temp_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6ds3_status_reg_t status_reg; + int32_t ret; + + ret = lsm6ds3_read_reg(ctx, LSM6DS3_STATUS_REG, (uint8_t*)&status_reg, 1); + *val = (uint8_t)status_reg.tda; + + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup LSM6DS3_Timestamp + * @brief This section groups all the functions that manage the + * timestamp generation. + * @{ + * + */ + +/** + * @brief Timestamp first byte data output register (r). The value is + * expressed as a 24-bit word and the bit resolution is defined + * by setting the value in WAKE_UP_DUR (5Ch).[get] + * + * @param ctx read / write interface definitions(ptr) + * @param buff buffer that stores data read + * + */ +int32_t lsm6ds3_timestamp_raw_get(stmdev_ctx_t *ctx, uint8_t *buff) +{ + int32_t ret; + ret = lsm6ds3_read_reg(ctx, LSM6DS3_TIMESTAMP0_REG, buff, + 3); + return ret; +} + +/** + * @brief Reset the timer.[set] + * + * @param ctx read / write interface definitions(ptr) + * @param buff buffer that stores data to be write + * + */ +int32_t lsm6ds3_timestamp_rst_set(stmdev_ctx_t *ctx) +{ + int32_t ret; + uint8_t rst_val = 0xAA; + + ret = lsm6ds3_write_reg(ctx, LSM6DS3_TIMESTAMP2_REG, &rst_val, 1); + return ret; +} + +/** + * @brief Timestamp count enable, output data are collected in + * TIMESTAMP0_REG (40h), TIMESTAMP1_REG (41h), + * TIMESTAMP2_REG (42h) register.[set] + * + * @param ctx read / write interface definitions(ptr) + * @param val change the values of timer_en in reg TAP_CFG + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6ds3_timestamp_set(stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6ds3_tap_cfg_t tap_cfg; + int32_t ret; + + ret = lsm6ds3_read_reg(ctx, LSM6DS3_TAP_CFG, (uint8_t*)&tap_cfg, 1); + if(ret == 0){ + tap_cfg.timer_en = (uint8_t)val; + ret = lsm6ds3_write_reg(ctx, LSM6DS3_TAP_CFG, (uint8_t*)&tap_cfg, 1); + } + return ret; +} + +/** + * @brief Timestamp count enable, output data are collected in + * TIMESTAMP0_REG (40h), TIMESTAMP1_REG (41h), + * TIMESTAMP2_REG (42h) register.[get] + * + * @param ctx read / write interface definitions(ptr) + * @param val get the values of timer_en in reg TAP_CFG + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6ds3_timestamp_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6ds3_tap_cfg_t tap_cfg; + int32_t ret; + + ret = lsm6ds3_read_reg(ctx, LSM6DS3_TAP_CFG, (uint8_t*)&tap_cfg, 1); + *val = (uint8_t)tap_cfg.timer_en; + + return ret; +} + +/** + * @brief Timestamp register resolution setting.[set] + * + * @param ctx read / write interface definitions(ptr) + * @param val change the values of timer_hr in reg LSM6DS3 + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6ds3_timestamp_res_set(stmdev_ctx_t *ctx, lsm6ds3_ts_res_t val) +{ + lsm6ds3_wake_up_dur_t wake_up_dur; + int32_t ret; + + ret = lsm6ds3_read_reg(ctx, LSM6DS3_WAKE_UP_DUR, (uint8_t*)&wake_up_dur, 1); + if(ret == 0){ + wake_up_dur.timer_hr = (uint8_t)val; + ret = lsm6ds3_write_reg(ctx, LSM6DS3_WAKE_UP_DUR, + (uint8_t*)&wake_up_dur, 1); + } + return ret; +} + +/** + * @brief Timestamp register resolution setting.[get] + * + * @param ctx read / write interface definitions(ptr) + * @param val get the values of timer_hr in reg WAKE_UP_DUR + * + */ +int32_t lsm6ds3_timestamp_res_get(stmdev_ctx_t *ctx, lsm6ds3_ts_res_t *val) +{ + lsm6ds3_wake_up_dur_t wake_up_dur; + int32_t ret; + + ret = lsm6ds3_read_reg(ctx, LSM6DS3_WAKE_UP_DUR, (uint8_t*)&wake_up_dur, 1); + + switch (wake_up_dur.timer_hr) + { + case LSM6DS3_LSB_6ms4: + *val = LSM6DS3_LSB_6ms4; + break; + case LSM6DS3_LSB_25us: + *val = LSM6DS3_LSB_25us; + break; + default: + *val = LSM6DS3_LSB_6ms4; + break; + } + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup LSM6DS3_Dataoutput + * @brief This section groups all the data output functions. + * @{ + * + */ + +/** + * @brief Circular burst-mode (rounding) read from output registers + * through the primary interface.[set] + * + * @param ctx read / write interface definitions(ptr) + * @param val change the values of rounding in reg LSM6DS3 + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6ds3_rounding_mode_set(stmdev_ctx_t *ctx, lsm6ds3_rounding_t val) +{ + lsm6ds3_ctrl5_c_t ctrl5_c; + int32_t ret; + + ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL5_C, (uint8_t*)&ctrl5_c, 1); + if(ret == 0){ + ctrl5_c.rounding = (uint8_t)val; + ret = lsm6ds3_write_reg(ctx, LSM6DS3_CTRL5_C, (uint8_t*)&ctrl5_c, 1); + } + return ret; +} + +/** + * @brief Circular burst-mode (rounding) read from output registers + * through the primary interface.[get] + * + * @param ctx read / write interface definitions(ptr) + * @param val get the values of rounding in reg CTRL5_C + * + */ +int32_t lsm6ds3_rounding_mode_get(stmdev_ctx_t *ctx, lsm6ds3_rounding_t *val) +{ + lsm6ds3_ctrl5_c_t ctrl5_c; + int32_t ret; + + ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL5_C, (uint8_t*)&ctrl5_c, 1); + + switch (ctrl5_c.rounding) + { + case LSM6DS3_ROUND_DISABLE: + *val = LSM6DS3_ROUND_DISABLE; + break; + case LSM6DS3_ROUND_XL: + *val = LSM6DS3_ROUND_XL; + break; + case LSM6DS3_ROUND_GY: + *val = LSM6DS3_ROUND_GY; + break; + case LSM6DS3_ROUND_GY_XL: + *val = LSM6DS3_ROUND_GY_XL; + break; + case LSM6DS3_ROUND_SH1_TO_SH6: + *val = LSM6DS3_ROUND_SH1_TO_SH6; + break; + case LSM6DS3_ROUND_XL_SH1_TO_SH6: + *val = LSM6DS3_ROUND_XL_SH1_TO_SH6; + break; + case LSM6DS3_ROUND_GY_XL_SH1_TO_SH12: + *val = LSM6DS3_ROUND_GY_XL_SH1_TO_SH12; + break; + case LSM6DS3_ROUND_GY_XL_SH1_TO_SH6: + *val = LSM6DS3_ROUND_GY_XL_SH1_TO_SH6; + break; + default: + *val = LSM6DS3_ROUND_DISABLE; + break; + } + return ret; +} + +/** + * @brief Temperature data output register (r). L and H registers together + * express a 16-bit word in two’s complement.[get] + * + * @param ctx read / write interface definitions(ptr) + * @param buff buffer that stores data read + * + */ +int32_t lsm6ds3_temperature_raw_get(stmdev_ctx_t *ctx, uint8_t *buff) +{ + int32_t ret; + ret = lsm6ds3_read_reg(ctx, LSM6DS3_OUT_TEMP_L, buff, 2); + return ret; +} + +/** + * @brief Angular rate sensor. The value is expressed as a 16-bit word + * in two’s complement..[get] + * + * @param ctx read / write interface definitions(ptr) + * @param buff buffer that stores data read + * + */ +int32_t lsm6ds3_angular_rate_raw_get(stmdev_ctx_t *ctx, uint8_t *buff) +{ + int32_t ret; + ret = lsm6ds3_read_reg(ctx, LSM6DS3_OUTX_L_G, buff, 6); + return ret; +} + +/** + * @brief Linear acceleration output register. The value is expressed + * as a 16-bit word in two’s complement.[get] + * + * @param ctx read / write interface definitions(ptr) + * @param buff buffer that stores data read + * + */ +int32_t lsm6ds3_acceleration_raw_get(stmdev_ctx_t *ctx, uint8_t *buff) +{ + int32_t ret; + ret = lsm6ds3_read_reg(ctx, LSM6DS3_OUTX_L_XL, buff, 6); + return ret; +} + +/** + * @brief fifo_raw_data: [get] read data in FIFO. + * + * @param stmdev_ctx_t *ctx: read / write interface definitions + * @param uint8_t *: data buffer to store FIFO data. + * @param uint8_t : number of data to read from FIFO. + * + */ +int32_t lsm6ds3_fifo_raw_data_get(stmdev_ctx_t *ctx, uint8_t *buffer, uint8_t len) +{ + int32_t ret; + ret = lsm6ds3_read_reg(ctx, LSM6DS3_FIFO_DATA_OUT_L, buffer, len); + return ret; +} + +/** + * @brief Step counter output register..[get] + * + * @param ctx read / write interface definitions(ptr) + * @param buff buffer that stores data read + * + */ +int32_t lsm6ds3_number_of_steps_get(stmdev_ctx_t *ctx, uint8_t *buff) +{ + int32_t ret; + ret = lsm6ds3_read_reg(ctx, LSM6DS3_STEP_COUNTER_L, buff, 2); + return ret; +} + +/** + * @brief magnetometer raw data.[get] + * + * @param ctx read / write interface definitions(ptr) + * @param buff buffer that stores data read + * + */ +int32_t lsm6ds3_mag_calibrated_raw_get(stmdev_ctx_t *ctx, uint8_t *buff) +{ + int32_t ret; + ret = lsm6ds3_read_reg(ctx, LSM6DS3_OUT_MAG_RAW_X_L, buff, 6); + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup LSM6DS3_Common + * @brief This section groups common usefull functions. + * @{ + * + */ + +/** + * @brief Enable access to the embedded functions.[set] + * + * @param ctx read / write interface definitions(ptr) + * @param val change the values of func_cfg_en in reg LSM6DS3 + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6ds3_mem_bank_set(stmdev_ctx_t *ctx, lsm6ds3_func_cfg_en_t val) +{ + lsm6ds3_func_cfg_access_t func_cfg_access; + int32_t ret; + + ret = lsm6ds3_read_reg(ctx, LSM6DS3_FUNC_CFG_ACCESS, + (uint8_t*)&func_cfg_access, 1); + if(ret == 0){ + func_cfg_access.func_cfg_en = (uint8_t)val; + ret = lsm6ds3_write_reg(ctx, LSM6DS3_FUNC_CFG_ACCESS, + (uint8_t*)&func_cfg_access, 1); + } + return ret; +} + +/** + * @brief Enable access to the embedded functions.[get] + * + * @param ctx read / write interface definitions(ptr) + * @param val get the values of func_cfg_en in reg FUNC_CFG_ACCESS + * + */ +int32_t lsm6ds3_mem_bank_get(stmdev_ctx_t *ctx, lsm6ds3_func_cfg_en_t *val) +{ + lsm6ds3_func_cfg_access_t func_cfg_access; + int32_t ret; + + ret = lsm6ds3_read_reg(ctx, LSM6DS3_FUNC_CFG_ACCESS, + (uint8_t*)&func_cfg_access, 1); + + switch (func_cfg_access.func_cfg_en) + { + case LSM6DS3_USER_BANK: + *val = LSM6DS3_USER_BANK; + break; + case LSM6DS3_EMBEDDED_FUNC_BANK: + *val = LSM6DS3_EMBEDDED_FUNC_BANK; + break; + default: + *val = LSM6DS3_USER_BANK; + break; + } + return ret; +} + +/** + * @brief DeviceWhoamI..[get] + * + * @param ctx read / write interface definitions(ptr) + * @param buff buffer that stores data read + * + */ +int32_t lsm6ds3_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff) +{ + int32_t ret; + ret = lsm6ds3_read_reg(ctx, LSM6DS3_WHO_AM_I, buff, 1); + return ret; +} + +/** + * @brief Software reset. Restore the default values in user registers.[set] + * + * @param ctx read / write interface definitions(ptr) + * @param val change the values of sw_reset in reg CTRL3_C + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6ds3_reset_set(stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6ds3_ctrl3_c_t ctrl3_c; + int32_t ret; + + ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL3_C, (uint8_t*)&ctrl3_c, 1); + if(ret == 0){ + ctrl3_c.sw_reset = (uint8_t)val; + ret = lsm6ds3_write_reg(ctx, LSM6DS3_CTRL3_C, (uint8_t*)&ctrl3_c, 1); + } + return ret; +} + +/** + * @brief Software reset. Restore the default values in user registers.[get] + * + * @param ctx read / write interface definitions(ptr) + * @param val get the values of sw_reset in reg CTRL3_C + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6ds3_reset_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6ds3_ctrl3_c_t ctrl3_c; + int32_t ret; + + ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL3_C, (uint8_t*)&ctrl3_c, 1); + *val = (uint8_t)ctrl3_c.sw_reset; + + return ret; +} + +/** + * @brief Big/Little Endian Data selection.[set] + * + * @param ctx read / write interface definitions(ptr) + * @param val change the values of ble in reg LSM6DS3 + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6ds3_data_format_set(stmdev_ctx_t *ctx, lsm6ds3_ble_t val) +{ + lsm6ds3_ctrl3_c_t ctrl3_c; + int32_t ret; + + ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL3_C, (uint8_t*)&ctrl3_c, 1); + if(ret == 0){ + ctrl3_c.ble = (uint8_t)val; + ret = lsm6ds3_write_reg(ctx, LSM6DS3_CTRL3_C, (uint8_t*)&ctrl3_c, 1); + } + return ret; +} + +/** + * @brief Big/Little Endian Data selection.[get] + * + * @param ctx read / write interface definitions(ptr) + * @param val get the values of ble in reg CTRL3_C + * + */ +int32_t lsm6ds3_data_format_get(stmdev_ctx_t *ctx, lsm6ds3_ble_t *val) +{ + lsm6ds3_ctrl3_c_t ctrl3_c; + int32_t ret; + + ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL3_C, (uint8_t*)&ctrl3_c, 1); + + switch (ctrl3_c.ble) + { + case LSM6DS3_LSB_AT_LOW_ADD: + *val = LSM6DS3_LSB_AT_LOW_ADD; + break; + case LSM6DS3_MSB_AT_LOW_ADD: + *val = LSM6DS3_MSB_AT_LOW_ADD; + break; + default: + *val = LSM6DS3_LSB_AT_LOW_ADD; + break; + } + return ret; +} + +/** + * @brief Register address automatically incremented during a multiple + * byte access with a serial interface.[set] + * + * @param ctx read / write interface definitions(ptr) + * @param val change the values of if_inc in reg CTRL3_C + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6ds3_auto_increment_set(stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6ds3_ctrl3_c_t ctrl3_c; + int32_t ret; + + ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL3_C, (uint8_t*)&ctrl3_c, 1); + if(ret == 0){ + ctrl3_c.if_inc = (uint8_t)val; + ret = lsm6ds3_write_reg(ctx, LSM6DS3_CTRL3_C, (uint8_t*)&ctrl3_c, 1); + } + return ret; +} + +/** + * @brief Register address automatically incremented during a multiple + * byte access with a serial interface.[get] + * + * @param ctx read / write interface definitions(ptr) + * @param val get the values of if_inc in reg CTRL3_C + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6ds3_auto_increment_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6ds3_ctrl3_c_t ctrl3_c; + int32_t ret; + + ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL3_C, (uint8_t*)&ctrl3_c, 1); + *val = (uint8_t)ctrl3_c.if_inc; + + return ret; +} + +/** + * @brief Reboot memory content. Reload the calibration parameters.[set] + * + * @param ctx read / write interface definitions(ptr) + * @param val change the values of boot in reg CTRL3_C + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6ds3_boot_set(stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6ds3_ctrl3_c_t ctrl3_c; + int32_t ret; + + ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL3_C, (uint8_t*)&ctrl3_c, 1); + if(ret == 0){ + ctrl3_c.boot = (uint8_t)val; + ret = lsm6ds3_write_reg(ctx, LSM6DS3_CTRL3_C, (uint8_t*)&ctrl3_c, 1); + } + return ret; +} + +/** + * @brief Reboot memory content. Reload the calibration parameters.[get] + * + * @param ctx read / write interface definitions(ptr) + * @param val get the values of boot in reg CTRL3_C + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6ds3_boot_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6ds3_ctrl3_c_t ctrl3_c; + int32_t ret; + + ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL3_C, (uint8_t*)&ctrl3_c, 1); + *val = (uint8_t)ctrl3_c.boot; + + return ret; +} + +/** + * @brief Linear acceleration sensor self-test enable.[set] + * + * @param ctx read / write interface definitions(ptr) + * @param val change the values of st_xl in reg LSM6DS3 + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6ds3_xl_self_test_set(stmdev_ctx_t *ctx, lsm6ds3_st_xl_t val) +{ + lsm6ds3_ctrl5_c_t ctrl5_c; + int32_t ret; + + ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL5_C, (uint8_t*)&ctrl5_c, 1); + if(ret == 0){ + ctrl5_c.st_xl = (uint8_t)val; + ret = lsm6ds3_write_reg(ctx, LSM6DS3_CTRL5_C, (uint8_t*)&ctrl5_c, 1); + } + return ret; +} + +/** + * @brief Linear acceleration sensor self-test enable.[get] + * + * @param ctx read / write interface definitions(ptr) + * @param val get the values of st_xl in reg CTRL5_C + * + */ +int32_t lsm6ds3_xl_self_test_get(stmdev_ctx_t *ctx, lsm6ds3_st_xl_t *val) +{ + lsm6ds3_ctrl5_c_t ctrl5_c; + int32_t ret; + + ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL5_C, (uint8_t*)&ctrl5_c, 1); + + switch (ctrl5_c.st_xl) + { + case LSM6DS3_XL_ST_DISABLE: + *val = LSM6DS3_XL_ST_DISABLE; + break; + case LSM6DS3_XL_ST_POSITIVE: + *val = LSM6DS3_XL_ST_POSITIVE; + break; + case LSM6DS3_XL_ST_NEGATIVE: + *val = LSM6DS3_XL_ST_NEGATIVE; + break; + default: + *val = LSM6DS3_XL_ST_DISABLE; + break; + } + return ret; +} + +/** + * @brief Angular rate sensor self-test enable.[set] + * + * @param ctx read / write interface definitions(ptr) + * @param val change the values of st_g in reg LSM6DS3 + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6ds3_gy_self_test_set(stmdev_ctx_t *ctx, lsm6ds3_st_g_t val) +{ + lsm6ds3_ctrl5_c_t ctrl5_c; + int32_t ret; + + ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL5_C, (uint8_t*)&ctrl5_c, 1); + if(ret == 0){ + ctrl5_c.st_g = (uint8_t)val; + ret = lsm6ds3_write_reg(ctx, LSM6DS3_CTRL5_C, (uint8_t*)&ctrl5_c, 1); + } + return ret; +} + +/** + * @brief Angular rate sensor self-test enable.[get] + * + * @param ctx read / write interface definitions(ptr) + * @param val get the values of st_g in reg CTRL5_C + * + */ +int32_t lsm6ds3_gy_self_test_get(stmdev_ctx_t *ctx, lsm6ds3_st_g_t *val) +{ + lsm6ds3_ctrl5_c_t ctrl5_c; + int32_t ret; + + ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL5_C, (uint8_t*)&ctrl5_c, 1); + + switch (ctrl5_c.st_g) + { + case LSM6DS3_GY_ST_DISABLE: + *val = LSM6DS3_GY_ST_DISABLE; + break; + case LSM6DS3_GY_ST_POSITIVE: + *val = LSM6DS3_GY_ST_POSITIVE; + break; + case LSM6DS3_GY_ST_NEGATIVE: + *val = LSM6DS3_GY_ST_NEGATIVE; + break; + default: + *val = LSM6DS3_GY_ST_DISABLE; + break; + } + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup LSM6DS3_Filters + * @brief This section group all the functions concerning the + * filters configuration + * @{ + * + */ + +/** + * @brief Mask DRDY on pin (both XL & Gyro) until filter settling ends + * (XL and Gyro independently masked).[set] + * + * @param ctx read / write interface definitions(ptr) + * @param val change the values of drdy_mask in reg CTRL4_C + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6ds3_filter_settling_mask_set(stmdev_ctx_t *ctx, + uint8_t val) +{ + lsm6ds3_ctrl4_c_t ctrl4_c; + int32_t ret; + + ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL4_C, (uint8_t*)&ctrl4_c, 1); + if(ret == 0){ + ctrl4_c.drdy_mask = (uint8_t)val; + ret = lsm6ds3_write_reg(ctx, LSM6DS3_CTRL4_C, (uint8_t*)&ctrl4_c, 1); + } + return ret; +} + +/** + * @brief Mask DRDY on pin (both XL & Gyro) until filter settling ends + * (XL and Gyro independently masked).[get] + * + * @param ctx read / write interface definitions(ptr) + * @param val get the values of drdy_mask in reg CTRL4_C + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6ds3_filter_settling_mask_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6ds3_ctrl4_c_t ctrl4_c; + int32_t ret; + + ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL4_C, (uint8_t*)&ctrl4_c, 1); + *val = (uint8_t)ctrl4_c.drdy_mask; + + return ret; +} + +/** + * @brief Gyroscope high-pass filter cutoff frequency selection.[set] + * + * @param ctx read / write interface definitions(ptr) + * @param val change the values of hpcf_g in reg LSM6DS3 + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6ds3_gy_hp_bandwidth_set(stmdev_ctx_t *ctx, lsm6ds3_hpcf_g_t val) +{ + lsm6ds3_ctrl7_g_t ctrl7_g; + int32_t ret; + + ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL7_G, (uint8_t*)&ctrl7_g, 1); + if(ret == 0){ + ctrl7_g.hpcf_g = (uint8_t)val; + ret = lsm6ds3_write_reg(ctx, LSM6DS3_CTRL7_G, (uint8_t*)&ctrl7_g, 1); + } + return ret; +} + +/** + * @brief Gyroscope high-pass filter cutoff frequency selection.[get] + * + * @param ctx read / write interface definitions(ptr) + * @param val get the values of hpcf_g in reg CTRL7_G + * + */ +int32_t lsm6ds3_gy_hp_bandwidth_get(stmdev_ctx_t *ctx, lsm6ds3_hpcf_g_t *val) +{ + lsm6ds3_ctrl7_g_t ctrl7_g; + int32_t ret; + + ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL7_G, (uint8_t*)&ctrl7_g, 1); + + switch (ctrl7_g.hpcf_g) + { + case LSM6DS3_HP_CUT_OFF_8mHz1: + *val = LSM6DS3_HP_CUT_OFF_8mHz1; + break; + case LSM6DS3_HP_CUT_OFF_32mHz4: + *val = LSM6DS3_HP_CUT_OFF_32mHz4; + break; + case LSM6DS3_HP_CUT_OFF_2Hz07: + *val = LSM6DS3_HP_CUT_OFF_2Hz07; + break; + case LSM6DS3_HP_CUT_OFF_16Hz32: + *val = LSM6DS3_HP_CUT_OFF_16Hz32; + break; + default: + *val = LSM6DS3_HP_CUT_OFF_8mHz1; + break; + } + return ret; +} + +/** + * @brief Gyro digital HP filter reset.[set] + * + * @param ctx read / write interface definitions(ptr) + * @param val change the values of hp_g_rst in reg CTRL7_G + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6ds3_gy_hp_reset_set(stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6ds3_ctrl7_g_t ctrl7_g; + int32_t ret; + + ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL7_G, (uint8_t*)&ctrl7_g, 1); + if(ret == 0){ + ctrl7_g.hp_g_rst = (uint8_t)val; + ret = lsm6ds3_write_reg(ctx, LSM6DS3_CTRL7_G, (uint8_t*)&ctrl7_g, 1); + } + return ret; +} + +/** + * @brief Gyro digital HP filter reset.[get] + * + * @param ctx read / write interface definitions(ptr) + * @param val get the values of hp_g_rst in reg CTRL7_G + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6ds3_gy_hp_reset_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6ds3_ctrl7_g_t ctrl7_g; + int32_t ret; + + ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL7_G, (uint8_t*)&ctrl7_g, 1); + *val = (uint8_t)ctrl7_g.hp_g_rst; + + return ret; +} + +/** + * @brief Accelerometer slope filter and high-pass filter configuration + * and cut-off setting.[set] + * + * @param ctx read / write interface definitions(ptr) + * @param val change the values of hp_slope_xl_en in reg LSM6DS3 + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6ds3_xl_hp_bandwidth_set(stmdev_ctx_t *ctx, lsm6ds3_hp_bw_t val) +{ + lsm6ds3_ctrl8_xl_t ctrl8_xl; + int32_t ret; + + ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL8_XL, (uint8_t*)&ctrl8_xl, 1); + if(ret == 0){ + ctrl8_xl.hp_slope_xl_en = PROPERTY_ENABLE; + ctrl8_xl.hpcf_xl = (uint8_t)val; + ret = lsm6ds3_write_reg(ctx, LSM6DS3_CTRL8_XL, (uint8_t*)&ctrl8_xl, 1); + } + return ret; +} + +/** + * @brief Accelerometer slope filter and high-pass filter configuration + * and cut-off setting.[get] + * + * @param ctx read / write interface definitions(ptr) + * @param val get the values of hp_slope_xl_en in reg CTRL8_XL + * + */ +int32_t lsm6ds3_xl_hp_bandwidth_get(stmdev_ctx_t *ctx, lsm6ds3_hp_bw_t *val) +{ + lsm6ds3_ctrl8_xl_t ctrl8_xl; + int32_t ret; + + ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL8_XL, (uint8_t*)&ctrl8_xl, 1); + + switch (ctrl8_xl.hpcf_xl) + { + case LSM6DS3_XL_HP_ODR_DIV_4: + *val = LSM6DS3_XL_HP_ODR_DIV_4; + break; + case LSM6DS3_XL_HP_ODR_DIV_100: + *val = LSM6DS3_XL_HP_ODR_DIV_100; + break; + case LSM6DS3_XL_HP_ODR_DIV_9: + *val = LSM6DS3_XL_HP_ODR_DIV_9; + break; + case LSM6DS3_XL_HP_ODR_DIV_400: + *val = LSM6DS3_XL_HP_ODR_DIV_400; + break; + default: + *val = LSM6DS3_XL_HP_ODR_DIV_4; + break; + } + return ret; +} + +/** + * @brief Accelerometer low-pass filter configuration and + * cut-off setting.[set] + * + * @param ctx read / write interface definitions(ptr) + * @param val change the values of lpf2_xl_en in reg LSM6DS3 + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6ds3_xl_lp2_bandwidth_set(stmdev_ctx_t *ctx, lsm6ds3_lp_bw_t val) +{ + lsm6ds3_ctrl8_xl_t ctrl8_xl; + int32_t ret; + + ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL8_XL, (uint8_t*)&ctrl8_xl, 1); + if(ret == 0){ + ctrl8_xl.lpf2_xl_en = PROPERTY_ENABLE; + ctrl8_xl.hpcf_xl= (uint8_t)val; + ret = lsm6ds3_write_reg(ctx, LSM6DS3_CTRL8_XL, (uint8_t*)&ctrl8_xl, 1); + } + return ret; +} + +/** + * @brief Accelerometer low-pass filter configuration and cut-off + * setting.[get] + * + * @param ctx read / write interface definitions(ptr) + * @param val get the values of lpf2_xl_en in reg CTRL8_XL + * + */ +int32_t lsm6ds3_xl_lp2_bandwidth_get(stmdev_ctx_t *ctx, lsm6ds3_lp_bw_t *val) +{ + lsm6ds3_ctrl8_xl_t ctrl8_xl; + int32_t ret; + + ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL8_XL, (uint8_t*)&ctrl8_xl, 1); + + switch (ctrl8_xl.hpcf_xl) + { + case LSM6DS3_XL_LP_ODR_DIV_50: + *val = LSM6DS3_XL_LP_ODR_DIV_50; + break; + case LSM6DS3_XL_LP_ODR_DIV_100: + *val = LSM6DS3_XL_LP_ODR_DIV_100; + break; + case LSM6DS3_XL_LP_ODR_DIV_9: + *val = LSM6DS3_XL_LP_ODR_DIV_9; + break; + case LSM6DS3_XL_LP_ODR_DIV_400: + *val = LSM6DS3_XL_LP_ODR_DIV_400; + break; + default: + *val = LSM6DS3_XL_LP_ODR_DIV_50; + break; + } + return ret; +} + +/** + * @brief Anti-aliasing filter bandwidth selection.[set] + * + * @param ctx read / write interface definitions(ptr) + * @param val change the values of bw_xl in reg LSM6DS3 + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6ds3_xl_filter_analog_set(stmdev_ctx_t *ctx, lsm6ds3_bw_xl_t val) +{ + lsm6ds3_ctrl1_xl_t ctrl1_xl; + int32_t ret; + + ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL1_XL, (uint8_t*)&ctrl1_xl, 1); + if(ret == 0){ + ctrl1_xl.bw_xl = (uint8_t)val; + ret = lsm6ds3_write_reg(ctx, LSM6DS3_CTRL1_XL, (uint8_t*)&ctrl1_xl, 1); + } + return ret; +} + +/** + * @brief Anti-aliasing filter bandwidth selection.[get] + * + * @param ctx read / write interface definitions(ptr) + * @param val get the values of bw_xl in reg CTRL1_XL + * + */ +int32_t lsm6ds3_xl_filter_analog_get(stmdev_ctx_t *ctx, lsm6ds3_bw_xl_t *val) +{ + lsm6ds3_ctrl1_xl_t ctrl1_xl; + int32_t ret; + + ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL1_XL, (uint8_t*)&ctrl1_xl, 1); + + switch (ctrl1_xl.bw_xl) + { + case LSM6DS3_ANTI_ALIASING_400Hz: + *val = LSM6DS3_ANTI_ALIASING_400Hz; + break; + case LSM6DS3_ANTI_ALIASING_200Hz: + *val = LSM6DS3_ANTI_ALIASING_200Hz; + break; + case LSM6DS3_ANTI_ALIASING_100Hz: + *val = LSM6DS3_ANTI_ALIASING_100Hz; + break; + case LSM6DS3_ANTI_ALIASING_50Hz: + *val = LSM6DS3_ANTI_ALIASING_50Hz; + break; + default: + *val = LSM6DS3_ANTI_ALIASING_400Hz; + break; + } + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup LSM6DS3_Serial_interface + * @brief This section groups all the functions concerning main + * serial interface management (not auxiliary) + * @{ + * + */ + +/** + * @brief SPI Serial Interface Mode selection.[set] + * + * @param ctx read / write interface definitions(ptr) + * @param val change the values of sim in reg LSM6DS3 + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6ds3_spi_mode_set(stmdev_ctx_t *ctx, lsm6ds3_sim_t val) +{ + lsm6ds3_ctrl3_c_t ctrl3_c; + int32_t ret; + + ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL3_C, (uint8_t*)&ctrl3_c, 1); + if(ret == 0){ + ctrl3_c.sim = (uint8_t)val; + ret = lsm6ds3_write_reg(ctx, LSM6DS3_CTRL3_C, (uint8_t*)&ctrl3_c, 1); + } + return ret; +} + +/** + * @brief SPI Serial Interface Mode selection.[get] + * + * @param ctx read / write interface definitions(ptr) + * @param val get the values of sim in reg CTRL3_C + * + */ +int32_t lsm6ds3_spi_mode_get(stmdev_ctx_t *ctx, lsm6ds3_sim_t *val) +{ + lsm6ds3_ctrl3_c_t ctrl3_c; + int32_t ret; + + ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL3_C, (uint8_t*)&ctrl3_c, 1); + + switch (ctrl3_c.sim) + { + case LSM6DS3_SPI_4_WIRE: + *val = LSM6DS3_SPI_4_WIRE; + break; + case LSM6DS3_SPI_3_WIRE: + *val = LSM6DS3_SPI_3_WIRE; + break; + default: + *val = LSM6DS3_SPI_4_WIRE; + break; + } + return ret; +} + +/** + * @brief Disable / Enable I2C interface.[set] + * + * @param ctx read / write interface definitions(ptr) + * @param val change the values of i2c_disable in reg LSM6DS3 + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6ds3_i2c_interface_set(stmdev_ctx_t *ctx, lsm6ds3_i2c_dis_t val) +{ + lsm6ds3_ctrl4_c_t ctrl4_c; + int32_t ret; + + ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL4_C, (uint8_t*)&ctrl4_c, 1); + if(ret == 0){ + ctrl4_c.i2c_disable = (uint8_t)val; + ret = lsm6ds3_write_reg(ctx, LSM6DS3_CTRL4_C, (uint8_t*)&ctrl4_c, 1); + } + return ret; +} + +/** + * @brief Disable / Enable I2C interface.[get] + * + * @param ctx read / write interface definitions(ptr) + * @param val get the values of i2c_disable in reg CTRL4_C + * + */ +int32_t lsm6ds3_i2c_interface_get(stmdev_ctx_t *ctx, lsm6ds3_i2c_dis_t *val) +{ + lsm6ds3_ctrl4_c_t ctrl4_c; + int32_t ret; + + ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL4_C, (uint8_t*)&ctrl4_c, 1); + + switch (ctrl4_c.i2c_disable) + { + case LSM6DS3_I2C_ENABLE: + *val = LSM6DS3_I2C_ENABLE; + break; + case LSM6DS3_I2C_DISABLE: + *val = LSM6DS3_I2C_DISABLE; + break; + default: + *val = LSM6DS3_I2C_ENABLE; + break; + } + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup LSM6DS3_Interrupt_pins + * @brief This section groups all the functions that manage + * interrupt pins + * @{ + * + */ + +/** + * @brief Select the signal that need to route on int1 pad.[set] + * + * @param ctx read / write interface definitions(ptr) + * @param val Select the signal that need to route on int1 pad. + * + */ +int32_t lsm6ds3_pin_int1_route_set(stmdev_ctx_t *ctx, + lsm6ds3_int1_route_t *val) +{ + lsm6ds3_int1_ctrl_t int1_ctrl; + lsm6ds3_md1_cfg_t md1_cfg; + lsm6ds3_master_config_t master_config; + int32_t ret; + + ret = lsm6ds3_read_reg(ctx, LSM6DS3_MASTER_CONFIG, + (uint8_t*)&master_config, 1); + + if(ret == 0) { + int1_ctrl.int1_drdy_xl = val->int1_drdy_xl; + int1_ctrl.int1_drdy_g = val->int1_drdy_g; + int1_ctrl.int1_boot = val->int1_boot; + int1_ctrl.int1_fth = val->int1_fth; + int1_ctrl.int1_fifo_ovr = val->int1_fifo_ovr; + int1_ctrl.int1_full_flag = val->int1_full_flag; + int1_ctrl.int1_sign_mot = val->int1_sign_mot; + int1_ctrl.int1_step_detector = val->int1_step_detector; + md1_cfg.int1_timer = val->int1_timer; + md1_cfg.int1_tilt = val->int1_tilt; + md1_cfg.int1_6d = val->int1_6d; + md1_cfg.int1_double_tap = val->int1_double_tap; + md1_cfg.int1_ff = val->int1_ff; + md1_cfg.int1_wu = val->int1_wu; + md1_cfg.int1_single_tap = val->int1_single_tap; + md1_cfg.int1_inact_state = val->int1_inact_state; + master_config.drdy_on_int1 = val->drdy_on_int1; + + ret = lsm6ds3_write_reg(ctx, LSM6DS3_INT1_CTRL, (uint8_t*)&int1_ctrl, 1); + if(ret == 0) { + ret = lsm6ds3_write_reg(ctx, LSM6DS3_MD1_CFG, (uint8_t*)&md1_cfg, 1); + } + if(ret == 0) { + ret = lsm6ds3_write_reg(ctx, LSM6DS3_MASTER_CONFIG, + (uint8_t*)&master_config, 1); + } + } + return ret; +} + +/** + * @brief Select the signal that need to route on int1 pad.[get] + * + * @param ctx read / write interface definitions(ptr) + * @param val Select the signal that need to route on int1 pad. + * + */ +int32_t lsm6ds3_pin_int1_route_get(stmdev_ctx_t *ctx, + lsm6ds3_int1_route_t *val) +{ + lsm6ds3_int1_ctrl_t int1_ctrl; + lsm6ds3_md1_cfg_t md1_cfg; + lsm6ds3_master_config_t master_config; + int32_t ret; + + ret = lsm6ds3_read_reg(ctx, LSM6DS3_INT1_CTRL, (uint8_t*)&int1_ctrl, 1); + if(ret == 0) { + ret = lsm6ds3_read_reg(ctx, LSM6DS3_MD1_CFG, (uint8_t*)&md1_cfg, 1); + } + if(ret == 0) { + ret = lsm6ds3_read_reg(ctx, LSM6DS3_MASTER_CONFIG, + (uint8_t*)&master_config, 1); + } + if(ret == 0) { + val->int1_drdy_xl = int1_ctrl.int1_drdy_xl; + val->int1_drdy_g = int1_ctrl.int1_drdy_g; + val->int1_boot = int1_ctrl.int1_boot; + val->int1_fth = int1_ctrl.int1_fth; + val->int1_fifo_ovr = int1_ctrl.int1_fifo_ovr; + val->int1_full_flag = int1_ctrl.int1_full_flag; + val->int1_sign_mot = int1_ctrl.int1_sign_mot; + val->int1_step_detector = int1_ctrl.int1_step_detector; + val->int1_timer = md1_cfg.int1_timer; + val->int1_tilt = md1_cfg.int1_tilt; + val->int1_6d = md1_cfg.int1_6d; + val->int1_double_tap = md1_cfg.int1_double_tap; + val->int1_ff = md1_cfg.int1_ff; + val->int1_wu = md1_cfg.int1_wu; + val->int1_single_tap = md1_cfg.int1_single_tap; + val->int1_inact_state = md1_cfg.int1_inact_state; + val->drdy_on_int1 = master_config.drdy_on_int1; + } + return ret; +} + +/** + * @brief Select the signal that need to route on int1 pad.[set] + * + * @param ctx read / write interface definitions(ptr) + * @param val Select the signal that need to route on int1 pad. + * + */ +int32_t lsm6ds3_pin_int2_route_set(stmdev_ctx_t *ctx, + lsm6ds3_int2_route_t *val) +{ + lsm6ds3_int2_ctrl_t int2_ctrl; + lsm6ds3_md2_cfg_t md2_cfg; + lsm6ds3_master_config_t master_config; + int32_t ret; + + ret = lsm6ds3_read_reg(ctx, LSM6DS3_MASTER_CONFIG, + (uint8_t*)&master_config, 1); + + if(ret == 0) { + int2_ctrl.int2_drdy_xl = val->int2_drdy_xl; + int2_ctrl.int2_drdy_g = val->int2_drdy_g; + int2_ctrl.int2_drdy_temp = val->int2_drdy_temp; + int2_ctrl.int2_fth = val->int2_fth; + int2_ctrl.int2_fifo_ovr = val->int2_fifo_ovr; + int2_ctrl.int2_full_flag = val->int2_full_flag; + int2_ctrl.int2_step_count_ov = val->int2_step_count_ov; + int2_ctrl.int2_step_delta = val->int2_step_delta; + md2_cfg.int2_iron = val->int2_iron; + md2_cfg.int2_tilt = val->int2_tilt; + md2_cfg.int2_6d = val->int2_6d; + md2_cfg.int2_double_tap = val->int2_double_tap; + md2_cfg.int2_ff = val->int2_ff; + md2_cfg.int2_wu = val->int2_wu; + md2_cfg.int2_single_tap = val->int2_single_tap; + md2_cfg.int2_inact_state = val->int2_inact_state; + master_config.start_config = val->start_config; + + ret = lsm6ds3_write_reg(ctx, LSM6DS3_INT2_CTRL, (uint8_t*)&int2_ctrl, 1); + } + if(ret == 0) { + ret = lsm6ds3_write_reg(ctx, LSM6DS3_MD2_CFG, (uint8_t*)&md2_cfg, 1); + } + if(ret == 0) { + ret = lsm6ds3_write_reg(ctx, LSM6DS3_MASTER_CONFIG, + (uint8_t*)&master_config, 1); + } + return ret; +} + +/** + * @brief Select the signal that need to route on int1 pad.[get] + * + * @param ctx read / write interface definitions(ptr) + * @param val Select the signal that need to route on int1 pad. + * + */ +int32_t lsm6ds3_pin_int2_route_get(stmdev_ctx_t *ctx, + lsm6ds3_int2_route_t *val) +{ + lsm6ds3_int2_ctrl_t int2_ctrl; + lsm6ds3_md2_cfg_t md2_cfg; + lsm6ds3_master_config_t master_config; + int32_t ret; + + ret = lsm6ds3_read_reg(ctx, LSM6DS3_INT2_CTRL, (uint8_t*)&int2_ctrl, 1); + if(ret == 0) { + ret = lsm6ds3_read_reg(ctx, LSM6DS3_MD2_CFG, (uint8_t*)&md2_cfg, 1); + } + if(ret == 0) { + ret = lsm6ds3_read_reg(ctx, LSM6DS3_MASTER_CONFIG, + (uint8_t*)&master_config, 1); + + val->int2_drdy_xl = int2_ctrl.int2_drdy_xl; + val->int2_drdy_g = int2_ctrl.int2_drdy_g; + val->int2_drdy_temp = int2_ctrl.int2_drdy_temp; + val->int2_fth = int2_ctrl.int2_fth; + val->int2_fifo_ovr = int2_ctrl.int2_fifo_ovr; + val->int2_full_flag = int2_ctrl.int2_full_flag; + val->int2_step_count_ov = int2_ctrl.int2_step_count_ov; + val->int2_step_delta = int2_ctrl.int2_step_delta; + val->int2_iron = md2_cfg.int2_iron; + val->int2_tilt = md2_cfg.int2_tilt; + val->int2_6d = md2_cfg.int2_6d; + val->int2_double_tap = md2_cfg.int2_double_tap; + val->int2_ff = md2_cfg.int2_ff; + val->int2_wu = md2_cfg.int2_wu; + val->int2_single_tap = md2_cfg.int2_single_tap; + val->int2_inact_state = md2_cfg.int2_inact_state; + val->start_config = master_config.start_config; + } + + return ret; +} + +/** + * @brief Push-pull/open drain selection on interrupt pads.[set] + * + * @param ctx read / write interface definitions(ptr) + * @param val change the values of pp_od in reg LSM6DS3 + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6ds3_pin_mode_set(stmdev_ctx_t *ctx, lsm6ds3_pp_od_t val) +{ + lsm6ds3_ctrl3_c_t ctrl3_c; + int32_t ret; + + ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL3_C, (uint8_t*)&ctrl3_c, 1); + if(ret == 0){ + ctrl3_c.pp_od = (uint8_t)val; + ret = lsm6ds3_write_reg(ctx, LSM6DS3_CTRL3_C, (uint8_t*)&ctrl3_c, 1); + } + return ret; +} + +/** + * @brief Push-pull/open drain selection on interrupt pads.[get] + * + * @param ctx read / write interface definitions(ptr) + * @param val get the values of pp_od in reg CTRL3_C + * + */ +int32_t lsm6ds3_pin_mode_get(stmdev_ctx_t *ctx, lsm6ds3_pp_od_t *val) +{ + lsm6ds3_ctrl3_c_t ctrl3_c; + int32_t ret; + + ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL3_C, (uint8_t*)&ctrl3_c, 1); + + switch (ctrl3_c.pp_od) + { + case LSM6DS3_PUSH_PULL: + *val = LSM6DS3_PUSH_PULL; + break; + case LSM6DS3_OPEN_DRAIN: + *val = LSM6DS3_OPEN_DRAIN; + break; + default: + *val = LSM6DS3_PUSH_PULL; + break; + } + return ret; +} + +/** + * @brief Interrupt active-high/low.Interrupt active-high/low.[set] + * + * @param ctx read / write interface definitions(ptr) + * @param val change the values of h_lactive in reg LSM6DS3 + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6ds3_pin_polarity_set(stmdev_ctx_t *ctx, lsm6ds3_pin_pol_t val) +{ + lsm6ds3_ctrl3_c_t ctrl3_c; + int32_t ret; + + ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL3_C, (uint8_t*)&ctrl3_c, 1); + if(ret == 0){ + ctrl3_c.h_lactive = (uint8_t)val; + ret = lsm6ds3_write_reg(ctx, LSM6DS3_CTRL3_C, (uint8_t*)&ctrl3_c, 1); + } + return ret; +} + +/** + * @brief Interrupt active-high/low.Interrupt active-high/low.[get] + * + * @param ctx read / write interface definitions(ptr) + * @param val get the values of h_lactive in reg CTRL3_C + * + */ +int32_t lsm6ds3_pin_polarity_get(stmdev_ctx_t *ctx, lsm6ds3_pin_pol_t *val) +{ + lsm6ds3_ctrl3_c_t ctrl3_c; + int32_t ret; + + ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL3_C, (uint8_t*)&ctrl3_c, 1); + + switch (ctrl3_c.h_lactive) + { + case LSM6DS3_ACTIVE_HIGH: + *val = LSM6DS3_ACTIVE_HIGH; + break; + case LSM6DS3_ACTIVE_LOW: + *val = LSM6DS3_ACTIVE_LOW; + break; + default: + *val = LSM6DS3_ACTIVE_HIGH; + break; + } + return ret; +} + +/** + * @brief All interrupt signals become available on INT1 pin.[set] + * + * @param ctx read / write interface definitions(ptr) + * @param val change the values of int2_on_int1 in reg CTRL4_C + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6ds3_all_on_int1_set(stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6ds3_ctrl4_c_t ctrl4_c; + int32_t ret; + + ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL4_C, (uint8_t*)&ctrl4_c, 1); + if(ret == 0){ + ctrl4_c.int2_on_int1 = (uint8_t)val; + ret = lsm6ds3_write_reg(ctx, LSM6DS3_CTRL4_C, (uint8_t*)&ctrl4_c, 1); + } + return ret; +} + +/** + * @brief All interrupt signals become available on INT1 pin.[get] + * + * @param ctx read / write interface definitions(ptr) + * @param val get the values of int2_on_int1 in reg CTRL4_C + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6ds3_all_on_int1_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6ds3_ctrl4_c_t ctrl4_c; + int32_t ret; + + ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL4_C, (uint8_t*)&ctrl4_c, 1); + *val = (uint8_t)ctrl4_c.int2_on_int1; + + return ret; +} + +/** + * @brief Latched/pulsed interrupt.[set] + * + * @param ctx read / write interface definitions(ptr) + * @param val change the values of lir in reg LSM6DS3 + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6ds3_int_notification_set(stmdev_ctx_t *ctx, lsm6ds3_lir_t val) +{ + lsm6ds3_tap_cfg_t tap_cfg; + int32_t ret; + + ret = lsm6ds3_read_reg(ctx, LSM6DS3_TAP_CFG, (uint8_t*)&tap_cfg, 1); + if(ret == 0){ + tap_cfg.lir = (uint8_t)val; + ret = lsm6ds3_write_reg(ctx, LSM6DS3_TAP_CFG, (uint8_t*)&tap_cfg, 1); + } + return ret; +} + +/** + * @brief Latched/pulsed interrupt.[get] + * + * @param ctx read / write interface definitions(ptr) + * @param val get the values of lir in reg TAP_CFG + * + */ +int32_t lsm6ds3_int_notification_get(stmdev_ctx_t *ctx, lsm6ds3_lir_t *val) +{ + lsm6ds3_tap_cfg_t tap_cfg; + int32_t ret; + + ret = lsm6ds3_read_reg(ctx, LSM6DS3_TAP_CFG, (uint8_t*)&tap_cfg, 1); + + switch (tap_cfg.lir) + { + case LSM6DS3_INT_PULSED: + *val = LSM6DS3_INT_PULSED; + break; + case LSM6DS3_INT_LATCHED: + *val = LSM6DS3_INT_LATCHED; + break; + default: + *val = LSM6DS3_INT_PULSED; + break; + } + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup LSM6DS3_Wake_Up_event + * @brief This section groups all the functions that manage the + * Wake Up event generation. + * @{ + * + */ + +/** + * @brief Read the wake_up_src status flag of the device.[get] + * + * @param ctx read / write interface definitions(ptr) + * @param val Read the wake_up_src status flag of the device. + * + */ +int32_t lsm6ds3_wkup_src_get(stmdev_ctx_t *ctx, lsm6ds3_wake_up_src_t *val) +{ + int32_t ret; + + ret = lsm6ds3_read_reg(ctx, LSM6DS3_WAKE_UP_SRC, (uint8_t*)val, 1); + + return ret; +} + +/** + * @brief Threshold for wakeup (1 LSB = FS_XL / 64).[set] + * + * @param ctx read / write interface definitions(ptr) + * @param val change the values of wk_ths in reg WAKE_UP_THS + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6ds3_wkup_threshold_set(stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6ds3_wake_up_ths_t wake_up_ths; + int32_t ret; + + ret = lsm6ds3_read_reg(ctx, LSM6DS3_WAKE_UP_THS, (uint8_t*)&wake_up_ths, 1); + if(ret == 0){ + wake_up_ths.wk_ths = (uint8_t)val; + ret = lsm6ds3_write_reg(ctx, LSM6DS3_WAKE_UP_THS, + (uint8_t*)&wake_up_ths, 1); + } + return ret; +} + +/** + * @brief Threshold for wakeup (1 LSB = FS_XL / 64).[get] + * + * @param ctx read / write interface definitions(ptr) + * @param val get the values of wk_ths in reg WAKE_UP_THS + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6ds3_wkup_threshold_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6ds3_wake_up_ths_t wake_up_ths; + int32_t ret; + + ret = lsm6ds3_read_reg(ctx, LSM6DS3_WAKE_UP_THS, (uint8_t*)&wake_up_ths, 1); + *val = (uint8_t)wake_up_ths.wk_ths; + + return ret; +} + +/** + * @brief Wake up duration event.1LSb = 1 / ODR[set] + * + * @param ctx read / write interface definitions(ptr) + * @param val change the values of wake_dur in reg WAKE_UP_DUR + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6ds3_wkup_dur_set(stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6ds3_wake_up_dur_t wake_up_dur; + int32_t ret; + + ret = lsm6ds3_read_reg(ctx, LSM6DS3_WAKE_UP_DUR, (uint8_t*)&wake_up_dur, 1); + if(ret == 0){ + wake_up_dur.wake_dur = (uint8_t)val; + ret = lsm6ds3_write_reg(ctx, LSM6DS3_WAKE_UP_DUR, + (uint8_t*)&wake_up_dur, 1); + } + return ret; +} + +/** + * @brief Wake up duration event.1LSb = 1 / ODR[get] + * + * @param ctx read / write interface definitions(ptr) + * @param val get the values of wake_dur in reg WAKE_UP_DUR + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6ds3_wkup_dur_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6ds3_wake_up_dur_t wake_up_dur; + int32_t ret; + + ret = lsm6ds3_read_reg(ctx, LSM6DS3_WAKE_UP_DUR, (uint8_t*)&wake_up_dur, 1); + *val = (uint8_t)wake_up_dur.wake_dur; + + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup LSM6DS3_Activity/Inactivity_detection + * @brief This section groups all the functions concerning + * activity/inactivity detection. + * @{ + * + */ + +/** + * @brief Enables gyroscope Sleep mode.[set] + * + * @param ctx read / write interface definitions(ptr) + * @param val change the values of sleep_g in reg CTRL4_C + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6ds3_gy_sleep_mode_set(stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6ds3_ctrl4_c_t ctrl4_c; + int32_t ret; + + ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL4_C, (uint8_t*)&ctrl4_c, 1); + if(ret == 0){ + ctrl4_c.sleep_g = (uint8_t)val; + ret = lsm6ds3_write_reg(ctx, LSM6DS3_CTRL4_C, (uint8_t*)&ctrl4_c, 1); + } + return ret; +} + +/** + * @brief Enables gyroscope Sleep mode.[get] + * + * @param ctx read / write interface definitions(ptr) + * @param val get the values of sleep_g in reg CTRL4_C + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6ds3_gy_sleep_mode_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6ds3_ctrl4_c_t ctrl4_c; + int32_t ret; + + ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL4_C, (uint8_t*)&ctrl4_c, 1); + *val = (uint8_t)ctrl4_c.sleep_g; + + return ret; +} + +/** + * @brief Enable/Disable inactivity function.[set] + * + * @param ctx read / write interface definitions(ptr) + * @param val change the values of inactivity in reg LSM6DS3 + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6ds3_act_mode_set(stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6ds3_wake_up_ths_t wake_up_ths; + int32_t ret; + + ret = lsm6ds3_read_reg(ctx, LSM6DS3_WAKE_UP_THS, (uint8_t*)&wake_up_ths, 1); + if(ret == 0){ + wake_up_ths.inactivity = (uint8_t)val; + ret = lsm6ds3_write_reg(ctx, LSM6DS3_WAKE_UP_THS, + (uint8_t*)&wake_up_ths, 1); + } + return ret; +} + +/** + * @brief Enable/Disable inactivity function.[get] + * + * @param ctx read / write interface definitions(ptr) + * @param val get the values of inactivity in reg WAKE_UP_THS + * + */ +int32_t lsm6ds3_act_mode_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6ds3_wake_up_ths_t wake_up_ths; + int32_t ret; + + ret = lsm6ds3_read_reg(ctx, LSM6DS3_WAKE_UP_THS, (uint8_t*)&wake_up_ths, 1); + *val = wake_up_ths.inactivity; + + return ret; +} + +/** + * @brief Duration to go in sleep mode. 1 LSb = 512 / ODR[set] + * + * @param ctx read / write interface definitions(ptr) + * @param val change the values of sleep_dur in reg WAKE_UP_DUR + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6ds3_act_sleep_dur_set(stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6ds3_wake_up_dur_t wake_up_dur; + int32_t ret; + + ret = lsm6ds3_read_reg(ctx, LSM6DS3_WAKE_UP_DUR, (uint8_t*)&wake_up_dur, 1); + if(ret == 0){ + wake_up_dur.sleep_dur = (uint8_t)val; + ret = lsm6ds3_write_reg(ctx, LSM6DS3_WAKE_UP_DUR, + (uint8_t*)&wake_up_dur, 1); + } + return ret; +} + +/** + * @brief Duration to go in sleep mode. 1 LSb = 512 / ODR[get] + * + * @param ctx read / write interface definitions(ptr) + * @param val get the values of sleep_dur in reg WAKE_UP_DUR + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6ds3_act_sleep_dur_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6ds3_wake_up_dur_t wake_up_dur; + int32_t ret; + + ret = lsm6ds3_read_reg(ctx, LSM6DS3_WAKE_UP_DUR, (uint8_t*)&wake_up_dur, 1); + *val = (uint8_t)wake_up_dur.sleep_dur; + + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup LSM6DS3_Tap_generator + * @brief This section groups all the functions that manage the + * tap and double tap event generation. + * @{ + * + */ + +/** + * @brief Read the tap_src status flag of the device.[get] + * + * @param ctx read / write interface definitions(ptr) + * @param val Read the tap_src status flag of the device. + * + */ +int32_t lsm6ds3_tap_src_get(stmdev_ctx_t *ctx, lsm6ds3_tap_src_t *val) +{ + int32_t ret; + + ret = lsm6ds3_read_reg(ctx, LSM6DS3_TAP_SRC, (uint8_t*)val, 1); + + return ret; +} + +/** + * @brief Enable Z direction in tap recognition.[set] + * + * @param ctx read / write interface definitions(ptr) + * @param val change the values of tap_z_en in reg TAP_CFG + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6ds3_tap_detection_on_z_set(stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6ds3_tap_cfg_t tap_cfg; + int32_t ret; + + ret = lsm6ds3_read_reg(ctx, LSM6DS3_TAP_CFG, (uint8_t*)&tap_cfg, 1); + if(ret == 0){ + tap_cfg.tap_z_en = (uint8_t)val; + ret = lsm6ds3_write_reg(ctx, LSM6DS3_TAP_CFG, (uint8_t*)&tap_cfg, 1); + } + return ret; +} + +/** + * @brief Enable Z direction in tap recognition.[get] + * + * @param ctx read / write interface definitions(ptr) + * @param val get the values of tap_z_en in reg TAP_CFG + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6ds3_tap_detection_on_z_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6ds3_tap_cfg_t tap_cfg; + int32_t ret; + + ret = lsm6ds3_read_reg(ctx, LSM6DS3_TAP_CFG, (uint8_t*)&tap_cfg, 1); + *val = (uint8_t)tap_cfg.tap_z_en; + + return ret; +} + +/** + * @brief Enable Y direction in tap recognition.[set] + * + * @param ctx read / write interface definitions(ptr) + * @param val change the values of tap_y_en in reg TAP_CFG + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6ds3_tap_detection_on_y_set(stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6ds3_tap_cfg_t tap_cfg; + int32_t ret; + + ret = lsm6ds3_read_reg(ctx, LSM6DS3_TAP_CFG, (uint8_t*)&tap_cfg, 1); + if(ret == 0){ + tap_cfg.tap_y_en = (uint8_t)val; + ret = lsm6ds3_write_reg(ctx, LSM6DS3_TAP_CFG, (uint8_t*)&tap_cfg, 1); + } + return ret; +} + +/** + * @brief Enable Y direction in tap recognition.[get] + * + * @param ctx read / write interface definitions(ptr) + * @param val get the values of tap_y_en in reg TAP_CFG + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6ds3_tap_detection_on_y_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6ds3_tap_cfg_t tap_cfg; + int32_t ret; + + ret = lsm6ds3_read_reg(ctx, LSM6DS3_TAP_CFG, (uint8_t*)&tap_cfg, 1); + *val = (uint8_t)tap_cfg.tap_y_en; + + return ret; +} + +/** + * @brief Enable X direction in tap recognition.[set] + * + * @param ctx read / write interface definitions(ptr) + * @param val change the values of tap_x_en in reg TAP_CFG + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6ds3_tap_detection_on_x_set(stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6ds3_tap_cfg_t tap_cfg; + int32_t ret; + + ret = lsm6ds3_read_reg(ctx, LSM6DS3_TAP_CFG, (uint8_t*)&tap_cfg, 1); + if(ret == 0){ + tap_cfg.tap_x_en = (uint8_t)val; + ret = lsm6ds3_write_reg(ctx, LSM6DS3_TAP_CFG, (uint8_t*)&tap_cfg, 1); + } + return ret; +} + +/** + * @brief Enable X direction in tap recognition.[get] + * + * @param ctx read / write interface definitions(ptr) + * @param val get the values of tap_x_en in reg TAP_CFG + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6ds3_tap_detection_on_x_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6ds3_tap_cfg_t tap_cfg; + int32_t ret; + + ret = lsm6ds3_read_reg(ctx, LSM6DS3_TAP_CFG, (uint8_t*)&tap_cfg, 1); + *val = (uint8_t)tap_cfg.tap_x_en; + + return ret; +} + +/** + * @brief Threshold for tap recognition.[set] + * + * @param ctx read / write interface definitions(ptr) + * @param val change the values of tap_ths in reg TAP_THS_6D + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6ds3_tap_threshold_set(stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6ds3_tap_ths_6d_t tap_ths_6d; + int32_t ret; + + ret = lsm6ds3_read_reg(ctx, LSM6DS3_TAP_THS_6D, (uint8_t*)&tap_ths_6d, 1); + if(ret == 0){ + tap_ths_6d.tap_ths = (uint8_t)val; + ret = lsm6ds3_write_reg(ctx, LSM6DS3_TAP_THS_6D, (uint8_t*)&tap_ths_6d, 1); + } + return ret; +} + +/** + * @brief Threshold for tap recognition.[get] + * + * @param ctx read / write interface definitions(ptr) + * @param val get the values of tap_ths in reg TAP_THS_6D + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6ds3_tap_threshold_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6ds3_tap_ths_6d_t tap_ths_6d; + int32_t ret; + + ret = lsm6ds3_read_reg(ctx, LSM6DS3_TAP_THS_6D, (uint8_t*)&tap_ths_6d, 1); + *val = (uint8_t)tap_ths_6d.tap_ths; + + return ret; +} + +/** + * @brief Maximum duration is the maximum time of an overthreshold signal + * detection to be recognized as a tap event. The default value + * of these bits is 00b which corresponds to 4*ODR_XL time. + * If the SHOCK[1:0] bits are set to a different value, + * 1LSB corresponds to 8*ODR_XL time.[set] + * + * @param ctx read / write interface definitions(ptr) + * @param val change the values of shock in reg INT_DUR2 + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6ds3_tap_shock_set(stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6ds3_int_dur2_t int_dur2; + int32_t ret; + + ret = lsm6ds3_read_reg(ctx, LSM6DS3_INT_DUR2, (uint8_t*)&int_dur2, 1); + if(ret == 0){ + int_dur2.shock = (uint8_t)val; + ret = lsm6ds3_write_reg(ctx, LSM6DS3_INT_DUR2, (uint8_t*)&int_dur2, 1); + } + return ret; +} + +/** + * @brief Maximum duration is the maximum time of an overthreshold signal + * detection to be recognized as a tap event. + * The default value of these bits is 00b which corresponds + * to 4*ODR_XL time. If the SHOCK[1:0] bits are set to a different + * value, 1LSB corresponds to 8*ODR_XL time.[get] + * + * @param ctx read / write interface definitions(ptr) + * @param val get the values of shock in reg INT_DUR2 + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6ds3_tap_shock_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6ds3_int_dur2_t int_dur2; + int32_t ret; + + ret = lsm6ds3_read_reg(ctx, LSM6DS3_INT_DUR2, (uint8_t*)&int_dur2, 1); + *val = (uint8_t)int_dur2.shock; + + return ret; +} + +/** + * @brief Quiet time is the time after the first detected tap in + * which there must not be any over-threshold event. + * The default value of these bits is 00b which corresponds + * to 2*ODR_XL time. If the QUIET[1:0] bits are set to a + * different value, 1LSB corresponds to 4*ODR_XL time.[set] + * + * @param ctx read / write interface definitions(ptr) + * @param val change the values of quiet in reg INT_DUR2 + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6ds3_tap_quiet_set(stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6ds3_int_dur2_t int_dur2; + int32_t ret; + + ret = lsm6ds3_read_reg(ctx, LSM6DS3_INT_DUR2, (uint8_t*)&int_dur2, 1); + if(ret == 0){ + int_dur2.quiet = (uint8_t)val; + ret = lsm6ds3_write_reg(ctx, LSM6DS3_INT_DUR2, (uint8_t*)&int_dur2, 1); + } + return ret; +} + +/** + * @brief Quiet time is the time after the first detected tap in which + * there must not be any over-threshold event. The default value + * of these bits is 00b which corresponds to 2*ODR_XL time. + * If the QUIET[1:0] bits are set to a different value, + * 1LSB corresponds to 4*ODR_XL time.[get] + * + * @param ctx read / write interface definitions(ptr) + * @param val get the values of quiet in reg INT_DUR2 + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6ds3_tap_quiet_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6ds3_int_dur2_t int_dur2; + int32_t ret; + + ret = lsm6ds3_read_reg(ctx, LSM6DS3_INT_DUR2, (uint8_t*)&int_dur2, 1); + *val = (uint8_t)int_dur2.quiet; + + return ret; +} + +/** + * @brief When double tap recognition is enabled, this register + * expresses the maximum time between two consecutive detected + * taps to determine a double tap event. The default value of + * these bits is 0000b which corresponds to 16*ODR_XL time. + * If the DUR[3:0] bits are set to a different value, + * 1LSB corresponds to 32*ODR_XL time.[set] + * + * @param ctx read / write interface definitions(ptr) + * @param val change the values of dur in reg INT_DUR2 + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6ds3_tap_dur_set(stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6ds3_int_dur2_t int_dur2; + int32_t ret; + + ret = lsm6ds3_read_reg(ctx, LSM6DS3_INT_DUR2, (uint8_t*)&int_dur2, 1); + if(ret == 0){ + int_dur2.dur = (uint8_t)val; + ret = lsm6ds3_write_reg(ctx, LSM6DS3_INT_DUR2, (uint8_t*)&int_dur2, 1); + } + return ret; +} + +/** + * @brief When double tap recognition is enabled, this register + * expresses the maximum time between two consecutive detected + * taps to determine a double tap event. + * The default value of these bits is 0000b which corresponds + * to 16*ODR_XL time. If the DUR[3:0] bits are set to a + * different value, 1LSB corresponds to 32*ODR_XL time.[get] + * + * @param ctx read / write interface definitions(ptr) + * @param val get the values of dur in reg INT_DUR2 + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6ds3_tap_dur_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6ds3_int_dur2_t int_dur2; + int32_t ret; + + ret = lsm6ds3_read_reg(ctx, LSM6DS3_INT_DUR2, (uint8_t*)&int_dur2, 1); + *val = (uint8_t)int_dur2.dur; + + return ret; +} + +/** + * @brief Single/double-tap event enable.[set] + * + * @param ctx read / write interface definitions(ptr) + * @param val change the values of single_double_tap in reg LSM6DS3 + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6ds3_tap_mode_set(stmdev_ctx_t *ctx, lsm6ds3_tap_md_t val) +{ + lsm6ds3_wake_up_ths_t wake_up_ths; + int32_t ret; + + ret = lsm6ds3_read_reg(ctx, LSM6DS3_WAKE_UP_THS, (uint8_t*)&wake_up_ths, 1); + if(ret == 0){ + wake_up_ths.single_double_tap = (uint8_t)val; + ret = lsm6ds3_write_reg(ctx, LSM6DS3_WAKE_UP_THS, + (uint8_t*)&wake_up_ths, 1); + } + return ret; +} + +/** + * @brief Single/double-tap event enable.[get] + * + * @param ctx read / write interface definitions(ptr) + * @param val get the values of single_double_tap in reg WAKE_UP_THS + * + */ +int32_t lsm6ds3_tap_mode_get(stmdev_ctx_t *ctx, lsm6ds3_tap_md_t *val) +{ + lsm6ds3_wake_up_ths_t wake_up_ths; + int32_t ret; + + ret = lsm6ds3_read_reg(ctx, LSM6DS3_WAKE_UP_THS, (uint8_t*)&wake_up_ths, 1); + + switch (wake_up_ths.single_double_tap) + { + case LSM6DS3_ONLY_DOUBLE: + *val = LSM6DS3_ONLY_DOUBLE; + break; + case LSM6DS3_SINGLE_DOUBLE: + *val = LSM6DS3_SINGLE_DOUBLE; + break; + default: + *val = LSM6DS3_ONLY_DOUBLE; + break; + } + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup LSM6DS3_Six_position_detection(6D/4D) + * @brief This section groups all the functions concerning + * six position detection (6D). + * @{ + * + */ + +/** + * @brief LPF2 feed 6D function selection.[set] + * + * @param ctx read / write interface definitions(ptr) + * @param val change the values of low_pass_on_6d in reg LSM6DS3 + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6ds3_6d_feed_data_set(stmdev_ctx_t *ctx, + lsm6ds3_low_pass_on_6d_t val) +{ + lsm6ds3_ctrl8_xl_t ctrl8_xl; + int32_t ret; + + ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL8_XL, (uint8_t*)&ctrl8_xl, 1); + if(ret == 0){ + ctrl8_xl.low_pass_on_6d = (uint8_t)val; + ret = lsm6ds3_write_reg(ctx, LSM6DS3_CTRL8_XL, (uint8_t*)&ctrl8_xl, 1); + } + return ret; +} + +/** + * @brief LPF2 feed 6D function selection.[get] + * + * @param ctx read / write interface definitions(ptr) + * @param val get the values of low_pass_on_6d in reg CTRL8_XL + * + */ +int32_t lsm6ds3_6d_feed_data_get(stmdev_ctx_t *ctx, + lsm6ds3_low_pass_on_6d_t *val) +{ + lsm6ds3_ctrl8_xl_t ctrl8_xl; + int32_t ret; + + ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL8_XL, (uint8_t*)&ctrl8_xl, 1); + + switch (ctrl8_xl.low_pass_on_6d) + { + case LSM6DS3_ODR_DIV_2_FEED: + *val = LSM6DS3_ODR_DIV_2_FEED; + break; + case LSM6DS3_LPF2_FEED: + *val = LSM6DS3_LPF2_FEED; + break; + default: + *val = LSM6DS3_ODR_DIV_2_FEED; + break; + } + return ret; +} + +/** + * @brief Read the d6d_src status flag of the device.[get] + * + * @param ctx read / write interface definitions(ptr) + * @param val Read the d6d_src status flag of the device. + * + */ +int32_t lsm6ds3_6d_src_get(stmdev_ctx_t *ctx, lsm6ds3_d6d_src_t *val) +{ + int32_t ret; + + ret = lsm6ds3_read_reg(ctx, LSM6DS3_D6D_SRC, (uint8_t*)val, 1); + + return ret; +} + +/** + * @brief Threshold for 4D/6D function.[set] + * + * @param ctx read / write interface definitions(ptr) + * @param val change the values of sixd_ths in reg LSM6DS3 + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6ds3_6d_threshold_set(stmdev_ctx_t *ctx, lsm6ds3_sixd_ths_t val) +{ + lsm6ds3_tap_ths_6d_t tap_ths_6d; + int32_t ret; + + ret = lsm6ds3_read_reg(ctx, LSM6DS3_TAP_THS_6D, (uint8_t*)&tap_ths_6d, 1); + if(ret == 0){ + tap_ths_6d.sixd_ths = (uint8_t)val; + ret = lsm6ds3_write_reg(ctx, LSM6DS3_TAP_THS_6D, + (uint8_t*)&tap_ths_6d, 1); + } + return ret; +} + +/** + * @brief Threshold for 4D/6D function.[get] + * + * @param ctx read / write interface definitions(ptr) + * @param val get the values of sixd_ths in reg TAP_THS_6D + * + */ +int32_t lsm6ds3_6d_threshold_get(stmdev_ctx_t *ctx, lsm6ds3_sixd_ths_t *val) +{ + lsm6ds3_tap_ths_6d_t tap_ths_6d; + int32_t ret; + + ret = lsm6ds3_read_reg(ctx, LSM6DS3_TAP_THS_6D, (uint8_t*)&tap_ths_6d, 1); + + switch (tap_ths_6d.sixd_ths) + { + case LSM6DS3_DEG_80: + *val = LSM6DS3_DEG_80; + break; + case LSM6DS3_DEG_70: + *val = LSM6DS3_DEG_70; + break; + case LSM6DS3_DEG_60: + *val = LSM6DS3_DEG_60; + break; + case LSM6DS3_DEG_50: + *val = LSM6DS3_DEG_50; + break; + default: + *val = LSM6DS3_DEG_80; + break; + } + return ret; +} + +/** + * @brief 4D orientation detection enable.[set] + * + * @param ctx read / write interface definitions(ptr) + * @param val change the values of d4d_en in reg TAP_THS_6D + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6ds3_4d_mode_set(stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6ds3_tap_ths_6d_t tap_ths_6d; + int32_t ret; + + ret = lsm6ds3_read_reg(ctx, LSM6DS3_TAP_THS_6D, (uint8_t*)&tap_ths_6d, 1); + if(ret == 0){ + tap_ths_6d.d4d_en = (uint8_t)val; + ret = lsm6ds3_write_reg(ctx, LSM6DS3_TAP_THS_6D, + (uint8_t*)&tap_ths_6d, 1); + } + return ret; +} + +/** + * @brief 4D orientation detection enable.[get] + * + * @param ctx read / write interface definitions(ptr) + * @param val get the values of d4d_en in reg TAP_THS_6D + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6ds3_4d_mode_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6ds3_tap_ths_6d_t tap_ths_6d; + int32_t ret; + + ret = lsm6ds3_read_reg(ctx, LSM6DS3_TAP_THS_6D, (uint8_t*)&tap_ths_6d, 1); + *val = (uint8_t)tap_ths_6d.d4d_en; + + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup LSM6DS3_Free_fall + * @brief This section group all the functions concerning the + * free fall detection. + * @{ + * + */ + +/** + * @brief Free fall threshold setting.[set] + * + * @param ctx read / write interface definitions(ptr) + * @param val change the values of ff_ths in reg LSM6DS3 + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6ds3_ff_threshold_set(stmdev_ctx_t *ctx, lsm6ds3_ff_ths_t val) +{ + lsm6ds3_free_fall_t free_fall; + int32_t ret; + + ret = lsm6ds3_read_reg(ctx, LSM6DS3_FREE_FALL, (uint8_t*)&free_fall, 1); + if(ret == 0){ + free_fall.ff_ths = (uint8_t)val; + ret = lsm6ds3_write_reg(ctx, LSM6DS3_FREE_FALL, (uint8_t*)&free_fall, 1); + } + return ret; +} + +/** + * @brief Free fall threshold setting.[get] + * + * @param ctx read / write interface definitions(ptr) + * @param val get the values of ff_ths in reg FREE_FALL + * + */ +int32_t lsm6ds3_ff_threshold_get(stmdev_ctx_t *ctx, lsm6ds3_ff_ths_t *val) +{ + lsm6ds3_free_fall_t free_fall; + int32_t ret; + + ret = lsm6ds3_read_reg(ctx, LSM6DS3_FREE_FALL, (uint8_t*)&free_fall, 1); + + switch (free_fall.ff_ths) + { + case LSM6DS3_156_mg: + *val = LSM6DS3_156_mg; + break; + case LSM6DS3_219_mg: + *val = LSM6DS3_219_mg; + break; + case LSM6DS3_250_mg: + *val = LSM6DS3_250_mg; + break; + case LSM6DS3_312_mg: + *val = LSM6DS3_312_mg; + break; + case LSM6DS3_344_mg: + *val = LSM6DS3_344_mg; + break; + case LSM6DS3_406_mg: + *val = LSM6DS3_406_mg; + break; + case LSM6DS3_469_mg: + *val = LSM6DS3_469_mg; + break; + case LSM6DS3_500_mg: + *val = LSM6DS3_500_mg; + break; + default: + *val = LSM6DS3_156_mg; + break; + } + return ret; +} + +/** + * @brief Free-fall duration event. 1LSb = 1 / ODR[set] + * + * @param ctx read / write interface definitions(ptr) + * @param val change the values of ff_dur in reg FREE_FALL + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6ds3_ff_dur_set(stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6ds3_free_fall_t free_fall; + int32_t ret; + + ret = lsm6ds3_read_reg(ctx, LSM6DS3_FREE_FALL, (uint8_t*)&free_fall, 1); + if(ret == 0){ + free_fall.ff_dur = (uint8_t)val; + ret = lsm6ds3_write_reg(ctx, LSM6DS3_FREE_FALL, (uint8_t*)&free_fall, 1); + } + return ret; +} + +/** + * @brief Free-fall duration event. 1LSb = 1 / ODR[get] + * + * @param ctx read / write interface definitions(ptr) + * @param val get the values of ff_dur in reg FREE_FALL + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6ds3_ff_dur_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6ds3_free_fall_t free_fall; + int32_t ret; + + ret = lsm6ds3_read_reg(ctx, LSM6DS3_FREE_FALL, (uint8_t*)&free_fall, 1); + *val = (uint8_t)free_fall.ff_dur; + + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup LSM6DS3_Fifo + * @brief This section group all the functions concerning the + * fifo usage + * @{ + * + */ + +/** + * @brief FIFO watermark level selection.[set] + * + * @param ctx read / write interface definitions(ptr) + * @param val change the values of fth in reg FIFO_CTRL1 + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6ds3_fifo_watermark_set(stmdev_ctx_t *ctx, uint16_t val) +{ + lsm6ds3_fifo_ctrl1_t fifo_ctrl1; + lsm6ds3_fifo_ctrl2_t fifo_ctrl2; + int32_t ret; + + ret = lsm6ds3_read_reg(ctx, LSM6DS3_FIFO_CTRL1, (uint8_t*)&fifo_ctrl1, 1); + if(ret == 0){ + ret = lsm6ds3_read_reg(ctx, LSM6DS3_FIFO_CTRL2, (uint8_t*)&fifo_ctrl2, 1); + } + if(ret == 0){ + fifo_ctrl2.fth = (uint8_t)((val & 0x0F00U) >> 8); + ret = lsm6ds3_write_reg(ctx, LSM6DS3_FIFO_CTRL2, (uint8_t*)&fifo_ctrl2, 1); + } + if(ret == 0){ + fifo_ctrl1.fth = (uint8_t)(val & 0x00FF0U); + ret = lsm6ds3_write_reg(ctx, LSM6DS3_FIFO_CTRL1, (uint8_t*)&fifo_ctrl1, 1); + } + return ret; +} + +/** + * @brief FIFO watermark level selection.[get] + * + * @param ctx read / write interface definitions(ptr) + * @param val get the values of fth in reg FIFO_CTRL1 + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6ds3_fifo_watermark_get(stmdev_ctx_t *ctx, uint16_t *val) +{ + lsm6ds3_fifo_ctrl1_t fifo_ctrl1; + lsm6ds3_fifo_ctrl2_t fifo_ctrl2; + int32_t ret; + + ret = lsm6ds3_read_reg(ctx, LSM6DS3_FIFO_CTRL1, (uint8_t*)&fifo_ctrl1, 1); + if(ret == 0){ + ret = lsm6ds3_read_reg(ctx, LSM6DS3_FIFO_CTRL2, (uint8_t*)&fifo_ctrl2, 1); + *val = (uint16_t)fifo_ctrl2.fth << 8; + *val |= fifo_ctrl1.fth; + } + return ret; +} + +/** + * @brief trigger signal for FIFO write operation.[set] + * + * @param ctx read / write interface definitions(ptr) + * @param val change the values of timer_pedo_fifo_drdy in reg LSM6DS3 + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6ds3_fifo_write_trigger_set(stmdev_ctx_t *ctx, + lsm6ds3_tmr_ped_fifo_drdy_t val) +{ + lsm6ds3_fifo_ctrl2_t fifo_ctrl2; + int32_t ret; + + ret = lsm6ds3_read_reg(ctx, LSM6DS3_FIFO_CTRL2, (uint8_t*)&fifo_ctrl2, 1); + if(ret == 0){ + fifo_ctrl2. timer_pedo_fifo_drdy = (uint8_t)val; + ret = lsm6ds3_write_reg(ctx, LSM6DS3_FIFO_CTRL2, (uint8_t*)&fifo_ctrl2, 1); + } + return ret; +} + +/** + * @brief trigger signal for FIFO write operation.[get] + * + * @param ctx read / write interface definitions(ptr) + * @param val get the values of timer_pedo_fifo_drdy in + * reg FIFO_CTRL2 + * + */ +int32_t lsm6ds3_fifo_write_trigger_get(stmdev_ctx_t *ctx, + lsm6ds3_tmr_ped_fifo_drdy_t *val) +{ + lsm6ds3_fifo_ctrl2_t fifo_ctrl2; + int32_t ret; + + ret = lsm6ds3_read_reg(ctx, LSM6DS3_FIFO_CTRL2, (uint8_t*)&fifo_ctrl2, 1); + + switch (fifo_ctrl2. timer_pedo_fifo_drdy) + { + case LSM6DS3_TRG_XL_GY_DRDY: + *val = LSM6DS3_TRG_XL_GY_DRDY; + break; + case LSM6DS3_TRG_STEP_DETECT: + *val = LSM6DS3_TRG_STEP_DETECT; + break; + default: + *val = LSM6DS3_TRG_XL_GY_DRDY; + break; + } + return ret; +} + +/** + * @brief Pedometer step counter and timestamp as 4th FIFO data set.[set] + * + * @param ctx read / write interface definitions(ptr) + * @param val change the values of timer_pedo_fifo_en in reg FIFO_CTRL2 + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6ds3_fifo_pedo_batch_set(stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6ds3_fifo_ctrl2_t fifo_ctrl2; + int32_t ret; + + ret = lsm6ds3_read_reg(ctx, LSM6DS3_FIFO_CTRL2, (uint8_t*)&fifo_ctrl2, 1); + if(ret == 0){ + fifo_ctrl2.timer_pedo_fifo_en = (uint8_t)val; + ret = lsm6ds3_write_reg(ctx, LSM6DS3_FIFO_CTRL2, + (uint8_t*)&fifo_ctrl2, 1); + } + return ret; +} + +/** + * @brief Pedometer step counter and timestamp as 4th FIFO data set.[get] + * + * @param ctx read / write interface definitions(ptr) + * @param val get the values of timer_pedo_fifo_en in reg FIFO_CTRL2 + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6ds3_fifo_pedo_batch_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6ds3_fifo_ctrl2_t fifo_ctrl2; + int32_t ret; + + ret = lsm6ds3_read_reg(ctx, LSM6DS3_FIFO_CTRL2, (uint8_t*)&fifo_ctrl2, 1); + *val = (uint8_t)fifo_ctrl2.timer_pedo_fifo_en; + + return ret; +} + +/** + * @brief Selects Batching Data Rate (writing frequency in FIFO) for + * accelerometer data.[set] + * + * @param ctx read / write interface definitions(ptr) + * @param val change the values of dec_fifo_xl in reg LSM6DS3 + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6ds3_fifo_xl_batch_set(stmdev_ctx_t *ctx, lsm6ds3_dec_fifo_xl_t val) +{ + lsm6ds3_fifo_ctrl3_t fifo_ctrl3; + int32_t ret; + + ret = lsm6ds3_read_reg(ctx, LSM6DS3_FIFO_CTRL3, (uint8_t*)&fifo_ctrl3, 1); + if(ret == 0){ + fifo_ctrl3.dec_fifo_xl = (uint8_t)val; + ret = lsm6ds3_write_reg(ctx, LSM6DS3_FIFO_CTRL3, + (uint8_t*)&fifo_ctrl3, 1); + } + return ret; +} + +/** + * @brief Selects Batching Data Rate (writing frequency in FIFO) for + * accelerometer data.[get] + * + * @param ctx read / write interface definitions(ptr) + * @param val get the values of dec_fifo_xl in reg FIFO_CTRL3 + * + */ +int32_t lsm6ds3_fifo_xl_batch_get(stmdev_ctx_t *ctx, + lsm6ds3_dec_fifo_xl_t *val) +{ + lsm6ds3_fifo_ctrl3_t fifo_ctrl3; + int32_t ret; + + ret = lsm6ds3_read_reg(ctx, LSM6DS3_FIFO_CTRL3, (uint8_t*)&fifo_ctrl3, 1); + + switch (fifo_ctrl3.dec_fifo_xl) + { + case LSM6DS3_FIFO_XL_DISABLE: + *val = LSM6DS3_FIFO_XL_DISABLE; + break; + case LSM6DS3_FIFO_XL_NO_DEC: + *val = LSM6DS3_FIFO_XL_NO_DEC; + break; + case LSM6DS3_FIFO_XL_DEC_2: + *val = LSM6DS3_FIFO_XL_DEC_2; + break; + case LSM6DS3_FIFO_XL_DEC_3: + *val = LSM6DS3_FIFO_XL_DEC_3; + break; + case LSM6DS3_FIFO_XL_DEC_4: + *val = LSM6DS3_FIFO_XL_DEC_4; + break; + case LSM6DS3_FIFO_XL_DEC_8: + *val = LSM6DS3_FIFO_XL_DEC_8; + break; + case LSM6DS3_FIFO_XL_DEC_16: + *val = LSM6DS3_FIFO_XL_DEC_16; + break; + case LSM6DS3_FIFO_XL_DEC_32: + *val = LSM6DS3_FIFO_XL_DEC_32; + break; + default: + *val = LSM6DS3_FIFO_XL_DISABLE; + break; + } + return ret; +} + +/** + * @brief Selects Batching Data Rate (writing frequency in FIFO) + * for gyroscope data.[set] + * + * @param ctx read / write interface definitions(ptr) + * @param val change the values of dec_fifo_gyro in reg LSM6DS3 + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6ds3_fifo_gy_batch_set(stmdev_ctx_t *ctx, lsm6ds3_dec_fifo_gyro_t val) +{ + lsm6ds3_fifo_ctrl3_t fifo_ctrl3; + int32_t ret; + + ret = lsm6ds3_read_reg(ctx, LSM6DS3_FIFO_CTRL3, (uint8_t*)&fifo_ctrl3, 1); + if(ret == 0){ + fifo_ctrl3.dec_fifo_gyro = (uint8_t)val; + ret = lsm6ds3_write_reg(ctx, LSM6DS3_FIFO_CTRL3, + (uint8_t*)&fifo_ctrl3, 1); + } + return ret; +} + +/** + * @brief Selects Batching Data Rate (writing frequency in FIFO) + * for gyroscope data.[get] + * + * @param ctx read / write interface definitions(ptr) + * @param val get the values of dec_fifo_gyro in reg FIFO_CTRL3 + * + */ +int32_t lsm6ds3_fifo_gy_batch_get(stmdev_ctx_t *ctx, + lsm6ds3_dec_fifo_gyro_t *val) +{ + lsm6ds3_fifo_ctrl3_t fifo_ctrl3; + int32_t ret; + + ret = lsm6ds3_read_reg(ctx, LSM6DS3_FIFO_CTRL3, (uint8_t*)&fifo_ctrl3, 1); + + switch (fifo_ctrl3.dec_fifo_gyro) + { + case LSM6DS3_FIFO_GY_DISABLE: + *val = LSM6DS3_FIFO_GY_DISABLE; + break; + case LSM6DS3_FIFO_GY_NO_DEC: + *val = LSM6DS3_FIFO_GY_NO_DEC; + break; + case LSM6DS3_FIFO_GY_DEC_2: + *val = LSM6DS3_FIFO_GY_DEC_2; + break; + case LSM6DS3_FIFO_GY_DEC_3: + *val = LSM6DS3_FIFO_GY_DEC_3; + break; + case LSM6DS3_FIFO_GY_DEC_4: + *val = LSM6DS3_FIFO_GY_DEC_4; + break; + case LSM6DS3_FIFO_GY_DEC_8: + *val = LSM6DS3_FIFO_GY_DEC_8; + break; + case LSM6DS3_FIFO_GY_DEC_16: + *val = LSM6DS3_FIFO_GY_DEC_16; + break; + case LSM6DS3_FIFO_GY_DEC_32: + *val = LSM6DS3_FIFO_GY_DEC_32; + break; + default: + *val = LSM6DS3_FIFO_GY_DISABLE; + break; + } + return ret; +} + +/** + * @brief Selects Batching Data Rate (writing frequency in FIFO) + * for third data set.[set] + * + * @param ctx read / write interface definitions(ptr) + * @param val change the values of dec_ds3_fifo in reg LSM6DS3 + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6ds3_fifo_dataset_3_batch_set(stmdev_ctx_t *ctx, + lsm6ds3_dec_ds3_fifo_t val) +{ + lsm6ds3_fifo_ctrl4_t fifo_ctrl4; + int32_t ret; + + ret = lsm6ds3_read_reg(ctx, LSM6DS3_FIFO_CTRL4, (uint8_t*)&fifo_ctrl4, 1); + if(ret == 0){ + fifo_ctrl4.dec_ds3_fifo = (uint8_t)val; + ret = lsm6ds3_write_reg(ctx, LSM6DS3_FIFO_CTRL4, + (uint8_t*)&fifo_ctrl4, 1); + } + return ret; +} + +/** + * @brief Selects Batching Data Rate (writing frequency in FIFO) + * for third data set.[get] + * + * @param ctx read / write interface definitions(ptr) + * @param val get the values of dec_ds3_fifo in reg FIFO_CTRL4 + * + */ +int32_t lsm6ds3_fifo_dataset_3_batch_get(stmdev_ctx_t *ctx, + lsm6ds3_dec_ds3_fifo_t *val) +{ + lsm6ds3_fifo_ctrl4_t fifo_ctrl4; + int32_t ret; + + ret = lsm6ds3_read_reg(ctx, LSM6DS3_FIFO_CTRL4, (uint8_t*)&fifo_ctrl4, 1); + + switch (fifo_ctrl4.dec_ds3_fifo) + { + case LSM6DS3_FIFO_DS3_DISABLE: + *val = LSM6DS3_FIFO_DS3_DISABLE; + break; + case LSM6DS3_FIFO_DS3_NO_DEC: + *val = LSM6DS3_FIFO_DS3_NO_DEC; + break; + case LSM6DS3_FIFO_DS3_DEC_2: + *val = LSM6DS3_FIFO_DS3_DEC_2; + break; + case LSM6DS3_FIFO_DS3_DEC_3: + *val = LSM6DS3_FIFO_DS3_DEC_3; + break; + case LSM6DS3_FIFO_DS3_DEC_4: + *val = LSM6DS3_FIFO_DS3_DEC_4; + break; + case LSM6DS3_FIFO_DS3_DEC_8: + *val = LSM6DS3_FIFO_DS3_DEC_8; + break; + case LSM6DS3_FIFO_DS3_DEC_16: + *val = LSM6DS3_FIFO_DS3_DEC_16; + break; + case LSM6DS3_FIFO_DS3_DEC_32: + *val = LSM6DS3_FIFO_DS3_DEC_32; + break; + default: + *val = LSM6DS3_FIFO_DS3_DISABLE; + break; + } + return ret; +} + +/** + * @brief Selects Batching Data Rate (writing frequency in FIFO) + * for fourth data set.[set] + * + * @param ctx read / write interface definitions(ptr) + * @param val change the values of dec_ds4_fifo in reg LSM6DS3 + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6ds3_fifo_dataset_4_batch_set(stmdev_ctx_t *ctx, + lsm6ds3_dec_ds4_fifo_t val) +{ + lsm6ds3_fifo_ctrl4_t fifo_ctrl4; + int32_t ret; + + ret = lsm6ds3_read_reg(ctx, LSM6DS3_FIFO_CTRL4, (uint8_t*)&fifo_ctrl4, 1); + if(ret == 0){ + fifo_ctrl4.dec_ds4_fifo = (uint8_t)val; + ret = lsm6ds3_write_reg(ctx, LSM6DS3_FIFO_CTRL4, + (uint8_t*)&fifo_ctrl4, 1); + } + return ret; +} + +/** + * @brief Selects Batching Data Rate (writing frequency in FIFO) + * for fourth data set.[get] + * + * @param ctx read / write interface definitions(ptr) + * @param val get the values of dec_ds4_fifo in reg FIFO_CTRL4 + * + */ +int32_t lsm6ds3_fifo_dataset_4_batch_get(stmdev_ctx_t *ctx, + lsm6ds3_dec_ds4_fifo_t *val) +{ + lsm6ds3_fifo_ctrl4_t fifo_ctrl4; + int32_t ret; + + ret = lsm6ds3_read_reg(ctx, LSM6DS3_FIFO_CTRL4, (uint8_t*)&fifo_ctrl4, 1); + + switch (fifo_ctrl4.dec_ds4_fifo) + { + case LSM6DS3_FIFO_DS4_DISABLE: + *val = LSM6DS3_FIFO_DS4_DISABLE; + break; + case LSM6DS3_FIFO_DS4_NO_DEC: + *val = LSM6DS3_FIFO_DS4_NO_DEC; + break; + case LSM6DS3_FIFO_DS4_DEC_2: + *val = LSM6DS3_FIFO_DS4_DEC_2; + break; + case LSM6DS3_FIFO_DS4_DEC_3: + *val = LSM6DS3_FIFO_DS4_DEC_3; + break; + case LSM6DS3_FIFO_DS4_DEC_4: + *val = LSM6DS3_FIFO_DS4_DEC_4; + break; + case LSM6DS3_FIFO_DS4_DEC_8: + *val = LSM6DS3_FIFO_DS4_DEC_8; + break; + case LSM6DS3_FIFO_DS4_DEC_16: + *val = LSM6DS3_FIFO_DS4_DEC_16; + break; + case LSM6DS3_FIFO_DS4_DEC_32: + *val = LSM6DS3_FIFO_DS4_DEC_32; + break; + default: + *val = LSM6DS3_FIFO_DS4_DISABLE; + break; + } + return ret; +} + +/** + * @brief 8-bit data storage in FIFO.[set] + * + * @param ctx read / write interface definitions(ptr) + * @param val change the values of only_high_data in reg FIFO_CTRL4 + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6ds3_fifo_xl_gy_8bit_format_set(stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6ds3_fifo_ctrl4_t fifo_ctrl4; + int32_t ret; + + ret = lsm6ds3_read_reg(ctx, LSM6DS3_FIFO_CTRL4, (uint8_t*)&fifo_ctrl4, 1); + if(ret == 0){ + fifo_ctrl4.only_high_data = (uint8_t)val; + ret = lsm6ds3_write_reg(ctx, LSM6DS3_FIFO_CTRL4, + (uint8_t*)&fifo_ctrl4, 1); + } + return ret; +} + +/** + * @brief 8-bit data storage in FIFO.[get] + * + * @param ctx read / write interface definitions(ptr) + * @param val get the values of only_high_data in reg FIFO_CTRL4 + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6ds3_fifo_xl_gy_8bit_format_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6ds3_fifo_ctrl4_t fifo_ctrl4; + int32_t ret; + + ret = lsm6ds3_read_reg(ctx, LSM6DS3_FIFO_CTRL4, (uint8_t*)&fifo_ctrl4, 1); + *val = (uint8_t)fifo_ctrl4.only_high_data; + + return ret; +} + +/** + * @brief FIFO mode selection.[set] + * + * @param ctx read / write interface definitions(ptr) + * @param val change the values of fifo_mode in reg LSM6DS3 + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6ds3_fifo_mode_set(stmdev_ctx_t *ctx, lsm6ds3_fifo_md_t val) +{ + lsm6ds3_fifo_ctrl5_t fifo_ctrl5; + int32_t ret; + + ret = lsm6ds3_read_reg(ctx, LSM6DS3_FIFO_CTRL5, (uint8_t*)&fifo_ctrl5, 1); + if(ret == 0){ + fifo_ctrl5.fifo_mode = (uint8_t)val; + ret = lsm6ds3_write_reg(ctx, LSM6DS3_FIFO_CTRL5, + (uint8_t*)&fifo_ctrl5, 1); + } + return ret; +} + +/** + * @brief FIFO mode selection.[get] + * + * @param ctx read / write interface definitions(ptr) + * @param val get the values of fifo_mode in reg FIFO_CTRL5 + * + */ +int32_t lsm6ds3_fifo_mode_get(stmdev_ctx_t *ctx, lsm6ds3_fifo_md_t *val) +{ + lsm6ds3_fifo_ctrl5_t fifo_ctrl5; + int32_t ret; + + ret = lsm6ds3_read_reg(ctx, LSM6DS3_FIFO_CTRL5, (uint8_t*)&fifo_ctrl5, 1); + + switch (fifo_ctrl5.fifo_mode) + { + case LSM6DS3_BYPASS_MODE: + *val = LSM6DS3_BYPASS_MODE; + break; + case LSM6DS3_FIFO_MODE: + *val = LSM6DS3_FIFO_MODE; + break; + case LSM6DS3_STREAM_TO_FIFO_MODE: + *val = LSM6DS3_STREAM_TO_FIFO_MODE; + break; + case LSM6DS3_BYPASS_TO_STREAM_MODE: + *val = LSM6DS3_BYPASS_TO_STREAM_MODE; + break; + default: + *val = LSM6DS3_BYPASS_MODE; + break; + } + return ret; +} + +/** + * @brief FIFO ODR selection, setting FIFO_MODE also.[set] + * + * @param ctx read / write interface definitions(ptr) + * @param val change the values of odr_fifo in reg LSM6DS3 + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6ds3_fifo_data_rate_set(stmdev_ctx_t *ctx, lsm6ds3_odr_fifo_t val) +{ + lsm6ds3_fifo_ctrl5_t fifo_ctrl5; + int32_t ret; + + ret = lsm6ds3_read_reg(ctx, LSM6DS3_FIFO_CTRL5, (uint8_t*)&fifo_ctrl5, 1); + if(ret == 0){ + fifo_ctrl5.odr_fifo = (uint8_t)val; + ret = lsm6ds3_write_reg(ctx, LSM6DS3_FIFO_CTRL5, + (uint8_t*)&fifo_ctrl5, 1); + } + return ret; +} + +/** + * @brief FIFO ODR selection, setting FIFO_MODE also.[get] + * + * @param ctx read / write interface definitions(ptr) + * @param val get the values of odr_fifo in reg FIFO_CTRL5 + * + */ +int32_t lsm6ds3_fifo_data_rate_get(stmdev_ctx_t *ctx, + lsm6ds3_odr_fifo_t *val) +{ + lsm6ds3_fifo_ctrl5_t fifo_ctrl5; + int32_t ret; + + ret = lsm6ds3_read_reg(ctx, LSM6DS3_FIFO_CTRL5, (uint8_t*)&fifo_ctrl5, 1); + + switch (fifo_ctrl5.odr_fifo) + { + case LSM6DS3_FIFO_DISABLE: + *val = LSM6DS3_FIFO_DISABLE; + break; + case LSM6DS3_FIFO_12Hz5: + *val = LSM6DS3_FIFO_12Hz5; + break; + case LSM6DS3_FIFO_26Hz: + *val = LSM6DS3_FIFO_26Hz; + break; + case LSM6DS3_FIFO_52Hz: + *val = LSM6DS3_FIFO_52Hz; + break; + case LSM6DS3_FIFO_104Hz: + *val = LSM6DS3_FIFO_104Hz; + break; + case LSM6DS3_FIFO_208Hz: + *val = LSM6DS3_FIFO_208Hz; + break; + case LSM6DS3_FIFO_416Hz: + *val = LSM6DS3_FIFO_416Hz; + break; + case LSM6DS3_FIFO_833Hz: + *val = LSM6DS3_FIFO_833Hz; + break; + case LSM6DS3_FIFO_1k66Hz: + *val = LSM6DS3_FIFO_1k66Hz; + break; + case LSM6DS3_FIFO_3k33Hz: + *val = LSM6DS3_FIFO_3k33Hz; + break; + case LSM6DS3_FIFO_6k66Hz: + *val = LSM6DS3_FIFO_6k66Hz; + break; + default: + *val = LSM6DS3_FIFO_DISABLE; + break; + } + return ret; +} + +/** + * @brief Sensing chain FIFO stop values memorization at + * threshold level.[set] + * + * @param ctx read / write interface definitions(ptr) + * @param val change the values of stop_on_fth in reg CTRL4_C + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6ds3_fifo_stop_on_wtm_set(stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6ds3_ctrl4_c_t ctrl4_c; + int32_t ret; + + ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL4_C, (uint8_t*)&ctrl4_c, 1); + if(ret == 0){ + ctrl4_c.stop_on_fth = (uint8_t)val; + ret = lsm6ds3_write_reg(ctx, LSM6DS3_CTRL4_C, (uint8_t*)&ctrl4_c, 1); + } + return ret; +} + +/** + * @brief Sensing chain FIFO stop values memorization at + * threshold level.[get] + * + * @param ctx read / write interface definitions(ptr) + * @param val get the values of stop_on_fth in reg CTRL4_C + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6ds3_fifo_stop_on_wtm_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6ds3_ctrl4_c_t ctrl4_c; + int32_t ret; + + ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL4_C, (uint8_t*)&ctrl4_c, 1); + *val = (uint8_t)ctrl4_c.stop_on_fth; + + return ret; +} + +/** + * @brief batching of temperature data.[set] + * + * @param ctx read / write interface definitions(ptr) + * @param val change the values of fifo_temp_en in reg CTRL4_C + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6ds3_fifo_temp_batch_set(stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6ds3_ctrl4_c_t ctrl4_c; + int32_t ret; + + ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL4_C, (uint8_t*)&ctrl4_c, 1); + if(ret == 0){ + ctrl4_c.fifo_temp_en = (uint8_t)val; + ret = lsm6ds3_write_reg(ctx, LSM6DS3_CTRL4_C, (uint8_t*)&ctrl4_c, 1); + } + return ret; +} + +/** + * @brief batching of temperature data.[get] + * + * @param ctx read / write interface definitions(ptr) + * @param val get the values of fifo_temp_en in reg CTRL4_C + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6ds3_fifo_temp_batch_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6ds3_ctrl4_c_t ctrl4_c; + int32_t ret; + + ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL4_C, (uint8_t*)&ctrl4_c, 1); + *val = (uint8_t)ctrl4_c.fifo_temp_en; + + return ret; +} + +/** + * @brief Number of unread words (16-bit axes) stored in FIFO.[get] + * + * @param ctx read / write interface definitions(ptr) + * @param val get the values of diff_fifo in reg FIFO_STATUS1 + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6ds3_fifo_data_level_get(stmdev_ctx_t *ctx, uint16_t *val) +{ + lsm6ds3_fifo_status1_t fifo_status1; + lsm6ds3_fifo_status2_t fifo_status2; + int32_t ret; + + ret = lsm6ds3_read_reg(ctx, LSM6DS3_FIFO_STATUS1, + (uint8_t*)&fifo_status1, 1); + + if(ret == 0){ + ret = lsm6ds3_read_reg(ctx, LSM6DS3_FIFO_STATUS2, + (uint8_t*)&fifo_status2, 1); + + *val = (uint16_t)fifo_status2.diff_fifo << 8; + *val |= fifo_status1.diff_fifo; + } + return ret; +} + +/** + * @brief Smart FIFO full status.[get] + * + * @param ctx read / write interface definitions(ptr) + * @param val get the values of fifo_empty in reg FIFO_STATUS2 + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6ds3_fifo_full_flag_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6ds3_fifo_status2_t fifo_status2; + int32_t ret; + + ret = lsm6ds3_read_reg(ctx, LSM6DS3_FIFO_STATUS2, + (uint8_t*)&fifo_status2, 1); + *val = (uint8_t)fifo_status2.fifo_empty; + + return ret; +} + +/** + * @brief FIFO overrun status.[get] + * + * @param ctx read / write interface definitions(ptr) + * @param val get the values of fifo_full in reg FIFO_STATUS2 + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6ds3_fifo_ovr_flag_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6ds3_fifo_status2_t fifo_status2; + int32_t ret; + + ret = lsm6ds3_read_reg(ctx, LSM6DS3_FIFO_STATUS2, + (uint8_t*)&fifo_status2, 1); + *val = (uint8_t)fifo_status2.fifo_full; + + return ret; +} + +/** + * @brief FIFO watermark status.[get] + * + * @param ctx read / write interface definitions(ptr) + * @param val get the values of fth in reg FIFO_STATUS2 + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6ds3_fifo_wtm_flag_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6ds3_fifo_status2_t fifo_status2; + int32_t ret; + + ret = lsm6ds3_read_reg(ctx, LSM6DS3_FIFO_STATUS2, + (uint8_t*)&fifo_status2, 1); + *val = (uint8_t)fifo_status2.fth; + + return ret; +} + +/** + * @brief Word of recursive pattern read at the next reading.[get] + * + * @param ctx read / write interface definitions(ptr) + * @param val get the values of fifo_pattern in reg FIFO_STATUS3 + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6ds3_fifo_pattern_get(stmdev_ctx_t *ctx, uint16_t *val) +{ + lsm6ds3_fifo_status3_t fifo_status3; + lsm6ds3_fifo_status4_t fifo_status4; + + int32_t ret; + + ret = lsm6ds3_read_reg(ctx, LSM6DS3_FIFO_STATUS3, + (uint8_t*)&fifo_status3, 1); + if(ret == 0){ + ret = lsm6ds3_read_reg(ctx, LSM6DS3_FIFO_STATUS4, + (uint8_t*)&fifo_status4, 1); + + *val = (uint16_t)fifo_status4.fifo_pattern << 8; + *val |= fifo_status3.fifo_pattern; + } + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup LSM6DS3_DEN_functionality + * @brief This section groups all the functions concerning DEN + * functionality. + * @{ + * + */ + +/** + * @brief DEN functionality marking mode.[set] + * + * @param ctx read / write interface definitions(ptr) + * @param val change the values of den_mode in reg CTRL6_C + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6ds3_den_mode_set(stmdev_ctx_t *ctx, lsm6ds3_den_mode_t val) +{ + lsm6ds3_ctrl6_c_t ctrl6_c; + int32_t ret; + + ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL6_C, (uint8_t*)&ctrl6_c, 1); + + if(ret == 0){ + ctrl6_c.den_mode = (uint8_t)val; + ret = lsm6ds3_write_reg(ctx, LSM6DS3_CTRL6_C, (uint8_t*)&ctrl6_c, 1); + } + return ret; +} + +/** + * @brief DEN functionality marking mode.[get] + * + * @param ctx read / write interface definitions(ptr) + * @param val get the values of den_mode in reg CTRL6_C + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6ds3_den_mode_get(stmdev_ctx_t *ctx, lsm6ds3_den_mode_t *val) +{ + lsm6ds3_ctrl6_c_t ctrl6_c; + int32_t ret; + + ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL6_C, (uint8_t*)&ctrl6_c, 1); + + switch (ctrl6_c.den_mode) + { + case LSM6DS3_DEN_DISABLE: + *val = LSM6DS3_DEN_DISABLE; + break; + case LSM6DS3_LEVEL_FIFO: + *val = LSM6DS3_LEVEL_FIFO; + break; + case LSM6DS3_LEVEL_LETCHED: + *val = LSM6DS3_LEVEL_LETCHED; + break; + case LSM6DS3_LEVEL_TRIGGER: + *val = LSM6DS3_LEVEL_TRIGGER; + break; + case LSM6DS3_EDGE_TRIGGER: + *val = LSM6DS3_EDGE_TRIGGER; + break; + default: + *val = LSM6DS3_DEN_DISABLE; + break; + } + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup LSM6DS3_Pedometer + * @brief This section groups all the functions that manage pedometer. + * @{ + * + */ + +/** + * @brief Reset pedometer step counter.[set] + * + * @param ctx read / write interface definitions(ptr) + * @param val change the values of pedo_rst_step in reg CTRL10_C + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6ds3_pedo_step_reset_set(stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6ds3_ctrl10_c_t ctrl10_c; + int32_t ret; + + ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL10_C, (uint8_t*)&ctrl10_c, 1); + if(ret == 0){ + ctrl10_c.pedo_rst_step = (uint8_t)val; + ret = lsm6ds3_write_reg(ctx, LSM6DS3_CTRL10_C, (uint8_t*)&ctrl10_c, 1); + } + return ret; +} + +/** + * @brief Reset pedometer step counter.[get] + * + * @param ctx read / write interface definitions(ptr) + * @param val get the values of pedo_rst_step in reg CTRL10_C + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6ds3_pedo_step_reset_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6ds3_ctrl10_c_t ctrl10_c; + int32_t ret; + + ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL10_C, (uint8_t*)&ctrl10_c, 1); + *val = (uint8_t)ctrl10_c.pedo_rst_step; + + return ret; +} + +/** + * @brief Step counter timestamp information register (r). When a step is + * detected, the value of TIMESTAMP_REG register is copied in + * STEP_TIMESTAMP_L..[get] + * + * @param ctx read / write interface definitions(ptr) + * @param buff buffer that stores data read + * + */ +int32_t lsm6ds3_pedo_timestamp_raw_get(stmdev_ctx_t *ctx, uint8_t *buff) +{ + int32_t ret; + ret = lsm6ds3_read_reg(ctx, LSM6DS3_STEP_TIMESTAMP_L, buff, 2); + return ret; +} + +/** + * @brief Step detector event detection status + * (0:not detected / 1:detected).[get] + * + * @param ctx read / write interface definitions(ptr) + * @param val get the values of step_detected in reg FUNC_SRC + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6ds3_pedo_step_detect_flag_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6ds3_func_src_t func_src; + int32_t ret; + + ret = lsm6ds3_read_reg(ctx, LSM6DS3_FUNC_SRC, (uint8_t*)&func_src, 1); + *val = (uint8_t)func_src.step_detected; + + return ret; +} + +/** + * @brief Enable pedometer algorithm.[set] + * + * @param ctx read / write interface definitions(ptr) + * @param val change the values of pedo_en in reg TAP_CFG + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6ds3_pedo_sens_set(stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6ds3_ctrl10_c_t ctrl10_c; + lsm6ds3_tap_cfg_t tap_cfg; + int32_t ret; + + ret = 0; + if (val == PROPERTY_ENABLE){ + ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL10_C, (uint8_t*)&ctrl10_c, 1); + if(ret == 0){ + ctrl10_c.func_en = PROPERTY_ENABLE; + ret = lsm6ds3_write_reg(ctx, LSM6DS3_CTRL10_C, (uint8_t*)&ctrl10_c, 1); + } + } + if(ret == 0){ + ret = lsm6ds3_read_reg(ctx, LSM6DS3_TAP_CFG, (uint8_t*)&tap_cfg, 1); + } + if(ret == 0){ + ret = lsm6ds3_read_reg(ctx, LSM6DS3_TAP_CFG, (uint8_t*)&tap_cfg, 1); + } + if(ret == 0){ + tap_cfg.pedo_en = (uint8_t)val; + ret = lsm6ds3_write_reg(ctx, LSM6DS3_TAP_CFG, (uint8_t*)&tap_cfg, 1); + } + return ret; +} + +/** + * @brief Enable pedometer algorithm.[get] + * + * @param ctx read / write interface definitions(ptr) + * @param val get the values of pedo_en in reg TAP_CFG + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6ds3_pedo_sens_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6ds3_tap_cfg_t tap_cfg; + int32_t ret; + + ret = lsm6ds3_read_reg(ctx, LSM6DS3_TAP_CFG, (uint8_t*)&tap_cfg, 1); + *val = (uint8_t)tap_cfg.pedo_en; + + return ret; +} + +/** + * @brief Configurable minimum threshold (PEDO_4G 1LSB = 16 mg , + * PEDO_2G 1LSB = 32 mg).[set] + * + * @param ctx read / write interface definitions(ptr) + * @param val change the values of ths_min in reg PEDO_THS_REG + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6ds3_pedo_threshold_set(stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6ds3_pedo_ths_reg_t pedo_ths_reg; + int32_t ret; + + ret = lsm6ds3_mem_bank_set(ctx, LSM6DS3_EMBEDDED_FUNC_BANK); + if(ret == 0){ + ret = lsm6ds3_read_reg(ctx, LSM6DS3_PEDO_THS_REG, + (uint8_t*)&pedo_ths_reg, 1); + } + if(ret == 0){ + pedo_ths_reg.ths_min = (uint8_t)val; + ret = lsm6ds3_write_reg(ctx, LSM6DS3_PEDO_THS_REG, + (uint8_t*)&pedo_ths_reg, 1); + } + if(ret == 0){ + ret = lsm6ds3_mem_bank_set(ctx, LSM6DS3_USER_BANK); + } + return ret; +} + +/** + * @brief Configurable minimum threshold (PEDO_4G 1LSB = 16 mg, + * PEDO_2G 1LSB = 32 mg).[get] + * + * @param ctx read / write interface definitions(ptr) + * @param val get the values of ths_min in reg PEDO_THS_REG + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6ds3_pedo_threshold_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6ds3_pedo_ths_reg_t pedo_ths_reg; + int32_t ret; + + ret = lsm6ds3_mem_bank_set(ctx, LSM6DS3_EMBEDDED_FUNC_BANK); + if(ret == 0){ + ret = lsm6ds3_read_reg(ctx, LSM6DS3_PEDO_THS_REG, + (uint8_t*)&pedo_ths_reg, 1); + } + if(ret == 0){ + ret = lsm6ds3_mem_bank_set(ctx, LSM6DS3_USER_BANK); + *val = (uint8_t)pedo_ths_reg.ths_min; + } + return ret; +} + +/** + * @brief This bit sets the internal full scale used in + * pedometer functions.[set] + * + * @param ctx read / write interface definitions(ptr) + * @param val change the values of pedo_4g in reg LSM6DS3 + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6ds3_pedo_full_scale_set(stmdev_ctx_t *ctx, lsm6ds3_pedo_fs_t val) +{ + lsm6ds3_pedo_ths_reg_t pedo_ths_reg; + int32_t ret; + + ret = lsm6ds3_mem_bank_set(ctx, LSM6DS3_EMBEDDED_FUNC_BANK); + if(ret == 0){ + ret = lsm6ds3_read_reg(ctx, LSM6DS3_PEDO_THS_REG, + (uint8_t*)&pedo_ths_reg, 1); + } + if(ret == 0){ + pedo_ths_reg.pedo_4g = (uint8_t)val; + ret = lsm6ds3_write_reg(ctx, LSM6DS3_PEDO_THS_REG, + (uint8_t*)&pedo_ths_reg, 1); + } + if(ret == 0){ + ret = lsm6ds3_mem_bank_set(ctx, LSM6DS3_USER_BANK); + } + return ret; +} + +/** + * @brief This bit sets the internal full scale used in pedometer + * functions.[get] + * + * @param ctx read / write interface definitions(ptr) + * @param val get the values of pedo_4g in reg PEDO_THS_REG + * + */ +int32_t lsm6ds3_pedo_full_scale_get(stmdev_ctx_t *ctx, lsm6ds3_pedo_fs_t *val) +{ + lsm6ds3_pedo_ths_reg_t pedo_ths_reg; + int32_t ret; + + ret = lsm6ds3_mem_bank_set(ctx, LSM6DS3_EMBEDDED_FUNC_BANK); + if(ret == 0){ + ret = lsm6ds3_read_reg(ctx, LSM6DS3_PEDO_THS_REG, + (uint8_t*)&pedo_ths_reg, 1); + switch (pedo_ths_reg.pedo_4g) + { + case LSM6DS3_PEDO_AT_2g: + *val = LSM6DS3_PEDO_AT_2g; + break; + case LSM6DS3_PEDO_AT_4g: + *val = LSM6DS3_PEDO_AT_4g; + break; + default: + *val = LSM6DS3_PEDO_AT_2g; + break; + } + } + if(ret == 0){ + ret = lsm6ds3_mem_bank_set(ctx, LSM6DS3_USER_BANK); + } + return ret; +} + +/** + * @brief Pedometer debounce configuration register (r/w).[set] + * + * @param ctx read / write interface definitions(ptr) + * @param val change the values of deb_step in reg PEDO_DEB_REG + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6ds3_pedo_debounce_steps_set(stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6ds3_pedo_deb_reg_t pedo_deb_reg; + int32_t ret; + + ret = lsm6ds3_mem_bank_set(ctx, LSM6DS3_EMBEDDED_FUNC_BANK); + if(ret == 0){ + ret = lsm6ds3_read_reg(ctx, LSM6DS3_PEDO_DEB_REG, + (uint8_t*)&pedo_deb_reg, 1); + } + if(ret == 0){ + pedo_deb_reg.deb_step = (uint8_t)val; + ret = lsm6ds3_write_reg(ctx, LSM6DS3_PEDO_DEB_REG, + (uint8_t*)&pedo_deb_reg, 1); + } + if(ret == 0){ + ret = lsm6ds3_mem_bank_set(ctx, LSM6DS3_USER_BANK); + } + return ret; +} + +/** + * @brief Pedometer debounce configuration register (r/w).[get] + * + * @param ctx read / write interface definitions(ptr) + * @param val get the values of deb_step in reg PEDO_DEB_REG + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6ds3_pedo_debounce_steps_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6ds3_pedo_deb_reg_t pedo_deb_reg; + int32_t ret; + + ret = lsm6ds3_mem_bank_set(ctx, LSM6DS3_EMBEDDED_FUNC_BANK); + if(ret == 0){ + ret = lsm6ds3_read_reg(ctx, LSM6DS3_PEDO_DEB_REG, + (uint8_t*)&pedo_deb_reg, 1); + } + if(ret == 0){ + ret = lsm6ds3_mem_bank_set(ctx, LSM6DS3_USER_BANK); + *val = (uint8_t)pedo_deb_reg.deb_step; + } + return ret; +} + +/** + * @brief Debounce time. If the time between two consecutive steps is + * greater than DEB_TIME*80ms, the debounce is reactivated.[set] + * + * @param ctx read / write interface definitions(ptr) + * @param val change the values of deb_time in reg PEDO_DEB_REG + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6ds3_pedo_timeout_set(stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6ds3_pedo_deb_reg_t pedo_deb_reg; + int32_t ret; + + ret = lsm6ds3_mem_bank_set(ctx, LSM6DS3_EMBEDDED_FUNC_BANK); + if(ret == 0){ + ret = lsm6ds3_read_reg(ctx, LSM6DS3_PEDO_DEB_REG, + (uint8_t*)&pedo_deb_reg, 1); + } + if(ret == 0){ + pedo_deb_reg.deb_time = (uint8_t)val; + ret = lsm6ds3_write_reg(ctx, LSM6DS3_PEDO_DEB_REG, + (uint8_t*)&pedo_deb_reg, 1); + } + if(ret == 0){ + ret = lsm6ds3_mem_bank_set(ctx, LSM6DS3_USER_BANK); + } + return ret; +} + +/** + * @brief Debounce time. If the time between two consecutive steps is + * greater than DEB_TIME*80ms, the debounce is reactivated.[get] + * + * @param ctx read / write interface definitions(ptr) + * @param val get the values of deb_time in reg PEDO_DEB_REG + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6ds3_pedo_timeout_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6ds3_pedo_deb_reg_t pedo_deb_reg; + int32_t ret; + + ret = lsm6ds3_mem_bank_set(ctx, LSM6DS3_EMBEDDED_FUNC_BANK); + if(ret == 0){ + ret = lsm6ds3_read_reg(ctx, LSM6DS3_PEDO_DEB_REG, + (uint8_t*)&pedo_deb_reg, 1); + } + if(ret == 0){ + *val = (uint8_t)pedo_deb_reg.deb_time; + ret = lsm6ds3_mem_bank_set(ctx, LSM6DS3_USER_BANK); + } + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup LSM6DS3_Significant_motion + * @brief This section groups all the functions that manage the + * significant motion detection. + * @{ + * + */ + +/** + * @brief Enable significant motion detection function.[set] + * + * @param ctx read / write interface definitions(ptr) + * @param val change the values of sign_motion_en in reg CTRL10_C + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6ds3_motion_sens_set(stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6ds3_ctrl10_c_t ctrl10_c; + int32_t ret; + + ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL10_C, (uint8_t*)&ctrl10_c, 1); + if(ret == 0){ + ctrl10_c.sign_motion_en = (uint8_t)val; + if (val == PROPERTY_ENABLE){ + ctrl10_c.func_en = PROPERTY_ENABLE; + } + ret = lsm6ds3_write_reg(ctx, LSM6DS3_CTRL10_C, (uint8_t*)&ctrl10_c, 1); + } + return ret; +} + +/** + * @brief Enable significant motion detection function.[get] + * + * @param ctx read / write interface definitions(ptr) + * @param val get the values of sign_motion_en in reg CTRL10_C + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6ds3_motion_sens_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6ds3_ctrl10_c_t ctrl10_c; + int32_t ret; + + ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL10_C, (uint8_t*)&ctrl10_c, 1); + *val = (uint8_t)ctrl10_c.sign_motion_en; + + return ret; +} + +/** + * @brief Significant motion event detection status + * (0:not detected / 1:detected).[get] + * + * @param ctx read / write interface definitions(ptr) + * @param val get the values of sign_motion_ia in reg FUNC_SRC + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6ds3_motion_event_flag_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6ds3_func_src_t func_src; + int32_t ret; + + ret = lsm6ds3_read_reg(ctx, LSM6DS3_FUNC_SRC, (uint8_t*)&func_src, 1); + *val = (uint8_t)func_src.sign_motion_ia; + + return ret; +} + +/** + * @brief Significant motion threshold.[set] + * + * @param ctx read / write interface definitions(ptr) + * @param val change the values of sm_ths in reg SM_THS + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6ds3_motion_threshold_set(stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6ds3_sm_ths_t sm_ths; + int32_t ret; + + ret = lsm6ds3_mem_bank_set(ctx, LSM6DS3_EMBEDDED_FUNC_BANK); + if(ret == 0){ + ret = lsm6ds3_read_reg(ctx, LSM6DS3_SM_THS, (uint8_t*)&sm_ths, 1); + } + if(ret == 0){ + sm_ths.sm_ths = (uint8_t)val; + ret = lsm6ds3_write_reg(ctx, LSM6DS3_SM_THS, (uint8_t*)&sm_ths, 1); + } + if(ret == 0){ + ret = lsm6ds3_mem_bank_set(ctx, LSM6DS3_USER_BANK); + } + return ret; +} + +/** + * @brief Significant motion threshold.[get] + * + * @param ctx read / write interface definitions(ptr) + * @param val get the values of sm_ths in reg SM_THS + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6ds3_motion_threshold_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6ds3_sm_ths_t sm_ths; + int32_t ret; + + ret = lsm6ds3_mem_bank_set(ctx, LSM6DS3_EMBEDDED_FUNC_BANK); + if(ret == 0){ + ret = lsm6ds3_read_reg(ctx, LSM6DS3_SM_THS, (uint8_t*)&sm_ths, 1); + } + if(ret == 0){ + ret = lsm6ds3_mem_bank_set(ctx, LSM6DS3_USER_BANK); + *val = (uint8_t)sm_ths.sm_ths; + } + return ret; +} + +/** + * @brief Time period register for step detection on delta time + * (1LSB = 1.6384 s).[set] + * + * @param ctx read / write interface definitions(ptr) + * @param val change the values of sc_delta in reg STEP_COUNT_DELTA + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6ds3_sc_delta_set(stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6ds3_step_count_delta_t step_count_delta; + int32_t ret; + + ret = lsm6ds3_mem_bank_set(ctx, LSM6DS3_EMBEDDED_FUNC_BANK); + if(ret == 0){ + ret = lsm6ds3_read_reg(ctx, LSM6DS3_STEP_COUNT_DELTA, + (uint8_t*)& step_count_delta, 1); + } + if(ret == 0){ + step_count_delta.sc_delta = (uint8_t)val; + ret = lsm6ds3_write_reg(ctx, LSM6DS3_STEP_COUNT_DELTA, + (uint8_t*)& step_count_delta, 1); + } + if(ret == 0){ + ret = lsm6ds3_mem_bank_set(ctx, LSM6DS3_USER_BANK); + } + return ret; +} + +/** + * @brief Time period register for step detection on delta time + * (1LSB = 1.6384 s).[get] + * + * @param ctx read / write interface definitions(ptr) + * @param val get the values of sc_delta in reg STEP_COUNT_DELTA + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6ds3_sc_delta_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6ds3_step_count_delta_t step_count_delta; + int32_t ret; + + ret = lsm6ds3_mem_bank_set(ctx, LSM6DS3_EMBEDDED_FUNC_BANK); + if(ret == 0){ + ret = lsm6ds3_read_reg(ctx, LSM6DS3_STEP_COUNT_DELTA, + (uint8_t*)& step_count_delta, 1); + } + if(ret == 0){ + ret = lsm6ds3_mem_bank_set(ctx, LSM6DS3_USER_BANK); + *val = (uint8_t) step_count_delta.sc_delta; + } + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup LSM6DS3_Tilt_detection + * @brief This section groups all the functions that manage + * the tilt event detection. + * @{ + * + */ + +/** + * @brief Tilt event detection status(0:not detected / 1:detected).[get] + * + * @param ctx read / write interface definitions(ptr) + * @param val get the values of tilt_ia in reg FUNC_SRC + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6ds3_tilt_event_flag_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6ds3_func_src_t func_src; + int32_t ret; + + ret = lsm6ds3_read_reg(ctx, LSM6DS3_FUNC_SRC, (uint8_t*)&func_src, 1); + *val = (uint8_t)func_src.tilt_ia; + + return ret; +} + +/** + * @brief Enable tilt calculation.[set] + * + * @param ctx read / write interface definitions(ptr) + * @param val change the values of tilt_en in reg TAP_CFG + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6ds3_tilt_sens_set(stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6ds3_ctrl10_c_t ctrl10_c; + lsm6ds3_tap_cfg_t tap_cfg; + int32_t ret; + + ret = 0; + if (val == PROPERTY_ENABLE){ + ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL10_C, (uint8_t*)&ctrl10_c, 1); + if(ret == 0){ + ctrl10_c.func_en = PROPERTY_ENABLE; + ret = lsm6ds3_write_reg(ctx, LSM6DS3_CTRL10_C, (uint8_t*)&ctrl10_c, 1); + } + } + if(ret == 0){ + ret = lsm6ds3_read_reg(ctx, LSM6DS3_TAP_CFG, (uint8_t*)&tap_cfg, 1); + } + if(ret == 0){ + tap_cfg.tilt_en = (uint8_t)val; + ret = lsm6ds3_write_reg(ctx, LSM6DS3_TAP_CFG, (uint8_t*)&tap_cfg, 1); + } + return ret; +} + +/** + * @brief Enable tilt calculation.[get] + * + * @param ctx read / write interface definitions(ptr) + * @param val get the values of tilt_en in reg TAP_CFG + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6ds3_tilt_sens_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6ds3_tap_cfg_t tap_cfg; + int32_t ret; + + ret = lsm6ds3_read_reg(ctx, LSM6DS3_TAP_CFG, (uint8_t*)&tap_cfg, 1); + *val = (uint8_t)tap_cfg.tilt_en; + + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup LSM6DS3_Magnetometer_sensor + * @brief This section groups all the functions that manage + * additional magnetometer sensor. + * @{ + * + */ + +/** + * @brief Enable soft-iron correction algorithm for magnetometer.[set] + * + * @param ctx read / write interface definitions(ptr) + * @param val change the values of soft_en in reg CTRL9_XL + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6ds3_mag_soft_iron_set(stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6ds3_ctrl10_c_t ctrl10_c; + lsm6ds3_ctrl9_xl_t ctrl9_xl; + int32_t ret; + + ret = 0; + if (val == PROPERTY_ENABLE){ + ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL10_C, (uint8_t*)&ctrl10_c, 1); + if(ret == 0){ + ctrl10_c.func_en = PROPERTY_ENABLE; + ret = lsm6ds3_write_reg(ctx, LSM6DS3_CTRL10_C, (uint8_t*)&ctrl10_c, 1); + } + } + if(ret == 0){ + ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL9_XL, (uint8_t*)&ctrl9_xl, 1); + } + if(ret == 0){ + ctrl9_xl.soft_en = (uint8_t)val; + ret = lsm6ds3_write_reg(ctx, LSM6DS3_CTRL9_XL, (uint8_t*)&ctrl9_xl, 1); + } + return ret; +} + +/** + * @brief Enable soft-iron correction algorithm for magnetometer.[get] + * + * @param ctx read / write interface definitions(ptr) + * @param val get the values of soft_en in reg CTRL9_XL + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6ds3_mag_soft_iron_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6ds3_ctrl9_xl_t ctrl9_xl; + int32_t ret; + + ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL9_XL, (uint8_t*)&ctrl9_xl, 1); + *val = (uint8_t)ctrl9_xl.soft_en; + + return ret; +} + +/** + * @brief Enable hard-iron correction algorithm for magnetometer.[set] + * + * @param ctx read / write interface definitions(ptr) + * @param val change the values of iron_en in reg MASTER_CONFIG + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6ds3_mag_hard_iron_set(stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6ds3_ctrl10_c_t ctrl10_c; + lsm6ds3_master_config_t master_config; + int32_t ret; + + ret = 0; + if (val == PROPERTY_ENABLE){ + ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL10_C, (uint8_t*)&ctrl10_c, 1); + ctrl10_c.func_en = PROPERTY_ENABLE; + if(ret == 0){ + ret = lsm6ds3_write_reg(ctx, LSM6DS3_CTRL10_C, (uint8_t*)&ctrl10_c, 1); + } + } + if(ret == 0){ + ret = lsm6ds3_read_reg(ctx, LSM6DS3_MASTER_CONFIG, + (uint8_t*)&master_config, 1); + } + if(ret == 0){ + master_config.iron_en = (uint8_t)val; + ret = lsm6ds3_write_reg(ctx, LSM6DS3_MASTER_CONFIG, + (uint8_t*)&master_config, 1); + } + return ret; +} + +/** + * @brief Enable hard-iron correction algorithm for magnetometer.[get] + * + * @param ctx read / write interface definitions(ptr) + * @param val get the values of iron_en in reg MASTER_CONFIG + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6ds3_mag_hard_iron_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6ds3_master_config_t master_config; + int32_t ret; + + ret = lsm6ds3_read_reg(ctx, LSM6DS3_MASTER_CONFIG, + (uint8_t*)&master_config, 1); + *val = (uint8_t)master_config.iron_en; + + return ret; +} + +/** + * @brief Hard/soft-iron calculation status (0: on-going / 1: idle).[get] + * + * @param ctx read / write interface definitions(ptr) + * @param val get the values of si_end_op in reg FUNC_SRC + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6ds3_mag_soft_iron_end_op_flag_get(stmdev_ctx_t *ctx, + uint8_t *val) +{ + lsm6ds3_func_src_t func_src; + int32_t ret; + + ret = lsm6ds3_read_reg(ctx, LSM6DS3_FUNC_SRC, (uint8_t*)&func_src, 1); + *val = (uint8_t)func_src.si_end_op; + + return ret; +} + +/** + * @brief Soft-iron matrix correction registers[set] + * + * @param ctx read / write interface definitions(ptr) + * @param buff buffer that stores data to be write + * + */ +int32_t lsm6ds3_mag_soft_iron_coeff_set(stmdev_ctx_t *ctx, uint8_t *buff) +{ + int32_t ret; + ret = lsm6ds3_mem_bank_set(ctx, LSM6DS3_EMBEDDED_FUNC_BANK); + if(ret == 0){ + ret = lsm6ds3_write_reg(ctx, LSM6DS3_MAG_SI_XX, buff, 9); + } + if(ret == 0){ + ret = lsm6ds3_mem_bank_set(ctx, LSM6DS3_USER_BANK); + } + return ret; +} + +/** + * @brief Soft-iron matrix correction registers[get] + * + * @param ctx read / write interface definitions(ptr) + * @param buff buffer that stores data read + * + */ +int32_t lsm6ds3_mag_soft_iron_coeff_get(stmdev_ctx_t *ctx, uint8_t *buff) +{ + int32_t ret; + + ret = lsm6ds3_mem_bank_set(ctx, LSM6DS3_EMBEDDED_FUNC_BANK); + if(ret == 0){ + ret = lsm6ds3_read_reg(ctx, LSM6DS3_MAG_SI_XX, buff, 9); + } + if(ret == 0){ + ret = lsm6ds3_mem_bank_set(ctx, LSM6DS3_USER_BANK); + } + return ret; +} + +/** + * @brief Offset for hard-iron compensation register (r/w). + * The value is expressed as a 16-bit word in two’s complement.[set] + * + * @param ctx read / write interface definitions(ptr) + * @param buff buffer that stores data to be write + * + */ +int32_t lsm6ds3_mag_offset_set(stmdev_ctx_t *ctx, uint8_t *buff) +{ + int32_t ret; + + ret = lsm6ds3_mem_bank_set(ctx, LSM6DS3_EMBEDDED_FUNC_BANK); + if(ret == 0){ + ret = lsm6ds3_write_reg(ctx, LSM6DS3_MAG_OFFX_L, buff, 6); + } + if(ret == 0){ + ret = lsm6ds3_mem_bank_set(ctx, LSM6DS3_USER_BANK); + } + return ret; +} + +/** + * @brief Offset for hard-iron compensation register(r/w). + * The value is expressed as a 16-bit word in two’s complement.[get] + * + * @param ctx read / write interface definitions(ptr) + * @param buff buffer that stores data read + * + */ +int32_t lsm6ds3_mag_offset_get(stmdev_ctx_t *ctx, uint8_t *buff) +{ + int32_t ret; + + ret = lsm6ds3_mem_bank_set(ctx, LSM6DS3_EMBEDDED_FUNC_BANK); + if(ret == 0){ + ret = lsm6ds3_read_reg(ctx, LSM6DS3_MAG_OFFX_L, buff, 6); + } + if(ret == 0){ + ret = lsm6ds3_mem_bank_set(ctx, LSM6DS3_USER_BANK); + } + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup LSM6DS3_Sensor_hub + * @brief This section groups all the functions that manage the + * sensor hub functionality. + * @{ + * + */ + +/** + * @brief Sensor synchronization time frame with the step of 500 ms + * and full range of 5 s. Unsigned 8-bit.[set] + * + * @param ctx read / write interface definitions(ptr) + * @param val change the values of tph in reg SENSOR_SYNC_TIME_FRAME + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6ds3_sh_sync_sens_frame_set(stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6ds3_sensor_sync_time_frame_t sensor_sync_time_frame; + int32_t ret; + + ret = lsm6ds3_read_reg(ctx, LSM6DS3_SENSOR_SYNC_TIME_FRAME, + (uint8_t*)& sensor_sync_time_frame, 1); + if(ret == 0){ + sensor_sync_time_frame.tph = (uint8_t)val; + ret = lsm6ds3_write_reg(ctx, LSM6DS3_SENSOR_SYNC_TIME_FRAME, + (uint8_t*)& sensor_sync_time_frame, 1); + } + return ret; +} + +/** + * @brief Sensor synchronization time frame with the step of 500 ms and + * full range of 5 s. Unsigned 8-bit.[get] + * + * @param ctx read / write interface definitions(ptr) + * @param val get the values of tph in reg SENSOR_SYNC_TIME_FRAME + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6ds3_sh_sync_sens_frame_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6ds3_sensor_sync_time_frame_t sensor_sync_time_frame; + int32_t ret; + + ret = lsm6ds3_read_reg(ctx, LSM6DS3_SENSOR_SYNC_TIME_FRAME, + (uint8_t*)& sensor_sync_time_frame, 1); + *val = (uint8_t) sensor_sync_time_frame.tph; + + return ret; +} +/** + * @brief Sensor hub I2C master enable.[set] + * + * @param ctx read / write interface definitions(ptr) + * @param val change the values of master_on in reg MASTER_CONFIG + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6ds3_sh_master_set(stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6ds3_ctrl10_c_t ctrl10_c; + lsm6ds3_master_config_t master_config; + int32_t ret; + + ret = 0; + if (val == PROPERTY_ENABLE){ + ret = lsm6ds3_read_reg(ctx, LSM6DS3_CTRL10_C, (uint8_t*)&ctrl10_c, 1); + if(ret == 0){ + ctrl10_c.func_en = PROPERTY_ENABLE; + ret = lsm6ds3_write_reg(ctx, LSM6DS3_CTRL10_C, (uint8_t*)&ctrl10_c, 1); + } + } + if(ret == 0){ + ret = lsm6ds3_read_reg(ctx, LSM6DS3_MASTER_CONFIG, + (uint8_t*)&master_config, 1); + } + if(ret == 0){ + master_config.master_on = (uint8_t)val; + ret = lsm6ds3_write_reg(ctx, LSM6DS3_MASTER_CONFIG, + (uint8_t*)&master_config, 1); + } + return ret; +} + +/** + * @brief Sensor hub I2C master enable.[get] + * + * @param ctx read / write interface definitions(ptr) + * @param val get the values of master_on in reg MASTER_CONFIG + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6ds3_sh_master_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6ds3_master_config_t master_config; + int32_t ret; + + ret = lsm6ds3_read_reg(ctx, LSM6DS3_MASTER_CONFIG, + (uint8_t*)&master_config, 1); + *val = (uint8_t)master_config.master_on; + + return ret; +} +/** + * @brief I2C interface pass-through.[set] + * + * @param ctx read / write interface definitions(ptr) + * @param val change the values of pass_through_mode in + * reg MASTER_CONFIG + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6ds3_sh_pass_through_set(stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6ds3_master_config_t master_config; + int32_t ret; + + ret = lsm6ds3_read_reg(ctx, LSM6DS3_MASTER_CONFIG, + (uint8_t*)&master_config, 1); + if(ret == 0){ + master_config.pass_through_mode = (uint8_t)val; + ret = lsm6ds3_write_reg(ctx, LSM6DS3_MASTER_CONFIG, + (uint8_t*)&master_config, 1); + } + return ret; +} + +/** + * @brief I2C interface pass-through.[get] + * + * @param ctx read / write interface definitions(ptr) + * @param val get the values of pass_through_mode in reg MASTER_CONFIG + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6ds3_sh_pass_through_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6ds3_master_config_t master_config; + int32_t ret; + + ret = lsm6ds3_read_reg(ctx, LSM6DS3_MASTER_CONFIG, + (uint8_t*)&master_config, 1); + *val = (uint8_t)master_config.pass_through_mode; + + return ret; +} +/** + * @brief Master I2C pull-up enable/disable.[set] + * + * @param ctx read / write interface definitions(ptr) + * @param val change the values of pull_up_en in reg LSM6DS3 + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6ds3_sh_pin_mode_set(stmdev_ctx_t *ctx, lsm6ds3_sh_pin_md_t val) +{ + lsm6ds3_master_config_t master_config; + int32_t ret; + + ret = lsm6ds3_read_reg(ctx, LSM6DS3_MASTER_CONFIG, + (uint8_t*)&master_config, 1); + if(ret == 0){ + master_config.pull_up_en = (uint8_t)val; + ret = lsm6ds3_write_reg(ctx, LSM6DS3_MASTER_CONFIG, + (uint8_t*)&master_config, 1); + } + return ret; +} + +/** + * @brief Master I2C pull-up enable/disable.[get] + * + * @param ctx read / write interface definitions(ptr) + * @param val get the values of pull_up_en in reg MASTER_CONFIG + * + */ +int32_t lsm6ds3_sh_pin_mode_get(stmdev_ctx_t *ctx, lsm6ds3_sh_pin_md_t *val) +{ + lsm6ds3_master_config_t master_config; + int32_t ret; + + ret = lsm6ds3_read_reg(ctx, LSM6DS3_MASTER_CONFIG, + (uint8_t*)&master_config, 1); + + switch (master_config.pull_up_en) + { + case LSM6DS3_EXT_PULL_UP: + *val = LSM6DS3_EXT_PULL_UP; + break; + case LSM6DS3_INTERNAL_PULL_UP: + *val = LSM6DS3_INTERNAL_PULL_UP; + break; + default: + *val = LSM6DS3_EXT_PULL_UP; + break; + } + return ret; +} + +/** + * @brief Sensor hub trigger signal selection.[set] + * + * @param ctx read / write interface definitions(ptr) + * @param val change the values of start_config in reg LSM6DS3 + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6ds3_sh_syncro_mode_set(stmdev_ctx_t *ctx, lsm6ds3_start_cfg_t val) +{ + lsm6ds3_master_config_t master_config; + int32_t ret; + + ret = lsm6ds3_read_reg(ctx, LSM6DS3_MASTER_CONFIG, + (uint8_t*)&master_config, 1); + if(ret == 0){ + master_config.start_config = (uint8_t)val; + ret = lsm6ds3_write_reg(ctx, LSM6DS3_MASTER_CONFIG, + (uint8_t*)&master_config, 1); + } + return ret; +} + +/** + * @brief Sensor hub trigger signal selection.[get] + * + * @param ctx read / write interface definitions(ptr) + * @param val get the values of start_config in reg MASTER_CONFIG + * + */ +int32_t lsm6ds3_sh_syncro_mode_get(stmdev_ctx_t *ctx, + lsm6ds3_start_cfg_t *val) +{ + lsm6ds3_master_config_t master_config; + int32_t ret; + + ret = lsm6ds3_read_reg(ctx, LSM6DS3_MASTER_CONFIG, + (uint8_t*)&master_config, 1); + + switch (master_config.start_config) + { + case LSM6DS3_XL_GY_DRDY: + *val = LSM6DS3_XL_GY_DRDY; + break; + case LSM6DS3_EXT_ON_INT2_PIN: + *val = LSM6DS3_EXT_ON_INT2_PIN; + break; + default: + *val = LSM6DS3_XL_GY_DRDY; + break; + } + return ret; +} + +/** + * @brief Sensor hub output registers.[get] + * + * @param ctx read / write interface definitions(ptr) + * @param buff buffer that stores data read + * + */ +int32_t lsm6ds3_sh_read_data_raw_get(stmdev_ctx_t *ctx, + lsm6ds3_sh_read_t *buff) +{ + int32_t ret; + ret = lsm6ds3_read_reg(ctx, LSM6DS3_SENSORHUB1_REG, + (uint8_t*)&(buff->sh_byte_1), 12); + + if(ret == 0){ + ret = lsm6ds3_read_reg(ctx, LSM6DS3_SENSORHUB13_REG, + (uint8_t*)&(buff->sh_byte_13), 6); + } + return ret; +} + +/** + * @brief sh_cfg_write: Configure slave 0 for perform a write. + * + * @param stmdev_ctx_t *ctx: read / write interface definitions + * @param lsm6ds3_sh_cfg_write_t: a structure that contain + * - uint8_t slv1_add; 8 bit i2c device address + * - uint8_t slv1_subadd; 8 bit register device address + * - uint8_t slv1_data; 8 bit data to write + * + */ +int32_t lsm6ds3_sh_cfg_write(stmdev_ctx_t *ctx, lsm6ds3_sh_cfg_write_t *val) +{ + lsm6ds3_slv0_add_t slv0_add; + int32_t ret; + + ret = lsm6ds3_mem_bank_set(ctx, LSM6DS3_EMBEDDED_FUNC_BANK); + if(ret == 0){ + slv0_add.slave0_add = val->slv0_add >> 1; + slv0_add.rw_0 = 0; + ret = lsm6ds3_write_reg(ctx, LSM6DS3_SLV0_ADD, (uint8_t*)&slv0_add, 1); + } + if(ret == 0){ + ret = lsm6ds3_write_reg(ctx, LSM6DS3_SLV0_SUBADD, + &(val->slv0_subadd), 1); + } + if(ret == 0){ + ret = lsm6ds3_write_reg(ctx, LSM6DS3_DATAWRITE_SRC_MODE_SUB_SLV0, + &(val->slv0_data), 1); + } + if(ret == 0){ + ret = lsm6ds3_mem_bank_set(ctx, LSM6DS3_USER_BANK); + } + + return ret; +} + +/** + * @brief sh_slv0_cfg_read: [get] Configure slave 0 for perform a write/read. + * + * @param stmdev_ctx_t *ctx: read / write interface definitions + * @param lsm6ds3_sh_cfg_read_t: a structure that contain + * - uint8_t slv1_add; 8 bit i2c device address + * - uint8_t slv1_subadd; 8 bit register device address + * - uint8_t slv1_len; num of bit to read + * + */ +int32_t lsm6ds3_sh_slv0_cfg_read(stmdev_ctx_t *ctx, + lsm6ds3_sh_cfg_read_t *val) +{ + lsm6ds3_slv0_add_t slv0_add; + lsm6ds3_slave0_config_t slave0_config; + int32_t ret; + + ret = lsm6ds3_mem_bank_set(ctx, LSM6DS3_EMBEDDED_FUNC_BANK); + if(ret == 0){ + slv0_add.slave0_add = val->slv_add >> 1; + slv0_add.rw_0 = 1; + ret = lsm6ds3_write_reg(ctx, LSM6DS3_SLV0_ADD, (uint8_t*)&slv0_add, 1); + } + if(ret == 0){ + ret = lsm6ds3_write_reg(ctx, LSM6DS3_SLV0_SUBADD, + &(val->slv_subadd), 1); + } + if(ret == 0){ + ret = lsm6ds3_read_reg(ctx, LSM6DS3_SLAVE0_CONFIG, + (uint8_t*)&slave0_config, 1); + } + if(ret == 0){ + slave0_config.slave0_numop = val->slv_len; + ret = lsm6ds3_write_reg(ctx, LSM6DS3_SLAVE0_CONFIG, + (uint8_t*)&slave0_config, 1); + } + if(ret == 0){ + ret = lsm6ds3_mem_bank_set(ctx, LSM6DS3_USER_BANK); + } + return ret; +} + +/** + * @brief sh_slv1_cfg_read: [get] Configure slave 0 for perform a write/read. + * + * @param stmdev_ctx_t *ctx: read / write interface definitions + * @param lsm6ds3_sh_cfg_read_t: a structure that contain + * - uint8_t slv1_add; 8 bit i2c device address + * - uint8_t slv1_subadd; 8 bit register device address + * - uint8_t slv1_len; num of bit to read + * + */ +int32_t lsm6ds3_sh_slv1_cfg_read(stmdev_ctx_t *ctx, + lsm6ds3_sh_cfg_read_t *val) +{ + lsm6ds3_slv1_add_t slv1_add; + lsm6ds3_slave1_config_t slave1_config; + int32_t ret; + + ret = lsm6ds3_mem_bank_set(ctx, LSM6DS3_EMBEDDED_FUNC_BANK); + if(ret == 0){ + slv1_add.slave1_add = val->slv_add >> 1;; + slv1_add.r_1 = 1; + ret = lsm6ds3_write_reg(ctx, LSM6DS3_SLV1_ADD, (uint8_t*)&slv1_add, 1); + } + if(ret == 0){ + ret = lsm6ds3_write_reg(ctx, LSM6DS3_SLV1_SUBADD, + &(val->slv_subadd), 1); + } + if(ret == 0){ + ret = lsm6ds3_read_reg(ctx, LSM6DS3_SLAVE1_CONFIG, (uint8_t*)&slave1_config, 1); + } + if(ret == 0){ + slave1_config.slave1_numop = val->slv_len; + ret = lsm6ds3_write_reg(ctx, LSM6DS3_SLAVE1_CONFIG, (uint8_t*)&slave1_config, 1); + } + if(ret == 0){ + ret = lsm6ds3_mem_bank_set(ctx, LSM6DS3_USER_BANK); + } + return ret; +} + +/** + * @brief sh_slv2_cfg_read: [get] Configure slave 0 for perform a write/read. + * + * @param stmdev_ctx_t *ctx: read / write interface definitions + * @param lsm6ds3_sh_cfg_read_t: a structure that contain + * - uint8_t slv2_add; 8 bit i2c device address + * - uint8_t slv2_subadd; 8 bit register device address + * - uint8_t slv2_len; num of bit to read + * + */ +int32_t lsm6ds3_sh_slv2_cfg_read(stmdev_ctx_t *ctx, + lsm6ds3_sh_cfg_read_t *val) +{ + lsm6ds3_slv2_add_t slv2_add; + lsm6ds3_slave2_config_t slave2_config; + int32_t ret; + + ret = lsm6ds3_mem_bank_set(ctx, LSM6DS3_EMBEDDED_FUNC_BANK); + if(ret == 0){ + slv2_add.slave2_add = val->slv_add >> 1; + slv2_add.r_2 = 1; + ret = lsm6ds3_write_reg(ctx, LSM6DS3_SLV2_ADD, + (uint8_t*)&slv2_add, 1); + } + if(ret == 0){ + ret = lsm6ds3_write_reg(ctx, LSM6DS3_SLV2_SUBADD, + &(val->slv_subadd), 1); + } + if(ret == 0){ + ret = lsm6ds3_read_reg(ctx, LSM6DS3_SLAVE2_CONFIG, + (uint8_t*)&slave2_config, 1); + } + if(ret == 0){ + slave2_config.slave2_numop = val->slv_len; + ret = lsm6ds3_write_reg(ctx, LSM6DS3_SLAVE2_CONFIG, + (uint8_t*)&slave2_config, 1); + } + if(ret == 0){ + ret = lsm6ds3_mem_bank_set(ctx, LSM6DS3_USER_BANK); + } + return ret; +} + +/** + * @brief sh_slv3_cfg_read: [get] Configure slave 0 for perform a write/read. + * + * @param stmdev_ctx_t *ctx: read / write interface definitions + * @param lsm6ds3_sh_cfg_read_t: a structure that contain + * - uint8_t slv3_add; 8 bit i2c device address + * - uint8_t slv3_subadd; 8 bit register device address + * - uint8_t slv3_len; num of bit to read + * + */ +int32_t lsm6ds3_sh_slv3_cfg_read(stmdev_ctx_t *ctx, + lsm6ds3_sh_cfg_read_t *val) +{ + lsm6ds3_slv3_add_t slv3_add; + lsm6ds3_slave3_config_t slave3_config; + int32_t ret; + + ret = lsm6ds3_mem_bank_set(ctx, LSM6DS3_EMBEDDED_FUNC_BANK); + if(ret == 0){ + slv3_add.slave3_add = val->slv_add >> 1; + slv3_add.r_3 = 1; + ret = lsm6ds3_write_reg(ctx, LSM6DS3_SLV3_ADD, (uint8_t*)&slv3_add, 1); + } + if(ret == 0){ + ret = lsm6ds3_write_reg(ctx, LSM6DS3_SLV3_SUBADD, + &(val->slv_subadd), 1); + } + if(ret == 0){ + ret = lsm6ds3_read_reg(ctx, LSM6DS3_SLAVE3_CONFIG, + (uint8_t*)&slave3_config, 1); + } + if(ret == 0){ + slave3_config.slave3_numop = val->slv_len; + ret = lsm6ds3_write_reg(ctx, LSM6DS3_SLAVE3_CONFIG, + (uint8_t*)&slave3_config, 1); + } + if(ret == 0){ + ret = lsm6ds3_mem_bank_set(ctx, LSM6DS3_USER_BANK); + } + return ret; +} + +/** + * @brief Sensor hub communication status (0: on-going / 1: idle).[get] + * + * @param ctx read / write interface definitions(ptr) + * @param val get the values of sensor_hub_end_op in reg FUNC_SRC + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6ds3_sh_end_op_flag_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6ds3_func_src_t func_src; + int32_t ret; + + ret = lsm6ds3_read_reg(ctx, LSM6DS3_FUNC_SRC, (uint8_t*)&func_src, 1); + *val = (uint8_t)func_src.sensor_hub_end_op; + + return ret; +} + +/** + * @brief xl_hp_path_internal: [set] HPF or SLOPE filter selection on + * wake-up and Activity/Inactivity + * functions. + * + * @param stmdev_ctx_t *ctx: read / write interface definitions + * @param lsm6ds3_slope_fds_t: change the values of slope_fds in reg TAP_CFG + * + */ +int32_t lsm6ds3_xl_hp_path_internal_set(stmdev_ctx_t *ctx, + lsm6ds3_slope_fds_t val) +{ + lsm6ds3_tap_cfg_t tap_cfg; + int32_t ret; + + ret = lsm6ds3_read_reg(ctx, LSM6DS3_TAP_CFG, (uint8_t*)&tap_cfg, 1); + if(ret == 0){ + tap_cfg.slope_fds = (uint8_t)val; + ret = lsm6ds3_write_reg(ctx, LSM6DS3_TAP_CFG, (uint8_t*)&tap_cfg, 1); + } + return ret; +} + +/** + * @brief xl_hp_path_internal: [get] HPF or SLOPE filter selection on + * wake-up and Activity/Inactivity + * functions. + * + * @param stmdev_ctx_t *ctx: read / write interface definitions + * @param lsm6ds3_slope_fds_t: Get the values of slope_fds in reg TAP_CFG + * + */ +int32_t lsm6ds3_xl_hp_path_internal_get(stmdev_ctx_t *ctx, + lsm6ds3_slope_fds_t *val) +{ + lsm6ds3_tap_cfg_t reg; + int32_t ret; + + ret = lsm6ds3_read_reg(ctx, LSM6DS3_TAP_CFG, (uint8_t*)®, 1); + switch (reg.slope_fds) + { + case LSM6DS3_USE_SLOPE: + *val = LSM6DS3_USE_SLOPE; + break; + case LSM6DS3_USE_HPF: + *val = LSM6DS3_USE_HPF; + break; + default: + *val = LSM6DS3_USE_SLOPE; + break; + } + return ret; +} + +/** + * @brief sh_num_of_dev_connected: [set] Number of external sensors to + * be read by the sensor hub. + * + * @param stmdev_ctx_t *ctx: read / write interface definitions + * @param lsm6ds3_aux_sens_on_t: change the values of aux_sens_on in + * reg SLAVE0_CONFIG + * + */ +int32_t lsm6ds3_sh_num_of_dev_connected_set(stmdev_ctx_t *ctx, + lsm6ds3_aux_sens_on_t val) +{ + lsm6ds3_slave0_config_t reg; + int32_t ret; + + ret = lsm6ds3_mem_bank_set(ctx, LSM6DS3_EMBEDDED_FUNC_BANK); + if(ret == 0){ + ret = lsm6ds3_read_reg(ctx, LSM6DS3_SLAVE0_CONFIG, (uint8_t*)®, 1); + } + if(ret == 0){ + reg.aux_sens_on = (uint8_t)val; + ret = lsm6ds3_write_reg(ctx, LSM6DS3_SLAVE0_CONFIG, (uint8_t*)®, 1); + } + if(ret == 0){ + ret = lsm6ds3_mem_bank_set(ctx, LSM6DS3_USER_BANK); + } + return ret; +} + +/** + * @brief sh_num_of_dev_connected: [get] Number of external sensors to + * be read by the sensor hub. + * + * @param stmdev_ctx_t *ctx: read / write interface definitions + * @param lsm6ds3_aux_sens_on_t: Get the values of aux_sens_on in + * reg SLAVE0_CONFIG + * + */ +int32_t lsm6ds3_sh_num_of_dev_connected_get(stmdev_ctx_t *ctx, + lsm6ds3_aux_sens_on_t *val) +{ + lsm6ds3_slave0_config_t reg; + int32_t ret; + + ret = lsm6ds3_mem_bank_set(ctx, LSM6DS3_EMBEDDED_FUNC_BANK); + if(ret == 0){ + ret = lsm6ds3_read_reg(ctx, LSM6DS3_SLAVE0_CONFIG, (uint8_t*)®, 1); + switch (reg.aux_sens_on) + { + case LSM6DS3_SLV_0: + *val = LSM6DS3_SLV_0; + break; + case LSM6DS3_SLV_0_1: + *val = LSM6DS3_SLV_0_1; + break; + case LSM6DS3_SLV_0_1_2: + *val = LSM6DS3_SLV_0_1_2; + break; + case LSM6DS3_SLV_0_1_2_3: + *val = LSM6DS3_SLV_0_1_2_3; + break; + default: + *val = LSM6DS3_SLV_0; + break; + } + } + if(ret == 0){ + ret = lsm6ds3_mem_bank_set(ctx, LSM6DS3_USER_BANK); + } + return ret; +} + +/** + * @} + * + */ + +/** + * @} + * + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/st/src/lsm6ds3tr_c_reg.c b/src/st/src/lsm6ds3tr_c_reg.c new file mode 100644 index 000000000..65e7cd997 --- /dev/null +++ b/src/st/src/lsm6ds3tr_c_reg.c @@ -0,0 +1,6805 @@ +/* + ****************************************************************************** + * @file lsm6ds3tr_c_reg.c + * @author Sensors Software Solution Team + * @brief LSM6DS3TR_C driver file + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2019 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +#include "lsm6ds3tr_c_reg.h" + +/** + * @defgroup LSM6DS3TR_C + * @brief This file provides a set of functions needed to drive the + * lsm6ds3tr_c enanced inertial module. + * @{ + * + */ + +/** + * @defgroup LSM6DS3TR_C_interfaces_functions + * @brief This section provide a set of functions used to read and + * write a generic register of the device. + * MANDATORY: return 0 -> no Error. + * @{ + * + */ + +/** + * @brief Read generic device register + * + * @param ctx read / write interface definitions(ptr) + * @param reg register to read + * @param data pointer to buffer that store the data read(ptr) + * @param len number of consecutive register to read + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6ds3tr_c_read_reg(stmdev_ctx_t* ctx, uint8_t reg, uint8_t* data, + uint16_t len) +{ + int32_t ret; + ret = ctx->read_reg(ctx->handle, reg, data, len); + return ret; +} + +/** + * @brief Write generic device register + * + * @param ctx read / write interface definitions(ptr) + * @param reg register to write + * @param data pointer to data to write in register reg(ptr) + * @param len number of consecutive register to write + * @retval interface status (MANDATORY: return 0 -> no Error) + * + */ +int32_t lsm6ds3tr_c_write_reg(stmdev_ctx_t* ctx, uint8_t reg, uint8_t* data, + uint16_t len) +{ + int32_t ret; + ret = ctx->write_reg(ctx->handle, reg, data, len); + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup LSM6DS3TR_C_Sensitivity + * @brief These functions convert raw-data into engineering units. + * @{ + * + */ + +float_t lsm6ds3tr_c_from_fs2g_to_mg(int16_t lsb) +{ + return ((float_t)lsb * 0.061f); +} + +float_t lsm6ds3tr_c_from_fs4g_to_mg(int16_t lsb) +{ + return ((float_t)lsb * 0.122f); +} + +float_t lsm6ds3tr_c_from_fs8g_to_mg(int16_t lsb) +{ + return ((float_t)lsb * 0.244f); +} + +float_t lsm6ds3tr_c_from_fs16g_to_mg(int16_t lsb) +{ + return ((float_t)lsb * 0.488f); +} + +float_t lsm6ds3tr_c_from_fs125dps_to_mdps(int16_t lsb) +{ + return ((float_t)lsb * 4.375f); +} + +float_t lsm6ds3tr_c_from_fs250dps_to_mdps(int16_t lsb) +{ + return ((float_t)lsb * 8.750f); +} + +float_t lsm6ds3tr_c_from_fs500dps_to_mdps(int16_t lsb) +{ + return ((float_t)lsb * 17.50f); +} + +float_t lsm6ds3tr_c_from_fs1000dps_to_mdps(int16_t lsb) +{ + return ((float_t)lsb * 35.0f); +} + +float_t lsm6ds3tr_c_from_fs2000dps_to_mdps(int16_t lsb) +{ + return ((float_t)lsb * 70.0f); +} + +float_t lsm6ds3tr_c_from_lsb_to_celsius(int16_t lsb) +{ + return (((float_t)lsb / 256.0f) + 25.0f); +} + +/** + * @} + * + */ + + +/** + * @defgroup LSM6DS3TR_C_data_generation + * @brief This section groups all the functions concerning data + * generation + * @{ + * +*/ + +/** + * @brief Accelerometer full-scale selection.[set] + * + * @param ctx Read / write interface definitions + * @param val Change the values of fs_xl in reg CTRL1_XL + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6ds3tr_c_xl_full_scale_set(stmdev_ctx_t *ctx, lsm6ds3tr_c_fs_xl_t val) +{ + lsm6ds3tr_c_ctrl1_xl_t ctrl1_xl; + int32_t ret; + + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL1_XL, (uint8_t*)&ctrl1_xl, 1); + if(ret == 0){ + ctrl1_xl.fs_xl = (uint8_t) val; + ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_CTRL1_XL, (uint8_t*)&ctrl1_xl, 1); + } + return ret; +} + +/** + * @brief Accelerometer full-scale selection.[get] + * + * @param ctx Read / write interface definitions + * @param val Get the values of fs_xl in reg CTRL1_XL + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6ds3tr_c_xl_full_scale_get(stmdev_ctx_t *ctx, lsm6ds3tr_c_fs_xl_t *val) +{ + lsm6ds3tr_c_ctrl1_xl_t ctrl1_xl; + int32_t ret; + + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL1_XL, (uint8_t*)&ctrl1_xl, 1); + switch (ctrl1_xl.fs_xl) { + case LSM6DS3TR_C_2g: + *val = LSM6DS3TR_C_2g; + break; + case LSM6DS3TR_C_16g: + *val = LSM6DS3TR_C_16g; + break; + case LSM6DS3TR_C_4g: + *val = LSM6DS3TR_C_4g; + break; + case LSM6DS3TR_C_8g: + *val = LSM6DS3TR_C_8g; + break; + default: + *val = LSM6DS3TR_C_XL_FS_ND; + break; + } + + return ret; +} + +/** + * @brief Accelerometer data rate selection.[set] + * + * @param ctx Read / write interface definitions + * @param val Change the values of odr_xl in reg CTRL1_XL + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6ds3tr_c_xl_data_rate_set(stmdev_ctx_t *ctx, lsm6ds3tr_c_odr_xl_t val) +{ + lsm6ds3tr_c_ctrl1_xl_t ctrl1_xl; + int32_t ret; + + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL1_XL, (uint8_t*)&ctrl1_xl, 1); + if(ret == 0){ + ctrl1_xl.odr_xl = (uint8_t) val; + ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_CTRL1_XL, (uint8_t*)&ctrl1_xl, 1); + } + return ret; +} + +/** + * @brief Accelerometer data rate selection.[get] + * + * @param ctx Read / write interface definitions + * @param val Get the values of odr_xl in reg CTRL1_XL + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6ds3tr_c_xl_data_rate_get(stmdev_ctx_t *ctx, lsm6ds3tr_c_odr_xl_t *val) +{ + lsm6ds3tr_c_ctrl1_xl_t ctrl1_xl; + int32_t ret; + + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL1_XL, (uint8_t*)&ctrl1_xl, 1); + switch (ctrl1_xl.odr_xl) { + case LSM6DS3TR_C_XL_ODR_OFF: + *val = LSM6DS3TR_C_XL_ODR_OFF; + break; + case LSM6DS3TR_C_XL_ODR_12Hz5: + *val = LSM6DS3TR_C_XL_ODR_12Hz5; + break; + case LSM6DS3TR_C_XL_ODR_26Hz: + *val = LSM6DS3TR_C_XL_ODR_26Hz; + break; + case LSM6DS3TR_C_XL_ODR_52Hz: + *val = LSM6DS3TR_C_XL_ODR_52Hz; + break; + case LSM6DS3TR_C_XL_ODR_104Hz: + *val = LSM6DS3TR_C_XL_ODR_104Hz; + break; + case LSM6DS3TR_C_XL_ODR_208Hz: + *val = LSM6DS3TR_C_XL_ODR_208Hz; + break; + case LSM6DS3TR_C_XL_ODR_416Hz: + *val = LSM6DS3TR_C_XL_ODR_416Hz; + break; + case LSM6DS3TR_C_XL_ODR_833Hz: + *val = LSM6DS3TR_C_XL_ODR_833Hz; + break; + case LSM6DS3TR_C_XL_ODR_1k66Hz: + *val = LSM6DS3TR_C_XL_ODR_1k66Hz; + break; + case LSM6DS3TR_C_XL_ODR_3k33Hz: + *val = LSM6DS3TR_C_XL_ODR_3k33Hz; + break; + case LSM6DS3TR_C_XL_ODR_6k66Hz: + *val = LSM6DS3TR_C_XL_ODR_6k66Hz; + break; + case LSM6DS3TR_C_XL_ODR_1Hz6: + *val = LSM6DS3TR_C_XL_ODR_1Hz6; + break; + default: + *val = LSM6DS3TR_C_XL_ODR_ND; + break; + } + + return ret; +} + +/** + * @brief Gyroscope chain full-scale selection.[set] + * + * @param ctx Read / write interface definitions + * @param val Change the values of fs_g in reg CTRL2_G + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6ds3tr_c_gy_full_scale_set(stmdev_ctx_t *ctx, lsm6ds3tr_c_fs_g_t val) +{ + lsm6ds3tr_c_ctrl2_g_t ctrl2_g; + int32_t ret; + + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL2_G, (uint8_t*)&ctrl2_g, 1); + if(ret == 0){ + ctrl2_g.fs_g = (uint8_t) val; + ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_CTRL2_G, (uint8_t*)&ctrl2_g, 1); + } + return ret; +} + +/** + * @brief Gyroscope chain full-scale selection.[get] + * + * @param ctx Read / write interface definitions + * @param val Get the values of fs_g in reg CTRL2_G + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6ds3tr_c_gy_full_scale_get(stmdev_ctx_t *ctx, lsm6ds3tr_c_fs_g_t *val) +{ + lsm6ds3tr_c_ctrl2_g_t ctrl2_g; + int32_t ret; + + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL2_G, (uint8_t*)&ctrl2_g, 1); + switch (ctrl2_g.fs_g) { + case LSM6DS3TR_C_250dps: + *val = LSM6DS3TR_C_250dps; + break; + case LSM6DS3TR_C_125dps: + *val = LSM6DS3TR_C_125dps; + break; + case LSM6DS3TR_C_500dps: + *val = LSM6DS3TR_C_500dps; + break; + case LSM6DS3TR_C_1000dps: + *val = LSM6DS3TR_C_1000dps; + break; + case LSM6DS3TR_C_2000dps: + *val = LSM6DS3TR_C_2000dps; + break; + default: + *val = LSM6DS3TR_C_GY_FS_ND; + break; + } + + return ret; +} + +/** + * @brief Gyroscope data rate selection.[set] + * + * @param ctx Read / write interface definitions + * @param val Change the values of odr_g in reg CTRL2_G + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6ds3tr_c_gy_data_rate_set(stmdev_ctx_t *ctx, lsm6ds3tr_c_odr_g_t val) +{ + lsm6ds3tr_c_ctrl2_g_t ctrl2_g; + int32_t ret; + + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL2_G, (uint8_t*)&ctrl2_g, 1); + if(ret == 0){ + ctrl2_g.odr_g = (uint8_t) val; + ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_CTRL2_G, (uint8_t*)&ctrl2_g, 1); + } + return ret; +} + +/** + * @brief Gyroscope data rate selection.[get] + * + * @param ctx Read / write interface definitions + * @param val Get the values of odr_g in reg CTRL2_G + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6ds3tr_c_gy_data_rate_get(stmdev_ctx_t *ctx, lsm6ds3tr_c_odr_g_t *val) +{ + lsm6ds3tr_c_ctrl2_g_t ctrl2_g; + int32_t ret; + + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL2_G, (uint8_t*)&ctrl2_g, 1); + switch (ctrl2_g.odr_g) { + case LSM6DS3TR_C_GY_ODR_OFF: + *val = LSM6DS3TR_C_GY_ODR_OFF; + break; + case LSM6DS3TR_C_GY_ODR_12Hz5: + *val = LSM6DS3TR_C_GY_ODR_12Hz5; + break; + case LSM6DS3TR_C_GY_ODR_26Hz: + *val = LSM6DS3TR_C_GY_ODR_26Hz; + break; + case LSM6DS3TR_C_GY_ODR_52Hz: + *val = LSM6DS3TR_C_GY_ODR_52Hz; + break; + case LSM6DS3TR_C_GY_ODR_104Hz: + *val = LSM6DS3TR_C_GY_ODR_104Hz; + break; + case LSM6DS3TR_C_GY_ODR_208Hz: + *val = LSM6DS3TR_C_GY_ODR_208Hz; + break; + case LSM6DS3TR_C_GY_ODR_416Hz: + *val = LSM6DS3TR_C_GY_ODR_416Hz; + break; + case LSM6DS3TR_C_GY_ODR_833Hz: + *val = LSM6DS3TR_C_GY_ODR_833Hz; + break; + case LSM6DS3TR_C_GY_ODR_1k66Hz: + *val = LSM6DS3TR_C_GY_ODR_1k66Hz; + break; + case LSM6DS3TR_C_GY_ODR_3k33Hz: + *val = LSM6DS3TR_C_GY_ODR_3k33Hz; + break; + case LSM6DS3TR_C_GY_ODR_6k66Hz: + *val = LSM6DS3TR_C_GY_ODR_6k66Hz; + break; + default: + *val = LSM6DS3TR_C_GY_ODR_ND; + break; + } + + return ret; +} + +/** + * @brief Block data update.[set] + * + * @param ctx Read / write interface definitions + * @param val Change the values of bdu in reg CTRL3_C + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6ds3tr_c_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6ds3tr_c_ctrl3_c_t ctrl3_c; + int32_t ret; + + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL3_C, (uint8_t*)&ctrl3_c, 1); + if(ret == 0){ + ctrl3_c.bdu = val; + ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_CTRL3_C, (uint8_t*)&ctrl3_c, 1); + } + return ret; +} + +/** + * @brief Block data update.[get] + * + * @param ctx Read / write interface definitions + * @param val Change the values of bdu in reg CTRL3_C + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6ds3tr_c_block_data_update_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6ds3tr_c_ctrl3_c_t ctrl3_c; + int32_t ret; + + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL3_C, (uint8_t*)&ctrl3_c, 1); + *val = ctrl3_c.bdu; + + return ret; +} + +/** + * @brief Weight of XL user offset bits of registers + * X_OFS_USR(73h), Y_OFS_USR(74h), Z_OFS_USR(75h).[set] + * + * @param ctx Read / write interface definitions + * @param val Change the values of usr_off_w in reg CTRL6_C + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6ds3tr_c_xl_offset_weight_set(stmdev_ctx_t *ctx, + lsm6ds3tr_c_usr_off_w_t val) +{ + lsm6ds3tr_c_ctrl6_c_t ctrl6_c; + int32_t ret; + + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL6_C, (uint8_t*)&ctrl6_c, 1); + if(ret == 0){ + ctrl6_c.usr_off_w = (uint8_t) val; + ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_CTRL6_C, (uint8_t*)&ctrl6_c, 1); + } + return ret; +} + +/** + * @brief Weight of XL user offset bits of registers + * X_OFS_USR(73h), Y_OFS_USR(74h), Z_OFS_USR(75h).[get] + * + * @param ctx Read / write interface definitions + * @param val Get the values of usr_off_w in reg CTRL6_C + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6ds3tr_c_xl_offset_weight_get(stmdev_ctx_t *ctx, + lsm6ds3tr_c_usr_off_w_t *val) +{ + lsm6ds3tr_c_ctrl6_c_t ctrl6_c; + int32_t ret; + + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL6_C, (uint8_t*)&ctrl6_c, 1); + switch (ctrl6_c.usr_off_w) { + case LSM6DS3TR_C_LSb_1mg: + *val = LSM6DS3TR_C_LSb_1mg; + break; + case LSM6DS3TR_C_LSb_16mg: + *val = LSM6DS3TR_C_LSb_16mg; + break; + default: + *val = LSM6DS3TR_C_WEIGHT_ND; + break; + } + + return ret; +} + +/** + * @brief High-performance operating mode for accelerometer[set] + * + * @param ctx Read / write interface definitions + * @param val Change the values of xl_hm_mode in reg CTRL6_C + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6ds3tr_c_xl_power_mode_set(stmdev_ctx_t *ctx, + lsm6ds3tr_c_xl_hm_mode_t val) +{ + lsm6ds3tr_c_ctrl6_c_t ctrl6_c; + int32_t ret; + + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL6_C, (uint8_t*)&ctrl6_c, 1); + if(ret == 0){ + ctrl6_c.xl_hm_mode = (uint8_t) val; + ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_CTRL6_C, (uint8_t*)&ctrl6_c, 1); + } + return ret; +} + +/** + * @brief High-performance operating mode for accelerometer.[get] + * + * @param ctx Read / write interface definitions + * @param val Get the values of xl_hm_mode in reg CTRL6_C + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6ds3tr_c_xl_power_mode_get(stmdev_ctx_t *ctx, + lsm6ds3tr_c_xl_hm_mode_t *val) +{ + lsm6ds3tr_c_ctrl6_c_t ctrl6_c; + int32_t ret; + + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL6_C, (uint8_t*)&ctrl6_c, 1); + switch (ctrl6_c.xl_hm_mode) { + case LSM6DS3TR_C_XL_HIGH_PERFORMANCE: + *val = LSM6DS3TR_C_XL_HIGH_PERFORMANCE; + break; + case LSM6DS3TR_C_XL_NORMAL: + *val = LSM6DS3TR_C_XL_NORMAL; + break; + default: + *val = LSM6DS3TR_C_XL_PW_MODE_ND; + break; + } + + return ret; +} + +/** + * @brief Source register rounding function on WAKE_UP_SRC (1Bh), + * TAP_SRC (1Ch), D6D_SRC (1Dh), STATUS_REG (1Eh) and + * FUNC_SRC1 (53h) registers in the primary interface.[set] + * + * @param ctx Read / write interface definitions + * @param val Change the values of rounding_status in reg CTRL7_G + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6ds3tr_c_rounding_on_status_set(stmdev_ctx_t *ctx, + lsm6ds3tr_c_rounding_status_t val) +{ + lsm6ds3tr_c_ctrl7_g_t ctrl7_g; + int32_t ret; + + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL7_G, (uint8_t*)&ctrl7_g, 1); + if(ret == 0){ + ctrl7_g.rounding_status = (uint8_t) val; + ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_CTRL7_G, (uint8_t*)&ctrl7_g, 1); + } + return ret; +} + +/** + * @brief Source register rounding function on WAKE_UP_SRC (1Bh), + * TAP_SRC (1Ch), D6D_SRC (1Dh), STATUS_REG (1Eh) and + * FUNC_SRC1 (53h) registers in the primary interface.[get] + * + * @param ctx Read / write interface definitions + * @param val Get the values of rounding_status in reg CTRL7_G + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6ds3tr_c_rounding_on_status_get(stmdev_ctx_t *ctx, + lsm6ds3tr_c_rounding_status_t *val) +{ + lsm6ds3tr_c_ctrl7_g_t ctrl7_g; + int32_t ret; + + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL7_G, (uint8_t*)&ctrl7_g, 1); + switch (ctrl7_g.rounding_status) { + case LSM6DS3TR_C_STAT_RND_DISABLE: + *val = LSM6DS3TR_C_STAT_RND_DISABLE; + break; + case LSM6DS3TR_C_STAT_RND_ENABLE: + *val = LSM6DS3TR_C_STAT_RND_ENABLE; + break; + default: + *val = LSM6DS3TR_C_STAT_RND_ND; + break; + } + + return ret; +} + +/** + * @brief High-performance operating mode disable for gyroscope.[set] + * + * @param ctx Read / write interface definitions + * @param val Change the values of g_hm_mode in reg CTRL7_G + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6ds3tr_c_gy_power_mode_set(stmdev_ctx_t *ctx, lsm6ds3tr_c_g_hm_mode_t val) +{ + lsm6ds3tr_c_ctrl7_g_t ctrl7_g; + int32_t ret; + + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL7_G, (uint8_t*)&ctrl7_g, 1); + if(ret == 0){ + ctrl7_g.g_hm_mode = (uint8_t) val; + ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_CTRL7_G, (uint8_t*)&ctrl7_g, 1); + } + return ret; +} + +/** + * @brief High-performance operating mode disable for gyroscope.[get] + * + * @param ctx Read / write interface definitions + * @param val Get the values of g_hm_mode in reg CTRL7_G + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6ds3tr_c_gy_power_mode_get(stmdev_ctx_t *ctx, lsm6ds3tr_c_g_hm_mode_t *val) +{ + lsm6ds3tr_c_ctrl7_g_t ctrl7_g; + int32_t ret; + + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL7_G, (uint8_t*)&ctrl7_g, 1); + switch (ctrl7_g.g_hm_mode) { + case LSM6DS3TR_C_GY_HIGH_PERFORMANCE: + *val = LSM6DS3TR_C_GY_HIGH_PERFORMANCE; + break; + case LSM6DS3TR_C_GY_NORMAL: + *val = LSM6DS3TR_C_GY_NORMAL; + break; + default: + *val = LSM6DS3TR_C_GY_PW_MODE_ND; + break; + } + + return ret; +} + +/** + * @brief Read all the interrupt/status flag of the device.[get] + * + * @param ctx Read / write interface definitions + * @param val WAKE_UP_SRC, TAP_SRC, D6D_SRC, STATUS_REG, + * FUNC_SRC1, FUNC_SRC2, WRIST_TILT_IA, A_WRIST_TILT_Mask + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6ds3tr_c_all_sources_get(stmdev_ctx_t *ctx, + lsm6ds3tr_c_all_sources_t *val) +{ + int32_t ret; + + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_WAKE_UP_SRC, + (uint8_t*)&(val->wake_up_src), 1); + if(ret == 0){ + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_TAP_SRC, + (uint8_t*)&(val->tap_src), 1); + } + if(ret == 0){ + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_D6D_SRC, + (uint8_t*)&(val->d6d_src), 1); + } + if(ret == 0){ + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_STATUS_REG, + (uint8_t*)&(val->status_reg), 1); + } + if(ret == 0){ + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_FUNC_SRC1, + (uint8_t*)&(val->func_src1), 1); + } + if(ret == 0){ + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_FUNC_SRC2, + (uint8_t*)&(val->func_src2), 1); + } + if(ret == 0){ + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_WRIST_TILT_IA, + (uint8_t*)&(val->wrist_tilt_ia), 1); + } + if(ret == 0){ + ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_BANK_B); + } + if(ret == 0){ + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_A_WRIST_TILT_MASK, + (uint8_t*)&(val->a_wrist_tilt_mask), 1); + } + if(ret == 0){ + ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_USER_BANK); + } + + return ret; +} +/** + * @brief The STATUS_REG register is read by the primary interface[get] + * + * @param ctx Read / write interface definitions + * @param val Registers STATUS_REG + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6ds3tr_c_status_reg_get(stmdev_ctx_t *ctx, lsm6ds3tr_c_status_reg_t *val) +{ + int32_t ret; + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_STATUS_REG, (uint8_t*) val, 1); + return ret; +} + +/** + * @brief Accelerometer new data available.[get] + * + * @param ctx Read / write interface definitions + * @param val Change the values of xlda in reg STATUS_REG + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6ds3tr_c_xl_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6ds3tr_c_status_reg_t status_reg; + int32_t ret; + + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_STATUS_REG, (uint8_t*)&status_reg, 1); + *val = status_reg.xlda; + + return ret; +} + +/** + * @brief Gyroscope new data available.[get] + * + * @param ctx Read / write interface definitions + * @param val Change the values of gda in reg STATUS_REG + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6ds3tr_c_gy_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6ds3tr_c_status_reg_t status_reg; + int32_t ret; + + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_STATUS_REG, (uint8_t*)&status_reg, 1); + *val = status_reg.gda; + + return ret; +} + +/** + * @brief Temperature new data available.[get] + * + * @param ctx Read / write interface definitions + * @param val Change the values of tda in reg STATUS_REG + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6ds3tr_c_temp_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6ds3tr_c_status_reg_t status_reg; + int32_t ret; + + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_STATUS_REG, (uint8_t*)&status_reg, 1); + *val = status_reg.tda; + + return ret; +} + +/** + * @brief Accelerometer axis user offset correction expressed in two’s + * complement, weight depends on USR_OFF_W in CTRL6_C. + * The value must be in the range [-127 127].[set] + * + * @param ctx Read / write interface definitions + * @param buff Buffer that contains data to write + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6ds3tr_c_xl_usr_offset_set(stmdev_ctx_t *ctx, uint8_t *buff) +{ + int32_t ret; + ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_X_OFS_USR, buff, 3); + return ret; +} + +/** + * @brief Accelerometer axis user offset correction xpressed in two’s + * complement, weight depends on USR_OFF_W in CTRL6_C. + * The value must be in the range [-127 127].[get] + * + * @param ctx Read / write interface definitions + * @param buff Buffer that stores data read + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6ds3tr_c_xl_usr_offset_get(stmdev_ctx_t *ctx, uint8_t *buff) +{ + int32_t ret; + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_X_OFS_USR, buff, 3); + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup LSM6DS3TR_C_Timestamp + * @brief This section groups all the functions that manage the + * timestamp generation. + * @{ + * + */ + +/** + * @brief Enable timestamp count. The count is saved in TIMESTAMP0_REG (40h), + * TIMESTAMP1_REG (41h) and TIMESTAMP2_REG (42h).[set] + * + * @param ctx Read / write interface definitions + * @param val Change the values of timer_en in reg CTRL10_C + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6ds3tr_c_timestamp_set(stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6ds3tr_c_ctrl10_c_t ctrl10_c; + int32_t ret; + + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL10_C, (uint8_t*)&ctrl10_c, 1); + if(ret == 0){ + ctrl10_c.timer_en = val; + if ( val != 0x00U) { + ctrl10_c.func_en = val; + ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_CTRL10_C, (uint8_t*)&ctrl10_c, 1); + } + } + return ret; +} + +/** + * @brief Enable timestamp count. The count is saved in TIMESTAMP0_REG (40h), + * TIMESTAMP1_REG (41h) and TIMESTAMP2_REG (42h).[get] + * + * @param ctx Read / write interface definitions + * @param val Change the values of timer_en in reg CTRL10_C + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6ds3tr_c_timestamp_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6ds3tr_c_ctrl10_c_t ctrl10_c; + int32_t ret; + + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL10_C, (uint8_t*)&ctrl10_c, 1); + *val = ctrl10_c.timer_en; + + return ret; +} + +/** + * @brief Timestamp register resolution setting. + * Configuration of this bit affects + * TIMESTAMP0_REG(40h), TIMESTAMP1_REG(41h), + * TIMESTAMP2_REG(42h), STEP_TIMESTAMP_L(49h), + * STEP_TIMESTAMP_H(4Ah) and + * STEP_COUNT_DELTA(15h) registers.[set] + * + * @param ctx Read / write interface definitions + * @param val Change the values of timer_hr in reg WAKE_UP_DUR + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6ds3tr_c_timestamp_res_set(stmdev_ctx_t *ctx, lsm6ds3tr_c_timer_hr_t val) +{ + lsm6ds3tr_c_wake_up_dur_t wake_up_dur; + int32_t ret; + + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_WAKE_UP_DUR, (uint8_t*)&wake_up_dur, 1); + if(ret == 0){ + wake_up_dur.timer_hr = (uint8_t) val; + ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_WAKE_UP_DUR, + (uint8_t*)&wake_up_dur, 1); + } + return ret; +} + +/** + * @brief Timestamp register resolution setting. + * Configuration of this bit affects + * TIMESTAMP0_REG(40h), TIMESTAMP1_REG(41h), + * TIMESTAMP2_REG(42h), STEP_TIMESTAMP_L(49h), + * STEP_TIMESTAMP_H(4Ah) and + * STEP_COUNT_DELTA(15h) registers.[get] + * + * @param ctx Read / write interface definitions + * @param val Get the values of timer_hr in reg WAKE_UP_DUR + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6ds3tr_c_timestamp_res_get(stmdev_ctx_t *ctx, lsm6ds3tr_c_timer_hr_t *val) +{ + lsm6ds3tr_c_wake_up_dur_t wake_up_dur; + int32_t ret; + + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_WAKE_UP_DUR, (uint8_t*)&wake_up_dur, 1); + switch (wake_up_dur.timer_hr) { + case LSM6DS3TR_C_LSB_6ms4: + *val = LSM6DS3TR_C_LSB_6ms4; + break; + case LSM6DS3TR_C_LSB_25us: + *val = LSM6DS3TR_C_LSB_25us; + break; + default: + *val = LSM6DS3TR_C_TS_RES_ND; + break; + } + + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup LSM6DS3TR_C_Dataoutput + * @brief This section groups all the data output functions. + * @{ + * + */ + +/** + * @brief Circular burst-mode (rounding) read from output registers + * through the primary interface.[set] + * + * @param ctx Read / write interface definitions + * @param val Change the values of rounding in reg CTRL5_C + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6ds3tr_c_rounding_mode_set(stmdev_ctx_t *ctx, lsm6ds3tr_c_rounding_t val) +{ + lsm6ds3tr_c_ctrl5_c_t ctrl5_c; + int32_t ret; + + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL5_C, (uint8_t*)&ctrl5_c, 1); + if(ret == 0){ + ctrl5_c.rounding = (uint8_t) val; + ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_CTRL5_C, (uint8_t*)&ctrl5_c, 1); + } + return ret; +} + +/** + * @brief Circular burst-mode (rounding) read from output registers + * through the primary interface.[get] + * + * @param ctx Read / write interface definitions + * @param val Get the values of rounding in reg CTRL5_C + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6ds3tr_c_rounding_mode_get(stmdev_ctx_t *ctx, lsm6ds3tr_c_rounding_t *val) +{ + lsm6ds3tr_c_ctrl5_c_t ctrl5_c; + int32_t ret; + + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL5_C, (uint8_t*)&ctrl5_c, 1); + switch (ctrl5_c.rounding) { + case LSM6DS3TR_C_ROUND_DISABLE: + *val = LSM6DS3TR_C_ROUND_DISABLE; + break; + case LSM6DS3TR_C_ROUND_XL: + *val = LSM6DS3TR_C_ROUND_XL; + break; + case LSM6DS3TR_C_ROUND_GY: + *val = LSM6DS3TR_C_ROUND_GY; + break; + case LSM6DS3TR_C_ROUND_GY_XL: + *val = LSM6DS3TR_C_ROUND_GY_XL; + break; + case LSM6DS3TR_C_ROUND_SH1_TO_SH6: + *val = LSM6DS3TR_C_ROUND_SH1_TO_SH6; + break; + case LSM6DS3TR_C_ROUND_XL_SH1_TO_SH6: + *val = LSM6DS3TR_C_ROUND_XL_SH1_TO_SH6; + break; + case LSM6DS3TR_C_ROUND_GY_XL_SH1_TO_SH12: + *val = LSM6DS3TR_C_ROUND_GY_XL_SH1_TO_SH12; + break; + case LSM6DS3TR_C_ROUND_GY_XL_SH1_TO_SH6: + *val = LSM6DS3TR_C_ROUND_GY_XL_SH1_TO_SH6; + break; + default: + *val = LSM6DS3TR_C_ROUND_OUT_ND; + break; + } + + return ret; +} + +/** + * @brief Temperature data output register (r). L and H registers together + * express a 16-bit word in two’s complement.[get] + * + * @param ctx Read / write interface definitions + * @param buff Buffer that stores data read + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6ds3tr_c_temperature_raw_get(stmdev_ctx_t *ctx, uint8_t *buff) +{ + int32_t ret; + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_OUT_TEMP_L, buff, 2); + return ret; +} + +/** + * @brief Angular rate sensor. The value is expressed as a 16-bit word in + * two’s complement.[get] + * + * @param ctx Read / write interface definitions + * @param buff Buffer that stores data read + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6ds3tr_c_angular_rate_raw_get(stmdev_ctx_t *ctx, uint8_t *buff) +{ + int32_t ret; + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_OUTX_L_G, buff, 6); + return ret; +} + +/** + * @brief Linear acceleration output register. The value is expressed + * as a 16-bit word in two’s complement.[get] + * + * @param ctx Read / write interface definitions + * @param buff Buffer that stores data read + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6ds3tr_c_acceleration_raw_get(stmdev_ctx_t *ctx, uint8_t *buff) +{ + int32_t ret; + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_OUTX_L_XL, buff, 6); + return ret; +} + +/** + * @brief External magnetometer raw data.[get] + * + * @param ctx Read / write interface definitions + * @param buff Buffer that stores data read + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6ds3tr_c_mag_calibrated_raw_get(stmdev_ctx_t *ctx, uint8_t *buff) +{ + int32_t ret; + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_OUT_MAG_RAW_X_L, buff, 6); + return ret; +} + +/** + * @brief Read data in FIFO.[get] + * + * @param ctx Read / write interface definitions + * @param buffer Data buffer to store FIFO data. + * @param len Number of data to read from FIFO. + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6ds3tr_c_fifo_raw_data_get(stmdev_ctx_t *ctx, uint8_t *buffer, + uint8_t len) +{ + int32_t ret; + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_FIFO_DATA_OUT_L, buffer, len); + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup LSM6DS3TR_C_common + * @brief This section groups common usefull functions. + * @{ + * + */ + +/** + * @brief Enable access to the embedded functions/sensor hub + * configuration registers[set] + * + * @param ctx Read / write interface definitions + * @param val Change the values of func_cfg_en in reg FUNC_CFG_ACCESS + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6ds3tr_c_mem_bank_set(stmdev_ctx_t *ctx, lsm6ds3tr_c_func_cfg_en_t val) +{ + lsm6ds3tr_c_func_cfg_access_t func_cfg_access; + int32_t ret; + + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_FUNC_CFG_ACCESS, + (uint8_t*)&func_cfg_access, 1); + if(ret == 0){ + func_cfg_access.func_cfg_en = (uint8_t) val; + ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_FUNC_CFG_ACCESS, + (uint8_t*)&func_cfg_access, 1); + } + + return ret; +} + +/** + * @brief Enable access to the embedded functions/sensor hub configuration + * registers[get] + * + * @param ctx Read / write interface definitions + * @param val Get the values of func_cfg_en in reg FUNC_CFG_ACCESS + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6ds3tr_c_mem_bank_get(stmdev_ctx_t *ctx, lsm6ds3tr_c_func_cfg_en_t *val) +{ + lsm6ds3tr_c_func_cfg_access_t func_cfg_access; + int32_t ret; + + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_FUNC_CFG_ACCESS, + (uint8_t*)&func_cfg_access, 1); + switch (func_cfg_access.func_cfg_en) { + case LSM6DS3TR_C_USER_BANK: + *val = LSM6DS3TR_C_USER_BANK; + break; + case LSM6DS3TR_C_BANK_B: + *val = LSM6DS3TR_C_BANK_B; + break; + default: + *val = LSM6DS3TR_C_BANK_ND; + break; + } + + return ret; +} + +/** + * @brief Data-ready pulsed / letched mode[set] + * + * @param ctx Read / write interface definitions + * @param val Change the values of drdy_pulsed in reg DRDY_PULSE_CFG + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6ds3tr_c_data_ready_mode_set(stmdev_ctx_t *ctx, + lsm6ds3tr_c_drdy_pulsed_g_t val) +{ + lsm6ds3tr_c_drdy_pulse_cfg_g_t drdy_pulse_cfg_g; + int32_t ret; + + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_DRDY_PULSE_CFG_G, + (uint8_t*)&drdy_pulse_cfg_g, 1); + if(ret == 0){ + drdy_pulse_cfg_g.drdy_pulsed = (uint8_t) val; + ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_DRDY_PULSE_CFG_G, + (uint8_t*)&drdy_pulse_cfg_g, 1); + } + return ret; +} + +/** + * @brief Data-ready pulsed / letched mode[get] + * + * @param ctx Read / write interface definitions + * @param val Get the values of drdy_pulsed in reg DRDY_PULSE_CFG + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6ds3tr_c_data_ready_mode_get(stmdev_ctx_t *ctx, + lsm6ds3tr_c_drdy_pulsed_g_t *val) +{ + lsm6ds3tr_c_drdy_pulse_cfg_g_t drdy_pulse_cfg_g; + int32_t ret; + + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_DRDY_PULSE_CFG_G, + (uint8_t*)&drdy_pulse_cfg_g, 1); + switch (drdy_pulse_cfg_g.drdy_pulsed) { + case LSM6DS3TR_C_DRDY_LATCHED: + *val = LSM6DS3TR_C_DRDY_LATCHED; + break; + case LSM6DS3TR_C_DRDY_PULSED: + *val = LSM6DS3TR_C_DRDY_PULSED; + break; + default: + *val = LSM6DS3TR_C_DRDY_ND; + break; + } + + return ret; +} + +/** + * @brief DeviceWhoamI.[get] + * + * @param ctx Read / write interface definitions + * @param buff Buffer that stores data read + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6ds3tr_c_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff) +{ + int32_t ret; + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_WHO_AM_I, buff, 1); + return ret; +} + +/** + * @brief Software reset. Restore the default values in user registers[set] + * + * @param ctx Read / write interface definitions + * @param val Change the values of sw_reset in reg CTRL3_C + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6ds3tr_c_reset_set(stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6ds3tr_c_ctrl3_c_t ctrl3_c; + int32_t ret; + + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL3_C, (uint8_t*)&ctrl3_c, 1); + if(ret == 0){ + ctrl3_c.sw_reset = val; + ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_CTRL3_C, (uint8_t*)&ctrl3_c, 1); + } + return ret; +} + +/** + * @brief Software reset. Restore the default values in user registers[get] + * + * @param ctx Read / write interface definitions + * @param val Change the values of sw_reset in reg CTRL3_C + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6ds3tr_c_reset_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6ds3tr_c_ctrl3_c_t ctrl3_c; + int32_t ret; + + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL3_C, (uint8_t*)&ctrl3_c, 1); + *val = ctrl3_c.sw_reset; + + return ret; +} + +/** + * @brief Big/Little Endian Data selection.[set] + * + * @param ctx Read / write interface definitions + * @param val Change the values of ble in reg CTRL3_C + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6ds3tr_c_data_format_set(stmdev_ctx_t *ctx, lsm6ds3tr_c_ble_t val) +{ + lsm6ds3tr_c_ctrl3_c_t ctrl3_c; + int32_t ret; + + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL3_C, (uint8_t*)&ctrl3_c, 1); + if(ret == 0){ + ctrl3_c.ble = (uint8_t) val; + ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_CTRL3_C, (uint8_t*)&ctrl3_c, 1); + } + return ret; +} + +/** + * @brief Big/Little Endian Data selection.[get] + * + * @param ctx Read / write interface definitions + * @param val Get the values of ble in reg CTRL3_C + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6ds3tr_c_data_format_get(stmdev_ctx_t *ctx, lsm6ds3tr_c_ble_t *val) +{ + lsm6ds3tr_c_ctrl3_c_t ctrl3_c; + int32_t ret; + + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL3_C, (uint8_t*)&ctrl3_c, 1); + switch (ctrl3_c.ble) { + case LSM6DS3TR_C_LSB_AT_LOW_ADD: + *val = LSM6DS3TR_C_LSB_AT_LOW_ADD; + break; + case LSM6DS3TR_C_MSB_AT_LOW_ADD: + *val = LSM6DS3TR_C_MSB_AT_LOW_ADD; + break; + default: + *val = LSM6DS3TR_C_DATA_FMT_ND; + break; + } + + return ret; +} + +/** + * @brief Register address automatically incremented during a multiple byte + * access with a serial interface.[set] + * + * @param ctx Read / write interface definitions + * @param val Change the values of if_inc in reg CTRL3_C + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6ds3tr_c_auto_increment_set(stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6ds3tr_c_ctrl3_c_t ctrl3_c; + int32_t ret; + + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL3_C, (uint8_t*)&ctrl3_c, 1); + if(ret == 0){ + ctrl3_c.if_inc = val; + ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_CTRL3_C, (uint8_t*)&ctrl3_c, 1); + } + return ret; +} + +/** + * @brief Register address automatically incremented during a multiple byte + * access with a serial interface.[get] + * + * @param ctx Read / write interface definitions + * @param val Change the values of if_inc in reg CTRL3_C + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6ds3tr_c_auto_increment_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6ds3tr_c_ctrl3_c_t ctrl3_c; + int32_t ret; + + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL3_C, (uint8_t*)&ctrl3_c, 1); + *val = ctrl3_c.if_inc; + + return ret; +} + +/** + * @brief Reboot memory content. Reload the calibration parameters.[set] + * + * @param ctx Read / write interface definitions + * @param val Change the values of boot in reg CTRL3_C + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6ds3tr_c_boot_set(stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6ds3tr_c_ctrl3_c_t ctrl3_c; + int32_t ret; + + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL3_C, (uint8_t*)&ctrl3_c, 1); + if(ret == 0){ + ctrl3_c.boot = val; + ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_CTRL3_C, (uint8_t*)&ctrl3_c, 1); + } + return ret; +} + +/** + * @brief Reboot memory content. Reload the calibration parameters.[get] + * + * @param ctx Read / write interface definitions + * @param val Change the values of boot in reg CTRL3_C + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6ds3tr_c_boot_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6ds3tr_c_ctrl3_c_t ctrl3_c; + int32_t ret; + + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL3_C, (uint8_t*)&ctrl3_c, 1); + *val = ctrl3_c.boot; + + return ret; +} + +/** + * @brief Linear acceleration sensor self-test enable.[set] + * + * @param ctx Read / write interface definitions + * @param val Change the values of st_xl in reg CTRL5_C + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6ds3tr_c_xl_self_test_set(stmdev_ctx_t *ctx, lsm6ds3tr_c_st_xl_t val) +{ + lsm6ds3tr_c_ctrl5_c_t ctrl5_c; + int32_t ret; + + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL5_C, (uint8_t*)&ctrl5_c, 1); + if(ret == 0){ + ctrl5_c.st_xl = (uint8_t) val; + ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_CTRL5_C, (uint8_t*)&ctrl5_c, 1); + } + return ret; +} + +/** + * @brief Linear acceleration sensor self-test enable.[get] + * + * @param ctx Read / write interface definitions + * @param val Get the values of st_xl in reg CTRL5_C + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6ds3tr_c_xl_self_test_get(stmdev_ctx_t *ctx, lsm6ds3tr_c_st_xl_t *val) +{ + lsm6ds3tr_c_ctrl5_c_t ctrl5_c; + int32_t ret; + + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL5_C, (uint8_t*)&ctrl5_c, 1); + switch (ctrl5_c.st_xl) { + case LSM6DS3TR_C_XL_ST_DISABLE: + *val = LSM6DS3TR_C_XL_ST_DISABLE; + break; + case LSM6DS3TR_C_XL_ST_POSITIVE: + *val = LSM6DS3TR_C_XL_ST_POSITIVE; + break; + case LSM6DS3TR_C_XL_ST_NEGATIVE: + *val = LSM6DS3TR_C_XL_ST_NEGATIVE; + break; + default: + *val = LSM6DS3TR_C_XL_ST_ND; + break; + } + return ret; +} + +/** + * @brief Angular rate sensor self-test enable.[set] + * + * @param ctx Read / write interface definitions + * @param val Change the values of st_g in reg CTRL5_C + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6ds3tr_c_gy_self_test_set(stmdev_ctx_t *ctx, lsm6ds3tr_c_st_g_t val) +{ + lsm6ds3tr_c_ctrl5_c_t ctrl5_c; + int32_t ret; + + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL5_C, (uint8_t*)&ctrl5_c, 1); + if(ret == 0){ + ctrl5_c.st_g = (uint8_t) val; + ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_CTRL5_C, (uint8_t*)&ctrl5_c, 1); + } + return ret; +} + +/** + * @brief Angular rate sensor self-test enable.[get] + * + * @param ctx Read / write interface definitions + * @param val Get the values of st_g in reg CTRL5_C + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6ds3tr_c_gy_self_test_get(stmdev_ctx_t *ctx, lsm6ds3tr_c_st_g_t *val) +{ + lsm6ds3tr_c_ctrl5_c_t ctrl5_c; + int32_t ret; + + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL5_C, (uint8_t*)&ctrl5_c, 1); + switch (ctrl5_c.st_g) { + case LSM6DS3TR_C_GY_ST_DISABLE: + *val = LSM6DS3TR_C_GY_ST_DISABLE; + break; + case LSM6DS3TR_C_GY_ST_POSITIVE: + *val = LSM6DS3TR_C_GY_ST_POSITIVE; + break; + case LSM6DS3TR_C_GY_ST_NEGATIVE: + *val = LSM6DS3TR_C_GY_ST_NEGATIVE; + break; + default: + *val = LSM6DS3TR_C_GY_ST_ND; + break; + } + + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup LSM6DS3TR_C_filters + * @brief This section group all the functions concerning the filters + * configuration that impact both accelerometer and gyro. + * @{ + * + */ + +/** + * @brief Mask DRDY on pin (both XL & Gyro) until filter settling ends + * (XL and Gyro independently masked).[set] + * + * @param ctx Read / write interface definitions + * @param val Change the values of drdy_mask in reg CTRL4_C + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6ds3tr_c_filter_settling_mask_set(stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6ds3tr_c_ctrl4_c_t ctrl4_c; + int32_t ret; + + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL4_C, (uint8_t*)&ctrl4_c, 1); + if(ret == 0){ + ctrl4_c.drdy_mask = val; + ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_CTRL4_C, (uint8_t*)&ctrl4_c, 1); + } + return ret; +} + +/** + * @brief Mask DRDY on pin (both XL & Gyro) until filter settling ends + * (XL and Gyro independently masked).[get] + * + * @param ctx Read / write interface definitions + * @param val Change the values of drdy_mask in reg CTRL4_C + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6ds3tr_c_filter_settling_mask_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6ds3tr_c_ctrl4_c_t ctrl4_c; + int32_t ret; + + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL4_C, (uint8_t*)&ctrl4_c, 1); + *val = ctrl4_c.drdy_mask; + + return ret; +} + +/** + * @brief HPF or SLOPE filter selection on wake-up and Activity/Inactivity + * functions.[set] + * + * @param ctx Read / write interface definitions + * @param val Change the values of slope_fds in reg TAP_CFG + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6ds3tr_c_xl_hp_path_internal_set(stmdev_ctx_t *ctx, + lsm6ds3tr_c_slope_fds_t val) +{ + lsm6ds3tr_c_tap_cfg_t tap_cfg; + int32_t ret; + + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_TAP_CFG, (uint8_t*)&tap_cfg, 1); + if(ret == 0){ + tap_cfg.slope_fds = (uint8_t) val; + ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_TAP_CFG, (uint8_t*)&tap_cfg, 1); + } + return ret; +} + +/** + * @brief HPF or SLOPE filter selection on wake-up and Activity/Inactivity + * functions.[get] + * + * @param ctx Read / write interface definitions + * @param val Get the values of slope_fds in reg TAP_CFG + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6ds3tr_c_xl_hp_path_internal_get(stmdev_ctx_t *ctx, + lsm6ds3tr_c_slope_fds_t *val) +{ + lsm6ds3tr_c_tap_cfg_t tap_cfg; + int32_t ret; + + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_TAP_CFG, (uint8_t*)&tap_cfg, 1); + switch (tap_cfg.slope_fds) { + case LSM6DS3TR_C_USE_SLOPE: + *val = LSM6DS3TR_C_USE_SLOPE; + break; + case LSM6DS3TR_C_USE_HPF: + *val = LSM6DS3TR_C_USE_HPF; + break; + default: + *val = LSM6DS3TR_C_HP_PATH_ND; + break; + } + + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup LSM6DS3TR_C_accelerometer_filters + * @brief This section group all the functions concerning the filters + * configuration that impact accelerometer in every mode. + * @{ + * + */ + +/** + * @brief Accelerometer analog chain bandwidth selection (only for + * accelerometer ODR ≥ 1.67 kHz).[set] + * + * @param ctx Read / write interface definitions + * @param val Change the values of bw0_xl in reg CTRL1_XL + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6ds3tr_c_xl_filter_analog_set(stmdev_ctx_t *ctx, lsm6ds3tr_c_bw0_xl_t val) +{ + lsm6ds3tr_c_ctrl1_xl_t ctrl1_xl; + int32_t ret; + + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL1_XL, (uint8_t*)&ctrl1_xl, 1); + if(ret == 0){ + ctrl1_xl.bw0_xl = (uint8_t) val; + ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_CTRL1_XL, (uint8_t*)&ctrl1_xl, 1); + } + return ret; +} + +/** + * @brief Accelerometer analog chain bandwidth selection (only for + * accelerometer ODR ≥ 1.67 kHz).[get] + * + * @param ctx Read / write interface definitions + * @param val Get the values of bw0_xl in reg CTRL1_XL + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6ds3tr_c_xl_filter_analog_get(stmdev_ctx_t *ctx, + lsm6ds3tr_c_bw0_xl_t *val) +{ + lsm6ds3tr_c_ctrl1_xl_t ctrl1_xl; + int32_t ret; + + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL1_XL, (uint8_t*)&ctrl1_xl, 1); + switch (ctrl1_xl.bw0_xl) { + case LSM6DS3TR_C_XL_ANA_BW_1k5Hz: + *val = LSM6DS3TR_C_XL_ANA_BW_1k5Hz; + break; + case LSM6DS3TR_C_XL_ANA_BW_400Hz: + *val = LSM6DS3TR_C_XL_ANA_BW_400Hz; + break; + default: + *val = LSM6DS3TR_C_XL_ANA_BW_ND; + break; + } + + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup LSM6DS3TR_C_accelerometer_filters + * @brief This section group all the functions concerning the filters + * configuration that impact accelerometer. + * @{ + * + */ + +/** + * @brief Accelerometer digital LPF (LPF1) bandwidth selection LPF2 is + * not used.[set] + * + * @param ctx Read / write interface definitions + * @param val Change the values of lpf1_bw_sel in reg CTRL1_XL + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6ds3tr_c_xl_lp1_bandwidth_set(stmdev_ctx_t *ctx, + lsm6ds3tr_c_lpf1_bw_sel_t val) +{ + lsm6ds3tr_c_ctrl1_xl_t ctrl1_xl; + lsm6ds3tr_c_ctrl8_xl_t ctrl8_xl; + int32_t ret; + + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL1_XL, (uint8_t*)&ctrl1_xl, 1); + if(ret == 0){ + ctrl1_xl.lpf1_bw_sel = (uint8_t) val; + ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_CTRL1_XL, (uint8_t*)&ctrl1_xl, 1); + if(ret == 0){ + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL8_XL, (uint8_t*)&ctrl8_xl, 1); + if(ret == 0){ + ctrl8_xl.lpf2_xl_en = 0; + ctrl8_xl.hp_slope_xl_en = 0; + ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_CTRL8_XL, (uint8_t*)&ctrl8_xl, 1); + } + } + } + return ret; +} + +/** + * @brief Accelerometer digital LPF (LPF1) bandwidth selection LPF2 + * is not used.[get] + * + * @param ctx Read / write interface definitions + * @param val Get the values of lpf1_bw_sel in reg CTRL1_XL + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6ds3tr_c_xl_lp1_bandwidth_get(stmdev_ctx_t *ctx, + lsm6ds3tr_c_lpf1_bw_sel_t *val) +{ + lsm6ds3tr_c_ctrl1_xl_t ctrl1_xl; + lsm6ds3tr_c_ctrl8_xl_t ctrl8_xl; + int32_t ret; + + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL8_XL, (uint8_t*)&ctrl8_xl, 1); + if(ret == 0){ + if ((ctrl8_xl.lpf2_xl_en != 0x00U) || + (ctrl8_xl.hp_slope_xl_en != 0x00U)){ + *val = LSM6DS3TR_C_XL_LP1_NA; + } + else{ + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL1_XL, (uint8_t*)&ctrl1_xl, 1); + switch ( ctrl1_xl.lpf1_bw_sel) { + case LSM6DS3TR_C_XL_LP1_ODR_DIV_2: + *val = LSM6DS3TR_C_XL_LP1_ODR_DIV_2; + break; + case LSM6DS3TR_C_XL_LP1_ODR_DIV_4: + *val = LSM6DS3TR_C_XL_LP1_ODR_DIV_4; + break; + default: + *val = LSM6DS3TR_C_XL_LP1_NA; + break; + } + } + } + return ret; +} + +/** + * @brief LPF2 on outputs[set] + * + * @param ctx Read / write interface definitions + * @param val Change the values of input_composite in reg CTRL8_XL + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6ds3tr_c_xl_lp2_bandwidth_set(stmdev_ctx_t *ctx, + lsm6ds3tr_c_input_composite_t val) +{ + lsm6ds3tr_c_ctrl8_xl_t ctrl8_xl; + int32_t ret; + + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL8_XL, (uint8_t*)&ctrl8_xl, 1); + if(ret == 0){ + ctrl8_xl.input_composite = ( (uint8_t) val & 0x10U ) >> 4; + ctrl8_xl.hpcf_xl = (uint8_t) val & 0x03U; + ctrl8_xl.lpf2_xl_en = 1; + ctrl8_xl.hp_slope_xl_en = 0; + ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_CTRL8_XL, (uint8_t*)&ctrl8_xl, 1); + } + return ret; +} + +/** + * @brief LPF2 on outputs[get] + * + * @param ctx Read / write interface definitions + * @param val Get the values of input_composite in reg CTRL8_XL + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6ds3tr_c_xl_lp2_bandwidth_get(stmdev_ctx_t *ctx, + lsm6ds3tr_c_input_composite_t *val) +{ + lsm6ds3tr_c_ctrl8_xl_t ctrl8_xl; + int32_t ret; + + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL8_XL, (uint8_t*)&ctrl8_xl, 1); + if(ret == 0){ + if ((ctrl8_xl.lpf2_xl_en == 0x00U) || + (ctrl8_xl.hp_slope_xl_en != 0x00U)){ + *val = LSM6DS3TR_C_XL_LP_NA; + } + else{ + switch ((ctrl8_xl.input_composite << 4) + ctrl8_xl.hpcf_xl) { + case LSM6DS3TR_C_XL_LOW_LAT_LP_ODR_DIV_50: + *val = LSM6DS3TR_C_XL_LOW_LAT_LP_ODR_DIV_50; + break; + case LSM6DS3TR_C_XL_LOW_LAT_LP_ODR_DIV_100: + *val = LSM6DS3TR_C_XL_LOW_LAT_LP_ODR_DIV_100; + break; + case LSM6DS3TR_C_XL_LOW_LAT_LP_ODR_DIV_9: + *val = LSM6DS3TR_C_XL_LOW_LAT_LP_ODR_DIV_9; + break; + case LSM6DS3TR_C_XL_LOW_LAT_LP_ODR_DIV_400: + *val = LSM6DS3TR_C_XL_LOW_LAT_LP_ODR_DIV_400; + break; + case LSM6DS3TR_C_XL_LOW_NOISE_LP_ODR_DIV_50: + *val = LSM6DS3TR_C_XL_LOW_NOISE_LP_ODR_DIV_50; + break; + case LSM6DS3TR_C_XL_LOW_NOISE_LP_ODR_DIV_100: + *val = LSM6DS3TR_C_XL_LOW_NOISE_LP_ODR_DIV_100; + break; + case LSM6DS3TR_C_XL_LOW_NOISE_LP_ODR_DIV_9: + *val = LSM6DS3TR_C_XL_LOW_NOISE_LP_ODR_DIV_9; + break; + case LSM6DS3TR_C_XL_LOW_NOISE_LP_ODR_DIV_400: + *val = LSM6DS3TR_C_XL_LOW_NOISE_LP_ODR_DIV_400; + break; + default: + *val = LSM6DS3TR_C_XL_LP_NA; + break; + } + } + } + + return ret; +} + +/** + * @brief Enable HP filter reference mode.[set] + * + * @param ctx Read / write interface definitions + * @param val Change the values of hp_ref_mode in reg CTRL8_XL + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6ds3tr_c_xl_reference_mode_set(stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6ds3tr_c_ctrl8_xl_t ctrl8_xl; + int32_t ret; + + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL8_XL, (uint8_t*)&ctrl8_xl, 1); + if(ret == 0){ + ctrl8_xl.hp_ref_mode = val; + ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_CTRL8_XL, (uint8_t*)&ctrl8_xl, 1); + } + return ret; +} + +/** + * @brief Enable HP filter reference mode.[get] + * + * @param ctx Read / write interface definitions + * @param val Change the values of hp_ref_mode in reg CTRL8_XL + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6ds3tr_c_xl_reference_mode_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6ds3tr_c_ctrl8_xl_t ctrl8_xl; + int32_t ret; + + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL8_XL, (uint8_t*)&ctrl8_xl, 1); + *val = ctrl8_xl.hp_ref_mode; + + return ret; +} + +/** + * @brief High pass/Slope on outputs.[set] + * + * @param ctx Read / write interface definitions + * @param val Change the values of hpcf_xl in reg CTRL8_XL + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6ds3tr_c_xl_hp_bandwidth_set(stmdev_ctx_t *ctx, lsm6ds3tr_c_hpcf_xl_t val) +{ + lsm6ds3tr_c_ctrl8_xl_t ctrl8_xl; + int32_t ret; + + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL8_XL, (uint8_t*)&ctrl8_xl, 1); + if(ret == 0){ + ctrl8_xl.input_composite = 0; + ctrl8_xl.hpcf_xl = (uint8_t)val & 0x03U; + ctrl8_xl.hp_slope_xl_en = 1; + ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_CTRL8_XL, (uint8_t*)&ctrl8_xl, 1); + } + return ret; +} + +/** + * @brief High pass/Slope on outputs.[get] + * + * @param ctx Read / write interface definitions + * @param val Get the values of hpcf_xl in reg CTRL8_XL + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6ds3tr_c_xl_hp_bandwidth_get(stmdev_ctx_t *ctx, lsm6ds3tr_c_hpcf_xl_t *val) +{ + lsm6ds3tr_c_ctrl8_xl_t ctrl8_xl; + int32_t ret; + + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL8_XL, (uint8_t*)&ctrl8_xl, 1); + if (ctrl8_xl.hp_slope_xl_en == 0x00U){ + *val = LSM6DS3TR_C_XL_HP_NA; + } + switch (ctrl8_xl.hpcf_xl) { + case LSM6DS3TR_C_XL_HP_ODR_DIV_4: + *val = LSM6DS3TR_C_XL_HP_ODR_DIV_4; + break; + case LSM6DS3TR_C_XL_HP_ODR_DIV_100: + *val = LSM6DS3TR_C_XL_HP_ODR_DIV_100; + break; + case LSM6DS3TR_C_XL_HP_ODR_DIV_9: + *val = LSM6DS3TR_C_XL_HP_ODR_DIV_9; + break; + case LSM6DS3TR_C_XL_HP_ODR_DIV_400: + *val = LSM6DS3TR_C_XL_HP_ODR_DIV_400; + break; + default: + *val = LSM6DS3TR_C_XL_HP_NA; + break; + } + + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup LSM6DS3TR_C_gyroscope_filters + * @brief This section group all the functions concerning the filters + * configuration that impact gyroscope. + * @{ + * + */ + +/** + * @brief Gyroscope low pass path bandwidth.[set] + * + * @param ctx Read / write interface definitions + * @param val gyroscope filtering chain configuration. + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6ds3tr_c_gy_band_pass_set(stmdev_ctx_t *ctx, lsm6ds3tr_c_lpf1_sel_g_t val) +{ + lsm6ds3tr_c_ctrl4_c_t ctrl4_c; + lsm6ds3tr_c_ctrl6_c_t ctrl6_c; + lsm6ds3tr_c_ctrl7_g_t ctrl7_g; + int32_t ret; + + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL7_G, (uint8_t*)&ctrl7_g, 1); + if(ret == 0){ + ctrl7_g.hpm_g = ( (uint8_t)val & 0x30U ) >> 4; + ctrl7_g.hp_en_g = ( (uint8_t)val & 0x80U ) >> 7; + ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_CTRL7_G, (uint8_t*)&ctrl7_g, 1); + if(ret == 0){ + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL6_C, (uint8_t*)&ctrl6_c, 1); + if(ret == 0){ + ctrl6_c.ftype = (uint8_t)val & 0x03U; + ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_CTRL6_C, (uint8_t*)&ctrl6_c, 1); + if(ret == 0){ + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL4_C, + (uint8_t*)&ctrl4_c, 1); + if(ret == 0){ + ctrl4_c.lpf1_sel_g = ( (uint8_t)val & 0x08U ) >> 3; + ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_CTRL4_C, + (uint8_t*)&ctrl4_c, 1); + } + } + } + } + } + return ret; +} + +/** + * @brief Gyroscope low pass path bandwidth.[get] + * + * @param ctx Read / write interface definitions + * @param val gyroscope filtering chain + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6ds3tr_c_gy_band_pass_get(stmdev_ctx_t *ctx, lsm6ds3tr_c_lpf1_sel_g_t *val) +{ + lsm6ds3tr_c_ctrl4_c_t ctrl4_c; + lsm6ds3tr_c_ctrl6_c_t ctrl6_c; + lsm6ds3tr_c_ctrl7_g_t ctrl7_g; + int32_t ret; + + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL6_C, (uint8_t*)&ctrl6_c, 1); + if(ret == 0){ + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL4_C, (uint8_t*)&ctrl4_c, 1); + if(ret == 0){ + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL7_G, (uint8_t*)&ctrl7_g, 1); + + switch ( ( ctrl7_g.hp_en_g << 7 ) + ( ctrl7_g.hpm_g << 4 ) + + ( ctrl4_c.lpf1_sel_g << 3) + ctrl6_c.ftype ) { + case LSM6DS3TR_C_HP_16mHz_LP2: + *val = LSM6DS3TR_C_HP_16mHz_LP2; + break; + case LSM6DS3TR_C_HP_65mHz_LP2: + *val = LSM6DS3TR_C_HP_65mHz_LP2; + break; + case LSM6DS3TR_C_HP_260mHz_LP2: + *val = LSM6DS3TR_C_HP_260mHz_LP2; + break; + case LSM6DS3TR_C_HP_1Hz04_LP2: + *val = LSM6DS3TR_C_HP_1Hz04_LP2; + break; + case LSM6DS3TR_C_HP_DISABLE_LP1_LIGHT: + *val = LSM6DS3TR_C_HP_DISABLE_LP1_LIGHT; + break; + case LSM6DS3TR_C_HP_DISABLE_LP1_NORMAL: + *val = LSM6DS3TR_C_HP_DISABLE_LP1_NORMAL; + break; + case LSM6DS3TR_C_HP_DISABLE_LP_STRONG: + *val = LSM6DS3TR_C_HP_DISABLE_LP_STRONG; + break; + case LSM6DS3TR_C_HP_DISABLE_LP1_AGGRESSIVE: + *val = LSM6DS3TR_C_HP_DISABLE_LP1_AGGRESSIVE; + break; + case LSM6DS3TR_C_HP_16mHz_LP1_LIGHT: + *val = LSM6DS3TR_C_HP_16mHz_LP1_LIGHT; + break; + case LSM6DS3TR_C_HP_65mHz_LP1_NORMAL: + *val = LSM6DS3TR_C_HP_65mHz_LP1_NORMAL; + break; + case LSM6DS3TR_C_HP_260mHz_LP1_STRONG: + *val = LSM6DS3TR_C_HP_260mHz_LP1_STRONG; + break; + case LSM6DS3TR_C_HP_1Hz04_LP1_AGGRESSIVE: + *val = LSM6DS3TR_C_HP_1Hz04_LP1_AGGRESSIVE; + break; + default: + *val = LSM6DS3TR_C_HP_GY_BAND_NA; + break; + } + } + } + + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup LSM6DS3TR_C_serial_interface + * @brief This section groups all the functions concerning serial + * interface management + * @{ + * + */ + +/** + * @brief SPI Serial Interface Mode selection.[set] + * + * @param ctx Read / write interface definitions + * @param val Change the values of sim in reg CTRL3_C + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6ds3tr_c_spi_mode_set(stmdev_ctx_t *ctx, lsm6ds3tr_c_sim_t val) +{ + lsm6ds3tr_c_ctrl3_c_t ctrl3_c; + int32_t ret; + + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL3_C, (uint8_t*)&ctrl3_c, 1); + if(ret == 0){ + ctrl3_c.sim = (uint8_t) val; + ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_CTRL3_C, (uint8_t*)&ctrl3_c, 1); + } + return ret; +} + +/** + * @brief SPI Serial Interface Mode selection.[get] + * + * @param ctx Read / write interface definitions + * @param val Get the values of sim in reg CTRL3_C + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6ds3tr_c_spi_mode_get(stmdev_ctx_t *ctx, lsm6ds3tr_c_sim_t *val) +{ + lsm6ds3tr_c_ctrl3_c_t ctrl3_c; + int32_t ret; + + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL3_C, (uint8_t*)&ctrl3_c, 1); + switch (ctrl3_c.sim) { + case LSM6DS3TR_C_SPI_4_WIRE: + *val = LSM6DS3TR_C_SPI_4_WIRE; + break; + case LSM6DS3TR_C_SPI_3_WIRE: + *val = LSM6DS3TR_C_SPI_3_WIRE; + break; + default: + *val = LSM6DS3TR_C_SPI_MODE_ND; + break; + } + return ret; +} + +/** + * @brief Disable / Enable I2C interface.[set] + * + * @param ctx Read / write interface definitions + * @param val Change the values of i2c_disable in reg CTRL4_C + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6ds3tr_c_i2c_interface_set(stmdev_ctx_t *ctx, + lsm6ds3tr_c_i2c_disable_t val) +{ + lsm6ds3tr_c_ctrl4_c_t ctrl4_c; + int32_t ret; + + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL4_C, (uint8_t*)&ctrl4_c, 1); + if(ret == 0){ + ctrl4_c.i2c_disable = (uint8_t)val; + ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_CTRL4_C, (uint8_t*)&ctrl4_c, 1); + } + return ret; +} + +/** + * @brief Disable / Enable I2C interface.[get] + * + * @param ctx Read / write interface definitions + * @param val Get the values of i2c_disable in reg CTRL4_C + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6ds3tr_c_i2c_interface_get(stmdev_ctx_t *ctx, + lsm6ds3tr_c_i2c_disable_t *val) +{ + lsm6ds3tr_c_ctrl4_c_t ctrl4_c; + int32_t ret; + + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL4_C, (uint8_t*)&ctrl4_c, 1); + switch (ctrl4_c.i2c_disable) { + case LSM6DS3TR_C_I2C_ENABLE: + *val = LSM6DS3TR_C_I2C_ENABLE; + break; + case LSM6DS3TR_C_I2C_DISABLE: + *val = LSM6DS3TR_C_I2C_DISABLE; + break; + default: + *val = LSM6DS3TR_C_I2C_MODE_ND; + break; + } + + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup LSM6DS3TR_C_interrupt_pins + * @brief This section groups all the functions that manage + * interrup pins + * @{ + * + */ + +/** + * @brief Select the signal that need to route on int1 pad[set] + * + * @param ctx Read / write interface definitions + * @param val configure INT1_CTRL, MD1_CFG, CTRL4_C(den_drdy_int1), + * MASTER_CONFIG(drdy_on_int1) + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6ds3tr_c_pin_int1_route_set(stmdev_ctx_t *ctx, + lsm6ds3tr_c_int1_route_t val) +{ + lsm6ds3tr_c_master_config_t master_config; + lsm6ds3tr_c_int1_ctrl_t int1_ctrl; + lsm6ds3tr_c_md1_cfg_t md1_cfg; + lsm6ds3tr_c_md2_cfg_t md2_cfg; + lsm6ds3tr_c_ctrl4_c_t ctrl4_c; + lsm6ds3tr_c_tap_cfg_t tap_cfg; + int32_t ret; + + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_INT1_CTRL, (uint8_t*)&int1_ctrl, 1); + if(ret == 0){ + int1_ctrl.int1_drdy_xl = val.int1_drdy_xl; + int1_ctrl.int1_drdy_g = val.int1_drdy_g; + int1_ctrl.int1_boot = val.int1_boot; + int1_ctrl.int1_fth = val.int1_fth; + int1_ctrl.int1_fifo_ovr = val.int1_fifo_ovr; + int1_ctrl.int1_full_flag = val.int1_full_flag; + int1_ctrl.int1_sign_mot = val.int1_sign_mot; + int1_ctrl.int1_step_detector = val.int1_step_detector; + ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_INT1_CTRL, (uint8_t*)&int1_ctrl, 1); + } + if(ret == 0){ + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_MD1_CFG, (uint8_t*)&md1_cfg, 1); + } + if(ret == 0){ + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_MD2_CFG, (uint8_t*)&md2_cfg, 1); + } + if(ret == 0){ + md1_cfg.int1_timer = val.int1_timer; + md1_cfg.int1_tilt = val.int1_tilt; + md1_cfg.int1_6d = val.int1_6d; + md1_cfg.int1_double_tap = val.int1_double_tap; + md1_cfg.int1_ff = val.int1_ff; + md1_cfg.int1_wu = val.int1_wu; + md1_cfg.int1_single_tap = val.int1_single_tap; + md1_cfg.int1_inact_state = val.int1_inact_state; + ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_MD1_CFG, (uint8_t*)&md1_cfg, 1); + } + if(ret == 0){ + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL4_C, (uint8_t*)&ctrl4_c, 1); + } + if(ret == 0){ + ctrl4_c.den_drdy_int1 = val.den_drdy_int1; + ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_CTRL4_C, (uint8_t*)&ctrl4_c, 1); + } + if(ret == 0){ + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_MASTER_CONFIG, + (uint8_t*)&master_config, 1); + } + if(ret == 0){ + master_config.drdy_on_int1 = val.den_drdy_int1; + ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_MASTER_CONFIG, + (uint8_t*)&master_config, 1); + } + if(ret == 0){ + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_TAP_CFG, (uint8_t*)&tap_cfg, 1); + if ((val.int1_6d != 0x00U) || + (val.int1_ff != 0x00U) || + (val.int1_wu != 0x00U) || + (val.int1_single_tap != 0x00U) || + (val.int1_double_tap != 0x00U) || + (val.int1_inact_state != 0x00U)|| + (md2_cfg.int2_6d != 0x00U) || + (md2_cfg.int2_ff != 0x00U) || + (md2_cfg.int2_wu != 0x00U) || + (md2_cfg.int2_single_tap != 0x00U) || + (md2_cfg.int2_double_tap != 0x00U) || + (md2_cfg.int2_inact_state!= 0x00U) ){ + tap_cfg.interrupts_enable = PROPERTY_ENABLE; + } + else{ + tap_cfg.interrupts_enable = PROPERTY_DISABLE; + } + } + if(ret == 0){ + ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_TAP_CFG, (uint8_t*)&tap_cfg, 1); + } + return ret; +} + +/** + * @brief Select the signal that need to route on int1 pad[get] + * + * @param ctx Read / write interface definitions + * @param val read INT1_CTRL, MD1_CFG, CTRL4_C(den_drdy_int1), + * MASTER_CONFIG(drdy_on_int1) + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6ds3tr_c_pin_int1_route_get(stmdev_ctx_t *ctx, + lsm6ds3tr_c_int1_route_t *val) +{ + lsm6ds3tr_c_master_config_t master_config; + lsm6ds3tr_c_int1_ctrl_t int1_ctrl; + lsm6ds3tr_c_md1_cfg_t md1_cfg; + lsm6ds3tr_c_ctrl4_c_t ctrl4_c; + + int32_t ret; + + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_INT1_CTRL, (uint8_t*)&int1_ctrl, 1); + if(ret == 0){ + val->int1_drdy_xl = int1_ctrl.int1_drdy_xl; + val->int1_drdy_g = int1_ctrl.int1_drdy_g; + val->int1_boot = int1_ctrl.int1_boot; + val->int1_fth = int1_ctrl.int1_fth; + val->int1_fifo_ovr = int1_ctrl.int1_fifo_ovr; + val->int1_full_flag = int1_ctrl.int1_full_flag; + val->int1_sign_mot = int1_ctrl.int1_sign_mot; + val->int1_step_detector = int1_ctrl.int1_step_detector ; + + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_MD1_CFG, (uint8_t*)&md1_cfg, 1); + if(ret == 0){ + val->int1_timer = md1_cfg.int1_timer; + val->int1_tilt = md1_cfg.int1_tilt; + val->int1_6d = md1_cfg.int1_6d; + val->int1_double_tap = md1_cfg.int1_double_tap; + val->int1_ff = md1_cfg.int1_ff; + val->int1_wu = md1_cfg.int1_wu; + val->int1_single_tap = md1_cfg.int1_single_tap; + val->int1_inact_state = md1_cfg.int1_inact_state; + + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL4_C, (uint8_t*)&ctrl4_c, 1); + if(ret == 0){ + val->den_drdy_int1 = ctrl4_c.den_drdy_int1; + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_MASTER_CONFIG, + (uint8_t*)&master_config, 1); + val->den_drdy_int1 = master_config.drdy_on_int1; + } + } + } + return ret; +} + +/** + * @brief Select the signal that need to route on int2 pad[set] + * + * @param ctx Read / write interface definitions + * @param val INT2_CTRL, DRDY_PULSE_CFG(int2_wrist_tilt), MD2_CFG + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6ds3tr_c_pin_int2_route_set(stmdev_ctx_t *ctx, + lsm6ds3tr_c_int2_route_t val) +{ + lsm6ds3tr_c_int2_ctrl_t int2_ctrl; + lsm6ds3tr_c_md1_cfg_t md1_cfg; + lsm6ds3tr_c_md2_cfg_t md2_cfg; + lsm6ds3tr_c_drdy_pulse_cfg_g_t drdy_pulse_cfg_g; + lsm6ds3tr_c_tap_cfg_t tap_cfg; + int32_t ret; + + + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_INT2_CTRL, (uint8_t*)&int2_ctrl, 1); + if(ret == 0){ + int2_ctrl.int2_drdy_xl = val.int2_drdy_xl; + int2_ctrl.int2_drdy_g = val.int2_drdy_g; + int2_ctrl.int2_drdy_temp = val.int2_drdy_temp; + int2_ctrl.int2_fth = val.int2_fth; + int2_ctrl.int2_fifo_ovr = val.int2_fifo_ovr; + int2_ctrl.int2_full_flag = val.int2_full_flag; + int2_ctrl.int2_step_count_ov = val.int2_step_count_ov; + int2_ctrl.int2_step_delta = val.int2_step_delta; + ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_INT2_CTRL, (uint8_t*)&int2_ctrl, 1); + } + if(ret == 0){ + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_MD1_CFG, (uint8_t*)&md1_cfg, 1); + } + if(ret == 0){ + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_MD2_CFG, (uint8_t*)&md2_cfg, 1); + } + if(ret == 0){ + md2_cfg.int2_iron = val.int2_iron; + md2_cfg.int2_tilt = val.int2_tilt; + md2_cfg.int2_6d = val.int2_6d; + md2_cfg.int2_double_tap = val.int2_double_tap; + md2_cfg.int2_ff = val.int2_ff; + md2_cfg.int2_wu = val.int2_wu; + md2_cfg.int2_single_tap = val.int2_single_tap; + md2_cfg.int2_inact_state = val.int2_inact_state; + ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_MD2_CFG, (uint8_t*)&md2_cfg, 1); + } + if(ret == 0){ + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_DRDY_PULSE_CFG_G, + (uint8_t*)&drdy_pulse_cfg_g, 1); + } + if(ret == 0){ + drdy_pulse_cfg_g.int2_wrist_tilt = val.int2_wrist_tilt; + ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_DRDY_PULSE_CFG_G, + (uint8_t*)&drdy_pulse_cfg_g, 1); + } + if(ret == 0){ + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_TAP_CFG, (uint8_t*)&tap_cfg, 1); + if ((md1_cfg.int1_6d != 0x00U) || + (md1_cfg.int1_ff != 0x00U) || + (md1_cfg.int1_wu != 0x00U) || + (md1_cfg.int1_single_tap != 0x00U) || + (md1_cfg.int1_double_tap != 0x00U) || + (md1_cfg.int1_inact_state != 0x00U) || + (val.int2_6d != 0x00U) || + (val.int2_ff != 0x00U) || + (val.int2_wu != 0x00U) || + (val.int2_single_tap != 0x00U) || + (val.int2_double_tap != 0x00U) || + (val.int2_inact_state!= 0x00U) ){ + tap_cfg.interrupts_enable = PROPERTY_ENABLE; + } + else{ + tap_cfg.interrupts_enable = PROPERTY_DISABLE; + } + } + if(ret == 0){ + ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_TAP_CFG, (uint8_t*)&tap_cfg, 1); + } + return ret; +} + +/** + * @brief Select the signal that need to route on int2 pad[get] + * + * @param ctx Read / write interface definitions + * @param val INT2_CTRL, DRDY_PULSE_CFG(int2_wrist_tilt), MD2_CFG + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6ds3tr_c_pin_int2_route_get(stmdev_ctx_t *ctx, +lsm6ds3tr_c_int2_route_t *val) +{ + lsm6ds3tr_c_int2_ctrl_t int2_ctrl; + lsm6ds3tr_c_md2_cfg_t md2_cfg; + lsm6ds3tr_c_drdy_pulse_cfg_g_t drdy_pulse_cfg_g; + + int32_t ret; + + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_INT2_CTRL, (uint8_t*)&int2_ctrl, 1); + if(ret == 0){ + val->int2_drdy_xl = int2_ctrl.int2_drdy_xl; + val->int2_drdy_g = int2_ctrl.int2_drdy_g; + val->int2_drdy_temp = int2_ctrl.int2_drdy_temp; + val->int2_fth = int2_ctrl.int2_fth; + val->int2_fifo_ovr = int2_ctrl.int2_fifo_ovr; + val->int2_full_flag = int2_ctrl.int2_full_flag; + val->int2_step_count_ov = int2_ctrl.int2_step_count_ov; + val->int2_step_delta = int2_ctrl.int2_step_delta; + + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_MD2_CFG, (uint8_t*)&md2_cfg, 1); + if(ret == 0){ + val->int2_iron = md2_cfg.int2_iron; + val->int2_tilt = md2_cfg.int2_tilt; + val->int2_6d = md2_cfg.int2_6d; + val->int2_double_tap = md2_cfg.int2_double_tap; + val->int2_ff = md2_cfg.int2_ff; + val->int2_wu = md2_cfg.int2_wu; + val->int2_single_tap = md2_cfg.int2_single_tap; + val->int2_inact_state = md2_cfg.int2_inact_state; + + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_DRDY_PULSE_CFG_G, + (uint8_t*)&drdy_pulse_cfg_g, 1); + val->int2_wrist_tilt = drdy_pulse_cfg_g.int2_wrist_tilt; + } + } + return ret; +} + +/** + * @brief Push-pull/open drain selection on interrupt pads.[set] + * + * @param ctx Read / write interface definitions + * @param val Change the values of pp_od in reg CTRL3_C + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6ds3tr_c_pin_mode_set(stmdev_ctx_t *ctx, lsm6ds3tr_c_pp_od_t val) +{ + lsm6ds3tr_c_ctrl3_c_t ctrl3_c; + int32_t ret; + + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL3_C, (uint8_t*)&ctrl3_c, 1); + if(ret == 0){ + ctrl3_c.pp_od = (uint8_t) val; + ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_CTRL3_C, (uint8_t*)&ctrl3_c, 1); + } + return ret; +} + +/** + * @brief Push-pull/open drain selection on interrupt pads.[get] + * + * @param ctx Read / write interface definitions + * @param val Get the values of pp_od in reg CTRL3_C + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6ds3tr_c_pin_mode_get(stmdev_ctx_t *ctx, lsm6ds3tr_c_pp_od_t *val) +{ + lsm6ds3tr_c_ctrl3_c_t ctrl3_c; + int32_t ret; + + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL3_C, (uint8_t*)&ctrl3_c, 1); + switch (ctrl3_c.pp_od) { + case LSM6DS3TR_C_PUSH_PULL: + *val = LSM6DS3TR_C_PUSH_PULL; + break; + case LSM6DS3TR_C_OPEN_DRAIN: + *val = LSM6DS3TR_C_OPEN_DRAIN; + break; + default: + *val = LSM6DS3TR_C_PIN_MODE_ND; + break; + } + + return ret; +} + +/** + * @brief Interrupt active-high/low.[set] + * + * @param ctx Read / write interface definitions + * @param val Change the values of h_lactive in reg CTRL3_C + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6ds3tr_c_pin_polarity_set(stmdev_ctx_t *ctx, lsm6ds3tr_c_h_lactive_t val) +{ + lsm6ds3tr_c_ctrl3_c_t ctrl3_c; + int32_t ret; + + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL3_C, (uint8_t*)&ctrl3_c, 1); + if(ret == 0){ + ctrl3_c.h_lactive = (uint8_t) val; + ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_CTRL3_C, (uint8_t*)&ctrl3_c, 1); + } + return ret; +} + +/** + * @brief Interrupt active-high/low.[get] + * + * @param ctx Read / write interface definitions + * @param val Get the values of h_lactive in reg CTRL3_C + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6ds3tr_c_pin_polarity_get(stmdev_ctx_t *ctx, lsm6ds3tr_c_h_lactive_t *val) +{ + lsm6ds3tr_c_ctrl3_c_t ctrl3_c; + int32_t ret; + + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL3_C, (uint8_t*)&ctrl3_c, 1); + switch (ctrl3_c.h_lactive) { + case LSM6DS3TR_C_ACTIVE_HIGH: + *val = LSM6DS3TR_C_ACTIVE_HIGH; + break; + case LSM6DS3TR_C_ACTIVE_LOW: + *val = LSM6DS3TR_C_ACTIVE_LOW; + break; + default: + *val = LSM6DS3TR_C_POLARITY_ND; + break; + } + + return ret; +} + +/** + * @brief All interrupt signals become available on INT1 pin.[set] + * + * @param ctx Read / write interface definitions + * @param val Change the values of int2_on_int1 in reg CTRL4_C + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6ds3tr_c_all_on_int1_set(stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6ds3tr_c_ctrl4_c_t ctrl4_c; + int32_t ret; + + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL4_C, (uint8_t*)&ctrl4_c, 1); + if(ret == 0){ + ctrl4_c.int2_on_int1 = val; + ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_CTRL4_C, (uint8_t*)&ctrl4_c, 1); + } + return ret; +} + +/** + * @brief All interrupt signals become available on INT1 pin.[get] + * + * @param ctx Read / write interface definitions + * @param val Change the values of int2_on_int1 in reg CTRL4_C + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6ds3tr_c_all_on_int1_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6ds3tr_c_ctrl4_c_t ctrl4_c; + int32_t ret; + + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL4_C, (uint8_t*)&ctrl4_c, 1); + *val = ctrl4_c.int2_on_int1; + + return ret; +} + +/** + * @brief Latched/pulsed interrupt.[set] + * + * @param ctx Read / write interface definitions + * @param val Change the values of lir in reg TAP_CFG + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6ds3tr_c_int_notification_set(stmdev_ctx_t *ctx, lsm6ds3tr_c_lir_t val) +{ + lsm6ds3tr_c_tap_cfg_t tap_cfg; + int32_t ret; + + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_TAP_CFG, (uint8_t*)&tap_cfg, 1); + if(ret == 0){ + tap_cfg.lir = (uint8_t) val; + ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_TAP_CFG, (uint8_t*)&tap_cfg, 1); + } + return ret; +} + +/** + * @brief Latched/pulsed interrupt.[get] + * + * @param ctx Read / write interface definitions + * @param val Get the values of lir in reg TAP_CFG + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6ds3tr_c_int_notification_get(stmdev_ctx_t *ctx, lsm6ds3tr_c_lir_t *val) +{ + lsm6ds3tr_c_tap_cfg_t tap_cfg; + int32_t ret; + + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_TAP_CFG, (uint8_t*)&tap_cfg, 1); + switch (tap_cfg.lir) { + case LSM6DS3TR_C_INT_PULSED: + *val = LSM6DS3TR_C_INT_PULSED; + break; + case LSM6DS3TR_C_INT_LATCHED: + *val = LSM6DS3TR_C_INT_LATCHED; + break; + default: + *val = LSM6DS3TR_C_INT_MODE; + break; + } + + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup LSM6DS3TR_C_Wake_Up_event + * @brief This section groups all the functions that manage the + * Wake Up event generation. + * @{ + * + */ + +/** + * @brief Threshold for wakeup.1 LSB = FS_XL / 64.[set] + * + * @param ctx Read / write interface definitions + * @param val Change the values of wk_ths in reg WAKE_UP_THS + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6ds3tr_c_wkup_threshold_set(stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6ds3tr_c_wake_up_ths_t wake_up_ths; + int32_t ret; + + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_WAKE_UP_THS, (uint8_t*)&wake_up_ths, 1); + if(ret == 0){ + wake_up_ths.wk_ths = val; + ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_WAKE_UP_THS, + (uint8_t*)&wake_up_ths, 1); + } + return ret; +} + +/** + * @brief Threshold for wakeup.1 LSB = FS_XL / 64.[get] + * + * @param ctx Read / write interface definitions + * @param val Change the values of wk_ths in reg WAKE_UP_THS + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6ds3tr_c_wkup_threshold_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6ds3tr_c_wake_up_ths_t wake_up_ths; + int32_t ret; + + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_WAKE_UP_THS, (uint8_t*)&wake_up_ths, 1); + *val = wake_up_ths.wk_ths; + + return ret; +} + +/** + * @brief Wake up duration event.1LSb = 1 / ODR[set] + * + * @param ctx Read / write interface definitions + * @param val Change the values of wake_dur in reg WAKE_UP_DUR + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6ds3tr_c_wkup_dur_set(stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6ds3tr_c_wake_up_dur_t wake_up_dur; + int32_t ret; + + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_WAKE_UP_DUR, (uint8_t*)&wake_up_dur, 1); + if(ret == 0){ + wake_up_dur.wake_dur = val; + ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_WAKE_UP_DUR, + (uint8_t*)&wake_up_dur, 1); + } + return ret; +} + +/** + * @brief Wake up duration event.1LSb = 1 / ODR[get] + * + * @param ctx Read / write interface definitions + * @param val Change the values of wake_dur in reg WAKE_UP_DUR + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6ds3tr_c_wkup_dur_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6ds3tr_c_wake_up_dur_t wake_up_dur; + int32_t ret; + + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_WAKE_UP_DUR, (uint8_t*)&wake_up_dur, 1); + *val = wake_up_dur.wake_dur; + + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup LSM6DS3TR_C_Activity/Inactivity_detection + * @brief This section groups all the functions concerning + * activity/inactivity detection. + * @{ + * + */ + +/** + * @brief Enables gyroscope Sleep mode.[set] + * + * @param ctx Read / write interface definitions + * @param val Change the values of sleep in reg CTRL4_C + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6ds3tr_c_gy_sleep_mode_set(stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6ds3tr_c_ctrl4_c_t ctrl4_c; + int32_t ret; + + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL4_C, (uint8_t*)&ctrl4_c, 1); + if(ret == 0){ + ctrl4_c.sleep = val; + ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_CTRL4_C, (uint8_t*)&ctrl4_c, 1); + } + return ret; +} + +/** + * @brief Enables gyroscope Sleep mode.[get] + * + * @param ctx Read / write interface definitions + * @param val Change the values of sleep in reg CTRL4_C + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6ds3tr_c_gy_sleep_mode_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6ds3tr_c_ctrl4_c_t ctrl4_c; + int32_t ret; + + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL4_C, (uint8_t*)&ctrl4_c, 1); + *val = ctrl4_c.sleep; + + return ret; +} + +/** + * @brief Enable inactivity function.[set] + * + * @param ctx Read / write interface definitions + * @param val Change the values of inact_en in reg TAP_CFG + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6ds3tr_c_act_mode_set(stmdev_ctx_t *ctx, lsm6ds3tr_c_inact_en_t val) +{ + lsm6ds3tr_c_tap_cfg_t tap_cfg; + int32_t ret; + + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_TAP_CFG, (uint8_t*)&tap_cfg, 1); + if(ret == 0){ + tap_cfg.inact_en = (uint8_t) val; + ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_TAP_CFG, (uint8_t*)&tap_cfg, 1); + } + return ret; +} + +/** + * @brief Enable inactivity function.[get] + * + * @param ctx Read / write interface definitions + * @param val Get the values of inact_en in reg TAP_CFG + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6ds3tr_c_act_mode_get(stmdev_ctx_t *ctx, lsm6ds3tr_c_inact_en_t *val) +{ + lsm6ds3tr_c_tap_cfg_t tap_cfg; + int32_t ret; + + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_TAP_CFG, (uint8_t*)&tap_cfg, 1); + switch (tap_cfg.inact_en) { + case LSM6DS3TR_C_PROPERTY_DISABLE: + *val = LSM6DS3TR_C_PROPERTY_DISABLE; + break; + case LSM6DS3TR_C_XL_12Hz5_GY_NOT_AFFECTED: + *val = LSM6DS3TR_C_XL_12Hz5_GY_NOT_AFFECTED; + break; + case LSM6DS3TR_C_XL_12Hz5_GY_SLEEP: + *val = LSM6DS3TR_C_XL_12Hz5_GY_SLEEP; + break; + case LSM6DS3TR_C_XL_12Hz5_GY_PD: + *val = LSM6DS3TR_C_XL_12Hz5_GY_PD; + break; + default: + *val = LSM6DS3TR_C_ACT_MODE_ND; + break; + } + + return ret; +} + +/** + * @brief Duration to go in sleep mode.1 LSb = 512 / ODR[set] + * + * @param ctx Read / write interface definitions + * @param val Change the values of sleep_dur in reg WAKE_UP_DUR + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6ds3tr_c_act_sleep_dur_set(stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6ds3tr_c_wake_up_dur_t wake_up_dur; + int32_t ret; + + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_WAKE_UP_DUR, (uint8_t*)&wake_up_dur, 1); + if(ret == 0){ + wake_up_dur.sleep_dur = val; + ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_WAKE_UP_DUR, + (uint8_t*)&wake_up_dur, 1); + } + return ret; +} + +/** + * @brief Duration to go in sleep mode. 1 LSb = 512 / ODR[get] + * + * @param ctx Read / write interface definitions + * @param val Change the values of sleep_dur in reg WAKE_UP_DUR + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6ds3tr_c_act_sleep_dur_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6ds3tr_c_wake_up_dur_t wake_up_dur; + int32_t ret; + + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_WAKE_UP_DUR, (uint8_t*)&wake_up_dur, 1); + *val = wake_up_dur.sleep_dur; + + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup LSM6DS3TR_C_tap_generator + * @brief This section groups all the functions that manage the + * tap and double tap event generation. + * @{ + * + */ + +/** + * @brief Read the tap / double tap source register.[get] + * + * @param ctx Read / write interface definitions + * @param val Structure of registers from TAP_SRC + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6ds3tr_c_tap_src_get(stmdev_ctx_t *ctx, lsm6ds3tr_c_tap_src_t *val) +{ + int32_t ret; + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_TAP_SRC, (uint8_t*) val, 1); + return ret; +} + +/** + * @brief Enable Z direction in tap recognition.[set] + * + * @param ctx Read / write interface definitions + * @param val Change the values of tap_z_en in reg TAP_CFG + * + */ +int32_t lsm6ds3tr_c_tap_detection_on_z_set(stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6ds3tr_c_tap_cfg_t tap_cfg; + int32_t ret; + + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_TAP_CFG, (uint8_t*)&tap_cfg, 1); + if(ret == 0){ + tap_cfg.tap_z_en = val; + ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_TAP_CFG, (uint8_t*)&tap_cfg, 1); + } + return ret; +} + +/** + * @brief Enable Z direction in tap recognition.[get] + * + * @param ctx Read / write interface definitions + * @param val Change the values of tap_z_en in reg TAP_CFG + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6ds3tr_c_tap_detection_on_z_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6ds3tr_c_tap_cfg_t tap_cfg; + int32_t ret; + + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_TAP_CFG, (uint8_t*)&tap_cfg, 1); + *val = tap_cfg.tap_z_en; + + return ret; +} + +/** + * @brief Enable Y direction in tap recognition.[set] + * + * @param ctx Read / write interface definitions + * @param val Change the values of tap_y_en in reg TAP_CFG + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6ds3tr_c_tap_detection_on_y_set(stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6ds3tr_c_tap_cfg_t tap_cfg; + int32_t ret; + + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_TAP_CFG, (uint8_t*)&tap_cfg, 1); + if(ret == 0){ + tap_cfg.tap_y_en = val; + ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_TAP_CFG, (uint8_t*)&tap_cfg, 1); + } + return ret; +} + +/** + * @brief Enable Y direction in tap recognition.[get] + * + * @param ctx Read / write interface definitions + * @param val Change the values of tap_y_en in reg TAP_CFG + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6ds3tr_c_tap_detection_on_y_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6ds3tr_c_tap_cfg_t tap_cfg; + int32_t ret; + + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_TAP_CFG, (uint8_t*)&tap_cfg, 1); + *val = tap_cfg.tap_y_en; + + return ret; +} + +/** + * @brief Enable X direction in tap recognition.[set] + * + * @param ctx Read / write interface definitions + * @param val Change the values of tap_x_en in reg TAP_CFG + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6ds3tr_c_tap_detection_on_x_set(stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6ds3tr_c_tap_cfg_t tap_cfg; + int32_t ret; + + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_TAP_CFG, (uint8_t*)&tap_cfg, 1); + if(ret == 0){ + tap_cfg.tap_x_en = val; + ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_TAP_CFG, (uint8_t*)&tap_cfg, 1); + } + return ret; +} + +/** + * @brief Enable X direction in tap recognition.[get] + * + * @param ctx Read / write interface definitions + * @param val Change the values of tap_x_en in reg TAP_CFG + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6ds3tr_c_tap_detection_on_x_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6ds3tr_c_tap_cfg_t tap_cfg; + int32_t ret; + + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_TAP_CFG, (uint8_t*)&tap_cfg, 1); + *val = tap_cfg.tap_x_en; + + return ret; +} + +/** + * @brief Threshold for tap recognition.[set] + * + * @param ctx Read / write interface definitions + * @param val Change the values of tap_ths in reg TAP_THS_6D + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6ds3tr_c_tap_threshold_x_set(stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6ds3tr_c_tap_ths_6d_t tap_ths_6d; + int32_t ret; + + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_TAP_THS_6D, (uint8_t*)&tap_ths_6d, 1); + if(ret == 0){ + tap_ths_6d.tap_ths = val; + ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_TAP_THS_6D, + (uint8_t*)&tap_ths_6d, 1); + } + return ret; +} + +/** + * @brief Threshold for tap recognition.[get] + * + * @param ctx Read / write interface definitions + * @param val Change the values of tap_ths in reg TAP_THS_6D + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6ds3tr_c_tap_threshold_x_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6ds3tr_c_tap_ths_6d_t tap_ths_6d; + int32_t ret; + + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_TAP_THS_6D, (uint8_t*)&tap_ths_6d, 1); + *val = tap_ths_6d.tap_ths; + + return ret; +} + +/** + * @brief Maximum duration is the maximum time of an overthreshold signal + * detection to be recognized as a tap event. + * The default value of these bits is 00b which corresponds to + * 4*ODR_XL time. + * If the SHOCK[1:0] bits are set to a different + * value, 1LSB corresponds to 8*ODR_XL time.[set] + * + * @param ctx Read / write interface definitions + * @param val Change the values of shock in reg INT_DUR2 + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6ds3tr_c_tap_shock_set(stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6ds3tr_c_int_dur2_t int_dur2; + int32_t ret; + + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_INT_DUR2, (uint8_t*)&int_dur2, 1); + if(ret == 0){ + int_dur2.shock = val; + ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_INT_DUR2, (uint8_t*)&int_dur2, 1); + } + return ret; +} + +/** + * @brief Maximum duration is the maximum time of an overthreshold signal + * detection to be recognized as a tap event. + * The default value of these bits is 00b which corresponds to + * 4*ODR_XL time. + * If the SHOCK[1:0] bits are set to a different value, 1LSB + * corresponds to 8*ODR_XL time.[get] + * + * @param ctx Read / write interface definitions + * @param val Change the values of shock in reg INT_DUR2 + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6ds3tr_c_tap_shock_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6ds3tr_c_int_dur2_t int_dur2; + int32_t ret; + + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_INT_DUR2, (uint8_t*)&int_dur2, 1); + *val = int_dur2.shock; + + return ret; +} + +/** + * @brief Quiet time is the time after the first detected tap in which there + * must not be any overthreshold event. + * The default value of these bits is 00b which corresponds to + * 2*ODR_XL time. + * If the QUIET[1:0] bits are set to a different value, 1LSB + * corresponds to 4*ODR_XL time.[set] + * + * @param ctx Read / write interface definitions + * @param val Change the values of quiet in reg INT_DUR2 + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6ds3tr_c_tap_quiet_set(stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6ds3tr_c_int_dur2_t int_dur2; + int32_t ret; + + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_INT_DUR2, (uint8_t*)&int_dur2, 1); + if(ret == 0){ + int_dur2.quiet = val; + ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_INT_DUR2, (uint8_t*)&int_dur2, 1); + } + return ret; +} + +/** + * @brief Quiet time is the time after the first detected tap in which there + * must not be any overthreshold event. + * The default value of these bits is 00b which corresponds to + * 2*ODR_XL time. + * If the QUIET[1:0] bits are set to a different value, 1LSB + * corresponds to 4*ODR_XL time.[get] + * + * @param ctx Read / write interface definitions + * @param val Change the values of quiet in reg INT_DUR2 + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6ds3tr_c_tap_quiet_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6ds3tr_c_int_dur2_t int_dur2; + int32_t ret; + + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_INT_DUR2, (uint8_t*)&int_dur2, 1); + *val = int_dur2.quiet; + + return ret; +} + +/** + * @brief When double tap recognition is enabled, this register expresses the + * maximum time between two consecutive detected taps to determine a + * double tap event. + * The default value of these bits is 0000b which corresponds to + * 16*ODR_XL time. + * If the DUR[3:0] bits are set to a different value,1LSB corresponds + * to 32*ODR_XL time.[set] + * + * @param ctx Read / write interface definitions + * @param val Change the values of dur in reg INT_DUR2 + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6ds3tr_c_tap_dur_set(stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6ds3tr_c_int_dur2_t int_dur2; + int32_t ret; + + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_INT_DUR2, (uint8_t*)&int_dur2, 1); + if(ret == 0){ + int_dur2.dur = val; + ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_INT_DUR2, (uint8_t*)&int_dur2, 1); + } + return ret; +} + +/** + * @brief When double tap recognition is enabled, this register expresses the + * maximum time between two consecutive detected taps to determine a + * double tap event. + * The default value of these bits is 0000b which corresponds to + * 16*ODR_XL time. + * If the DUR[3:0] bits are set to a different value,1LSB corresponds + * to 32*ODR_XL time.[get] + * + * @param ctx Read / write interface definitions + * @param val Change the values of dur in reg INT_DUR2 + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6ds3tr_c_tap_dur_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6ds3tr_c_int_dur2_t int_dur2; + int32_t ret; + + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_INT_DUR2, (uint8_t*)&int_dur2, 1); + *val = int_dur2.dur; + + return ret; +} + +/** + * @brief Single/double-tap event enable/disable.[set] + * + * @param ctx Read / write interface definitions + * @param val Change the values of + * single_double_tap in reg WAKE_UP_THS + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6ds3tr_c_tap_mode_set(stmdev_ctx_t *ctx, + lsm6ds3tr_c_single_double_tap_t val) +{ + lsm6ds3tr_c_wake_up_ths_t wake_up_ths; + int32_t ret; + + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_WAKE_UP_THS, (uint8_t*)&wake_up_ths, 1); + if(ret == 0){ + wake_up_ths.single_double_tap = (uint8_t) val; + ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_WAKE_UP_THS, + (uint8_t*)&wake_up_ths, 1); + } + return ret; +} + +/** + * @brief Single/double-tap event enable/disable.[get] + * + * @param ctx Read / write interface definitions + * @param val Get the values of single_double_tap + * in reg WAKE_UP_THS + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6ds3tr_c_tap_mode_get(stmdev_ctx_t *ctx, + lsm6ds3tr_c_single_double_tap_t *val) +{ + lsm6ds3tr_c_wake_up_ths_t wake_up_ths; + int32_t ret; + + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_WAKE_UP_THS, (uint8_t*)&wake_up_ths, 1); + switch (wake_up_ths.single_double_tap) { + case LSM6DS3TR_C_ONLY_SINGLE: + *val = LSM6DS3TR_C_ONLY_SINGLE; + break; + case LSM6DS3TR_C_BOTH_SINGLE_DOUBLE: + *val = LSM6DS3TR_C_BOTH_SINGLE_DOUBLE; + break; + default: + *val = LSM6DS3TR_C_TAP_MODE_ND; + break; + } + + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup LSM6DS3TR_C_ Six_position_detection(6D/4D) + * @brief This section groups all the functions concerning six + * position detection (6D). + * @{ + * + */ + +/** + * @brief LPF2 feed 6D function selection.[set] + * + * @param ctx Read / write interface definitions + * @param val Change the values of low_pass_on_6d in + * reg CTRL8_XL + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6ds3tr_c_6d_feed_data_set(stmdev_ctx_t *ctx, + lsm6ds3tr_c_low_pass_on_6d_t val) +{ + lsm6ds3tr_c_ctrl8_xl_t ctrl8_xl; + int32_t ret; + + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL8_XL, (uint8_t*)&ctrl8_xl, 1); + if(ret == 0){ + ctrl8_xl.low_pass_on_6d = (uint8_t) val; + ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_CTRL8_XL, (uint8_t*)&ctrl8_xl, 1); + } + return ret; +} + +/** + * @brief LPF2 feed 6D function selection.[get] + * + * @param ctx Read / write interface definitions + * @param val Get the values of low_pass_on_6d in reg CTRL8_XL + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6ds3tr_c_6d_feed_data_get(stmdev_ctx_t *ctx, + lsm6ds3tr_c_low_pass_on_6d_t *val) +{ + lsm6ds3tr_c_ctrl8_xl_t ctrl8_xl; + int32_t ret; + + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL8_XL, (uint8_t*)&ctrl8_xl, 1); + switch (ctrl8_xl.low_pass_on_6d) { + case LSM6DS3TR_C_ODR_DIV_2_FEED: + *val = LSM6DS3TR_C_ODR_DIV_2_FEED; + break; + case LSM6DS3TR_C_LPF2_FEED: + *val = LSM6DS3TR_C_LPF2_FEED; + break; + default: + *val = LSM6DS3TR_C_6D_FEED_ND; + break; + } + + return ret; +} + +/** + * @brief Threshold for 4D/6D function.[set] + * + * @param ctx Read / write interface definitions + * @param val Change the values of sixd_ths in reg TAP_THS_6D + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6ds3tr_c_6d_threshold_set(stmdev_ctx_t *ctx, lsm6ds3tr_c_sixd_ths_t val) +{ + lsm6ds3tr_c_tap_ths_6d_t tap_ths_6d; + int32_t ret; + + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_TAP_THS_6D, (uint8_t*)&tap_ths_6d, 1); + if(ret == 0){ + tap_ths_6d.sixd_ths = (uint8_t) val; + ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_TAP_THS_6D, (uint8_t*)&tap_ths_6d, 1); + } + return ret; +} + +/** + * @brief Threshold for 4D/6D function.[get] + * + * @param ctx Read / write interface definitions + * @param val Get the values of sixd_ths in reg TAP_THS_6D + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6ds3tr_c_6d_threshold_get(stmdev_ctx_t *ctx, lsm6ds3tr_c_sixd_ths_t *val) +{ + lsm6ds3tr_c_tap_ths_6d_t tap_ths_6d; + int32_t ret; + + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_TAP_THS_6D, (uint8_t*)&tap_ths_6d, 1); + switch (tap_ths_6d.sixd_ths) { + case LSM6DS3TR_C_DEG_80: + *val = LSM6DS3TR_C_DEG_80; + break; + case LSM6DS3TR_C_DEG_70: + *val = LSM6DS3TR_C_DEG_70; + break; + case LSM6DS3TR_C_DEG_60: + *val = LSM6DS3TR_C_DEG_60; + break; + case LSM6DS3TR_C_DEG_50: + *val = LSM6DS3TR_C_DEG_50; + break; + default: + *val = LSM6DS3TR_C_6D_TH_ND; + break; + } + + return ret; +} + +/** + * @brief 4D orientation detection enable.[set] + * + * @param ctx Read / write interface definitions + * @param val Change the values of d4d_en in reg TAP_THS_6D + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6ds3tr_c_4d_mode_set(stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6ds3tr_c_tap_ths_6d_t tap_ths_6d; + int32_t ret; + + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_TAP_THS_6D, (uint8_t*)&tap_ths_6d, 1); + if(ret == 0){ + tap_ths_6d.d4d_en = val; + ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_TAP_THS_6D, + (uint8_t*)&tap_ths_6d, 1); + } + return ret; +} + +/** + * @brief 4D orientation detection enable.[get] + * + * @param ctx Read / write interface definitions + * @param val Change the values of d4d_en in reg TAP_THS_6D + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6ds3tr_c_4d_mode_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6ds3tr_c_tap_ths_6d_t tap_ths_6d; + int32_t ret; + + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_TAP_THS_6D, (uint8_t*)&tap_ths_6d, 1); + *val = tap_ths_6d.d4d_en; + + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup LSM6DS3TR_C_free_fall + * @brief This section group all the functions concerning the free + * fall detection. + * @{ + * + */ + +/** + * @brief Free-fall duration event. 1LSb = 1 / ODR[set] + * + * @param ctx Read / write interface definitions + * @param val Change the values of ff_dur in reg WAKE_UP_DUR + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6ds3tr_c_ff_dur_set(stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6ds3tr_c_wake_up_dur_t wake_up_dur; + lsm6ds3tr_c_free_fall_t free_fall; + int32_t ret; + + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_FREE_FALL, (uint8_t*)&free_fall, 1); + if(ret == 0){ + free_fall.ff_dur = (val & 0x1FU); + ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_FREE_FALL, (uint8_t*)&free_fall, 1); + if(ret == 0){ + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_WAKE_UP_DUR, + (uint8_t*)&wake_up_dur, 1); + if(ret == 0){ + wake_up_dur.ff_dur = (val & 0x20U) >> 5; + ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_WAKE_UP_DUR, + (uint8_t*)&wake_up_dur, 1); + } + } + } + return ret; +} + +/** + * @brief Free-fall duration event. 1LSb = 1 / ODR[get] + * + * @param ctx Read / write interface definitions + * @param val Change the values of ff_dur in reg WAKE_UP_DUR + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6ds3tr_c_ff_dur_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6ds3tr_c_wake_up_dur_t wake_up_dur; + lsm6ds3tr_c_free_fall_t free_fall; + int32_t ret; + + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_WAKE_UP_DUR, (uint8_t*)&wake_up_dur, 1); + if(ret == 0){ + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_FREE_FALL, (uint8_t*)&free_fall, 1); + } + *val = (wake_up_dur.ff_dur << 5) + free_fall.ff_dur; + + return ret; +} + +/** + * @brief Free fall threshold setting.[set] + * + * @param ctx Read / write interface definitions + * @param val Change the values of ff_ths in reg FREE_FALL + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6ds3tr_c_ff_threshold_set(stmdev_ctx_t *ctx, lsm6ds3tr_c_ff_ths_t val) +{ + lsm6ds3tr_c_free_fall_t free_fall; + int32_t ret; + + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_FREE_FALL, (uint8_t*)&free_fall, 1); + if(ret == 0){ + free_fall.ff_ths = (uint8_t) val; + ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_FREE_FALL, (uint8_t*)&free_fall, 1); + } + return ret; +} + +/** + * @brief Free fall threshold setting.[get] + * + * @param ctx Read / write interface definitions + * @param val Get the values of ff_ths in reg FREE_FALL + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6ds3tr_c_ff_threshold_get(stmdev_ctx_t *ctx, lsm6ds3tr_c_ff_ths_t *val) +{ + lsm6ds3tr_c_free_fall_t free_fall; + int32_t ret; + + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_FREE_FALL, (uint8_t*)&free_fall, 1); + switch (free_fall.ff_ths) { + case LSM6DS3TR_C_FF_TSH_156mg: + *val = LSM6DS3TR_C_FF_TSH_156mg; + break; + case LSM6DS3TR_C_FF_TSH_219mg: + *val = LSM6DS3TR_C_FF_TSH_219mg; + break; + case LSM6DS3TR_C_FF_TSH_250mg: + *val = LSM6DS3TR_C_FF_TSH_250mg; + break; + case LSM6DS3TR_C_FF_TSH_312mg: + *val = LSM6DS3TR_C_FF_TSH_312mg; + break; + case LSM6DS3TR_C_FF_TSH_344mg: + *val = LSM6DS3TR_C_FF_TSH_344mg; + break; + case LSM6DS3TR_C_FF_TSH_406mg: + *val = LSM6DS3TR_C_FF_TSH_406mg; + break; + case LSM6DS3TR_C_FF_TSH_469mg: + *val = LSM6DS3TR_C_FF_TSH_469mg; + break; + case LSM6DS3TR_C_FF_TSH_500mg: + *val = LSM6DS3TR_C_FF_TSH_500mg; + break; + default: + *val = LSM6DS3TR_C_FF_TSH_ND; + break; + } + + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup LSM6DS3TR_C_fifo + * @brief This section group all the functions concerning the + * fifo usage + * @{ + * + */ + +/** + * @brief FIFO watermark level selection.[set] + * + * @param ctx Read / write interface definitions + * @param val Change the values of fth in reg FIFO_CTRL1 + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6ds3tr_c_fifo_watermark_set(stmdev_ctx_t *ctx, uint16_t val) +{ + lsm6ds3tr_c_fifo_ctrl1_t fifo_ctrl1; + lsm6ds3tr_c_fifo_ctrl2_t fifo_ctrl2; + int32_t ret; + + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_FIFO_CTRL2, (uint8_t*)&fifo_ctrl2, 1); + if(ret == 0){ + fifo_ctrl1.fth = (uint8_t) (0x00FFU & val); + fifo_ctrl2.fth = (uint8_t) (( 0x0700U & val ) >> 8); + ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_FIFO_CTRL1, (uint8_t*)&fifo_ctrl1, 1); + if(ret == 0){ + ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_FIFO_CTRL2, + (uint8_t*)&fifo_ctrl2, 1); + } + } + return ret; +} + +/** + * @brief FIFO watermark level selection.[get] + * + * @param ctx Read / write interface definitions + * @param val Change the values of fth in reg FIFO_CTRL1 + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6ds3tr_c_fifo_watermark_get(stmdev_ctx_t *ctx, uint16_t *val) +{ + lsm6ds3tr_c_fifo_ctrl1_t fifo_ctrl1; + lsm6ds3tr_c_fifo_ctrl2_t fifo_ctrl2; + int32_t ret; + + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_FIFO_CTRL1, (uint8_t*)&fifo_ctrl1, 1); + if(ret == 0){ + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_FIFO_CTRL2, (uint8_t*)&fifo_ctrl2, 1); + } + *val = ((uint16_t)fifo_ctrl2.fth << 8) + (uint16_t)fifo_ctrl1.fth; + + return ret; +} + +/** + * @brief FIFO data level.[get] + * + * @param ctx Read / write interface definitions + * @param val get the values of diff_fifo in reg FIFO_STATUS1 and + * FIFO_STATUS2(diff_fifo), it is recommended to set the + * BDU bit. + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6ds3tr_c_fifo_data_level_get(stmdev_ctx_t *ctx, uint16_t *val) +{ + lsm6ds3tr_c_fifo_status1_t fifo_status1; + lsm6ds3tr_c_fifo_status2_t fifo_status2; + int32_t ret; + + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_FIFO_STATUS1, + (uint8_t*)&fifo_status1, 1); + if(ret == 0){ + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_FIFO_STATUS2, + (uint8_t*)&fifo_status2, 1); + *val = ( (uint16_t) fifo_status2.diff_fifo << 8) + + (uint16_t) fifo_status1.diff_fifo; + } + + return ret; +} + +/** + * @brief FIFO watermark.[get] + * + * @param ctx Read / write interface definitions + * @param val get the values of watermark in reg FIFO_STATUS2 and + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6ds3tr_c_fifo_wtm_flag_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6ds3tr_c_fifo_status2_t fifo_status2; + int32_t ret; + + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_FIFO_STATUS2, (uint8_t*)&fifo_status2, 1); + *val = fifo_status2.waterm; + + return ret; +} + +/** + * @brief FIFO pattern.[get] + * + * @param ctx Read / write interface definitions + * @param val get the values of fifo_pattern in reg FIFO_STATUS3 and + * FIFO_STATUS4, it is recommended to set the BDU bit + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6ds3tr_c_fifo_pattern_get(stmdev_ctx_t *ctx, uint16_t *val) +{ + lsm6ds3tr_c_fifo_status3_t fifo_status3; + lsm6ds3tr_c_fifo_status4_t fifo_status4; + int32_t ret; + + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_FIFO_STATUS3, + (uint8_t*)&fifo_status3, 1); + if(ret == 0){ + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_FIFO_STATUS4, + (uint8_t*)&fifo_status4, 1); + *val = ( (uint16_t)fifo_status4.fifo_pattern << 8) + + fifo_status3.fifo_pattern; + } + return ret; +} + +/** + * @brief Batching of temperature data[set] + * + * @param ctx Read / write interface definitions + * @param val Change the values of fifo_temp_en in reg FIFO_CTRL2 + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6ds3tr_c_fifo_temp_batch_set(stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6ds3tr_c_fifo_ctrl2_t fifo_ctrl2; + int32_t ret; + + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_FIFO_CTRL2, (uint8_t*)&fifo_ctrl2, 1); + if(ret == 0){ + fifo_ctrl2.fifo_temp_en = val; + ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_FIFO_CTRL2, + (uint8_t*)&fifo_ctrl2, 1); + } + + return ret; +} + +/** + * @brief Batching of temperature data[get] + * + * @param ctx Read / write interface definitions + * @param val Change the values of fifo_temp_en in reg FIFO_CTRL2 + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6ds3tr_c_fifo_temp_batch_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6ds3tr_c_fifo_ctrl2_t fifo_ctrl2; + int32_t ret; + + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_FIFO_CTRL2, (uint8_t*)&fifo_ctrl2, 1); + *val = fifo_ctrl2.fifo_temp_en; + + return ret; +} + +/** + * @brief Trigger signal for FIFO write operation.[set] + * + * @param ctx Read / write interface definitions + * @param val act on FIFO_CTRL2(timer_pedo_fifo_drdy) + * and MASTER_CONFIG(data_valid_sel_fifo) + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6ds3tr_c_fifo_write_trigger_set(stmdev_ctx_t *ctx, + lsm6ds3tr_c_trigger_fifo_t val) +{ + lsm6ds3tr_c_fifo_ctrl2_t fifo_ctrl2; + lsm6ds3tr_c_master_config_t master_config; + int32_t ret; + + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_FIFO_CTRL2, (uint8_t*)&fifo_ctrl2, 1); + if(ret == 0){ + fifo_ctrl2.timer_pedo_fifo_drdy = (uint8_t)val & 0x01U; + ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_FIFO_CTRL2, + (uint8_t*)&fifo_ctrl2, 1); + if(ret == 0){ + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_MASTER_CONFIG, + (uint8_t*)&master_config, 1); + if(ret == 0){ + master_config.data_valid_sel_fifo = (((uint8_t)val & 0x02U) >> 1); + ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_MASTER_CONFIG, + (uint8_t*)&master_config, 1); + } + } + } + + return ret; +} + +/** + * @brief Trigger signal for FIFO write operation.[get] + * + * @param ctx Read / write interface definitions + * @param val act on FIFO_CTRL2(timer_pedo_fifo_drdy) + * and MASTER_CONFIG(data_valid_sel_fifo) + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6ds3tr_c_fifo_write_trigger_get(stmdev_ctx_t *ctx, + lsm6ds3tr_c_trigger_fifo_t *val) +{ + lsm6ds3tr_c_fifo_ctrl2_t fifo_ctrl2; + lsm6ds3tr_c_master_config_t master_config; + int32_t ret; + + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_FIFO_CTRL2, (uint8_t*)&fifo_ctrl2, 1); + if(ret == 0){ + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_MASTER_CONFIG, + (uint8_t*)&master_config, 1); + + switch ( ( fifo_ctrl2.timer_pedo_fifo_drdy << 1 ) + + fifo_ctrl2. timer_pedo_fifo_drdy ) { + case LSM6DS3TR_C_TRG_XL_GY_DRDY: + *val = LSM6DS3TR_C_TRG_XL_GY_DRDY; + break; + case LSM6DS3TR_C_TRG_STEP_DETECT: + *val = LSM6DS3TR_C_TRG_STEP_DETECT; + break; + case LSM6DS3TR_C_TRG_SH_DRDY: + *val = LSM6DS3TR_C_TRG_SH_DRDY; + break; + default: + *val = LSM6DS3TR_C_TRG_SH_ND; + break; + } + } + + return ret; +} + +/** + * @brief Enable pedometer step counter and timestamp as 4th + * FIFO data set.[set] + * + * @param ctx Read / write interface definitions + * @param val Change the values of timer_pedo_fifo_en in reg FIFO_CTRL2 + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6ds3tr_c_fifo_pedo_and_timestamp_batch_set(stmdev_ctx_t *ctx, + uint8_t val) +{ + lsm6ds3tr_c_fifo_ctrl2_t fifo_ctrl2; + int32_t ret; + + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_FIFO_CTRL2, (uint8_t*)&fifo_ctrl2, 1); + if(ret == 0){ + fifo_ctrl2.timer_pedo_fifo_en = val; + ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_FIFO_CTRL2, + (uint8_t*)&fifo_ctrl2, 1); + } + return ret; +} + +/** + * @brief Enable pedometer step counter and timestamp as 4th + * FIFO data set.[get] + * + * @param ctx Read / write interface definitions + * @param val Change the values of timer_pedo_fifo_en in reg FIFO_CTRL2 + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6ds3tr_c_fifo_pedo_and_timestamp_batch_get(stmdev_ctx_t *ctx, + uint8_t *val) +{ + lsm6ds3tr_c_fifo_ctrl2_t fifo_ctrl2; + int32_t ret; + + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_FIFO_CTRL2, (uint8_t*)&fifo_ctrl2, 1); + *val = fifo_ctrl2.timer_pedo_fifo_en; + + return ret; +} + +/** + * @brief Selects Batching Data Rate (writing frequency in FIFO) for + * accelerometer data.[set] + * + * @param ctx Read / write interface definitions + * @param val Change the values of dec_fifo_xl in reg FIFO_CTRL3 + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6ds3tr_c_fifo_xl_batch_set(stmdev_ctx_t *ctx, + lsm6ds3tr_c_dec_fifo_xl_t val) +{ + lsm6ds3tr_c_fifo_ctrl3_t fifo_ctrl3; + int32_t ret; + + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_FIFO_CTRL3, (uint8_t*)&fifo_ctrl3, 1); + if(ret == 0){ + fifo_ctrl3.dec_fifo_xl = (uint8_t)val; + ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_FIFO_CTRL3, + (uint8_t*)&fifo_ctrl3, 1); + } + return ret; +} + +/** + * @brief Selects Batching Data Rate (writing frequency in FIFO) for + * accelerometer data.[get] + * + * @param ctx Read / write interface definitions + * @param val Get the values of dec_fifo_xl in reg FIFO_CTRL3 + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6ds3tr_c_fifo_xl_batch_get(stmdev_ctx_t *ctx, + lsm6ds3tr_c_dec_fifo_xl_t *val) +{ + lsm6ds3tr_c_fifo_ctrl3_t fifo_ctrl3; + int32_t ret; + + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_FIFO_CTRL3, (uint8_t*)&fifo_ctrl3, 1); + switch (fifo_ctrl3.dec_fifo_xl) { + case LSM6DS3TR_C_FIFO_XL_DISABLE: + *val = LSM6DS3TR_C_FIFO_XL_DISABLE; + break; + case LSM6DS3TR_C_FIFO_XL_NO_DEC: + *val = LSM6DS3TR_C_FIFO_XL_NO_DEC; + break; + case LSM6DS3TR_C_FIFO_XL_DEC_2: + *val = LSM6DS3TR_C_FIFO_XL_DEC_2; + break; + case LSM6DS3TR_C_FIFO_XL_DEC_3: + *val = LSM6DS3TR_C_FIFO_XL_DEC_3; + break; + case LSM6DS3TR_C_FIFO_XL_DEC_4: + *val = LSM6DS3TR_C_FIFO_XL_DEC_4; + break; + case LSM6DS3TR_C_FIFO_XL_DEC_8: + *val = LSM6DS3TR_C_FIFO_XL_DEC_8; + break; + case LSM6DS3TR_C_FIFO_XL_DEC_16: + *val = LSM6DS3TR_C_FIFO_XL_DEC_16; + break; + case LSM6DS3TR_C_FIFO_XL_DEC_32: + *val = LSM6DS3TR_C_FIFO_XL_DEC_32; + break; + default: + *val = LSM6DS3TR_C_FIFO_XL_DEC_ND; + break; + } + + return ret; +} + +/** + * @brief Selects Batching Data Rate (writing frequency in FIFO) + * for gyroscope data.[set] + * + * @param ctx Read / write interface definitions + * @param val Change the values of dec_fifo_gyro in reg FIFO_CTRL3 + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6ds3tr_c_fifo_gy_batch_set(stmdev_ctx_t *ctx, + lsm6ds3tr_c_dec_fifo_gyro_t val) +{ + lsm6ds3tr_c_fifo_ctrl3_t fifo_ctrl3; + int32_t ret; + + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_FIFO_CTRL3, (uint8_t*)&fifo_ctrl3, 1); + if(ret == 0){ + fifo_ctrl3.dec_fifo_gyro = (uint8_t)val; + ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_FIFO_CTRL3, (uint8_t*)&fifo_ctrl3, 1); + } + return ret; +} + +/** + * @brief Selects Batching Data Rate (writing frequency in FIFO) + * for gyroscope data.[get] + * + * @param ctx Read / write interface definitions + * @param val Get the values of dec_fifo_gyro in reg FIFO_CTRL3 + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6ds3tr_c_fifo_gy_batch_get(stmdev_ctx_t *ctx, + lsm6ds3tr_c_dec_fifo_gyro_t *val) +{ + lsm6ds3tr_c_fifo_ctrl3_t fifo_ctrl3; + int32_t ret; + + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_FIFO_CTRL3, (uint8_t*)&fifo_ctrl3, 1); + switch (fifo_ctrl3.dec_fifo_gyro) { + case LSM6DS3TR_C_FIFO_GY_DISABLE: + *val = LSM6DS3TR_C_FIFO_GY_DISABLE; + break; + case LSM6DS3TR_C_FIFO_GY_NO_DEC: + *val = LSM6DS3TR_C_FIFO_GY_NO_DEC; + break; + case LSM6DS3TR_C_FIFO_GY_DEC_2: + *val = LSM6DS3TR_C_FIFO_GY_DEC_2; + break; + case LSM6DS3TR_C_FIFO_GY_DEC_3: + *val = LSM6DS3TR_C_FIFO_GY_DEC_3; + break; + case LSM6DS3TR_C_FIFO_GY_DEC_4: + *val = LSM6DS3TR_C_FIFO_GY_DEC_4; + break; + case LSM6DS3TR_C_FIFO_GY_DEC_8: + *val = LSM6DS3TR_C_FIFO_GY_DEC_8; + break; + case LSM6DS3TR_C_FIFO_GY_DEC_16: + *val = LSM6DS3TR_C_FIFO_GY_DEC_16; + break; + case LSM6DS3TR_C_FIFO_GY_DEC_32: + *val = LSM6DS3TR_C_FIFO_GY_DEC_32; + break; + default: + *val = LSM6DS3TR_C_FIFO_GY_DEC_ND; + break; + } + + return ret; +} + +/** + * @brief Selects Batching Data Rate (writing frequency in FIFO) + * for third data set.[set] + * + * @param ctx Read / write interface definitions + * @param val Change the values of dec_ds3_fifo in reg FIFO_CTRL4 + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6ds3tr_c_fifo_dataset_3_batch_set(stmdev_ctx_t *ctx, + lsm6ds3tr_c_dec_ds3_fifo_t val) +{ + lsm6ds3tr_c_fifo_ctrl4_t fifo_ctrl4; + int32_t ret; + + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_FIFO_CTRL4, (uint8_t*)&fifo_ctrl4, 1); + if(ret == 0){ + fifo_ctrl4.dec_ds3_fifo = (uint8_t)val; + ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_FIFO_CTRL4, + (uint8_t*)&fifo_ctrl4, 1); + } + return ret; +} + +/** + * @brief Selects Batching Data Rate (writing frequency in FIFO) + * for third data set.[get] + * + * @param ctx Read / write interface definitions + * @param val Get the values of dec_ds3_fifo in reg FIFO_CTRL4 + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6ds3tr_c_fifo_dataset_3_batch_get(stmdev_ctx_t *ctx, + lsm6ds3tr_c_dec_ds3_fifo_t *val) +{ + lsm6ds3tr_c_fifo_ctrl4_t fifo_ctrl4; + int32_t ret; + + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_FIFO_CTRL4, (uint8_t*)&fifo_ctrl4, 1); + switch (fifo_ctrl4.dec_ds3_fifo) { + case LSM6DS3TR_C_FIFO_DS3_DISABLE: + *val = LSM6DS3TR_C_FIFO_DS3_DISABLE; + break; + case LSM6DS3TR_C_FIFO_DS3_NO_DEC: + *val = LSM6DS3TR_C_FIFO_DS3_NO_DEC; + break; + case LSM6DS3TR_C_FIFO_DS3_DEC_2: + *val = LSM6DS3TR_C_FIFO_DS3_DEC_2; + break; + case LSM6DS3TR_C_FIFO_DS3_DEC_3: + *val = LSM6DS3TR_C_FIFO_DS3_DEC_3; + break; + case LSM6DS3TR_C_FIFO_DS3_DEC_4: + *val = LSM6DS3TR_C_FIFO_DS3_DEC_4; + break; + case LSM6DS3TR_C_FIFO_DS3_DEC_8: + *val = LSM6DS3TR_C_FIFO_DS3_DEC_8; + break; + case LSM6DS3TR_C_FIFO_DS3_DEC_16: + *val = LSM6DS3TR_C_FIFO_DS3_DEC_16; + break; + case LSM6DS3TR_C_FIFO_DS3_DEC_32: + *val = LSM6DS3TR_C_FIFO_DS3_DEC_32; + break; + default: + *val = LSM6DS3TR_C_FIFO_DS3_DEC_ND; + break; + } + + return ret; +} + +/** + * @brief Selects Batching Data Rate (writing frequency in FIFO) + * for fourth data set.[set] + * + * @param ctx Read / write interface definitions + * @param val Change the values of dec_ds4_fifo in reg FIFO_CTRL4 + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6ds3tr_c_fifo_dataset_4_batch_set(stmdev_ctx_t *ctx, + lsm6ds3tr_c_dec_ds4_fifo_t val) +{ + lsm6ds3tr_c_fifo_ctrl4_t fifo_ctrl4; + int32_t ret; + + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_FIFO_CTRL4, (uint8_t*)&fifo_ctrl4, 1); + if(ret == 0){ + fifo_ctrl4.dec_ds4_fifo = (uint8_t)val; + ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_FIFO_CTRL4, + (uint8_t*)&fifo_ctrl4, 1); + } + return ret; +} + +/** + * @brief Selects Batching Data Rate (writing frequency in FIFO) for + * fourth data set.[get] + * + * @param ctx Read / write interface definitions + * @param val Get the values of dec_ds4_fifo in reg FIFO_CTRL4 + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6ds3tr_c_fifo_dataset_4_batch_get(stmdev_ctx_t *ctx, + lsm6ds3tr_c_dec_ds4_fifo_t *val) +{ + lsm6ds3tr_c_fifo_ctrl4_t fifo_ctrl4; + int32_t ret; + + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_FIFO_CTRL4, (uint8_t*)&fifo_ctrl4, 1); + switch (fifo_ctrl4.dec_ds4_fifo) { + case LSM6DS3TR_C_FIFO_DS4_DISABLE: + *val = LSM6DS3TR_C_FIFO_DS4_DISABLE; + break; + case LSM6DS3TR_C_FIFO_DS4_NO_DEC: + *val = LSM6DS3TR_C_FIFO_DS4_NO_DEC; + break; + case LSM6DS3TR_C_FIFO_DS4_DEC_2: + *val = LSM6DS3TR_C_FIFO_DS4_DEC_2; + break; + case LSM6DS3TR_C_FIFO_DS4_DEC_3: + *val = LSM6DS3TR_C_FIFO_DS4_DEC_3; + break; + case LSM6DS3TR_C_FIFO_DS4_DEC_4: + *val = LSM6DS3TR_C_FIFO_DS4_DEC_4; + break; + case LSM6DS3TR_C_FIFO_DS4_DEC_8: + *val = LSM6DS3TR_C_FIFO_DS4_DEC_8; + break; + case LSM6DS3TR_C_FIFO_DS4_DEC_16: + *val = LSM6DS3TR_C_FIFO_DS4_DEC_16; + break; + case LSM6DS3TR_C_FIFO_DS4_DEC_32: + *val = LSM6DS3TR_C_FIFO_DS4_DEC_32; + break; + default: + *val = LSM6DS3TR_C_FIFO_DS4_DEC_ND; + break; + } + + return ret; +} + +/** + * @brief 8-bit data storage in FIFO.[set] + * + * @param ctx Read / write interface definitions + * @param val Change the values of only_high_data in reg FIFO_CTRL4 + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6ds3tr_c_fifo_xl_gy_8bit_format_set(stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6ds3tr_c_fifo_ctrl4_t fifo_ctrl4; + int32_t ret; + + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_FIFO_CTRL4, (uint8_t*)&fifo_ctrl4, 1); + if(ret == 0){ + fifo_ctrl4.only_high_data = val; + ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_FIFO_CTRL4, (uint8_t*)&fifo_ctrl4, 1); + } + return ret; +} + +/** + * @brief 8-bit data storage in FIFO.[get] + * + * @param ctx Read / write interface definitions + * @param val Change the values of only_high_data in reg FIFO_CTRL4 + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6ds3tr_c_fifo_xl_gy_8bit_format_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6ds3tr_c_fifo_ctrl4_t fifo_ctrl4; + int32_t ret; + + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_FIFO_CTRL4, (uint8_t*)&fifo_ctrl4, 1); + *val = fifo_ctrl4.only_high_data; + + return ret; +} + +/** + * @brief Sensing chain FIFO stop values memorization at threshold + * level.[set] + * + * @param ctx Read / write interface definitions + * @param val Change the values of stop_on_fth in reg FIFO_CTRL4 + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6ds3tr_c_fifo_stop_on_wtm_set(stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6ds3tr_c_fifo_ctrl4_t fifo_ctrl4; + int32_t ret; + + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_FIFO_CTRL4, (uint8_t*)&fifo_ctrl4, 1); + if(ret == 0){ + fifo_ctrl4.stop_on_fth = val; + ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_FIFO_CTRL4, (uint8_t*)&fifo_ctrl4, 1); + } + return ret; +} + +/** + * @brief Sensing chain FIFO stop values memorization at threshold + * level.[get] + * + * @param ctx Read / write interface definitions + * @param val Change the values of stop_on_fth in reg FIFO_CTRL4 + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6ds3tr_c_fifo_stop_on_wtm_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6ds3tr_c_fifo_ctrl4_t fifo_ctrl4; + int32_t ret; + + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_FIFO_CTRL4, (uint8_t*)&fifo_ctrl4, 1); + *val = fifo_ctrl4.stop_on_fth; + + return ret; +} + +/** + * @brief FIFO mode selection.[set] + * + * @param ctx Read / write interface definitions + * @param val Change the values of fifo_mode in reg FIFO_CTRL5 + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6ds3tr_c_fifo_mode_set(stmdev_ctx_t *ctx, lsm6ds3tr_c_fifo_mode_t val) +{ + lsm6ds3tr_c_fifo_ctrl5_t fifo_ctrl5; + int32_t ret; + + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_FIFO_CTRL5, (uint8_t*)&fifo_ctrl5, 1); + if(ret == 0){ + fifo_ctrl5.fifo_mode = (uint8_t)val; + ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_FIFO_CTRL5, (uint8_t*)&fifo_ctrl5, 1); + } + return ret; +} + +/** + * @brief FIFO mode selection.[get] + * + * @param ctx Read / write interface definitions + * @param val Get the values of fifo_mode in reg FIFO_CTRL5 + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6ds3tr_c_fifo_mode_get(stmdev_ctx_t *ctx, lsm6ds3tr_c_fifo_mode_t *val) +{ + lsm6ds3tr_c_fifo_ctrl5_t fifo_ctrl5; + int32_t ret; + + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_FIFO_CTRL5, (uint8_t*)&fifo_ctrl5, 1); + switch (fifo_ctrl5.fifo_mode) { + case LSM6DS3TR_C_BYPASS_MODE: + *val = LSM6DS3TR_C_BYPASS_MODE; + break; + case LSM6DS3TR_C_FIFO_MODE: + *val = LSM6DS3TR_C_FIFO_MODE; + break; + case LSM6DS3TR_C_STREAM_TO_FIFO_MODE: + *val = LSM6DS3TR_C_STREAM_TO_FIFO_MODE; + break; + case LSM6DS3TR_C_BYPASS_TO_STREAM_MODE: + *val = LSM6DS3TR_C_BYPASS_TO_STREAM_MODE; + break; + case LSM6DS3TR_C_STREAM_MODE: + *val = LSM6DS3TR_C_STREAM_MODE; + break; + default: + *val = LSM6DS3TR_C_FIFO_MODE_ND; + break; + } + + return ret; +} + +/** + * @brief FIFO ODR selection, setting FIFO_MODE also.[set] + * + * @param ctx Read / write interface definitions + * @param val Change the values of odr_fifo in reg FIFO_CTRL5 + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6ds3tr_c_fifo_data_rate_set(stmdev_ctx_t *ctx, lsm6ds3tr_c_odr_fifo_t val) +{ + lsm6ds3tr_c_fifo_ctrl5_t fifo_ctrl5; + int32_t ret; + + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_FIFO_CTRL5, (uint8_t*)&fifo_ctrl5, 1); + if(ret == 0){ + fifo_ctrl5.odr_fifo = (uint8_t)val; + ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_FIFO_CTRL5, (uint8_t*)&fifo_ctrl5, 1); + } + return ret; +} + +/** + * @brief FIFO ODR selection, setting FIFO_MODE also.[get] + * + * @param ctx Read / write interface definitions + * @param val Get the values of odr_fifo in reg FIFO_CTRL5 + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6ds3tr_c_fifo_data_rate_get(stmdev_ctx_t *ctx, lsm6ds3tr_c_odr_fifo_t *val) +{ + lsm6ds3tr_c_fifo_ctrl5_t fifo_ctrl5; + int32_t ret; + + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_FIFO_CTRL5, (uint8_t*)&fifo_ctrl5, 1); + switch (fifo_ctrl5.odr_fifo) { + case LSM6DS3TR_C_FIFO_DISABLE: + *val = LSM6DS3TR_C_FIFO_DISABLE; + break; + case LSM6DS3TR_C_FIFO_12Hz5: + *val = LSM6DS3TR_C_FIFO_12Hz5; + break; + case LSM6DS3TR_C_FIFO_26Hz: + *val = LSM6DS3TR_C_FIFO_26Hz; + break; + case LSM6DS3TR_C_FIFO_52Hz: + *val = LSM6DS3TR_C_FIFO_52Hz; + break; + case LSM6DS3TR_C_FIFO_104Hz: + *val = LSM6DS3TR_C_FIFO_104Hz; + break; + case LSM6DS3TR_C_FIFO_208Hz: + *val = LSM6DS3TR_C_FIFO_208Hz; + break; + case LSM6DS3TR_C_FIFO_416Hz: + *val = LSM6DS3TR_C_FIFO_416Hz; + break; + case LSM6DS3TR_C_FIFO_833Hz: + *val = LSM6DS3TR_C_FIFO_833Hz; + break; + case LSM6DS3TR_C_FIFO_1k66Hz: + *val = LSM6DS3TR_C_FIFO_1k66Hz; + break; + case LSM6DS3TR_C_FIFO_3k33Hz: + *val = LSM6DS3TR_C_FIFO_3k33Hz; + break; + case LSM6DS3TR_C_FIFO_6k66Hz: + *val = LSM6DS3TR_C_FIFO_6k66Hz; + break; + default: + *val = LSM6DS3TR_C_FIFO_RATE_ND; + break; + } + + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup LSM6DS3TR_C_DEN_functionality + * @brief This section groups all the functions concerning DEN + * functionality. + * @{ + * + */ + +/** + * @brief DEN active level configuration.[set] + * + * @param ctx Read / write interface definitions + * @param val Change the values of den_lh in reg CTRL5_C + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ + int32_t lsm6ds3tr_c_den_polarity_set(stmdev_ctx_t *ctx, lsm6ds3tr_c_den_lh_t val) +{ + lsm6ds3tr_c_ctrl5_c_t ctrl5_c; + int32_t ret; + + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL5_C, (uint8_t*)&ctrl5_c, 1); + if(ret == 0){ + ctrl5_c.den_lh = (uint8_t)val; + ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_CTRL5_C, (uint8_t*)&ctrl5_c, 1); + } + return ret; +} + +/** + * @brief DEN active level configuration.[get] + * + * @param ctx Read / write interface definitions + * @param val Get the values of den_lh in reg CTRL5_C + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6ds3tr_c_den_polarity_get(stmdev_ctx_t *ctx, lsm6ds3tr_c_den_lh_t *val) +{ + lsm6ds3tr_c_ctrl5_c_t ctrl5_c; + int32_t ret; + + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL5_C, (uint8_t*)&ctrl5_c, 1); + switch (ctrl5_c.den_lh) { + case LSM6DS3TR_C_DEN_ACT_LOW: + *val = LSM6DS3TR_C_DEN_ACT_LOW; + break; + case LSM6DS3TR_C_DEN_ACT_HIGH: + *val = LSM6DS3TR_C_DEN_ACT_HIGH; + break; + default: + *val = LSM6DS3TR_C_DEN_POL_ND; + break; + } + + return ret; +} + +/** + * @brief DEN functionality marking mode[set] + * + * @param ctx Read / write interface definitions + * @param val Change the values of den_mode in reg CTRL6_C + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6ds3tr_c_den_mode_set(stmdev_ctx_t *ctx, lsm6ds3tr_c_den_mode_t val) +{ + lsm6ds3tr_c_ctrl6_c_t ctrl6_c; + int32_t ret; + + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL6_C, (uint8_t*)&ctrl6_c, 1); + if(ret == 0){ + ctrl6_c.den_mode = (uint8_t)val; + ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_CTRL6_C, (uint8_t*)&ctrl6_c, 1); + } + return ret; +} + +/** + * @brief DEN functionality marking mode[get] + * + * @param ctx Read / write interface definitions + * @param val Change the values of den_mode in reg CTRL6_C + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6ds3tr_c_den_mode_get(stmdev_ctx_t *ctx, lsm6ds3tr_c_den_mode_t *val) +{ + lsm6ds3tr_c_ctrl6_c_t ctrl6_c; + int32_t ret; + + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL6_C, (uint8_t*)&ctrl6_c, 1); + switch (ctrl6_c.den_mode) { + case LSM6DS3TR_C_DEN_DISABLE: + *val = LSM6DS3TR_C_DEN_DISABLE; + break; + case LSM6DS3TR_C_LEVEL_LETCHED: + *val = LSM6DS3TR_C_LEVEL_LETCHED; + break; + case LSM6DS3TR_C_LEVEL_TRIGGER: + *val = LSM6DS3TR_C_LEVEL_TRIGGER; + break; + case LSM6DS3TR_C_EDGE_TRIGGER: + *val = LSM6DS3TR_C_EDGE_TRIGGER; + break; + default: + *val = LSM6DS3TR_C_DEN_MODE_ND; + break; + } + + return ret; +} + +/** + * @brief Extend DEN functionality to accelerometer sensor.[set] + * + * @param ctx Read / write interface definitions + * @param val Change the values of den_xl_g in reg CTRL9_XL + * and den_xl_en in CTRL4_C. + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6ds3tr_c_den_enable_set(stmdev_ctx_t *ctx, lsm6ds3tr_c_den_xl_en_t val) +{ + lsm6ds3tr_c_ctrl4_c_t ctrl4_c; + lsm6ds3tr_c_ctrl9_xl_t ctrl9_xl; + int32_t ret; + + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL9_XL, (uint8_t*)&ctrl9_xl, 1); + if(ret == 0){ + ctrl9_xl.den_xl_g = (uint8_t)val & 0x01U; + ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_CTRL9_XL, (uint8_t*)&ctrl9_xl, 1); + if(ret == 0){ + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL4_C, (uint8_t*)&ctrl4_c, 1); + if(ret == 0){ + ctrl4_c.den_xl_en = (uint8_t)val & 0x02U; + ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_CTRL4_C, (uint8_t*)&ctrl4_c, 1); + } + } + } + return ret; +} + +/** + * @brief Extend DEN functionality to accelerometer sensor. [get] + * + * @param ctx Read / write interface definitions + * @param val Get the values of den_xl_g in reg CTRL9_XL + * and den_xl_en in CTRL4_C. + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6ds3tr_c_den_enable_get(stmdev_ctx_t *ctx, lsm6ds3tr_c_den_xl_en_t *val) +{ + lsm6ds3tr_c_ctrl4_c_t ctrl4_c; + lsm6ds3tr_c_ctrl9_xl_t ctrl9_xl; + int32_t ret; + + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL4_C, (uint8_t*)&ctrl4_c, 1); + if(ret == 0){ + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL9_XL, (uint8_t*)&ctrl9_xl, 1); + switch ( ( ctrl4_c.den_xl_en << 1) + ctrl9_xl.den_xl_g ) { + case LSM6DS3TR_C_STAMP_IN_GY_DATA: + *val = LSM6DS3TR_C_STAMP_IN_GY_DATA; + break; + case LSM6DS3TR_C_STAMP_IN_XL_DATA: + *val = LSM6DS3TR_C_STAMP_IN_XL_DATA; + break; + case LSM6DS3TR_C_STAMP_IN_GY_XL_DATA: + *val = LSM6DS3TR_C_STAMP_IN_GY_XL_DATA; + break; + default: + *val = LSM6DS3TR_C_DEN_STAMP_ND; + break; + } + } + + return ret; +} + +/** + * @brief DEN value stored in LSB of Z-axis.[set] + * + * @param ctx Read / write interface definitions + * @param val Change the values of den_z in reg CTRL9_XL + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6ds3tr_c_den_mark_axis_z_set(stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6ds3tr_c_ctrl9_xl_t ctrl9_xl; + int32_t ret; + + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL9_XL, (uint8_t*)&ctrl9_xl, 1); + if(ret == 0){ + ctrl9_xl.den_z = val; + ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_CTRL9_XL, (uint8_t*)&ctrl9_xl, 1); + } + return ret; +} + +/** + * @brief DEN value stored in LSB of Z-axis.[get] + * + * @param ctx Read / write interface definitions + * @param val Change the values of den_z in reg CTRL9_XL + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6ds3tr_c_den_mark_axis_z_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6ds3tr_c_ctrl9_xl_t ctrl9_xl; + int32_t ret; + + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL9_XL, (uint8_t*)&ctrl9_xl, 1); + *val = ctrl9_xl.den_z; + + return ret; +} + +/** + * @brief DEN value stored in LSB of Y-axis.[set] + * + * @param ctx Read / write interface definitions + * @param val Change the values of den_y in reg CTRL9_XL + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6ds3tr_c_den_mark_axis_y_set(stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6ds3tr_c_ctrl9_xl_t ctrl9_xl; + int32_t ret; + + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL9_XL, (uint8_t*)&ctrl9_xl, 1); + if(ret == 0){ + ctrl9_xl.den_y = val; + ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_CTRL9_XL, (uint8_t*)&ctrl9_xl, 1); + } + return ret; +} + +/** + * @brief DEN value stored in LSB of Y-axis.[get] + * + * @param ctx Read / write interface definitions + * @param val Change the values of den_y in reg CTRL9_XL + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6ds3tr_c_den_mark_axis_y_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6ds3tr_c_ctrl9_xl_t ctrl9_xl; + int32_t ret; + + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL9_XL, (uint8_t*)&ctrl9_xl, 1); + *val = ctrl9_xl.den_y; + + return ret; +} + +/** + * @brief DEN value stored in LSB of X-axis.[set] + * + * @param ctx Read / write interface definitions + * @param val Change the values of den_x in reg CTRL9_XL + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6ds3tr_c_den_mark_axis_x_set(stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6ds3tr_c_ctrl9_xl_t ctrl9_xl; + int32_t ret; + + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL9_XL, (uint8_t*)&ctrl9_xl, 1); + if(ret == 0){ + ctrl9_xl.den_x = val; + ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_CTRL9_XL, (uint8_t*)&ctrl9_xl, 1); + } + return ret; +} + +/** + * @brief DEN value stored in LSB of X-axis.[get] + * + * @param ctx Read / write interface definitions + * @param val Change the values of den_x in reg CTRL9_XL + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6ds3tr_c_den_mark_axis_x_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6ds3tr_c_ctrl9_xl_t ctrl9_xl; + int32_t ret; + + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL9_XL, (uint8_t*)&ctrl9_xl, 1); + *val = ctrl9_xl.den_x; + + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup LSM6DS3TR_C_Pedometer + * @brief This section groups all the functions that manage pedometer. + * @{ + * + */ + +/** + * @brief Reset pedometer step counter.[set] + * + * @param ctx Read / write interface definitions + * @param val Change the values of pedo_rst_step in reg CTRL10_C + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6ds3tr_c_pedo_step_reset_set(stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6ds3tr_c_ctrl10_c_t ctrl10_c; + int32_t ret; + + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL10_C, (uint8_t*)&ctrl10_c, 1); + if(ret == 0){ + ctrl10_c.pedo_rst_step = val; + ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_CTRL10_C, (uint8_t*)&ctrl10_c, 1); + } + return ret; +} + +/** + * @brief Reset pedometer step counter.[get] + * + * @param ctx Read / write interface definitions + * @param val Change the values of pedo_rst_step in reg CTRL10_C + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6ds3tr_c_pedo_step_reset_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6ds3tr_c_ctrl10_c_t ctrl10_c; + int32_t ret; + + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL10_C, (uint8_t*)&ctrl10_c, 1); + *val = ctrl10_c.pedo_rst_step; + + return ret; +} + +/** + * @brief Enable pedometer algorithm.[set] + * + * @param ctx Read / write interface definitions + * @param val Change the values of pedo_en in reg CTRL10_C + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6ds3tr_c_pedo_sens_set(stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6ds3tr_c_ctrl10_c_t ctrl10_c; + int32_t ret; + + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL10_C, (uint8_t*)&ctrl10_c, 1); + if(ret == 0){ + ctrl10_c.pedo_en = val; + if (val != 0x00U) { + ctrl10_c.func_en = val; + } + ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_CTRL10_C, (uint8_t*)&ctrl10_c, 1); + } + + return ret; +} + +/** + * @brief pedo_sens: Enable pedometer algorithm.[get] + * + * @param ctx Read / write interface definitions + * @param val Change the values of pedo_en in reg CTRL10_C + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6ds3tr_c_pedo_sens_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6ds3tr_c_ctrl10_c_t ctrl10_c; + int32_t ret; + + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL10_C, (uint8_t*)&ctrl10_c, 1); + *val = ctrl10_c.pedo_en; + + return ret; +} + +/** + * @brief Minimum threshold to detect a peak. Default is 10h.[set] + * + * @param ctx Read / write interface definitions + * @param val Change the values of ths_min in reg + * CONFIG_PEDO_THS_MIN + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6ds3tr_c_pedo_threshold_set(stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6ds3tr_c_config_pedo_ths_min_t config_pedo_ths_min; + int32_t ret; + + ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_BANK_A); + if(ret == 0){ + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CONFIG_PEDO_THS_MIN, + (uint8_t*)&config_pedo_ths_min, 1); + if(ret == 0){ + config_pedo_ths_min.ths_min = val; + ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_CONFIG_PEDO_THS_MIN, + (uint8_t*)&config_pedo_ths_min, 1); + if(ret == 0){ + ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_USER_BANK); + } + } + } + return ret; +} + +/** + * @brief Minimum threshold to detect a peak. Default is 10h.[get] + * + * @param ctx Read / write interface definitions + * @param val Change the values of ths_min in reg CONFIG_PEDO_THS_MIN + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6ds3tr_c_pedo_threshold_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6ds3tr_c_config_pedo_ths_min_t config_pedo_ths_min; + int32_t ret; + + ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_BANK_A); + if(ret == 0){ + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CONFIG_PEDO_THS_MIN, + (uint8_t*)&config_pedo_ths_min, 1); + if(ret == 0){ + *val = config_pedo_ths_min.ths_min; + ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_USER_BANK); + } + } + return ret; +} + +/** + * @brief pedo_full_scale: Pedometer data range.[set] + * + * @param ctx Read / write interface definitions + * @param val Change the values of pedo_fs in + * reg CONFIG_PEDO_THS_MIN + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6ds3tr_c_pedo_full_scale_set(stmdev_ctx_t *ctx, lsm6ds3tr_c_pedo_fs_t val) +{ + lsm6ds3tr_c_config_pedo_ths_min_t config_pedo_ths_min; + int32_t ret; + + ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_BANK_A); + if(ret == 0){ + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CONFIG_PEDO_THS_MIN, + (uint8_t*)&config_pedo_ths_min, 1); + if(ret == 0){ + config_pedo_ths_min.pedo_fs = (uint8_t) val; + ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_CONFIG_PEDO_THS_MIN, + (uint8_t*)&config_pedo_ths_min, 1); + if(ret == 0){ + ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_USER_BANK); + } + } + } + return ret; +} + +/** + * @brief Pedometer data range.[get] + * + * @param ctx Read / write interface definitions + * @param val Get the values of pedo_fs in + * reg CONFIG_PEDO_THS_MIN + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6ds3tr_c_pedo_full_scale_get(stmdev_ctx_t *ctx, lsm6ds3tr_c_pedo_fs_t *val) +{ + lsm6ds3tr_c_config_pedo_ths_min_t config_pedo_ths_min; + int32_t ret; + + ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_BANK_A); + if(ret == 0){ + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CONFIG_PEDO_THS_MIN, + (uint8_t*)&config_pedo_ths_min, 1); + if(ret == 0){ + switch (config_pedo_ths_min.pedo_fs) { + case LSM6DS3TR_C_PEDO_AT_2g: + *val = LSM6DS3TR_C_PEDO_AT_2g; + break; + case LSM6DS3TR_C_PEDO_AT_4g: + *val = LSM6DS3TR_C_PEDO_AT_4g; + break; + default: + *val = LSM6DS3TR_C_PEDO_FS_ND; + break; + } + ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_USER_BANK); + } + } + return ret; +} + +/** + * @brief Pedometer debounce configuration register (r/w).[set] + * + * @param ctx Read / write interface definitions + * @param val Change the values of deb_step in reg PEDO_DEB_REG + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6ds3tr_c_pedo_debounce_steps_set(stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6ds3tr_c_pedo_deb_reg_t pedo_deb_reg; + int32_t ret; + + ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_BANK_A); + if(ret == 0){ + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_PEDO_DEB_REG, + (uint8_t*)&pedo_deb_reg, 1); + if(ret == 0){ + pedo_deb_reg.deb_step = val; + ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_PEDO_DEB_REG, + (uint8_t*)&pedo_deb_reg, 1); + if(ret == 0){ + ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_USER_BANK); + } + } + } + return ret; +} + +/** + * @brief Pedometer debounce configuration register (r/w).[get] + * + * @param ctx Read / write interface definitions + * @param val Change the values of deb_step in reg PEDO_DEB_REG + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6ds3tr_c_pedo_debounce_steps_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6ds3tr_c_pedo_deb_reg_t pedo_deb_reg; + int32_t ret; + + ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_BANK_A); + if(ret == 0){ + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_PEDO_DEB_REG, + (uint8_t*)&pedo_deb_reg, 1); + if(ret == 0){ + *val = pedo_deb_reg.deb_step; + ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_USER_BANK); + } + } + + return ret; +} + +/** + * @brief Debounce time. If the time between two consecutive steps is + * greater than DEB_TIME*80ms, the debouncer is reactivated. + * Default value: 01101[set] + * + * @param ctx Read / write interface definitions + * @param val Change the values of deb_time in reg PEDO_DEB_REG + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6ds3tr_c_pedo_timeout_set(stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6ds3tr_c_pedo_deb_reg_t pedo_deb_reg; + int32_t ret; + + ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_BANK_A); + if(ret == 0){ + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_PEDO_DEB_REG, + (uint8_t*)&pedo_deb_reg, 1); + if(ret == 0){ + pedo_deb_reg.deb_time = val; + ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_PEDO_DEB_REG, + (uint8_t*)&pedo_deb_reg, 1); + if(ret == 0){ + ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_USER_BANK); + } + } + } + return ret; +} + +/** + * @brief Debounce time. If the time between two consecutive steps is + * greater than DEB_TIME*80ms, the debouncer is reactivated. + * Default value: 01101[get] + * + * @param ctx Read / write interface definitions + * @param val Change the values of deb_time in reg PEDO_DEB_REG + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6ds3tr_c_pedo_timeout_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6ds3tr_c_pedo_deb_reg_t pedo_deb_reg; + int32_t ret; + + ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_BANK_A); + if(ret == 0){ + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_PEDO_DEB_REG, + (uint8_t*)&pedo_deb_reg, 1); + if(ret == 0){ + *val = pedo_deb_reg.deb_time; + ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_USER_BANK); + } + } + return ret; +} + +/** + * @brief Time period register for step detection on delta time (r/w).[set] + * + * @param ctx Read / write interface definitions + * @param buff Buffer that contains data to write + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6ds3tr_c_pedo_steps_period_set(stmdev_ctx_t *ctx, uint8_t *buff) +{ + int32_t ret; + + ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_BANK_A); + if(ret == 0){ + ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_STEP_COUNT_DELTA, buff, 1); + if(ret == 0){ + ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_USER_BANK); + } + } + return ret; +} + +/** + * @brief Time period register for step detection on delta time (r/w).[get] + * + * @param ctx Read / write interface definitions + * @param buff Buffer that stores data read + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6ds3tr_c_pedo_steps_period_get(stmdev_ctx_t *ctx, uint8_t *buff) +{ + int32_t ret; + + ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_BANK_A); + if(ret == 0){ + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_STEP_COUNT_DELTA, buff, 1); + if(ret == 0){ + ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_USER_BANK); + } + } + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup LSM6DS3TR_C_significant_motion + * @brief This section groups all the functions that manage the + * significant motion detection. + * @{ + * + */ + +/** + * @brief Enable significant motion detection function.[set] + * + * @param ctx Read / write interface definitions + * @param val Change the values of sign_motion_en in reg CTRL10_C + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6ds3tr_c_motion_sens_set(stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6ds3tr_c_ctrl10_c_t ctrl10_c; + int32_t ret; + + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL10_C, (uint8_t*)&ctrl10_c, 1); + if(ret == 0){ + ctrl10_c.sign_motion_en = val; + if (val != 0x00U) { + ctrl10_c.func_en = val; + ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_CTRL10_C, (uint8_t*)&ctrl10_c, 1); + } + } + return ret; +} + +/** + * @brief Enable significant motion detection function.[get] + * + * @param ctx Read / write interface definitions + * @param val Change the values of sign_motion_en in reg CTRL10_C + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6ds3tr_c_motion_sens_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6ds3tr_c_ctrl10_c_t ctrl10_c; + int32_t ret; + + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL10_C, (uint8_t*)&ctrl10_c, 1); + *val = ctrl10_c.sign_motion_en; + + return ret; +} + +/** + * @brief Significant motion threshold.[set] + * + * @param ctx Read / write interface definitions + * @param buff Buffer that store significant motion threshold. + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6ds3tr_c_motion_threshold_set(stmdev_ctx_t *ctx, uint8_t *buff) +{ + int32_t ret; + + ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_BANK_A); + if(ret == 0){ + ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_SM_THS, buff, 1); + if(ret == 0){ + ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_USER_BANK); + } + } + return ret; +} + +/** + * @brief Significant motion threshold.[get] + * + * @param ctx Read / write interface definitions + * @param buff Buffer that store significant motion threshold. + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6ds3tr_c_motion_threshold_get(stmdev_ctx_t *ctx, uint8_t *buff) +{ + int32_t ret; + + ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_BANK_A); + if(ret == 0){ + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_SM_THS, buff, 1); + if(ret == 0){ + ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_USER_BANK); + } + } + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup LSM6DS3TR_C_tilt_detection + * @brief This section groups all the functions that manage the tilt + * event detection. + * @{ + * + */ + +/** + * @brief Enable tilt calculation.[set] + * + * @param ctx Read / write interface definitions + * @param val Change the values of tilt_en in reg CTRL10_C + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6ds3tr_c_tilt_sens_set(stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6ds3tr_c_ctrl10_c_t ctrl10_c; + int32_t ret; + + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL10_C, (uint8_t*)&ctrl10_c, 1); + if(ret == 0){ + ctrl10_c.tilt_en = val; + if (val != 0x00U) { + ctrl10_c.func_en = val; + } + ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_CTRL10_C, (uint8_t*)&ctrl10_c, 1); + } + return ret; +} + +/** + * @brief Enable tilt calculation.[get] + * + * @param ctx Read / write interface definitions + * @param val Change the values of tilt_en in reg CTRL10_C + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6ds3tr_c_tilt_sens_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6ds3tr_c_ctrl10_c_t ctrl10_c; + int32_t ret; + + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL10_C, (uint8_t*)&ctrl10_c, 1); + *val = ctrl10_c.tilt_en; + + return ret; +} + +/** + * @brief Enable tilt calculation.[set] + * + * @param ctx Read / write interface definitions + * @param val Change the values of tilt_en in reg CTRL10_C + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6ds3tr_c_wrist_tilt_sens_set(stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6ds3tr_c_ctrl10_c_t ctrl10_c; + int32_t ret; + + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL10_C, (uint8_t*)&ctrl10_c, 1); + if(ret == 0){ + ctrl10_c.wrist_tilt_en = val; + if (val != 0x00U) { + ctrl10_c.func_en = val; + } + ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_CTRL10_C, (uint8_t*)&ctrl10_c, 1); + } + return ret; +} + +/** + * @brief Enable tilt calculation.[get] + * + * @param ctx Read / write interface definitions + * @param val Change the values of tilt_en in reg CTRL10_C + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6ds3tr_c_wrist_tilt_sens_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6ds3tr_c_ctrl10_c_t ctrl10_c; + int32_t ret; + + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL10_C, (uint8_t*)&ctrl10_c, 1); + *val = ctrl10_c.wrist_tilt_en; + + return ret; +} + +/** + * @brief Absolute Wrist Tilt latency register (r/w). + * Absolute wrist tilt latency parameters. + * 1 LSB = 40 ms. Default value: 0Fh (600 ms).[set] + * + * @param ctx Read / write interface definitions + * @param buff Buffer that contains data to write + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6ds3tr_c_tilt_latency_set(stmdev_ctx_t *ctx, uint8_t *buff) +{ + int32_t ret; + + ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_BANK_B); + if(ret == 0){ + ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_A_WRIST_TILT_LAT, buff, 1); + if(ret == 0){ + ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_USER_BANK); + } + } + return ret; +} + +/** + * @brief Absolute Wrist Tilt latency register (r/w). + * Absolute wrist tilt latency parameters. + * 1 LSB = 40 ms. Default value: 0Fh (600 ms).[get] + * + * @param ctx Read / write interface definitions + * @param buff Buffer that stores data read + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6ds3tr_c_tilt_latency_get(stmdev_ctx_t *ctx, uint8_t *buff) +{ + int32_t ret; + + ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_BANK_B); + if(ret == 0){ + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_A_WRIST_TILT_LAT, buff, 1); + if(ret == 0){ + ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_USER_BANK); + } + } + return ret; +} + +/** + * @brief Absolute Wrist Tilt threshold register(r/w). + * Absolute wrist tilt threshold parameters. + * 1 LSB = 15.625 mg.Default value: 20h (500 mg).[set] + * + * @param ctx Read / write interface definitions + * @param buff Buffer that contains data to write + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6ds3tr_c_tilt_threshold_set(stmdev_ctx_t *ctx, uint8_t *buff) +{ + int32_t ret; + + ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_BANK_B); + if(ret == 0){ + ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_A_WRIST_TILT_THS, buff, 1); + if(ret == 0){ + ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_USER_BANK); + } + } + return ret; +} + +/** + * @brief Absolute Wrist Tilt threshold register(r/w). + * Absolute wrist tilt threshold parameters. + * 1 LSB = 15.625 mg.Default value: 20h (500 mg).[get] + * + * @param ctx Read / write interface definitions + * @param buff Buffer that stores data read + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6ds3tr_c_tilt_threshold_get(stmdev_ctx_t *ctx, uint8_t *buff) +{ + int32_t ret; + + ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_BANK_B); + if(ret == 0){ + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_A_WRIST_TILT_THS, buff, 1); + if(ret == 0){ + ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_USER_BANK); + } + } + return ret; +} + +/** + * @brief Absolute Wrist Tilt mask register (r/w).[set] + * + * @param ctx Read / write interface definitions + * @param val Registers A_WRIST_TILT_MASK + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6ds3tr_c_tilt_src_set(stmdev_ctx_t *ctx, + lsm6ds3tr_c_a_wrist_tilt_mask_t *val) +{ + int32_t ret; + + ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_BANK_B); + if(ret == 0){ + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_A_WRIST_TILT_MASK, + (uint8_t*) val, 1); + if(ret == 0){ + ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_USER_BANK); + } + } + return ret; +} + +/** + * @brief Absolute Wrist Tilt mask register (r/w).[get] + * + * @param ctx Read / write interface definitions + * @param val Registers A_WRIST_TILT_MASK + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6ds3tr_c_tilt_src_get(stmdev_ctx_t *ctx, + lsm6ds3tr_c_a_wrist_tilt_mask_t *val) +{ + int32_t ret; + + ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_BANK_B); + if(ret == 0){ + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_A_WRIST_TILT_MASK, + (uint8_t*) val, 1); + if(ret == 0){ + ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_USER_BANK); + } + } + return ret; + +} + +/** + * @} + * + */ + +/** + * @defgroup LSM6DS3TR_C_ magnetometer_sensor + * @brief This section groups all the functions that manage additional + * magnetometer sensor. + * @{ + * + */ + +/** + * @brief Enable soft-iron correction algorithm for magnetometer.[set] + * + * @param ctx Read / write interface definitions + * @param val Change the values of soft_en in reg CTRL9_XL + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6ds3tr_c_mag_soft_iron_set(stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6ds3tr_c_ctrl9_xl_t ctrl9_xl; + int32_t ret; + + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL9_XL, (uint8_t*)&ctrl9_xl, 1); + if(ret == 0){ + ctrl9_xl.soft_en = val; + ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_CTRL9_XL, (uint8_t*)&ctrl9_xl, 1); + } + return ret; +} + +/** + * @brief Enable soft-iron correction algorithm for magnetometer.[get] + * + * @param ctx Read / write interface definitions + * @param val Change the values of soft_en in reg CTRL9_XL + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6ds3tr_c_mag_soft_iron_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6ds3tr_c_ctrl9_xl_t ctrl9_xl; + int32_t ret; + + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL9_XL, (uint8_t*)&ctrl9_xl, 1); + *val = ctrl9_xl.soft_en; + + return ret; +} + +/** + * @brief Enable hard-iron correction algorithm for magnetometer.[set] + * + * @param ctx Read / write interface definitions + * @param val Change the values of iron_en in reg MASTER_CONFIG + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6ds3tr_c_mag_hard_iron_set(stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6ds3tr_c_master_config_t master_config; + lsm6ds3tr_c_ctrl10_c_t ctrl10_c; + int32_t ret; + + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_MASTER_CONFIG, + (uint8_t*)&master_config, 1); + if(ret == 0){ + master_config.iron_en = val; + ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_MASTER_CONFIG, + (uint8_t*)&master_config, 1); + if(ret == 0){ + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL10_C, (uint8_t*)&ctrl10_c, 1); + if(ret == 0){ + if (val != 0x00U) { + ctrl10_c.func_en = val; + } + ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_CTRL10_C, + (uint8_t*)&ctrl10_c, 1); + } + } + } + return ret; +} + +/** + * @brief Enable hard-iron correction algorithm for magnetometer.[get] + * + * @param ctx Read / write interface definitions + * @param val Change the values of iron_en in reg MASTER_CONFIG + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6ds3tr_c_mag_hard_iron_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6ds3tr_c_master_config_t master_config; + int32_t ret; + + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_MASTER_CONFIG, + (uint8_t*)&master_config, 1); + *val = master_config.iron_en; + + return ret; +} + +/** + * @brief Soft iron 3x3 matrix. Value are expressed in sign-module format. + * (Es. SVVVVVVVb where S is the sign 0/+1/- and V is the value).[set] + * + * @param ctx Read / write interface definitions + * @param buff Buffer that contains data to write + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6ds3tr_c_mag_soft_iron_mat_set(stmdev_ctx_t *ctx, uint8_t *buff) +{ + int32_t ret; + + ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_BANK_A); + if(ret == 0){ + ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_MAG_SI_XX, buff, 9); + if(ret == 0){ + ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_USER_BANK); + } + } + return ret; +} + +/** + * @brief Soft iron 3x3 matrix. Value are expressed in sign-module format. + * (Es. SVVVVVVVb where S is the sign 0/+1/- and V is the value).[get] + * + * @param ctx Read / write interface definitions + * @param buff Buffer that stores data read + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6ds3tr_c_mag_soft_iron_mat_get(stmdev_ctx_t *ctx, uint8_t *buff) +{ + int32_t ret; + + ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_BANK_A); + if(ret == 0){ + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_MAG_SI_XX, buff, 9); + if(ret == 0){ + ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_USER_BANK); + } + } + return ret; +} + +/** + * @brief Offset for hard-iron compensation register (r/w). The value is + * expressed as a 16-bit word in two’s complement.[set] + * + * @param ctx Read / write interface definitions + * @param buff Buffer that contains data to write + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6ds3tr_c_mag_offset_set(stmdev_ctx_t *ctx, uint8_t *buff) +{ + int32_t ret; + + ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_BANK_A); + if(ret == 0){ + ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_MAG_OFFX_L, buff, 6); + if(ret == 0){ + ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_USER_BANK); + } + } + return ret; +} + +/** + * @brief Offset for hard-iron compensation register(r/w). + * The value is expressed as a 16-bit word in two’s complement.[get] + * + * @param ctx Read / write interface definitions + * @param buff Buffer that stores data read + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6ds3tr_c_mag_offset_get(stmdev_ctx_t *ctx, uint8_t *buff) +{ + int32_t ret; + + ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_BANK_A); + if(ret == 0){ + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_MAG_OFFX_L, buff, 6); + if(ret == 0){ + ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_USER_BANK); + } + } + return ret; +} + +/** + * @} + * + */ + +/** + * @defgroup LSM6DS3TR_C_Sensor_hub + * @brief This section groups all the functions that manage the sensor + * hub functionality. + * @{ + * + */ + + /** + * @brief Enable function.[set] + * + * @param ctx Read / write interface definitions + * @param val Change the values func_en + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6ds3tr_c_func_en_set(stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6ds3tr_c_ctrl10_c_t ctrl10_c; + int32_t ret; + + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL10_C, (uint8_t*)&ctrl10_c, 1); + if(ret == 0){ + ctrl10_c.func_en = val; + ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_CTRL10_C, (uint8_t*)&ctrl10_c, 1); + } + + return ret; +} + +/** + * @brief Sensor synchronization time frame with the step of 500 ms and + * full range of 5s. Unsigned 8-bit.[set] + * + * @param ctx Read / write interface definitions + * @param val Change the values of tph in reg SENSOR_SYNC_TIME_FRAME + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6ds3tr_c_sh_sync_sens_frame_set(stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6ds3tr_c_sensor_sync_time_frame_t sensor_sync_time_frame; + int32_t ret; + + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_SENSOR_SYNC_TIME_FRAME, + (uint8_t*)&sensor_sync_time_frame, 1); + if(ret == 0){ + sensor_sync_time_frame.tph = val; + ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_SENSOR_SYNC_TIME_FRAME, + (uint8_t*)&sensor_sync_time_frame, 1); + } + return ret; +} + +/** + * @brief Sensor synchronization time frame with the step of 500 ms and + * full range of 5s. Unsigned 8-bit.[get] + * + * @param ctx Read / write interface definitions + * @param val Change the values of tph in reg SENSOR_SYNC_TIME_FRAME + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6ds3tr_c_sh_sync_sens_frame_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6ds3tr_c_sensor_sync_time_frame_t sensor_sync_time_frame; + int32_t ret; + + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_SENSOR_SYNC_TIME_FRAME, + (uint8_t*)&sensor_sync_time_frame, 1); + *val = sensor_sync_time_frame.tph; + + return ret; +} + +/** + * @brief Resolution ratio of error code for sensor synchronization.[set] + * + * @param ctx Read / write interface definitions + * @param val Change the values of rr in reg SENSOR_SYNC_RES_RATIO + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6ds3tr_c_sh_sync_sens_ratio_set(stmdev_ctx_t *ctx, lsm6ds3tr_c_rr_t val) +{ + lsm6ds3tr_c_sensor_sync_res_ratio_t sensor_sync_res_ratio; + int32_t ret; + + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_SENSOR_SYNC_RES_RATIO, + (uint8_t*)&sensor_sync_res_ratio, 1); + if(ret == 0){ + sensor_sync_res_ratio.rr = (uint8_t) val; + ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_SENSOR_SYNC_RES_RATIO, + (uint8_t*)&sensor_sync_res_ratio, 1); + } + return ret; +} + +/** + * @brief Resolution ratio of error code for sensor synchronization.[get] + * + * @param ctx Read / write interface definitions + * @param val Get the values of rr in reg SENSOR_SYNC_RES_RATIO + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6ds3tr_c_sh_sync_sens_ratio_get(stmdev_ctx_t *ctx, lsm6ds3tr_c_rr_t *val) +{ + lsm6ds3tr_c_sensor_sync_res_ratio_t sensor_sync_res_ratio; + int32_t ret; + + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_SENSOR_SYNC_RES_RATIO, + (uint8_t*)&sensor_sync_res_ratio, 1); + + switch ( sensor_sync_res_ratio.rr) { + case LSM6DS3TR_C_RES_RATIO_2_11: + *val = LSM6DS3TR_C_RES_RATIO_2_11; + break; + case LSM6DS3TR_C_RES_RATIO_2_12: + *val = LSM6DS3TR_C_RES_RATIO_2_12; + break; + case LSM6DS3TR_C_RES_RATIO_2_13: + *val = LSM6DS3TR_C_RES_RATIO_2_13; + break; + case LSM6DS3TR_C_RES_RATIO_2_14: + *val = LSM6DS3TR_C_RES_RATIO_2_14; + break; + default: + *val = LSM6DS3TR_C_RES_RATIO_ND; + break; + } + + return ret; +} + +/** + * @brief Sensor hub I2C master enable.[set] + * + * @param ctx Read / write interface definitions + * @param val Change the values of master_on in reg MASTER_CONFIG + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6ds3tr_c_sh_master_set(stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6ds3tr_c_master_config_t master_config; + int32_t ret; + + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_MASTER_CONFIG, + (uint8_t*)&master_config, 1); + if(ret == 0){ + master_config.master_on = val; + ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_MASTER_CONFIG, + (uint8_t*)&master_config, 1); + } + return ret; +} + +/** + * @brief Sensor hub I2C master enable.[get] + * + * @param ctx Read / write interface definitions + * @param val Change the values of master_on in reg MASTER_CONFIG + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6ds3tr_c_sh_master_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6ds3tr_c_master_config_t master_config; + int32_t ret; + + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_MASTER_CONFIG, + (uint8_t*)&master_config, 1); + *val = master_config.master_on; + + return ret; +} + +/** + * @brief I2C interface pass-through.[set] + * + * @param ctx Read / write interface definitions + * @param val Change the values of pass_through_mode in reg MASTER_CONFIG + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6ds3tr_c_sh_pass_through_set(stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6ds3tr_c_master_config_t master_config; + int32_t ret; + + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_MASTER_CONFIG, + (uint8_t*)&master_config, 1); + if(ret == 0){ + master_config.pass_through_mode = val; + ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_MASTER_CONFIG, + (uint8_t*)&master_config, 1); + } + return ret; +} + +/** + * @brief I2C interface pass-through.[get] + * + * @param ctx Read / write interface definitions + * @param val Change the values of pass_through_mode in reg MASTER_CONFIG + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6ds3tr_c_sh_pass_through_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6ds3tr_c_master_config_t master_config; + int32_t ret; + + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_MASTER_CONFIG, + (uint8_t*)&master_config, 1); + *val = master_config.pass_through_mode; + + return ret; +} + +/** + * @brief Master I2C pull-up enable/disable.[set] + * + * @param ctx Read / write interface definitions + * @param val Change the values of pull_up_en in reg MASTER_CONFIG + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6ds3tr_c_sh_pin_mode_set(stmdev_ctx_t *ctx, lsm6ds3tr_c_pull_up_en_t val) +{ + lsm6ds3tr_c_master_config_t master_config; + int32_t ret; + + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_MASTER_CONFIG, + (uint8_t*)&master_config, 1); + if(ret == 0){ + master_config.pull_up_en = (uint8_t) val; + ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_MASTER_CONFIG, + (uint8_t*)&master_config, 1); + } + + return ret; +} + +/** + * @brief Master I2C pull-up enable/disable.[get] + * + * @param ctx Read / write interface definitions + * @param val Get the values of pull_up_en in reg MASTER_CONFIG + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6ds3tr_c_sh_pin_mode_get(stmdev_ctx_t *ctx, lsm6ds3tr_c_pull_up_en_t *val) +{ + lsm6ds3tr_c_master_config_t master_config; + int32_t ret; + + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_MASTER_CONFIG, + (uint8_t*)&master_config, 1); + switch (master_config.pull_up_en) { + case LSM6DS3TR_C_EXT_PULL_UP: + *val = LSM6DS3TR_C_EXT_PULL_UP; + break; + case LSM6DS3TR_C_INTERNAL_PULL_UP: + *val = LSM6DS3TR_C_INTERNAL_PULL_UP; + break; + default: + *val = LSM6DS3TR_C_SH_PIN_MODE; + break; + } + return ret; +} + +/** + * @brief Sensor hub trigger signal selection.[set] + * + * @param ctx Read / write interface definitions + * @param val Change the values of start_config in reg MASTER_CONFIG + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6ds3tr_c_sh_syncro_mode_set(stmdev_ctx_t *ctx, + lsm6ds3tr_c_start_config_t val) +{ + lsm6ds3tr_c_master_config_t master_config; + int32_t ret; + + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_MASTER_CONFIG, + (uint8_t*)&master_config, 1); + if(ret == 0){ + master_config.start_config = (uint8_t)val; + ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_MASTER_CONFIG, + (uint8_t*)&master_config, 1); + } + return ret; +} + +/** + * @brief Sensor hub trigger signal selection.[get] + * + * @param ctx Read / write interface definitions + * @param val Get the values of start_config in reg MASTER_CONFIG + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6ds3tr_c_sh_syncro_mode_get(stmdev_ctx_t *ctx, + lsm6ds3tr_c_start_config_t *val) +{ + lsm6ds3tr_c_master_config_t master_config; + int32_t ret; + + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_MASTER_CONFIG, + (uint8_t*)&master_config, 1); + switch (master_config.start_config) { + case LSM6DS3TR_C_XL_GY_DRDY: + *val = LSM6DS3TR_C_XL_GY_DRDY; + break; + case LSM6DS3TR_C_EXT_ON_INT2_PIN: + *val = LSM6DS3TR_C_EXT_ON_INT2_PIN; + break; + default: + *val = LSM6DS3TR_C_SH_SYNCRO_ND; + break; + } + + return ret; +} + +/** + * @brief Manage the Master DRDY signal on INT1 pad.[set] + * + * @param ctx Read / write interface definitions + * @param val Change the values of drdy_on_int1 in reg MASTER_CONFIG + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6ds3tr_c_sh_drdy_on_int1_set(stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6ds3tr_c_master_config_t master_config; + int32_t ret; + + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_MASTER_CONFIG, + (uint8_t*)&master_config, 1); + if(ret == 0){ + master_config.drdy_on_int1 = val; + ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_MASTER_CONFIG, + (uint8_t*)&master_config, 1); + } + return ret; +} + +/** + * @brief Manage the Master DRDY signal on INT1 pad.[get] + * + * @param ctx Read / write interface definitions + * @param val Change the values of drdy_on_int1 in reg MASTER_CONFIG + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6ds3tr_c_sh_drdy_on_int1_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6ds3tr_c_master_config_t master_config; + int32_t ret; + + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_MASTER_CONFIG, + (uint8_t*)&master_config, 1); + *val = master_config.drdy_on_int1; + + return ret; +} + +/** + * @brief Sensor hub output registers.[get] + * + * @param ctx Read / write interface definitions + * @param val Structure of registers from SENSORHUB1_REG + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6ds3tr_c_sh_read_data_raw_get(stmdev_ctx_t *ctx, + lsm6ds3tr_c_emb_sh_read_t *val) +{ + int32_t ret; + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_SENSORHUB1_REG, + (uint8_t*)&(val->sh_byte_1), 12); + if(ret == 0){ + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_SENSORHUB13_REG, + (uint8_t*)&(val->sh_byte_13), 6); + } + return ret; +} + +/** + * @brief Master command code used for stamping for sensor sync.[set] + * + * @param ctx Read / write interface definitions + * @param val Change the values of master_cmd_code in + * reg MASTER_CMD_CODE + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6ds3tr_c_sh_cmd_sens_sync_set(stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6ds3tr_c_master_cmd_code_t master_cmd_code; + int32_t ret; + + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_MASTER_CMD_CODE, + (uint8_t*)&master_cmd_code, 1); + if(ret == 0){ + master_cmd_code.master_cmd_code = val; + ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_MASTER_CMD_CODE, + (uint8_t*)&master_cmd_code, 1); + } + return ret; +} + +/** + * @brief Master command code used for stamping for sensor sync.[get] + * + * @param ctx Read / write interface definitions + * @param val Change the values of master_cmd_code in + * reg MASTER_CMD_CODE + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6ds3tr_c_sh_cmd_sens_sync_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6ds3tr_c_master_cmd_code_t master_cmd_code; + int32_t ret; + + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_MASTER_CMD_CODE, + (uint8_t*)&master_cmd_code, 1); + *val = master_cmd_code.master_cmd_code; + + return ret; +} + +/** + * @brief Error code used for sensor synchronization.[set] + * + * @param ctx Read / write interface definitions + * @param val Change the values of error_code in + * reg SENS_SYNC_SPI_ERROR_CODE. + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6ds3tr_c_sh_spi_sync_error_set(stmdev_ctx_t *ctx, uint8_t val) +{ + lsm6ds3tr_c_sens_sync_spi_error_code_t sens_sync_spi_error_code; + int32_t ret; + + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_SENS_SYNC_SPI_ERROR_CODE, + (uint8_t*)&sens_sync_spi_error_code, 1); + if(ret == 0){ + sens_sync_spi_error_code.error_code = val; + ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_SENS_SYNC_SPI_ERROR_CODE, + (uint8_t*)&sens_sync_spi_error_code, 1); + } + return ret; +} + +/** + * @brief Error code used for sensor synchronization.[get] + * + * @param ctx Read / write interface definitions + * @param val Change the values of error_code in + * reg SENS_SYNC_SPI_ERROR_CODE. + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6ds3tr_c_sh_spi_sync_error_get(stmdev_ctx_t *ctx, uint8_t *val) +{ + lsm6ds3tr_c_sens_sync_spi_error_code_t sens_sync_spi_error_code; + int32_t ret; + + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_SENS_SYNC_SPI_ERROR_CODE, + (uint8_t*)&sens_sync_spi_error_code, 1); + *val = sens_sync_spi_error_code.error_code; + + return ret; +} + +/** + * @brief Number of external sensors to be read by the sensor hub.[set] + * + * @param ctx Read / write interface definitions + * @param val Change the values of aux_sens_on in reg SLAVE0_CONFIG. + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6ds3tr_c_sh_num_of_dev_connected_set(stmdev_ctx_t *ctx, + lsm6ds3tr_c_aux_sens_on_t val) +{ + lsm6ds3tr_c_slave0_config_t slave0_config; + int32_t ret; + + ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_BANK_A); + if(ret == 0){ + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_SLAVE0_CONFIG, + (uint8_t*)&slave0_config, 1); + if(ret == 0){ + slave0_config.aux_sens_on = (uint8_t) val; + ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_SLAVE0_CONFIG, + (uint8_t*)&slave0_config, 1); + if(ret == 0){ + ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_USER_BANK); + } + } + } + return ret; +} + +/** + * @brief Number of external sensors to be read by the sensor hub.[get] + * + * @param ctx Read / write interface definitions + * @param val Get the values of aux_sens_on in reg SLAVE0_CONFIG. + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6ds3tr_c_sh_num_of_dev_connected_get(stmdev_ctx_t *ctx, + lsm6ds3tr_c_aux_sens_on_t *val) +{ + lsm6ds3tr_c_slave0_config_t slave0_config; + int32_t ret; + + ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_BANK_A); + if(ret == 0){ + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_SLAVE0_CONFIG, + (uint8_t*)&slave0_config, 1); + if(ret == 0){ + switch (slave0_config.aux_sens_on) { + case LSM6DS3TR_C_SLV_0: + *val = LSM6DS3TR_C_SLV_0; + break; + case LSM6DS3TR_C_SLV_0_1: + *val = LSM6DS3TR_C_SLV_0_1; + break; + case LSM6DS3TR_C_SLV_0_1_2: + *val = LSM6DS3TR_C_SLV_0_1_2; + break; + case LSM6DS3TR_C_SLV_0_1_2_3: + *val = LSM6DS3TR_C_SLV_0_1_2_3; + break; + default: + *val = LSM6DS3TR_C_SLV_EN_ND; + break; + } + ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_USER_BANK); + } + } + + return ret; +} + +/** + * @brief Configure slave 0 for perform a write.[set] + * + * @param ctx Read / write interface definitions + * @param val Structure that contain: + * - uint8_t slv_add; 8 bit i2c device address + * - uint8_t slv_subadd; 8 bit register device address + * - uint8_t slv_data; 8 bit data to write + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6ds3tr_c_sh_cfg_write(stmdev_ctx_t *ctx, lsm6ds3tr_c_sh_cfg_write_t *val) +{ + lsm6ds3tr_c_slv0_add_t slv0_add; + int32_t ret; + + ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_BANK_A); + if(ret == 0){ + slv0_add.slave0_add = val->slv0_add; + slv0_add.rw_0 = 0; + ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_SLV0_ADD, (uint8_t*)&slv0_add, 1); + if(ret == 0){ + ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_SLV0_SUBADD, + &(val->slv0_subadd), 1); + if(ret == 0){ + ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_DATAWRITE_SRC_MODE_SUB_SLV0, + &(val->slv0_data), 1); + if(ret == 0){ + ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_USER_BANK); + } + } + } + } + return ret; +} + +/** + * @brief Configure slave 0 for perform a read.[get] + * + * @param ctx Read / write interface definitions + * @param val Structure that contain: + * - uint8_t slv_add; 8 bit i2c device address + * - uint8_t slv_subadd; 8 bit register device address + * - uint8_t slv_len; num of bit to read + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6ds3tr_c_sh_slv0_cfg_read(stmdev_ctx_t *ctx, + lsm6ds3tr_c_sh_cfg_read_t *val) +{ + lsm6ds3tr_c_slave0_config_t slave0_config; + lsm6ds3tr_c_slv0_add_t slv0_add; + int32_t ret; + + ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_BANK_A); + if(ret == 0){ + slv0_add.slave0_add = val->slv_add; + slv0_add.rw_0 = 1; + ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_SLV0_ADD, (uint8_t*)&slv0_add, 1); + if(ret == 0){ + ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_SLV0_SUBADD, + &(val->slv_subadd), 1); + if(ret == 0){ + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_SLAVE0_CONFIG, + (uint8_t*)&slave0_config, 1); + slave0_config.slave0_numop = val->slv_len; + if(ret == 0){ + ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_SLAVE0_CONFIG, + (uint8_t*)&slave0_config, 1); + if(ret == 0){ + ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_USER_BANK); + } + } + } + } + } + return ret; +} + +/** + * @brief Configure slave 1 for perform a read.[get] + * + * @param ctx Read / write interface definitions + * @param val Structure that contain: + * - uint8_t slv_add; 8 bit i2c device address + * - uint8_t slv_subadd; 8 bit register device address + * - uint8_t slv_len; num of bit to read + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6ds3tr_c_sh_slv1_cfg_read(stmdev_ctx_t *ctx, + lsm6ds3tr_c_sh_cfg_read_t *val) +{ + lsm6ds3tr_c_slave1_config_t slave1_config; + lsm6ds3tr_c_slv1_add_t slv1_add; + int32_t ret; + + ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_BANK_A); + if(ret == 0){ + slv1_add.slave1_add = val->slv_add; + slv1_add.r_1 = 1; + ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_SLV1_ADD, (uint8_t*)&slv1_add, 1); + if(ret == 0){ + ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_SLV1_SUBADD, + &(val->slv_subadd), 1); + if(ret == 0){ + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_SLAVE1_CONFIG, + (uint8_t*)&slave1_config, 1); + slave1_config.slave1_numop = val->slv_len; + if(ret == 0){ + ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_SLAVE1_CONFIG, + (uint8_t*)&slave1_config, 1); + if(ret == 0){ + ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_USER_BANK); + } + } + } + } + } + return ret; +} + +/** + * @brief Configure slave 2 for perform a read.[get] + * + * @param ctx Read / write interface definitions + * @param val Structure that contain: + * - uint8_t slv_add; 8 bit i2c device address + * - uint8_t slv_subadd; 8 bit register device address + * - uint8_t slv_len; num of bit to read + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6ds3tr_c_sh_slv2_cfg_read(stmdev_ctx_t *ctx, + lsm6ds3tr_c_sh_cfg_read_t *val) +{ + lsm6ds3tr_c_slv2_add_t slv2_add; + lsm6ds3tr_c_slave2_config_t slave2_config; + int32_t ret; + + ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_BANK_A); + if(ret == 0){ + slv2_add.slave2_add = val->slv_add; + slv2_add.r_2 = 1; + ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_SLV2_ADD, (uint8_t*)&slv2_add, 1); + if(ret == 0){ + ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_SLV2_SUBADD, + &(val->slv_subadd), 1); + if(ret == 0){ + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_SLAVE2_CONFIG, + (uint8_t*)&slave2_config, 1); + if(ret == 0){ + slave2_config.slave2_numop = val->slv_len; + ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_SLAVE2_CONFIG, + (uint8_t*)&slave2_config, 1); + if(ret == 0){ + ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_USER_BANK); + } + } + } + } + } + + return ret; +} + +/** + * @brief Configure slave 3 for perform a read.[get] + * + * @param ctx Read / write interface definitions + * @param val Structure that contain: + * - uint8_t slv_add; 8 bit i2c device address + * - uint8_t slv_subadd; 8 bit register device address + * - uint8_t slv_len; num of bit to read + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6ds3tr_c_sh_slv3_cfg_read(stmdev_ctx_t *ctx, + lsm6ds3tr_c_sh_cfg_read_t *val) +{ + lsm6ds3tr_c_slave3_config_t slave3_config; + lsm6ds3tr_c_slv3_add_t slv3_add; + int32_t ret; + + ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_BANK_A); + if(ret == 0){ + slv3_add.slave3_add = val->slv_add; + slv3_add.r_3 = 1; + ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_SLV3_ADD, (uint8_t*)&slv3_add, 1); + if(ret == 0){ + ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_SLV3_SUBADD, + (uint8_t*)&(val->slv_subadd), 1); + if(ret == 0){ + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_SLAVE3_CONFIG, + (uint8_t*)&slave3_config, 1); + if(ret == 0){ + slave3_config.slave3_numop = val->slv_len; + ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_SLAVE3_CONFIG, + (uint8_t*)&slave3_config, 1); + if(ret == 0){ + ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_USER_BANK); + } + } + } + } + } + return ret; +} + +/** + * @brief Decimation of read operation on Slave 0 starting from the + * sensor hub trigger.[set] + * + * @param ctx Read / write interface definitions + * @param val Change the values of slave0_rate in reg SLAVE0_CONFIG + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6ds3tr_c_sh_slave_0_dec_set(stmdev_ctx_t *ctx, + lsm6ds3tr_c_slave0_rate_t val) +{ + lsm6ds3tr_c_slave0_config_t slave0_config; + int32_t ret; + + ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_BANK_A); + if(ret == 0){ + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_SLAVE0_CONFIG, + (uint8_t*)&slave0_config, 1); + if(ret == 0){ + slave0_config.slave0_rate = (uint8_t) val; + ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_SLAVE0_CONFIG, + (uint8_t*)&slave0_config, 1); + if(ret == 0){ + ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_USER_BANK); + } + } + } + return ret; +} + +/** + * @brief Decimation of read operation on Slave 0 starting from the + * sensor hub trigger.[get] + * + * @param ctx Read / write interface definitions + * @param val Get the values of slave0_rate in reg SLAVE0_CONFIG + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6ds3tr_c_sh_slave_0_dec_get(stmdev_ctx_t *ctx, + lsm6ds3tr_c_slave0_rate_t *val) +{ + lsm6ds3tr_c_slave0_config_t slave0_config; + int32_t ret; + + ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_BANK_A); + if(ret == 0){ + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_SLAVE0_CONFIG, + (uint8_t*)&slave0_config, 1); + if(ret == 0){ + switch (slave0_config.slave0_rate) { + case LSM6DS3TR_C_SL0_NO_DEC: + *val = LSM6DS3TR_C_SL0_NO_DEC; + break; + case LSM6DS3TR_C_SL0_DEC_2: + *val = LSM6DS3TR_C_SL0_DEC_2; + break; + case LSM6DS3TR_C_SL0_DEC_4: + *val = LSM6DS3TR_C_SL0_DEC_4; + break; + case LSM6DS3TR_C_SL0_DEC_8: + *val = LSM6DS3TR_C_SL0_DEC_8; + break; + default: + *val = LSM6DS3TR_C_SL0_DEC_ND; + break; + } + ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_USER_BANK); + } + } + + return ret; +} + +/** + * @brief Slave 0 write operation is performed only at the first sensor + * hub cycle. + * This is effective if the Aux_sens_on[1:0] field in + * SLAVE0_CONFIG(04h) is set to a value other than 00.[set] + * + * @param ctx Read / write interface definitions + * @param val Change the values of write_once in reg SLAVE1_CONFIG + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6ds3tr_c_sh_write_mode_set(stmdev_ctx_t *ctx, lsm6ds3tr_c_write_once_t val) +{ + lsm6ds3tr_c_slave1_config_t slave1_config; + int32_t ret; + + ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_BANK_A); + if(ret == 0){ + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_SLAVE1_CONFIG, + (uint8_t*)&slave1_config, 1); + slave1_config.write_once = (uint8_t) val; + if(ret == 0){ + ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_SLAVE1_CONFIG, + (uint8_t*)&slave1_config, 1); + if(ret == 0){ + ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_USER_BANK); + } + } + } + return ret; +} + +/** + * @brief Slave 0 write operation is performed only at the first sensor + * hub cycle. + * This is effective if the Aux_sens_on[1:0] field in + * SLAVE0_CONFIG(04h) is set to a value other than 00.[get] + * + * @param ctx Read / write interface definitions + * @param val Get the values of write_once in reg SLAVE1_CONFIG + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6ds3tr_c_sh_write_mode_get(stmdev_ctx_t *ctx, + lsm6ds3tr_c_write_once_t *val) +{ + lsm6ds3tr_c_slave1_config_t slave1_config; + int32_t ret; + + ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_BANK_A); + if(ret == 0){ + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_SLAVE1_CONFIG, + (uint8_t*)&slave1_config, 1); + if(ret == 0){ + switch (slave1_config.write_once) { + case LSM6DS3TR_C_EACH_SH_CYCLE: + *val = LSM6DS3TR_C_EACH_SH_CYCLE; + break; + case LSM6DS3TR_C_ONLY_FIRST_CYCLE: + *val = LSM6DS3TR_C_ONLY_FIRST_CYCLE; + break; + default: + *val = LSM6DS3TR_C_SH_WR_MODE_ND; + break; + } + ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_USER_BANK); + } + } + + return ret; +} + +/** + * @brief Decimation of read operation on Slave 1 starting from the + * sensor hub trigger.[set] + * + * @param ctx Read / write interface definitions + * @param val Change the values of slave1_rate in reg SLAVE1_CONFIG + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6ds3tr_c_sh_slave_1_dec_set(stmdev_ctx_t *ctx, + lsm6ds3tr_c_slave1_rate_t val) +{ + lsm6ds3tr_c_slave1_config_t slave1_config; + int32_t ret; + + ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_BANK_A); + if(ret == 0){ + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_SLAVE1_CONFIG, + (uint8_t*)&slave1_config, 1); + if(ret == 0){ + slave1_config.slave1_rate = (uint8_t) val; + ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_SLAVE1_CONFIG, + (uint8_t*)&slave1_config, 1); + if(ret == 0){ + ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_USER_BANK); + } + } + } + return ret; +} + +/** + * @brief Decimation of read operation on Slave 1 starting from the + * sensor hub trigger.[get] + * + * @param ctx Read / write interface definitions reg SLAVE1_CONFIG + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6ds3tr_c_sh_slave_1_dec_get(stmdev_ctx_t *ctx, + lsm6ds3tr_c_slave1_rate_t *val) +{ + lsm6ds3tr_c_slave1_config_t slave1_config; + int32_t ret; + + ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_BANK_A); + if(ret == 0){ + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_SLAVE1_CONFIG, + (uint8_t*)&slave1_config, 1); + if(ret == 0){ + switch (slave1_config.slave1_rate) { + case LSM6DS3TR_C_SL1_NO_DEC: + *val = LSM6DS3TR_C_SL1_NO_DEC; + break; + case LSM6DS3TR_C_SL1_DEC_2: + *val = LSM6DS3TR_C_SL1_DEC_2; + break; + case LSM6DS3TR_C_SL1_DEC_4: + *val = LSM6DS3TR_C_SL1_DEC_4; + break; + case LSM6DS3TR_C_SL1_DEC_8: + *val = LSM6DS3TR_C_SL1_DEC_8; + break; + default: + *val = LSM6DS3TR_C_SL1_DEC_ND; + break; + } + ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_USER_BANK); + } + } + + return ret; +} + +/** + * @brief Decimation of read operation on Slave 2 starting from the + * sensor hub trigger.[set] + * + * @param ctx Read / write interface definitions + * @param val Change the values of slave2_rate in reg SLAVE2_CONFIG + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6ds3tr_c_sh_slave_2_dec_set(stmdev_ctx_t *ctx, + lsm6ds3tr_c_slave2_rate_t val) +{ + lsm6ds3tr_c_slave2_config_t slave2_config; + int32_t ret; + + ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_BANK_A); + if(ret == 0){ + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_SLAVE2_CONFIG, + (uint8_t*)&slave2_config, 1); + if(ret == 0){ + slave2_config.slave2_rate =(uint8_t) val; + ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_SLAVE2_CONFIG, + (uint8_t*)&slave2_config, 1); + if(ret == 0){ + ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_USER_BANK); + } + } + } + return ret; +} + +/** + * @brief Decimation of read operation on Slave 2 starting from the + * sensor hub trigger.[get] + * + * @param ctx Read / write interface definitions + * @param val Get the values of slave2_rate in reg SLAVE2_CONFIG + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6ds3tr_c_sh_slave_2_dec_get(stmdev_ctx_t *ctx, + lsm6ds3tr_c_slave2_rate_t *val) +{ + lsm6ds3tr_c_slave2_config_t slave2_config; + int32_t ret; + + ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_BANK_A); + if(ret == 0){ + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_SLAVE2_CONFIG, + (uint8_t*)&slave2_config, 1); + if(ret == 0){ + switch (slave2_config.slave2_rate) { + case LSM6DS3TR_C_SL2_NO_DEC: + *val = LSM6DS3TR_C_SL2_NO_DEC; + break; + case LSM6DS3TR_C_SL2_DEC_2: + *val = LSM6DS3TR_C_SL2_DEC_2; + break; + case LSM6DS3TR_C_SL2_DEC_4: + *val = LSM6DS3TR_C_SL2_DEC_4; + break; + case LSM6DS3TR_C_SL2_DEC_8: + *val = LSM6DS3TR_C_SL2_DEC_8; + break; + default: + *val = LSM6DS3TR_C_SL2_DEC_ND; + break; + } + ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_USER_BANK); + } + } + + return ret; +} + +/** + * @brief Decimation of read operation on Slave 3 starting from the + * sensor hub trigger.[set] + * + * @param ctx Read / write interface definitions + * @param val Change the values of slave3_rate in reg SLAVE3_CONFIG + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6ds3tr_c_sh_slave_3_dec_set(stmdev_ctx_t *ctx, + lsm6ds3tr_c_slave3_rate_t val) +{ + lsm6ds3tr_c_slave3_config_t slave3_config; + int32_t ret; + + ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_BANK_A); + if(ret == 0){ + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_SLAVE3_CONFIG, + (uint8_t*)&slave3_config, 1); + slave3_config.slave3_rate = (uint8_t)val; + if(ret == 0){ + ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_SLAVE3_CONFIG, + (uint8_t*)&slave3_config, 1); + if(ret == 0){ + ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_USER_BANK); + } + } + } + return ret; +} + +/** + * @brief Decimation of read operation on Slave 3 starting from the + * sensor hub trigger.[get] + * + * @param ctx Read / write interface definitions + * @param val Get the values of slave3_rate in reg SLAVE3_CONFIG. + * @retval Interface status (MANDATORY: return 0 -> no Error). + * + */ +int32_t lsm6ds3tr_c_sh_slave_3_dec_get(stmdev_ctx_t *ctx, + lsm6ds3tr_c_slave3_rate_t *val) +{ + lsm6ds3tr_c_slave3_config_t slave3_config; + int32_t ret; + + ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_BANK_A); + if(ret == 0){ + ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_SLAVE3_CONFIG, + (uint8_t*)&slave3_config, 1); + if(ret == 0){ + switch (slave3_config.slave3_rate) { + case LSM6DS3TR_C_SL3_NO_DEC: + *val = LSM6DS3TR_C_SL3_NO_DEC; + break; + case LSM6DS3TR_C_SL3_DEC_2: + *val = LSM6DS3TR_C_SL3_DEC_2; + break; + case LSM6DS3TR_C_SL3_DEC_4: + *val = LSM6DS3TR_C_SL3_DEC_4; + break; + case LSM6DS3TR_C_SL3_DEC_8: + *val = LSM6DS3TR_C_SL3_DEC_8; + break; + default: + *val = LSM6DS3TR_C_SL3_DEC_ND; + break; + } + ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_USER_BANK); + } + } + + return ret; +} + +/** + * @} + * + */ + +/** + * @} + * + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/