ports/stm32: Rename port files consistently.

Just a search/replace/rename for consistency with other
ports.

Signed-off-by: iabdalkader <i.abdalkader@gmail.com>
This commit is contained in:
iabdalkader 2025-07-03 20:35:47 +02:00
parent ad751631a1
commit 92a168742c
13 changed files with 68 additions and 73 deletions

View File

@ -84,7 +84,7 @@
#include "usbdbg.h"
#include "sdram.h"
#include "xspi_psram.h"
#include "stm_xspi.h"
#include "fb_alloc.h"
#include "dma_alloc.h"
#include "file_utils.h"
@ -164,13 +164,13 @@ int main(void) {
#endif
#if OMV_XSPI_PSRAM_SIZE
if (xspi_psram_init() != 0) {
if (stm_xspi_psram_init() != 0) {
__fatal_error("Failed to init XSPI PSRAM!");
}
#endif
#if OMV_XSPI_PSRAM_STARTUP_TEST
if (xspi_psram_test(true) == 0) {
if (stm_xspi_psram_test(true) == 0) {
__fatal_error("XSPI PSRAM test failed");
}
#endif

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@ -39,7 +39,7 @@
#include "fb_alloc.h"
#include "omv_boardconfig.h"
#include "omv_common.h"
#include "dma_utils.h"
#include "stm_dma.h"
#if MICROPY_PY_AUDIO
@ -378,7 +378,7 @@ static mp_obj_t py_audio_init(uint n_args, const mp_obj_t *pos_args, mp_map_t *k
__HAL_LINKDMA(&hdfsdm_filter[0], hdmaReg, hdma_filter[0]);
// Set DMA IRQ handle
dma_utils_set_irq_descr(OMV_DFSDM_FLT0_DMA_STREAM, &hdma_filter[0]);
stm_dma_set_irq_descr(OMV_DFSDM_FLT0_DMA_STREAM, &hdma_filter[0]);
// Initialize the DMA stream
HAL_DMA_DeInit(&hdma_filter[0]);
@ -474,7 +474,7 @@ static mp_obj_t py_audio_init(uint n_args, const mp_obj_t *pos_args, mp_map_t *k
}
// Set DMA IRQ handle
dma_utils_set_irq_descr(OMV_MDF_FLT0_DMA_STREAM, &hdma_filter[0]);
stm_dma_set_irq_descr(OMV_MDF_FLT0_DMA_STREAM, &hdma_filter[0]);
// Configure and enable MDF Filter 0 DMA IRQ.
NVIC_SetPriority(OMV_MDF_FLT0_IRQ, IRQ_PRI_DMA21);

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@ -41,7 +41,7 @@
#include "omv_gpio.h"
#include "omv_i2c.h"
#include "omv_csi.h"
#include "dma_utils.h"
#include "stm_dma.h"
#if defined(DMA2)
#define USE_DMA (1)
@ -129,7 +129,7 @@ static int stm_csi_config(omv_csi_t *csi, omv_csi_config_t config) {
}
// Set DMA IRQ handle
dma_utils_set_irq_descr(DMA2_Stream1, &csi->dma);
stm_dma_set_irq_descr(DMA2_Stream1, &csi->dma);
// Configure the DMA IRQ Channel
NVIC_SetPriority(DMA2_Stream1_IRQn, IRQ_PRI_DMA21);

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@ -22,7 +22,7 @@
# Set startup and system files for CMSIS Makefile.
SYSTEM ?= st/system_stm32
LDSCRIPT ?= stm32
LDSCRIPT ?= stm
STARTUP ?= st/startup_$(shell echo $(MCU) | tr '[:upper:]' '[:lower:]')
MCU_SERIES := $(shell echo $(MCU) | cut -c6-7 | tr '[:upper:]' '[:lower:]')
MCU_LOWER := $(shell echo $(MCU) | tr '[:upper:]' '[:lower:]')

View File

@ -33,7 +33,7 @@
#include "omv_boardconfig.h"
#include "irq.h"
#include "omv_common.h"
#include "dma_utils.h"
#include "stm_dma.h"
#include "omv_gpio.h"
#include "omv_spi.h"
@ -397,10 +397,10 @@ static int omv_spi_dma_init(omv_spi_t *spi, uint32_t direction, omv_spi_config_t
}
// Set the SPI handle used by the DMA channel's IRQ handler.
dma_utils_set_irq_descr(dma_descr->Instance, dma_descr);
stm_dma_set_irq_descr(dma_descr->Instance, dma_descr);
// Get DMA channel's IRQ number.
uint8_t dma_irqn = dma_utils_channel_to_irqn(dma_descr->Instance);
uint8_t dma_irqn = stm_dma_channel_to_irqn(dma_descr->Instance);
// Configure and enable DMA IRQ channel.
NVIC_SetPriority(dma_irqn, IRQ_PRI_DMA);

View File

@ -29,7 +29,7 @@
#include "omv_boardconfig.h"
#include "omv_common.h"
#include "dma_utils.h"
#include "stm_dma.h"
#if defined(GPDMA1)
static DMA_HandleTypeDef *dma_handle[32];
@ -38,7 +38,7 @@ static DMA_HandleTypeDef *dma_handle[32];
extern DMA_HandleTypeDef *dma_handle[16];
#endif
uint8_t dma_utils_channel_to_irqn(void *dma_channel) {
uint8_t stm_dma_channel_to_irqn(void *dma_channel) {
if (0) {
#if defined(DMA1_Stream0)
} else if ((((uint32_t) dma_channel) & 0xFFFFFF00) == DMA1_BASE) {
@ -63,7 +63,7 @@ uint8_t dma_utils_channel_to_irqn(void *dma_channel) {
// This returns a DMA ID that can be used to index into the dma_handle
// array defined in micropython. Setting a DMA handle in that array allows
// DMA IRQ handlers (which are all defined in micropython) to use it.
uint8_t dma_utils_channel_to_id(void *dma_channel) {
uint8_t stm_dma_channel_to_id(void *dma_channel) {
if (0) {
#if defined(DMA1_Stream0)
} else if ((((uint32_t) dma_channel) & 0xFFFFFF00) == DMA1_BASE) {
@ -85,8 +85,8 @@ uint8_t dma_utils_channel_to_id(void *dma_channel) {
return -1;
}
int dma_utils_set_irq_descr(void *dma_channel, DMA_HandleTypeDef *dma_descr) {
uint8_t dma_id = dma_utils_channel_to_id(dma_channel);
int stm_dma_set_irq_descr(void *dma_channel, DMA_HandleTypeDef *dma_descr) {
uint8_t dma_id = stm_dma_channel_to_id(dma_channel);
if (dma_id != -1) {
dma_handle[dma_id] = dma_descr;
return 0;
@ -94,7 +94,7 @@ int dma_utils_set_irq_descr(void *dma_channel, DMA_HandleTypeDef *dma_descr) {
return -1;
}
uint8_t dma_utils_mpu_region_size(uint32_t size) {
uint8_t stm_dma_mpu_region_size(uint32_t size) {
#if (__ARM_ARCH <= 7)
switch (size) {
case 0x00000020U: {
@ -187,137 +187,137 @@ uint8_t dma_utils_mpu_region_size(uint32_t size) {
}
#if defined(GPDMA1)
static inline void dma_utils_irq_handler(size_t irqn) {
static inline void stm_dma_irq_handler(size_t irqn) {
if (dma_handle[irqn] != NULL) {
HAL_DMA_IRQHandler(dma_handle[irqn]);
}
}
void GPDMA1_Channel0_IRQHandler(void) {
dma_utils_irq_handler(0);
stm_dma_irq_handler(0);
}
void GPDMA1_Channel1_IRQHandler(void) {
dma_utils_irq_handler(1);
stm_dma_irq_handler(1);
}
void GPDMA1_Channel2_IRQHandler(void) {
dma_utils_irq_handler(2);
stm_dma_irq_handler(2);
}
void GPDMA1_Channel3_IRQHandler(void) {
dma_utils_irq_handler(3);
stm_dma_irq_handler(3);
}
void GPDMA1_Channel4_IRQHandler(void) {
dma_utils_irq_handler(4);
stm_dma_irq_handler(4);
}
void GPDMA1_Channel5_IRQHandler(void) {
dma_utils_irq_handler(5);
stm_dma_irq_handler(5);
}
void GPDMA1_Channel6_IRQHandler(void) {
dma_utils_irq_handler(6);
stm_dma_irq_handler(6);
}
void GPDMA1_Channel7_IRQHandler(void) {
dma_utils_irq_handler(7);
stm_dma_irq_handler(7);
}
void GPDMA1_Channel8_IRQHandler(void) {
dma_utils_irq_handler(8);
stm_dma_irq_handler(8);
}
void GPDMA1_Channel9_IRQHandler(void) {
dma_utils_irq_handler(9);
stm_dma_irq_handler(9);
}
void GPDMA1_Channel10_IRQHandler(void) {
dma_utils_irq_handler(10);
stm_dma_irq_handler(10);
}
void GPDMA1_Channel11_IRQHandler(void) {
dma_utils_irq_handler(11);
stm_dma_irq_handler(11);
}
void GPDMA1_Channel12_IRQHandler(void) {
dma_utils_irq_handler(12);
stm_dma_irq_handler(12);
}
void GPDMA1_Channel13_IRQHandler(void) {
dma_utils_irq_handler(13);
stm_dma_irq_handler(13);
}
void GPDMA1_Channel14_IRQHandler(void) {
dma_utils_irq_handler(14);
stm_dma_irq_handler(14);
}
void GPDMA1_Channel15_IRQHandler(void) {
dma_utils_irq_handler(15);
stm_dma_irq_handler(15);
}
void HPDMA1_Channel0_IRQHandler(void) {
dma_utils_irq_handler(16);
stm_dma_irq_handler(16);
}
void HPDMA1_Channel1_IRQHandler(void) {
dma_utils_irq_handler(17);
stm_dma_irq_handler(17);
}
void HPDMA1_Channel2_IRQHandler(void) {
dma_utils_irq_handler(18);
stm_dma_irq_handler(18);
}
void HPDMA1_Channel3_IRQHandler(void) {
dma_utils_irq_handler(19);
stm_dma_irq_handler(19);
}
void HPDMA1_Channel4_IRQHandler(void) {
dma_utils_irq_handler(20);
stm_dma_irq_handler(20);
}
void HPDMA1_Channel5_IRQHandler(void) {
dma_utils_irq_handler(21);
stm_dma_irq_handler(21);
}
void HPDMA1_Channel6_IRQHandler(void) {
dma_utils_irq_handler(22);
stm_dma_irq_handler(22);
}
void HPDMA1_Channel7_IRQHandler(void) {
dma_utils_irq_handler(23);
stm_dma_irq_handler(23);
}
void HPDMA1_Channel8_IRQHandler(void) {
dma_utils_irq_handler(24);
stm_dma_irq_handler(24);
}
void HPDMA1_Channel9_IRQHandler(void) {
dma_utils_irq_handler(25);
stm_dma_irq_handler(25);
}
void HPDMA1_Channel10_IRQHandler(void) {
dma_utils_irq_handler(26);
stm_dma_irq_handler(26);
}
void HPDMA1_Channel11_IRQHandler(void) {
dma_utils_irq_handler(27);
stm_dma_irq_handler(27);
}
void HPDMA1_Channel12_IRQHandler(void) {
dma_utils_irq_handler(28);
stm_dma_irq_handler(28);
}
void HPDMA1_Channel13_IRQHandler(void) {
dma_utils_irq_handler(29);
stm_dma_irq_handler(29);
}
void HPDMA1_Channel14_IRQHandler(void) {
dma_utils_irq_handler(30);
stm_dma_irq_handler(30);
}
void HPDMA1_Channel15_IRQHandler(void) {
dma_utils_irq_handler(31);
stm_dma_irq_handler(31);
}
#endif

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@ -23,16 +23,10 @@
*
* STM32 DMA helper functions.
*/
#ifndef __DMA_UTILS_H__
#define __DMA_UTILS_H__
#ifdef MDMA
#define MDMA_CHAN_TO_INSTANCE(x) \
(MDMA_Channel_TypeDef *) (MDMA_Channel0_BASE + ((MDMA_Channel1_BASE - MDMA_Channel0_BASE) * x))
#endif
uint8_t dma_utils_channel_to_irqn(void *dma_channel);
uint8_t dma_utils_channel_to_id(void *dma_channel);
int dma_utils_set_irq_descr(void *dma_channel, DMA_HandleTypeDef *dma_descr);
uint8_t dma_utils_mpu_region_size(uint32_t size);
#endif // __DMA_UTILS_H__
#ifndef __STM_DMA_H__
#define __STM_DMA_H__
uint8_t stm_dma_channel_to_irqn(void *dma_channel);
uint8_t stm_dma_channel_to_id(void *dma_channel);
int stm_dma_set_irq_descr(void *dma_channel, DMA_HandleTypeDef *dma_descr);
uint8_t stm_dma_mpu_region_size(uint32_t size);
#endif // __STM_DMA_H__

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@ -32,7 +32,7 @@
// Define pin objects in this file.
#define OMV_GPIO_DEFINE_PINS (1)
#include "omv_gpio.h"
#include "dma_utils.h"
#include "stm_dma.h"
#if defined(MPU_REGION_NUMBER15)
#define MPU_REGION_NUMBER_MAX (MPU_REGION_NUMBER15)
@ -116,7 +116,7 @@ void HAL_MspInit(void) {
MPU_InitStruct.Number = region_number--;
MPU_InitStruct.Enable = MPU_REGION_ENABLE;
MPU_InitStruct.BaseAddress = buf->addr;
MPU_InitStruct.Size = dma_utils_mpu_region_size(buf->size);
MPU_InitStruct.Size = stm_dma_mpu_region_size(buf->size);
HAL_MPU_ConfigRegion(&MPU_InitStruct);
}
}

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@ -32,7 +32,7 @@
#include STM32_HAL_H
#include "irq.h"
#include "dma_utils.h"
#include "stm_dma.h"
#define JPEG_CODEC_TIMEOUT (1000)
#define JPEG_ALLOC_PADDING ((__SCB_DCACHE_LINE_SIZE) * 4)

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@ -36,6 +36,7 @@
#include STM32_HAL_H
#include "omv_boardconfig.h"
#include "stm_xspi.h"
#if defined(OMV_XSPI_PSRAM_ID)
@ -164,7 +165,7 @@ static int xspi_psram_memory_map(XSPI_HandleTypeDef *xspi, uint32_t burst_enable
return 0;
}
int xspi_psram_init() {
int stm_xspi_psram_init(void) {
uint32_t xspi_clk = 0;
// Reset and enable XSPI clock.
@ -225,7 +226,7 @@ extern void __fatal_error(const char *msg);
#pragma GCC diagnostic ignored "-Wstringop-overflow"
#endif
bool __attribute__((optimize("Os"))) xspi_psram_test(bool exhaustive) {
bool __attribute__((optimize("Os"))) stm_xspi_psram_test(bool exhaustive) {
uint8_t const pattern = 0xaa;
uint8_t const antipattern = 0x55;
volatile uint8_t *const mem_base = (uint8_t *) 0x90000000;

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@ -30,7 +30,7 @@
*
* STM32 XSPI PSRAM driver.
*/
#ifndef __XSPI_PSRAM_H__
int xspi_psram_init();
bool xspi_psram_test(bool exhaustive);
#endif // __XSPI_PSRAM_H__
#ifndef __STM_XSPI_H__
int stm_xspi_psram_init();
bool stm_xspi_psram_test(bool exhaustive);
#endif // __STM_XSPI_H__