mirror of
https://github.com/openmv/openmv.git
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ports/stm32: Rename port files consistently.
Just a search/replace/rename for consistency with other ports. Signed-off-by: iabdalkader <i.abdalkader@gmail.com>
This commit is contained in:
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ad751631a1
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92a168742c
@ -84,7 +84,7 @@
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#include "usbdbg.h"
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#include "sdram.h"
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#include "xspi_psram.h"
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#include "stm_xspi.h"
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#include "fb_alloc.h"
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#include "dma_alloc.h"
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#include "file_utils.h"
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@ -164,13 +164,13 @@ int main(void) {
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#endif
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#if OMV_XSPI_PSRAM_SIZE
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if (xspi_psram_init() != 0) {
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if (stm_xspi_psram_init() != 0) {
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__fatal_error("Failed to init XSPI PSRAM!");
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}
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#endif
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#if OMV_XSPI_PSRAM_STARTUP_TEST
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if (xspi_psram_test(true) == 0) {
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if (stm_xspi_psram_test(true) == 0) {
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__fatal_error("XSPI PSRAM test failed");
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}
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#endif
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@ -39,7 +39,7 @@
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#include "fb_alloc.h"
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#include "omv_boardconfig.h"
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#include "omv_common.h"
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#include "dma_utils.h"
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#include "stm_dma.h"
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#if MICROPY_PY_AUDIO
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@ -378,7 +378,7 @@ static mp_obj_t py_audio_init(uint n_args, const mp_obj_t *pos_args, mp_map_t *k
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__HAL_LINKDMA(&hdfsdm_filter[0], hdmaReg, hdma_filter[0]);
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// Set DMA IRQ handle
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dma_utils_set_irq_descr(OMV_DFSDM_FLT0_DMA_STREAM, &hdma_filter[0]);
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stm_dma_set_irq_descr(OMV_DFSDM_FLT0_DMA_STREAM, &hdma_filter[0]);
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// Initialize the DMA stream
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HAL_DMA_DeInit(&hdma_filter[0]);
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@ -474,7 +474,7 @@ static mp_obj_t py_audio_init(uint n_args, const mp_obj_t *pos_args, mp_map_t *k
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}
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// Set DMA IRQ handle
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dma_utils_set_irq_descr(OMV_MDF_FLT0_DMA_STREAM, &hdma_filter[0]);
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stm_dma_set_irq_descr(OMV_MDF_FLT0_DMA_STREAM, &hdma_filter[0]);
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// Configure and enable MDF Filter 0 DMA IRQ.
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NVIC_SetPriority(OMV_MDF_FLT0_IRQ, IRQ_PRI_DMA21);
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@ -41,7 +41,7 @@
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#include "omv_gpio.h"
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#include "omv_i2c.h"
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#include "omv_csi.h"
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#include "dma_utils.h"
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#include "stm_dma.h"
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#if defined(DMA2)
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#define USE_DMA (1)
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@ -129,7 +129,7 @@ static int stm_csi_config(omv_csi_t *csi, omv_csi_config_t config) {
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}
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// Set DMA IRQ handle
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dma_utils_set_irq_descr(DMA2_Stream1, &csi->dma);
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stm_dma_set_irq_descr(DMA2_Stream1, &csi->dma);
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// Configure the DMA IRQ Channel
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NVIC_SetPriority(DMA2_Stream1_IRQn, IRQ_PRI_DMA21);
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@ -22,7 +22,7 @@
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# Set startup and system files for CMSIS Makefile.
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SYSTEM ?= st/system_stm32
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LDSCRIPT ?= stm32
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LDSCRIPT ?= stm
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STARTUP ?= st/startup_$(shell echo $(MCU) | tr '[:upper:]' '[:lower:]')
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MCU_SERIES := $(shell echo $(MCU) | cut -c6-7 | tr '[:upper:]' '[:lower:]')
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MCU_LOWER := $(shell echo $(MCU) | tr '[:upper:]' '[:lower:]')
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@ -33,7 +33,7 @@
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#include "omv_boardconfig.h"
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#include "irq.h"
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#include "omv_common.h"
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#include "dma_utils.h"
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#include "stm_dma.h"
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#include "omv_gpio.h"
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#include "omv_spi.h"
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@ -397,10 +397,10 @@ static int omv_spi_dma_init(omv_spi_t *spi, uint32_t direction, omv_spi_config_t
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}
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// Set the SPI handle used by the DMA channel's IRQ handler.
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dma_utils_set_irq_descr(dma_descr->Instance, dma_descr);
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stm_dma_set_irq_descr(dma_descr->Instance, dma_descr);
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// Get DMA channel's IRQ number.
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uint8_t dma_irqn = dma_utils_channel_to_irqn(dma_descr->Instance);
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uint8_t dma_irqn = stm_dma_channel_to_irqn(dma_descr->Instance);
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// Configure and enable DMA IRQ channel.
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NVIC_SetPriority(dma_irqn, IRQ_PRI_DMA);
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@ -29,7 +29,7 @@
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#include "omv_boardconfig.h"
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#include "omv_common.h"
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#include "dma_utils.h"
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#include "stm_dma.h"
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#if defined(GPDMA1)
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static DMA_HandleTypeDef *dma_handle[32];
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@ -38,7 +38,7 @@ static DMA_HandleTypeDef *dma_handle[32];
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extern DMA_HandleTypeDef *dma_handle[16];
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#endif
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uint8_t dma_utils_channel_to_irqn(void *dma_channel) {
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uint8_t stm_dma_channel_to_irqn(void *dma_channel) {
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if (0) {
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#if defined(DMA1_Stream0)
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} else if ((((uint32_t) dma_channel) & 0xFFFFFF00) == DMA1_BASE) {
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@ -63,7 +63,7 @@ uint8_t dma_utils_channel_to_irqn(void *dma_channel) {
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// This returns a DMA ID that can be used to index into the dma_handle
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// array defined in micropython. Setting a DMA handle in that array allows
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// DMA IRQ handlers (which are all defined in micropython) to use it.
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uint8_t dma_utils_channel_to_id(void *dma_channel) {
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uint8_t stm_dma_channel_to_id(void *dma_channel) {
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if (0) {
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#if defined(DMA1_Stream0)
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} else if ((((uint32_t) dma_channel) & 0xFFFFFF00) == DMA1_BASE) {
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@ -85,8 +85,8 @@ uint8_t dma_utils_channel_to_id(void *dma_channel) {
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return -1;
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}
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int dma_utils_set_irq_descr(void *dma_channel, DMA_HandleTypeDef *dma_descr) {
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uint8_t dma_id = dma_utils_channel_to_id(dma_channel);
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int stm_dma_set_irq_descr(void *dma_channel, DMA_HandleTypeDef *dma_descr) {
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uint8_t dma_id = stm_dma_channel_to_id(dma_channel);
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if (dma_id != -1) {
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dma_handle[dma_id] = dma_descr;
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return 0;
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@ -94,7 +94,7 @@ int dma_utils_set_irq_descr(void *dma_channel, DMA_HandleTypeDef *dma_descr) {
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return -1;
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}
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uint8_t dma_utils_mpu_region_size(uint32_t size) {
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uint8_t stm_dma_mpu_region_size(uint32_t size) {
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#if (__ARM_ARCH <= 7)
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switch (size) {
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case 0x00000020U: {
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@ -187,137 +187,137 @@ uint8_t dma_utils_mpu_region_size(uint32_t size) {
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}
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#if defined(GPDMA1)
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static inline void dma_utils_irq_handler(size_t irqn) {
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static inline void stm_dma_irq_handler(size_t irqn) {
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if (dma_handle[irqn] != NULL) {
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HAL_DMA_IRQHandler(dma_handle[irqn]);
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}
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}
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void GPDMA1_Channel0_IRQHandler(void) {
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dma_utils_irq_handler(0);
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stm_dma_irq_handler(0);
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}
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void GPDMA1_Channel1_IRQHandler(void) {
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dma_utils_irq_handler(1);
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stm_dma_irq_handler(1);
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}
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void GPDMA1_Channel2_IRQHandler(void) {
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dma_utils_irq_handler(2);
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stm_dma_irq_handler(2);
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}
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void GPDMA1_Channel3_IRQHandler(void) {
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dma_utils_irq_handler(3);
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stm_dma_irq_handler(3);
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}
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void GPDMA1_Channel4_IRQHandler(void) {
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dma_utils_irq_handler(4);
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stm_dma_irq_handler(4);
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}
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void GPDMA1_Channel5_IRQHandler(void) {
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dma_utils_irq_handler(5);
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stm_dma_irq_handler(5);
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}
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void GPDMA1_Channel6_IRQHandler(void) {
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dma_utils_irq_handler(6);
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stm_dma_irq_handler(6);
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}
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void GPDMA1_Channel7_IRQHandler(void) {
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dma_utils_irq_handler(7);
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stm_dma_irq_handler(7);
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}
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void GPDMA1_Channel8_IRQHandler(void) {
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dma_utils_irq_handler(8);
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stm_dma_irq_handler(8);
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}
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void GPDMA1_Channel9_IRQHandler(void) {
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dma_utils_irq_handler(9);
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stm_dma_irq_handler(9);
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}
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void GPDMA1_Channel10_IRQHandler(void) {
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dma_utils_irq_handler(10);
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stm_dma_irq_handler(10);
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}
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void GPDMA1_Channel11_IRQHandler(void) {
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dma_utils_irq_handler(11);
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stm_dma_irq_handler(11);
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}
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void GPDMA1_Channel12_IRQHandler(void) {
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dma_utils_irq_handler(12);
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stm_dma_irq_handler(12);
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}
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void GPDMA1_Channel13_IRQHandler(void) {
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dma_utils_irq_handler(13);
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stm_dma_irq_handler(13);
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}
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void GPDMA1_Channel14_IRQHandler(void) {
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dma_utils_irq_handler(14);
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stm_dma_irq_handler(14);
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}
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void GPDMA1_Channel15_IRQHandler(void) {
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dma_utils_irq_handler(15);
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stm_dma_irq_handler(15);
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}
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void HPDMA1_Channel0_IRQHandler(void) {
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dma_utils_irq_handler(16);
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stm_dma_irq_handler(16);
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}
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void HPDMA1_Channel1_IRQHandler(void) {
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dma_utils_irq_handler(17);
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stm_dma_irq_handler(17);
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}
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void HPDMA1_Channel2_IRQHandler(void) {
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dma_utils_irq_handler(18);
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stm_dma_irq_handler(18);
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}
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void HPDMA1_Channel3_IRQHandler(void) {
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dma_utils_irq_handler(19);
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stm_dma_irq_handler(19);
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}
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void HPDMA1_Channel4_IRQHandler(void) {
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dma_utils_irq_handler(20);
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stm_dma_irq_handler(20);
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}
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void HPDMA1_Channel5_IRQHandler(void) {
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dma_utils_irq_handler(21);
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stm_dma_irq_handler(21);
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}
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void HPDMA1_Channel6_IRQHandler(void) {
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dma_utils_irq_handler(22);
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stm_dma_irq_handler(22);
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}
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void HPDMA1_Channel7_IRQHandler(void) {
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dma_utils_irq_handler(23);
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stm_dma_irq_handler(23);
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}
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void HPDMA1_Channel8_IRQHandler(void) {
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dma_utils_irq_handler(24);
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stm_dma_irq_handler(24);
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}
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void HPDMA1_Channel9_IRQHandler(void) {
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dma_utils_irq_handler(25);
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stm_dma_irq_handler(25);
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}
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void HPDMA1_Channel10_IRQHandler(void) {
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dma_utils_irq_handler(26);
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stm_dma_irq_handler(26);
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}
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void HPDMA1_Channel11_IRQHandler(void) {
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dma_utils_irq_handler(27);
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stm_dma_irq_handler(27);
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}
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void HPDMA1_Channel12_IRQHandler(void) {
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dma_utils_irq_handler(28);
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stm_dma_irq_handler(28);
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}
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void HPDMA1_Channel13_IRQHandler(void) {
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dma_utils_irq_handler(29);
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stm_dma_irq_handler(29);
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}
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void HPDMA1_Channel14_IRQHandler(void) {
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dma_utils_irq_handler(30);
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stm_dma_irq_handler(30);
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}
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void HPDMA1_Channel15_IRQHandler(void) {
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dma_utils_irq_handler(31);
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stm_dma_irq_handler(31);
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}
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#endif
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@ -23,16 +23,10 @@
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*
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* STM32 DMA helper functions.
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*/
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#ifndef __DMA_UTILS_H__
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#define __DMA_UTILS_H__
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#ifdef MDMA
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#define MDMA_CHAN_TO_INSTANCE(x) \
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(MDMA_Channel_TypeDef *) (MDMA_Channel0_BASE + ((MDMA_Channel1_BASE - MDMA_Channel0_BASE) * x))
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#endif
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uint8_t dma_utils_channel_to_irqn(void *dma_channel);
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uint8_t dma_utils_channel_to_id(void *dma_channel);
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int dma_utils_set_irq_descr(void *dma_channel, DMA_HandleTypeDef *dma_descr);
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uint8_t dma_utils_mpu_region_size(uint32_t size);
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#endif // __DMA_UTILS_H__
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#ifndef __STM_DMA_H__
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#define __STM_DMA_H__
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uint8_t stm_dma_channel_to_irqn(void *dma_channel);
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uint8_t stm_dma_channel_to_id(void *dma_channel);
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int stm_dma_set_irq_descr(void *dma_channel, DMA_HandleTypeDef *dma_descr);
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uint8_t stm_dma_mpu_region_size(uint32_t size);
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#endif // __STM_DMA_H__
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@ -32,7 +32,7 @@
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// Define pin objects in this file.
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#define OMV_GPIO_DEFINE_PINS (1)
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#include "omv_gpio.h"
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#include "dma_utils.h"
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#include "stm_dma.h"
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#if defined(MPU_REGION_NUMBER15)
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#define MPU_REGION_NUMBER_MAX (MPU_REGION_NUMBER15)
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@ -116,7 +116,7 @@ void HAL_MspInit(void) {
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MPU_InitStruct.Number = region_number--;
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MPU_InitStruct.Enable = MPU_REGION_ENABLE;
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MPU_InitStruct.BaseAddress = buf->addr;
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MPU_InitStruct.Size = dma_utils_mpu_region_size(buf->size);
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MPU_InitStruct.Size = stm_dma_mpu_region_size(buf->size);
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HAL_MPU_ConfigRegion(&MPU_InitStruct);
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}
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}
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@ -32,7 +32,7 @@
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#include STM32_HAL_H
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#include "irq.h"
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#include "dma_utils.h"
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#include "stm_dma.h"
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#define JPEG_CODEC_TIMEOUT (1000)
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#define JPEG_ALLOC_PADDING ((__SCB_DCACHE_LINE_SIZE) * 4)
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@ -36,6 +36,7 @@
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#include STM32_HAL_H
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#include "omv_boardconfig.h"
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#include "stm_xspi.h"
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#if defined(OMV_XSPI_PSRAM_ID)
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@ -164,7 +165,7 @@ static int xspi_psram_memory_map(XSPI_HandleTypeDef *xspi, uint32_t burst_enable
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return 0;
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}
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int xspi_psram_init() {
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int stm_xspi_psram_init(void) {
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uint32_t xspi_clk = 0;
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// Reset and enable XSPI clock.
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@ -225,7 +226,7 @@ extern void __fatal_error(const char *msg);
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#pragma GCC diagnostic ignored "-Wstringop-overflow"
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#endif
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bool __attribute__((optimize("Os"))) xspi_psram_test(bool exhaustive) {
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bool __attribute__((optimize("Os"))) stm_xspi_psram_test(bool exhaustive) {
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uint8_t const pattern = 0xaa;
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uint8_t const antipattern = 0x55;
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volatile uint8_t *const mem_base = (uint8_t *) 0x90000000;
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@ -30,7 +30,7 @@
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*
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* STM32 XSPI PSRAM driver.
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*/
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#ifndef __XSPI_PSRAM_H__
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int xspi_psram_init();
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bool xspi_psram_test(bool exhaustive);
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#endif // __XSPI_PSRAM_H__
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#ifndef __STM_XSPI_H__
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int stm_xspi_psram_init();
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bool stm_xspi_psram_test(bool exhaustive);
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#endif // __STM_XSPI_H__
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