Merge pull request #2480 from openmv/stm32_system

hal/stm32: Clean up system file.
This commit is contained in:
Ibrahim Abdelkader 2024-11-03 20:27:32 +02:00 committed by GitHub
commit 9582ba159b
No known key found for this signature in database
GPG Key ID: B5690EEEBB952194

View File

@ -1,156 +1,117 @@
/**
******************************************************************************
* @file system_stm32f4xx.c
* @author MCD Application Team
* @version V2.0.0
* @date 18-February-2014
* @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File.
*
* This file provides two functions and one global variable to be called from
* user application:
* - SystemInit(): This function is called at startup just after reset and
* before branch to main program. This call is made inside
* the "startup_stm32f4xx.s" file.
*
* - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
* by the user application to setup the SysTick
* timer or configure other parameters.
*
* - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
* be called whenever the core clock is changed
* during program execution.
*
*
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/*
* SPDX-License-Identifier: MIT
*
* Copyright (C) 2013-2024 OpenMV, LLC.
* Copyright (c) 2013-2024 STMicroelectronics.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*
* STM32 system initialization code.
*/
#include STM32_HAL_H
#include "omv_boardconfig.h"
/** This variable is updated in two ways:
* 1) by calling HAL API function HAL_RCC_GetHCLKFreq()
* 2) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
*/
uint32_t SystemCoreClock = 16000000;
extern void __fatal_error(const char *msg);
// This variable is updated in two ways:
// 1) by calling HAL API function HAL_RCC_GetHCLKFreq()
// 2) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
uint32_t SystemCoreClock = HSI_VALUE;
#if defined(STM32H7)
#define SRAM_BASE D1_AXISRAM_BASE
#define FLASH_BASE FLASH_BANK1_BASE
#define CONFIG_RCC_CR_1ST (RCC_CR_HSION)
#define CONFIG_RCC_CR_2ND (0xEAF6ED7F)
#define CONFIG_RCC_PLLCFGR (0x00000000)
uint32_t SystemD2Clock = 64000000;
const uint8_t D1CorePrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9};
#elif defined(STM32F4) || defined(STM32F7)
#define CONFIG_RCC_CR_1ST (RCC_CR_HSION)
#define CONFIG_RCC_CR_2ND (0xFEF6FFFF)
#define CONFIG_RCC_PLLCFGR (0x24003010)
const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4};
const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
#endif
/**
* @brief Setup the microcontroller system
* Initialize the FPU setting, vector table location and External memory
* configuration.
* @param None
* @retval None
*/
void SystemInit(void)
{
/* FPU settings ------------------------------------------------------------*/
extern void __fatal_error(const char *msg);
void SystemInit(void) {
// Configure IRQ vector table address.
SCB->VTOR = OMV_VTOR_BASE;
// FPU settings
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
SCB->CPACR |= ((3UL << 20U)|(3UL << 22U)); // Set CP10 and CP11 Full Access
#endif
/*SEVONPEND enabled so that an interrupt coming from the CPU(n) interrupt
signal is detectable by the CPU after a WFI/WFE instruction. */
#if defined(STM32F4) || defined(STM32F7) || defined(STM32H7)
// Enable to allow other cores to interrupt during WFI/WFE.
//SCB->SCR |= SCB_SCR_SEVONPEND_Msk;
/* Reset the RCC clock configuration to the default reset state ------------*/
/* Set HSION bit */
// Set HSION bit
RCC->CR |= CONFIG_RCC_CR_1ST;
/* Reset CFGR register */
// Reset CFGR register
RCC->CFGR = 0x00000000;
/* Reset HSEON, CSSON and PLLON bits */
// Reset HSEON, CSSON and PLLON
RCC->CR &= (uint32_t) CONFIG_RCC_CR_2ND;
/* Reset PLLCFGR register */
// Reset PLLCFGR register
RCC->PLLCFGR = CONFIG_RCC_PLLCFGR;
#if defined(STM32H7)
/* Reset D1CFGR register */
// Reset D1CFGR register
RCC->D1CFGR = 0x00000000;
/* Reset D2CFGR register */
// Reset D2CFGR register
RCC->D2CFGR = 0x00000000;
/* Reset D3CFGR register */
// Reset D3CFGR register
RCC->D3CFGR = 0x00000000;
/* Reset PLLCKSELR register */
// Reset PLLCKSELR register
RCC->PLLCKSELR = 0x00000000;
/* Reset PLL1DIVR register */
// Reset PLL1DIVR register
RCC->PLL1DIVR = 0x00000000;
/* Reset PLL1FRACR register */
// Reset PLL1FRACR register
RCC->PLL1FRACR = 0x00000000;
/* Reset PLL2DIVR register */
// Reset PLL2DIVR register
RCC->PLL2DIVR = 0x00000000;
/* Reset PLL2FRACR register */
// Reset PLL2FRACR register
RCC->PLL2FRACR = 0x00000000;
/* Reset PLL3DIVR register */
// Reset PLL3DIVR register
RCC->PLL3DIVR = 0x00000000;
/* Reset PLL3FRACR register */
// Reset PLL3FRACR register
RCC->PLL3FRACR = 0x00000000;
#endif // defined(STM32H7)
/* Reset HSEBYP bit */
RCC->CR &= (uint32_t)0xFFFBFFFF;
#endif // STM32F4 || STM32F7 || STM32H7
/* Disable all interrupts */
// Disable all interrupts
#if defined(STM32F4) || defined(STM32F7)
RCC->CIR = 0x00000000;
#elif defined(STM32L4) || defined(STM32H7)
@ -158,12 +119,12 @@ void SystemInit(void)
#endif
#if defined(STM32H7)
/* Change the switch matrix read issuing capability to 1 for the AXI SRAM target (Target 7) */
// See Errata 2.2.9 "Reading from AXI SRAM may lead to data read corruption"
// Change the switch matrix read issuing capability to 1 for AXI SRAM.
// Errata 2.2.9 "Reading from AXI SRAM may lead to data read corruption"
*((__IO uint32_t*)0x51008108) = 0x00000001;
#endif // defined(STM32H7)
/* dpgeorge: enable 8-byte stack alignment for IRQ handlers, in accord with EABI */
// Enable 8-byte stack alignment for IRQ handlers, in accord with EABI
SCB->CCR |= SCB_CCR_STKALIGN_Msk;
#if !defined(NDEBUG)
@ -175,13 +136,9 @@ void SystemInit(void)
DBGMCU->CR |= DBGMCU_CR_DBG_STANDBYD1;
#endif
#endif
/* Configure the Vector Table location add offset address ------------------*/
SCB->VTOR = OMV_VTOR_BASE;
}
void SystemClock_Config(void)
{
void SystemClock_Config(void) {
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
#if defined(STM32H7)
@ -189,16 +146,14 @@ void SystemClock_Config(void)
#endif
#if defined(STM32H7)
/* Supply configuration update enable */
// Supply configuration update enable
HAL_PWREx_ConfigSupply(OMV_PWR_SUPPLY);
#else
/* Enable Power Control clock */
#elif defined(STM32F4) || defined(STM32F7)
// Enable Power Control clock
__PWR_CLK_ENABLE();
#endif
/* The voltage scaling allows optimizing the power consumption when the device is
clocked below the maximum system frequency, to update the voltage scaling value
regarding system frequency refer to product datasheet. */
// Configure voltage scaling.
#if defined(STM32H7)
// Enable VSCALE0 for revision V devices.
if (HAL_GetREVID() >= 0x2003) {
@ -224,10 +179,7 @@ void SystemClock_Config(void)
HAL_PWR_DisableBkUpAccess();
#endif
/* Macro to configure the PLL clock source */
__HAL_RCC_PLL_PLLSOURCE_CONFIG(OMV_OSC_PLL_CLKSOURCE);
/* Enable HSE Oscillator and activate PLL with HSE as source */
// Configure and enable oscillators
#if defined(OMV_OSC_LSE_STATE)
RCC_OscInitStruct.LSEState = OMV_OSC_LSE_STATE;
RCC_OscInitStruct.OscillatorType |= RCC_OSCILLATORTYPE_LSE;
@ -243,7 +195,8 @@ void SystemClock_Config(void)
#if defined(OMV_OSC_HSI_STATE)
RCC_OscInitStruct.HSIState = OMV_OSC_HSI_STATE;
RCC_OscInitStruct.OscillatorType |= RCC_OSCILLATORTYPE_HSI;
RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
RCC_OscInitStruct.HSIDiv = OMV_OSC_HSI_CAL;
RCC_OscInitStruct.HSICalibrationValue = OMV_OSC_HSI_DIV;
#endif
#if defined(OMV_OSC_CSI_STATE)
RCC_OscInitStruct.CSIState = OMV_OSC_CSI_STATE;
@ -391,7 +344,7 @@ void SystemClock_Config(void)
}
#endif
/* Select PLL as system clock source and configure the HCLK, PCLK clocks dividers */
// Configure CPU and System bus clock source.
#if defined(STM32H7)
RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_D1PCLK1 |
RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2 | RCC_CLOCKTYPE_D3PCLK1);
@ -402,8 +355,9 @@ void SystemClock_Config(void)
RCC_ClkInitStruct.APB2CLKDivider = RCC_APB2_DIV2;
RCC_ClkInitStruct.APB3CLKDivider = RCC_APB3_DIV2;
RCC_ClkInitStruct.APB4CLKDivider = RCC_APB4_DIV2;
#else
RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
#elif defined(STM32F4) || defined(STM32F7)
RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 |
RCC_CLOCKTYPE_PCLK2);
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4;