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Merge pull request #2480 from openmv/stm32_system
hal/stm32: Clean up system file.
This commit is contained in:
commit
9582ba159b
@ -1,156 +1,117 @@
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/**
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/*
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******************************************************************************
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* SPDX-License-Identifier: MIT
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* @file system_stm32f4xx.c
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*
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* @author MCD Application Team
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* Copyright (C) 2013-2024 OpenMV, LLC.
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* @version V2.0.0
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* Copyright (c) 2013-2024 STMicroelectronics.
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* @date 18-February-2014
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*
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* @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File.
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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*
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* of this software and associated documentation files (the "Software"), to deal
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* This file provides two functions and one global variable to be called from
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* in the Software without restriction, including without limitation the rights
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* user application:
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* - SystemInit(): This function is called at startup just after reset and
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* copies of the Software, and to permit persons to whom the Software is
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* before branch to main program. This call is made inside
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* furnished to do so, subject to the following conditions:
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* the "startup_stm32f4xx.s" file.
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*
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*
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* The above copyright notice and this permission notice shall be included in
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* - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
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* all copies or substantial portions of the Software.
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* by the user application to setup the SysTick
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*
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* timer or configure other parameters.
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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*
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* be called whenever the core clock is changed
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* during program execution.
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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*
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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*
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* THE SOFTWARE.
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******************************************************************************
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*
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* @attention
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* STM32 system initialization code.
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*
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*/
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* <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
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*
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted provided that the following conditions are met:
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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* 3. Neither the name of STMicroelectronics nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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******************************************************************************
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*/
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#include STM32_HAL_H
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#include STM32_HAL_H
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#include "omv_boardconfig.h"
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#include "omv_boardconfig.h"
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/** This variable is updated in two ways:
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// This variable is updated in two ways:
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* 1) by calling HAL API function HAL_RCC_GetHCLKFreq()
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// 1) by calling HAL API function HAL_RCC_GetHCLKFreq()
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* 2) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
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// 2) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
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*/
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uint32_t SystemCoreClock = HSI_VALUE;
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uint32_t SystemCoreClock = 16000000;
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extern void __fatal_error(const char *msg);
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#if defined(STM32H7)
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#if defined(STM32H7)
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#define SRAM_BASE D1_AXISRAM_BASE
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#define FLASH_BASE FLASH_BANK1_BASE
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#define CONFIG_RCC_CR_1ST (RCC_CR_HSION)
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#define CONFIG_RCC_CR_1ST (RCC_CR_HSION)
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#define CONFIG_RCC_CR_2ND (0xEAF6ED7F)
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#define CONFIG_RCC_CR_2ND (0xEAF6ED7F)
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#define CONFIG_RCC_PLLCFGR (0x00000000)
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#define CONFIG_RCC_PLLCFGR (0x00000000)
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uint32_t SystemD2Clock = 64000000;
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uint32_t SystemD2Clock = 64000000;
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const uint8_t D1CorePrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9};
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const uint8_t D1CorePrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9};
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#elif defined(STM32F4) || defined(STM32F7)
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#elif defined(STM32F4) || defined(STM32F7)
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#define CONFIG_RCC_CR_1ST (RCC_CR_HSION)
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#define CONFIG_RCC_CR_1ST (RCC_CR_HSION)
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#define CONFIG_RCC_CR_2ND (0xFEF6FFFF)
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#define CONFIG_RCC_CR_2ND (0xFEF6FFFF)
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#define CONFIG_RCC_PLLCFGR (0x24003010)
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#define CONFIG_RCC_PLLCFGR (0x24003010)
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const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4};
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const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4};
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const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
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const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
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#endif
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#endif
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/**
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extern void __fatal_error(const char *msg);
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* @brief Setup the microcontroller system
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* Initialize the FPU setting, vector table location and External memory
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void SystemInit(void) {
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* configuration.
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// Configure IRQ vector table address.
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* @param None
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SCB->VTOR = OMV_VTOR_BASE;
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* @retval None
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*/
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// FPU settings
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void SystemInit(void)
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{
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/* FPU settings ------------------------------------------------------------*/
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#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
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#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
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SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
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SCB->CPACR |= ((3UL << 20U)|(3UL << 22U)); // Set CP10 and CP11 Full Access
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#endif
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#endif
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/*SEVONPEND enabled so that an interrupt coming from the CPU(n) interrupt
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#if defined(STM32F4) || defined(STM32F7) || defined(STM32H7)
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signal is detectable by the CPU after a WFI/WFE instruction. */
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// Enable to allow other cores to interrupt during WFI/WFE.
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//SCB->SCR |= SCB_SCR_SEVONPEND_Msk;
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//SCB->SCR |= SCB_SCR_SEVONPEND_Msk;
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/* Reset the RCC clock configuration to the default reset state ------------*/
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// Set HSION bit
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/* Set HSION bit */
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RCC->CR |= CONFIG_RCC_CR_1ST;
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RCC->CR |= CONFIG_RCC_CR_1ST;
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/* Reset CFGR register */
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// Reset CFGR register
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RCC->CFGR = 0x00000000;
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RCC->CFGR = 0x00000000;
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/* Reset HSEON, CSSON and PLLON bits */
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// Reset HSEON, CSSON and PLLON
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RCC->CR &= (uint32_t) CONFIG_RCC_CR_2ND;
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RCC->CR &= (uint32_t) CONFIG_RCC_CR_2ND;
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/* Reset PLLCFGR register */
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// Reset PLLCFGR register
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RCC->PLLCFGR = CONFIG_RCC_PLLCFGR;
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RCC->PLLCFGR = CONFIG_RCC_PLLCFGR;
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#if defined(STM32H7)
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#if defined(STM32H7)
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/* Reset D1CFGR register */
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// Reset D1CFGR register
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RCC->D1CFGR = 0x00000000;
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RCC->D1CFGR = 0x00000000;
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/* Reset D2CFGR register */
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// Reset D2CFGR register
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RCC->D2CFGR = 0x00000000;
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RCC->D2CFGR = 0x00000000;
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/* Reset D3CFGR register */
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// Reset D3CFGR register
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RCC->D3CFGR = 0x00000000;
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RCC->D3CFGR = 0x00000000;
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/* Reset PLLCKSELR register */
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// Reset PLLCKSELR register
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RCC->PLLCKSELR = 0x00000000;
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RCC->PLLCKSELR = 0x00000000;
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/* Reset PLL1DIVR register */
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// Reset PLL1DIVR register
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RCC->PLL1DIVR = 0x00000000;
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RCC->PLL1DIVR = 0x00000000;
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/* Reset PLL1FRACR register */
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// Reset PLL1FRACR register
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RCC->PLL1FRACR = 0x00000000;
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RCC->PLL1FRACR = 0x00000000;
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/* Reset PLL2DIVR register */
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// Reset PLL2DIVR register
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RCC->PLL2DIVR = 0x00000000;
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RCC->PLL2DIVR = 0x00000000;
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/* Reset PLL2FRACR register */
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// Reset PLL2FRACR register
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RCC->PLL2FRACR = 0x00000000;
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RCC->PLL2FRACR = 0x00000000;
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/* Reset PLL3DIVR register */
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// Reset PLL3DIVR register
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RCC->PLL3DIVR = 0x00000000;
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RCC->PLL3DIVR = 0x00000000;
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/* Reset PLL3FRACR register */
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// Reset PLL3FRACR register
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RCC->PLL3FRACR = 0x00000000;
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RCC->PLL3FRACR = 0x00000000;
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#endif // defined(STM32H7)
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#endif // defined(STM32H7)
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/* Reset HSEBYP bit */
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/* Reset HSEBYP bit */
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RCC->CR &= (uint32_t)0xFFFBFFFF;
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RCC->CR &= (uint32_t)0xFFFBFFFF;
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#endif // STM32F4 || STM32F7 || STM32H7
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/* Disable all interrupts */
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// Disable all interrupts
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#if defined(STM32F4) || defined(STM32F7)
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#if defined(STM32F4) || defined(STM32F7)
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RCC->CIR = 0x00000000;
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RCC->CIR = 0x00000000;
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#elif defined(STM32L4) || defined(STM32H7)
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#elif defined(STM32L4) || defined(STM32H7)
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@ -158,12 +119,12 @@ void SystemInit(void)
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#endif
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#endif
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#if defined(STM32H7)
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#if defined(STM32H7)
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/* Change the switch matrix read issuing capability to 1 for the AXI SRAM target (Target 7) */
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// Change the switch matrix read issuing capability to 1 for AXI SRAM.
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// See Errata 2.2.9 "Reading from AXI SRAM may lead to data read corruption"
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// Errata 2.2.9 "Reading from AXI SRAM may lead to data read corruption"
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*((__IO uint32_t*)0x51008108) = 0x00000001;
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*((__IO uint32_t*)0x51008108) = 0x00000001;
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#endif // defined(STM32H7)
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#endif // defined(STM32H7)
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/* dpgeorge: enable 8-byte stack alignment for IRQ handlers, in accord with EABI */
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// Enable 8-byte stack alignment for IRQ handlers, in accord with EABI
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SCB->CCR |= SCB_CCR_STKALIGN_Msk;
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SCB->CCR |= SCB_CCR_STKALIGN_Msk;
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#if !defined(NDEBUG)
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#if !defined(NDEBUG)
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@ -175,13 +136,9 @@ void SystemInit(void)
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DBGMCU->CR |= DBGMCU_CR_DBG_STANDBYD1;
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DBGMCU->CR |= DBGMCU_CR_DBG_STANDBYD1;
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#endif
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#endif
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#endif
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#endif
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/* Configure the Vector Table location add offset address ------------------*/
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SCB->VTOR = OMV_VTOR_BASE;
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}
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}
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void SystemClock_Config(void)
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void SystemClock_Config(void) {
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{
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RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
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RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
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RCC_OscInitTypeDef RCC_OscInitStruct = {0};
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RCC_OscInitTypeDef RCC_OscInitStruct = {0};
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#if defined(STM32H7)
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#if defined(STM32H7)
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@ -189,16 +146,14 @@ void SystemClock_Config(void)
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#endif
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#endif
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#if defined(STM32H7)
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#if defined(STM32H7)
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/* Supply configuration update enable */
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// Supply configuration update enable
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HAL_PWREx_ConfigSupply(OMV_PWR_SUPPLY);
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HAL_PWREx_ConfigSupply(OMV_PWR_SUPPLY);
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#else
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#elif defined(STM32F4) || defined(STM32F7)
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/* Enable Power Control clock */
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// Enable Power Control clock
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__PWR_CLK_ENABLE();
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__PWR_CLK_ENABLE();
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#endif
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#endif
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/* The voltage scaling allows optimizing the power consumption when the device is
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// Configure voltage scaling.
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clocked below the maximum system frequency, to update the voltage scaling value
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regarding system frequency refer to product datasheet. */
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#if defined(STM32H7)
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#if defined(STM32H7)
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// Enable VSCALE0 for revision V devices.
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// Enable VSCALE0 for revision V devices.
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if (HAL_GetREVID() >= 0x2003) {
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if (HAL_GetREVID() >= 0x2003) {
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@ -224,10 +179,7 @@ void SystemClock_Config(void)
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HAL_PWR_DisableBkUpAccess();
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HAL_PWR_DisableBkUpAccess();
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#endif
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#endif
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/* Macro to configure the PLL clock source */
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// Configure and enable oscillators
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__HAL_RCC_PLL_PLLSOURCE_CONFIG(OMV_OSC_PLL_CLKSOURCE);
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/* Enable HSE Oscillator and activate PLL with HSE as source */
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#if defined(OMV_OSC_LSE_STATE)
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#if defined(OMV_OSC_LSE_STATE)
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RCC_OscInitStruct.LSEState = OMV_OSC_LSE_STATE;
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RCC_OscInitStruct.LSEState = OMV_OSC_LSE_STATE;
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RCC_OscInitStruct.OscillatorType |= RCC_OSCILLATORTYPE_LSE;
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RCC_OscInitStruct.OscillatorType |= RCC_OSCILLATORTYPE_LSE;
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@ -243,7 +195,8 @@ void SystemClock_Config(void)
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#if defined(OMV_OSC_HSI_STATE)
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#if defined(OMV_OSC_HSI_STATE)
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RCC_OscInitStruct.HSIState = OMV_OSC_HSI_STATE;
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RCC_OscInitStruct.HSIState = OMV_OSC_HSI_STATE;
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RCC_OscInitStruct.OscillatorType |= RCC_OSCILLATORTYPE_HSI;
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RCC_OscInitStruct.OscillatorType |= RCC_OSCILLATORTYPE_HSI;
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RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
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RCC_OscInitStruct.HSIDiv = OMV_OSC_HSI_CAL;
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RCC_OscInitStruct.HSICalibrationValue = OMV_OSC_HSI_DIV;
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#endif
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#endif
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#if defined(OMV_OSC_CSI_STATE)
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#if defined(OMV_OSC_CSI_STATE)
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RCC_OscInitStruct.CSIState = OMV_OSC_CSI_STATE;
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RCC_OscInitStruct.CSIState = OMV_OSC_CSI_STATE;
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@ -391,7 +344,7 @@ void SystemClock_Config(void)
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}
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}
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#endif
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#endif
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/* Select PLL as system clock source and configure the HCLK, PCLK clocks dividers */
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// Configure CPU and System bus clock source.
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#if defined(STM32H7)
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#if defined(STM32H7)
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RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_D1PCLK1 |
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RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_D1PCLK1 |
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RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2 | RCC_CLOCKTYPE_D3PCLK1);
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RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2 | RCC_CLOCKTYPE_D3PCLK1);
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@ -402,8 +355,9 @@ void SystemClock_Config(void)
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RCC_ClkInitStruct.APB2CLKDivider = RCC_APB2_DIV2;
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RCC_ClkInitStruct.APB2CLKDivider = RCC_APB2_DIV2;
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RCC_ClkInitStruct.APB3CLKDivider = RCC_APB3_DIV2;
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RCC_ClkInitStruct.APB3CLKDivider = RCC_APB3_DIV2;
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RCC_ClkInitStruct.APB4CLKDivider = RCC_APB4_DIV2;
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RCC_ClkInitStruct.APB4CLKDivider = RCC_APB4_DIV2;
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#else
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#elif defined(STM32F4) || defined(STM32F7)
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RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
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RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 |
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RCC_CLOCKTYPE_PCLK2);
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RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
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RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
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RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
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RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
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RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4;
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RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4;
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