diff --git a/src/cmsis/src/st/system_stm32f4xx.c b/src/cmsis/src/st/system_stm32f4xx.c index 187642ae1..93f6871dd 100644 --- a/src/cmsis/src/st/system_stm32f4xx.c +++ b/src/cmsis/src/st/system_stm32f4xx.c @@ -540,23 +540,24 @@ void SystemClock_Config(void) RCC_OscInitStruct.HSEState = RCC_HSE_ON; RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; - RCC_OscInitStruct.PLL.PLLM = HSE_VALUE/1000000; -#ifdef STM32F429xx +#ifdef STM32F407xx // 180MHz/48MHz + RCC_OscInitStruct.PLL.PLLM = 12; RCC_OscInitStruct.PLL.PLLN = 336; -#else - RCC_OscInitStruct.PLL.PLLN = 336; -#endif - RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; RCC_OscInitStruct.PLL.PLLQ = 7; - if(HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) - { + RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; +#else// 168MHz/48MHz + RCC_OscInitStruct.PLL.PLLM = 6; + RCC_OscInitStruct.PLL.PLLN = 360; + RCC_OscInitStruct.PLL.PLLQ = 15; + RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV4; +#endif //STM32F407xx + if(HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { /* Initialization Error */ Error_Handler(); } #ifdef STM32F429xx - if(HAL_PWREx_ActivateOverDrive() != HAL_OK) - { + if(HAL_PWREx_ActivateOverDrive() != HAL_OK) { /* Initialization Error */ Error_Handler(); } @@ -568,8 +569,7 @@ void SystemClock_Config(void) RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4; RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2; - if(HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5) != HAL_OK) - { + if(HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5) != HAL_OK) { /* Initialization Error */ Error_Handler(); }