From 99dc3365b6ef31bf2baa99a1ed6c72e28cd49762 Mon Sep 17 00:00:00 2001 From: iabdalkader Date: Sat, 10 Mar 2018 20:17:36 +0200 Subject: [PATCH] Update H7 CMSIS headers. --- src/cmsis/include/st/stm32h743xx.h | 882 ++++++++++++++++++----------- src/cmsis/include/st/stm32h7xx.h | 20 +- 2 files changed, 575 insertions(+), 327 deletions(-) diff --git a/src/cmsis/include/st/stm32h743xx.h b/src/cmsis/include/st/stm32h743xx.h index a90469405..8df344463 100644 --- a/src/cmsis/include/st/stm32h743xx.h +++ b/src/cmsis/include/st/stm32h743xx.h @@ -2,14 +2,14 @@ ****************************************************************************** * @file stm32h743xx.h * @author MCD Application Team - * @version V1.1.0 - * @date 31-August-2017 + * @version V1.2.0 + * @date 29-December-2017 * @brief CMSIS STM32H743xx Device Peripheral Access Layer Header File. * * This file contains: * - Data structures and the address mapping for all peripherals * - Peripheral's registers declarations and bits definition - * - Macros to access peripheral’s registers hardware + * - Macros to access peripheral's registers hardware * ****************************************************************************** * @attention @@ -49,8 +49,8 @@ * @{ */ -#ifndef __STM32H743xx_H -#define __STM32H743xx_H +#ifndef STM32H743xx_H +#define STM32H743xx_H #ifdef __cplusplus extern "C" { @@ -212,7 +212,7 @@ typedef enum LPTIM4_IRQn = 140, /*!< LP TIM4 global interrupt */ LPTIM5_IRQn = 141, /*!< LP TIM5 global interrupt */ LPUART1_IRQn = 142, /*!< LP UART1 interrupt */ - CRS_IRQn = 144, /*!< Clock Recovery Global Interrupt */ + CRS_IRQn = 144, /*!< Clock Recovery Global Interrupt */ SAI4_IRQn = 146, /*!< SAI4 global interrupt */ WAKEUP_PIN_IRQn = 149, /*!< Interrupt for all 6 wake-up pins */ } IRQn_Type; @@ -536,7 +536,6 @@ typedef struct /** * @brief Debug MCU */ - typedef struct { __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ @@ -552,7 +551,6 @@ typedef struct uint32_t RESERVED8; /*!< Reserved, Address offset: 0x50 */ __IO uint32_t APB4FZ1; /*!< Debug MCU APB4FZ1 freeze register, Address offset: 0x54 */ }DBGMCU_TypeDef; - /** * @brief DCMI */ @@ -912,49 +910,49 @@ __IO uint32_t PR3; /*!< EXTI Pending register, typedef struct { - __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */ - __IO uint32_t KEYR1; /*!< Flash Key Register for bank1, Address offset: 0x04 */ - __IO uint32_t OPTKEYR; /*!< Flash Option Key Register, Address offset: 0x08 */ - __IO uint32_t CR1; /*!< Flash Control Register for bank1, Address offset: 0x0C */ - __IO uint32_t SR1; /*!< Flash Status Register for bank1, Address offset: 0x10 */ - __IO uint32_t CCR1; /*!< Flash Control Register for bank1, Address offset: 0x14 */ - __IO uint32_t OPTCR; /*!< Flash Option Control Register, Address offset: 0x18 */ + __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */ + __IO uint32_t KEYR1; /*!< Flash Key Register for bank1, Address offset: 0x04 */ + __IO uint32_t OPTKEYR; /*!< Flash Option Key Register, Address offset: 0x08 */ + __IO uint32_t CR1; /*!< Flash Control Register for bank1, Address offset: 0x0C */ + __IO uint32_t SR1; /*!< Flash Status Register for bank1, Address offset: 0x10 */ + __IO uint32_t CCR1; /*!< Flash Control Register for bank1, Address offset: 0x14 */ + __IO uint32_t OPTCR; /*!< Flash Option Control Register, Address offset: 0x18 */ __IO uint32_t OPTSR_CUR; /*!< Flash Option Status Current Register, Address offset: 0x1C */ __IO uint32_t OPTSR_PRG; /*!< Flash Option Status Current Register, Address offset: 0x20 */ __IO uint32_t OPTCCR; /*!< Flash Option Clear Control Register, Address offset: 0x24 */ - __IO uint32_t PRAR_CUR1; /*!< Flash Current Protection Address Register for bank1, Address offset: 0x28 */ - __IO uint32_t PRAR_PRG1; /*!< Flash Protection Address to Program Register for bank1, Address offset: 0x2C */ - __IO uint32_t SCAR_CUR1; /*!< Flash Current Secure Address Register for bank1, Address offset: 0x30 */ - __IO uint32_t SCAR_PRG1; /*!< Flash Secure Address Register for bank1, Address offset: 0x34 */ - __IO uint32_t WPSN_CUR1; /*!< Flash Current Write Protection Register on bank1, Address offset: 0x38 */ - __IO uint32_t WPSN_PRG1; /*!< Flash Write Protection to Program Register on bank1, Address offset: 0x3C */ - __IO uint32_t BOOT_CUR; /*!< Flash Current Boot Address for Pelican Core Register, Address offset: 0x40 */ - __IO uint32_t BOOT_PRG; /*!< Flash Boot Address to Program for Pelican Core Register, Address offset: 0x44 */ - uint32_t RESERVED0[2]; /*!< Reserved, 0x48 to 0x4C */ - __IO uint32_t CRCCR1; /*!< Flash CRC Control register For Bank1 Register , Address offset: 0x50 */ - __IO uint32_t CRCSADD1; /*!< Flash CRC Start Address Register for Bank1 , Address offset: 0x54 */ - __IO uint32_t CRCEADD1; /*!< Flash CRC End Address Register for Bank1 , Address offset: 0x58 */ - __IO uint32_t CRCDATA; /*!< Flash CRC Data Register for Bank1 , Address offset: 0x5C */ - __IO uint32_t ECC_FA1; /*!< Flash ECC Fail Address For Bank1 Register , Address offset: 0x60 */ - uint32_t RESERVED1[40]; /*!< Reserved, 0x64 to 0x100 */ - __IO uint32_t KEYR2; /*!< Flash Key Register for bank2, Address offset: 0x104 */ - uint32_t RESERVED2; /*!< Reserved, 0x108 */ - __IO uint32_t CR2; /*!< Flash Control Register for bank2, Address offset: 0x10C */ - __IO uint32_t SR2; /*!< Flash Status Register for bank2, Address offset: 0x110 */ - __IO uint32_t CCR2; /*!< Flash Status Register for bank2, Address offset: 0x114 */ - uint32_t RESERVED3[4]; /*!< Reserved, 0x118 to 0x124 */ - __IO uint32_t PRAR_CUR2; /*!< Flash Current Protection Address Register for bank2, Address offset: 0x128 */ - __IO uint32_t PRAR_PRG2; /*!< Flash Protection Address to Program Register for bank2, Address offset: 0x12C */ - __IO uint32_t SCAR_CUR2; /*!< Flash Current Secure Address Register for bank2, Address offset: 0x130 */ - __IO uint32_t SCAR_PRG2; /*!< Flash Secure Address Register for bank2, Address offset: 0x134 */ - __IO uint32_t WPSN_CUR2; /*!< Flash Current Write Protection Register on bank2, Address offset: 0x138 */ - __IO uint32_t WPSN_PRG2; /*!< Flash Write Protection to Program Register on bank2, Address offset: 0x13C */ - uint32_t RESERVED4[4]; /*!< Reserved, 0x140 to 0x14C */ - __IO uint32_t CRCCR2; /*!< Flash CRC Control register For Bank2 Register , Address offset: 0x150 */ - __IO uint32_t CRCSADD2; /*!< Flash CRC Start Address Register for Bank2 , Address offset: 0x154 */ - __IO uint32_t CRCEADD2; /*!< Flash CRC End Address Register for Bank2 , Address offset: 0x158 */ - __IO uint32_t CRCDATA2; /*!< Flash CRC Data Register for Bank2 , Address offset: 0x15C */ - __IO uint32_t ECC_FA2; /*!< Flash ECC Fail Address For Bank2 Register , Address offset: 0x160 */ + __IO uint32_t PRAR_CUR1; /*!< Flash Current Protection Address Register for bank1, Address offset: 0x28 */ + __IO uint32_t PRAR_PRG1; /*!< Flash Protection Address to Program Register for bank1, Address offset: 0x2C */ + __IO uint32_t SCAR_CUR1; /*!< Flash Current Secure Address Register for bank1, Address offset: 0x30 */ + __IO uint32_t SCAR_PRG1; /*!< Flash Secure Address Register for bank1, Address offset: 0x34 */ + __IO uint32_t WPSN_CUR1; /*!< Flash Current Write Protection Register on bank1, Address offset: 0x38 */ + __IO uint32_t WPSN_PRG1; /*!< Flash Write Protection to Program Register on bank1, Address offset: 0x3C */ + __IO uint32_t BOOT_CUR; /*!< Flash Current Boot Address for Pelican Core Register, Address offset: 0x40 */ + __IO uint32_t BOOT_PRG; /*!< Flash Boot Address to Program for Pelican Core Register, Address offset: 0x44 */ + uint32_t RESERVED0[2]; /*!< Reserved, 0x48 to 0x4C */ + __IO uint32_t CRCCR1; /*!< Flash CRC Control register For Bank1 Register , Address offset: 0x50 */ + __IO uint32_t CRCSADD1; /*!< Flash CRC Start Address Register for Bank1 , Address offset: 0x54 */ + __IO uint32_t CRCEADD1; /*!< Flash CRC End Address Register for Bank1 , Address offset: 0x58 */ + __IO uint32_t CRCDATA; /*!< Flash CRC Data Register for Bank1 , Address offset: 0x5C */ + __IO uint32_t ECC_FA1; /*!< Flash ECC Fail Address For Bank1 Register , Address offset: 0x60 */ + uint32_t RESERVED1[40]; /*!< Reserved, 0x64 to 0x100 */ + __IO uint32_t KEYR2; /*!< Flash Key Register for bank2, Address offset: 0x104 */ + uint32_t RESERVED2; /*!< Reserved, 0x108 */ + __IO uint32_t CR2; /*!< Flash Control Register for bank2, Address offset: 0x10C */ + __IO uint32_t SR2; /*!< Flash Status Register for bank2, Address offset: 0x110 */ + __IO uint32_t CCR2; /*!< Flash Status Register for bank2, Address offset: 0x114 */ + uint32_t RESERVED3[4]; /*!< Reserved, 0x118 to 0x124 */ + __IO uint32_t PRAR_CUR2; /*!< Flash Current Protection Address Register for bank2, Address offset: 0x128 */ + __IO uint32_t PRAR_PRG2; /*!< Flash Protection Address to Program Register for bank2, Address offset: 0x12C */ + __IO uint32_t SCAR_CUR2; /*!< Flash Current Secure Address Register for bank2, Address offset: 0x130 */ + __IO uint32_t SCAR_PRG2; /*!< Flash Secure Address Register for bank2, Address offset: 0x134 */ + __IO uint32_t WPSN_CUR2; /*!< Flash Current Write Protection Register on bank2, Address offset: 0x138 */ + __IO uint32_t WPSN_PRG2; /*!< Flash Write Protection to Program Register on bank2, Address offset: 0x13C */ + uint32_t RESERVED4[4]; /*!< Reserved, 0x140 to 0x14C */ + __IO uint32_t CRCCR2; /*!< Flash CRC Control register For Bank2 Register , Address offset: 0x150 */ + __IO uint32_t CRCSADD2; /*!< Flash CRC Start Address Register for Bank2 , Address offset: 0x154 */ + __IO uint32_t CRCEADD2; /*!< Flash CRC End Address Register for Bank2 , Address offset: 0x158 */ + __IO uint32_t CRCDATA2; /*!< Flash CRC Data Register for Bank2 , Address offset: 0x15C */ + __IO uint32_t ECC_FA2; /*!< Flash ECC Fail Address For Bank2 Register , Address offset: 0x160 */ } FLASH_TypeDef; /** @@ -1041,8 +1039,8 @@ typedef struct typedef struct { - __IO uint32_t CSR; /*!< OPAMP control/status register, Address offset: 0x00 */ - __IO uint32_t OTR; /*!< OPAMP offset trimming register for normal mode, Address offset: 0x04 */ + __IO uint32_t CSR; /*!< OPAMP control/status register, Address offset: 0x00 */ + __IO uint32_t OTR; /*!< OPAMP offset trimming register for normal mode, Address offset: 0x04 */ __IO uint32_t HSOTR; /*!< OPAMP offset trimming register for high speed mode, Address offset: 0x08 */ } OPAMP_TypeDef; @@ -1055,7 +1053,7 @@ typedef struct uint32_t RESERVED1; /*!< Reserved, Address offset: 0x00 */ __IO uint32_t PMCR; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */ __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */ - uint32_t RESERVED2[2]; /*!< Reserved, Address offset: 0x18-0x1C */ + uint32_t RESERVED2[2]; /*!< Reserved, Address offset: 0x18-0x1C */ __IO uint32_t CCCSR; /*!< SYSCFG compensation cell control/status register, Address offset: 0x20 */ __IO uint32_t CCVR; /*!< SYSCFG compensation cell value register, Address offset: 0x24 */ __IO uint32_t CCCR; /*!< SYSCFG compensation cell code register, Address offset: 0x28 */ @@ -1160,23 +1158,23 @@ typedef struct typedef struct { - uint32_t RESERVED0[2]; /*!< Reserved, 0x00-0x04 */ + uint32_t RESERVED0[2]; /*!< Reserved, 0x00-0x04 */ __IO uint32_t SSCR; /*!< LTDC Synchronization Size Configuration Register, Address offset: 0x08 */ __IO uint32_t BPCR; /*!< LTDC Back Porch Configuration Register, Address offset: 0x0C */ __IO uint32_t AWCR; /*!< LTDC Active Width Configuration Register, Address offset: 0x10 */ __IO uint32_t TWCR; /*!< LTDC Total Width Configuration Register, Address offset: 0x14 */ __IO uint32_t GCR; /*!< LTDC Global Control Register, Address offset: 0x18 */ - uint32_t RESERVED1[2]; /*!< Reserved, 0x1C-0x20 */ + uint32_t RESERVED1[2]; /*!< Reserved, 0x1C-0x20 */ __IO uint32_t SRCR; /*!< LTDC Shadow Reload Configuration Register, Address offset: 0x24 */ - uint32_t RESERVED2[1]; /*!< Reserved, 0x28 */ + uint32_t RESERVED2[1]; /*!< Reserved, 0x28 */ __IO uint32_t BCCR; /*!< LTDC Background Color Configuration Register, Address offset: 0x2C */ - uint32_t RESERVED3[1]; /*!< Reserved, 0x30 */ + uint32_t RESERVED3[1]; /*!< Reserved, 0x30 */ __IO uint32_t IER; /*!< LTDC Interrupt Enable Register, Address offset: 0x34 */ __IO uint32_t ISR; /*!< LTDC Interrupt Status Register, Address offset: 0x38 */ __IO uint32_t ICR; /*!< LTDC Interrupt Clear Register, Address offset: 0x3C */ __IO uint32_t LIPCR; /*!< LTDC Line Interrupt Position Configuration Register, Address offset: 0x40 */ __IO uint32_t CPSR; /*!< LTDC Current Position Status Register, Address offset: 0x44 */ - __IO uint32_t CDSR; /*!< LTDC Current Display Status Register, Address offset: 0x48 */ + __IO uint32_t CDSR; /*!< LTDC Current Display Status Register, Address offset: 0x48 */ } LTDC_TypeDef; /** @@ -1405,32 +1403,32 @@ typedef struct typedef struct { - __IO uint32_t POWER; /*!< SDMMC power control register, Address offset: 0x00 */ - __IO uint32_t CLKCR; /*!< SDMMC clock control register, Address offset: 0x04 */ - __IO uint32_t ARG; /*!< SDMMC argument register, Address offset: 0x08 */ - __IO uint32_t CMD; /*!< SDMMC command register, Address offset: 0x0C */ - __I uint32_t RESPCMD; /*!< SDMMC command response register, Address offset: 0x10 */ - __I uint32_t RESP1; /*!< SDMMC response 1 register, Address offset: 0x14 */ - __I uint32_t RESP2; /*!< SDMMC response 2 register, Address offset: 0x18 */ - __I uint32_t RESP3; /*!< SDMMC response 3 register, Address offset: 0x1C */ - __I uint32_t RESP4; /*!< SDMMC response 4 register, Address offset: 0x20 */ - __IO uint32_t DTIMER; /*!< SDMMC data timer register, Address offset: 0x24 */ - __IO uint32_t DLEN; /*!< SDMMC data length register, Address offset: 0x28 */ - __IO uint32_t DCTRL; /*!< SDMMC data control register, Address offset: 0x2C */ - __I uint32_t DCOUNT; /*!< SDMMC data counter register, Address offset: 0x30 */ - __I uint32_t STA; /*!< SDMMC status register, Address offset: 0x34 */ - __IO uint32_t ICR; /*!< SDMMC interrupt clear register, Address offset: 0x38 */ - __IO uint32_t MASK; /*!< SDMMC mask register, Address offset: 0x3C */ - __IO uint32_t ACKTIME; /*!< SDMMC Acknowledgement timer register, Address offset: 0x40 */ - uint32_t RESERVED0[3]; /*!< Reserved, 0x44 - 0x4C - 0x4C */ - __IO uint32_t IDMACTRL; /*!< SDMMC DMA control register, Address offset: 0x50 */ - __IO uint32_t IDMABSIZE; /*!< SDMMC DMA buffer size register, Address offset: 0x54 */ - __IO uint32_t IDMABASE0; /*!< SDMMC DMA buffer 0 base address register, Address offset: 0x58 */ - __IO uint32_t IDMABASE1; /*!< SDMMC DMA buffer 1 base address register, Address offset: 0x5C */ - uint32_t RESERVED1[8]; /*!< Reserved, 0x60-0x7C */ - __IO uint32_t FIFO; /*!< SDMMC data FIFO register, Address offset: 0x80 */ - uint32_t RESERVED2[222]; /*!< Reserved, 0x84-0x3F8 */ - __IO uint32_t IPVR; /*!< SDMMC data FIFO register, Address offset: 0x3FC */ + __IO uint32_t POWER; /*!< SDMMC power control register, Address offset: 0x00 */ + __IO uint32_t CLKCR; /*!< SDMMC clock control register, Address offset: 0x04 */ + __IO uint32_t ARG; /*!< SDMMC argument register, Address offset: 0x08 */ + __IO uint32_t CMD; /*!< SDMMC command register, Address offset: 0x0C */ + __I uint32_t RESPCMD; /*!< SDMMC command response register, Address offset: 0x10 */ + __I uint32_t RESP1; /*!< SDMMC response 1 register, Address offset: 0x14 */ + __I uint32_t RESP2; /*!< SDMMC response 2 register, Address offset: 0x18 */ + __I uint32_t RESP3; /*!< SDMMC response 3 register, Address offset: 0x1C */ + __I uint32_t RESP4; /*!< SDMMC response 4 register, Address offset: 0x20 */ + __IO uint32_t DTIMER; /*!< SDMMC data timer register, Address offset: 0x24 */ + __IO uint32_t DLEN; /*!< SDMMC data length register, Address offset: 0x28 */ + __IO uint32_t DCTRL; /*!< SDMMC data control register, Address offset: 0x2C */ + __I uint32_t DCOUNT; /*!< SDMMC data counter register, Address offset: 0x30 */ + __I uint32_t STA; /*!< SDMMC status register, Address offset: 0x34 */ + __IO uint32_t ICR; /*!< SDMMC interrupt clear register, Address offset: 0x38 */ + __IO uint32_t MASK; /*!< SDMMC mask register, Address offset: 0x3C */ + __IO uint32_t ACKTIME; /*!< SDMMC Acknowledgement timer register, Address offset: 0x40 */ + uint32_t RESERVED0[3]; /*!< Reserved, 0x44 - 0x4C - 0x4C */ + __IO uint32_t IDMACTRL; /*!< SDMMC DMA control register, Address offset: 0x50 */ + __IO uint32_t IDMABSIZE; /*!< SDMMC DMA buffer size register, Address offset: 0x54 */ + __IO uint32_t IDMABASE0; /*!< SDMMC DMA buffer 0 base address register, Address offset: 0x58 */ + __IO uint32_t IDMABASE1; /*!< SDMMC DMA buffer 1 base address register, Address offset: 0x5C */ + uint32_t RESERVED1[8]; /*!< Reserved, 0x60-0x7C */ + __IO uint32_t FIFO; /*!< SDMMC data FIFO register, Address offset: 0x80 */ + uint32_t RESERVED2[222]; /*!< Reserved, 0x84-0x3F8 */ + __IO uint32_t IPVR; /*!< SDMMC data FIFO register, Address offset: 0x3FC */ } SDMMC_TypeDef; @@ -1456,9 +1454,9 @@ typedef struct __IO uint32_t ICR; /*!< HSEM Interrupt clear register , Address offset: 104h */ __IO uint32_t ISR; /*!< HSEM Interrupt Status register , Address offset: 108h */ __IO uint32_t MISR; /*!< HSEM Interrupt Masked Status register , Address offset: 10Ch */ - uint32_t Reserved[12]; /* Reserved Address offset: 110h-13Ch*/ - __IO uint32_t CR; /*!< HSEM Semaphore clear register , Address offset: 140h */ - __IO uint32_t KEYR; /*!< HSEM Semaphore clear key register , Address offset: 144h */ + uint32_t Reserved[12]; /* Reserved Address offset: 110h-13Ch */ + __IO uint32_t CR; /*!< HSEM Semaphore clear register , Address offset: 140h */ + __IO uint32_t KEYR; /*!< HSEM Semaphore clear key register , Address offset: 144h */ } HSEM_TypeDef; @@ -1555,16 +1553,16 @@ typedef struct */ typedef struct { - __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */ - __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */ - __IO uint32_t IER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */ - __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */ - __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */ - __IO uint32_t CMP; /*!< LPTIM Compare register, Address offset: 0x14 */ - __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */ - __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */ - uint16_t RESERVED1; /*!< Reserved, 0x20 */ - __IO uint32_t CFGR2; /*!< LPTIM Option register, Address offset: 0x24 */ + __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */ + __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */ + __IO uint32_t IER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */ + __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */ + __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */ + __IO uint32_t CMP; /*!< LPTIM Compare register, Address offset: 0x14 */ + __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */ + __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */ + uint16_t RESERVED1; /*!< Reserved, 0x20 */ + __IO uint32_t CFGR2; /*!< LPTIM Option register, Address offset: 0x24 */ } LPTIM_TypeDef; /** @@ -1573,8 +1571,8 @@ typedef struct typedef struct { __IO uint32_t SR; /*!< Comparator status register, Address offset: 0x00 */ - __IO uint32_t ICFR; /*!< Comparator interrupt clear flag register, Address offset: 0x04 */ - __IO uint32_t OR; /*!< Comparator option register, Address offset: 0x08 */ + __IO uint32_t ICFR; /*!< Comparator interrupt clear flag register, Address offset: 0x04 */ + __IO uint32_t OR; /*!< Comparator option register, Address offset: 0x08 */ } COMPOPT_TypeDef; typedef struct @@ -1652,7 +1650,7 @@ typedef struct __IO uint32_t MPER; /*!< HRTIM Master Timer period register, Address offset: 0x14 */ __IO uint32_t MREP; /*!< HRTIM Master Timer repetition register, Address offset: 0x18 */ __IO uint32_t MCMP1R; /*!< HRTIM Master Timer compare 1 register, Address offset: 0x1C */ - uint32_t RESERVED0; /*!< Reserved, 0x20 */ + uint32_t RESERVED0; /*!< Reserved, 0x20 */ __IO uint32_t MCMP2R; /*!< HRTIM Master Timer compare 2 register, Address offset: 0x24 */ __IO uint32_t MCMP3R; /*!< HRTIM Master Timer compare 3 register, Address offset: 0x28 */ __IO uint32_t MCMP4R; /*!< HRTIM Master Timer compare 4 register, Address offset: 0x2C */ @@ -1662,19 +1660,19 @@ typedef struct /* HRTIM Timer A to E registers definition */ typedef struct { - __IO uint32_t TIMxCR; /*!< HRTIM Timerx control register, Address offset: 0x00 */ - __IO uint32_t TIMxISR; /*!< HRTIM Timerx interrupt status register, Address offset: 0x04 */ - __IO uint32_t TIMxICR; /*!< HRTIM Timerx interrupt clear register, Address offset: 0x08 */ - __IO uint32_t TIMxDIER; /*!< HRTIM Timerx DMA/interrupt enable register, Address offset: 0x0C */ - __IO uint32_t CNTxR; /*!< HRTIM Timerx counter register, Address offset: 0x10 */ - __IO uint32_t PERxR; /*!< HRTIM Timerx period register, Address offset: 0x14 */ - __IO uint32_t REPxR; /*!< HRTIM Timerx repetition register, Address offset: 0x18 */ - __IO uint32_t CMP1xR; /*!< HRTIM Timerx compare 1 register, Address offset: 0x1C */ - __IO uint32_t CMP1CxR; /*!< HRTIM Timerx compare 1 compound register, Address offset: 0x20 */ - __IO uint32_t CMP2xR; /*!< HRTIM Timerx compare 2 register, Address offset: 0x24 */ - __IO uint32_t CMP3xR; /*!< HRTIM Timerx compare 3 register, Address offset: 0x28 */ - __IO uint32_t CMP4xR; /*!< HRTIM Timerx compare 4 register, Address offset: 0x2C */ - __IO uint32_t CPT1xR; /*!< HRTIM Timerx capture 1 register, Address offset: 0x30 */ + __IO uint32_t TIMxCR; /*!< HRTIM Timerx control register, Address offset: 0x00 */ + __IO uint32_t TIMxISR; /*!< HRTIM Timerx interrupt status register, Address offset: 0x04 */ + __IO uint32_t TIMxICR; /*!< HRTIM Timerx interrupt clear register, Address offset: 0x08 */ + __IO uint32_t TIMxDIER; /*!< HRTIM Timerx DMA/interrupt enable register, Address offset: 0x0C */ + __IO uint32_t CNTxR; /*!< HRTIM Timerx counter register, Address offset: 0x10 */ + __IO uint32_t PERxR; /*!< HRTIM Timerx period register, Address offset: 0x14 */ + __IO uint32_t REPxR; /*!< HRTIM Timerx repetition register, Address offset: 0x18 */ + __IO uint32_t CMP1xR; /*!< HRTIM Timerx compare 1 register, Address offset: 0x1C */ + __IO uint32_t CMP1CxR; /*!< HRTIM Timerx compare 1 compound register, Address offset: 0x20 */ + __IO uint32_t CMP2xR; /*!< HRTIM Timerx compare 2 register, Address offset: 0x24 */ + __IO uint32_t CMP3xR; /*!< HRTIM Timerx compare 3 register, Address offset: 0x28 */ + __IO uint32_t CMP4xR; /*!< HRTIM Timerx compare 4 register, Address offset: 0x2C */ + __IO uint32_t CPT1xR; /*!< HRTIM Timerx capture 1 register, Address offset: 0x30 */ __IO uint32_t CPT2xR; /*!< HRTIM Timerx capture 2 register, Address offset: 0x34 */ __IO uint32_t DTxR; /*!< HRTIM Timerx dead time register, Address offset: 0x38 */ __IO uint32_t SETx1R; /*!< HRTIM Timerx output 1 set register, Address offset: 0x3C */ @@ -1689,7 +1687,7 @@ typedef struct __IO uint32_t CPT2xCR; /*!< HRTIM Timerx Capture 2 register, Address offset: 0x60 */ __IO uint32_t OUTxR; /*!< HRTIM Timerx Output register, Address offset: 0x64 */ __IO uint32_t FLTxR; /*!< HRTIM Timerx Fault register, Address offset: 0x68 */ - uint32_t RESERVED0[5]; /*!< Reserved, 0x6C..0x7C */ + uint32_t RESERVED0[5]; /*!< Reserved, 0x6C..0x7C */ }HRTIM_Timerx_TypeDef; /* HRTIM common register definition */ @@ -1846,9 +1844,9 @@ typedef struct uint32_t Reserved30[2]; /*!< Reserved 030h */ __IO uint32_t GCCFG; /*!< General Purpose IO Register 038h */ __IO uint32_t CID; /*!< User ID Register 03Ch */ - __IO uint32_t GSNPSID; /* USB_OTG core ID 040h*/ - __IO uint32_t GHWCFG1; /* User HW config1 044h*/ - __IO uint32_t GHWCFG2; /* User HW config2 048h*/ + __IO uint32_t GSNPSID; /* USB_OTG core ID 040h*/ + __IO uint32_t GHWCFG1; /* User HW config1 044h*/ + __IO uint32_t GHWCFG2; /* User HW config2 048h*/ __IO uint32_t GHWCFG3; /*!< User HW config3 04Ch */ uint32_t Reserved6; /*!< Reserved 050h */ __IO uint32_t GLPMCFG; /*!< LPM Register 054h */ @@ -1968,11 +1966,16 @@ typedef struct #define D3_SRAM_BASE ((uint32_t)0x38000000) /*!< Base address of : Backup SRAM(64 KB) over AXI->AHB Bridge */ #define PERIPH_BASE ((uint32_t)0x40000000) /*!< Base address of : AHB/ABP Peripherals */ -#define QSPI_BASE ((uint32_t)0x90000000) /*!< Base address of : QSPI memories accessible over AXI */ +#define QSPI_BASE ((uint32_t)0x90000000) /*!< Base address of : QSPI memories accessible over AXI */ -#define FLASH_BANK1_BASE ((uint32_t)0x08000000) /*!< Base address of : Flash Bank1 accessible over AXI */ -#define FLASH_BANK2_BASE ((uint32_t)0x08100000) /*!< Base address of : Flash Bank2 accessible over AXI */ +#define FLASH_BANK1_BASE ((uint32_t)0x08000000) /*!< Base address of : (up to 1 MB) Flash Bank1 accessible over AXI */ +#define FLASH_BANK2_BASE ((uint32_t)0x08100000) /*!< Base address of : (up to 1 MB) Flash Bank2 accessible over AXI */ #define FLASH_END ((uint32_t)0x081FFFFF) /*!< FLASH end address */ + +#define FLASH_OTP_BANK1_BASE ((uint32_t)0x1FF00000) /*!< Base address of : (up to 128KB) embedded FLASH Bank1 OTP Area */ +#define FLASH_OTP_BANK1_END ((uint32_t)0x1FF1FFFF) /*!< End address of : (up to 128KB) embedded FLASH Bank1 OTP Area */ +#define FLASH_OTP_BANK2_BASE ((uint32_t)0x1FF40000) /*!< Base address of : (up to 128KB) embedded FLASH Bank2 OTP Area */ +#define FLASH_OTP_BANK2_END ((uint32_t)0x1FF5FFFF) /*!< End address of : (up to 128KB) embedded FLASH Bank2 OTP Area */ /* Legacy define */ #define FLASH_BASE FLASH_BANK1_BASE @@ -2303,6 +2306,8 @@ typedef struct #define VREFBUF ((VREFBUF_TypeDef *) VREFBUF_BASE) #define RTC ((RTC_TypeDef *) RTC_BASE) #define WWDG1 ((WWDG_TypeDef *) WWDG1_BASE) + + #define IWDG1 ((IWDG_TypeDef *) IWDG1_BASE) #define SPI2 ((SPI_TypeDef *) SPI2_BASE) #define SPI3 ((SPI_TypeDef *) SPI3_BASE) @@ -2347,6 +2352,7 @@ typedef struct #define EXTI ((EXTI_TypeDef *) EXTI_BASE) #define EXTI_D1 ((EXTI_Core_TypeDef *) EXTI_D1_BASE) #define EXTI_D2 ((EXTI_Core_TypeDef *) EXTI_D2_BASE) +#define SDMMC ((SDMMC_TypeDef *) SDMMC_BASE) #define TIM1 ((TIM_TypeDef *) TIM1_BASE) #define SPI1 ((SPI_TypeDef *) SPI1_BASE) #define TIM8 ((TIM_TypeDef *) TIM8_BASE) @@ -2520,6 +2526,7 @@ typedef struct #define LTDC ((LTDC_TypeDef *)LTDC_BASE) #define LTDC_Layer1 ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE) #define LTDC_Layer2 ((LTDC_Layer_TypeDef *)LTDC_Layer2_BASE) + #define MDIOS ((MDIOS_TypeDef *) MDIOS_BASE) #define ETH ((ETH_TypeDef *)ETH_BASE) @@ -2552,7 +2559,6 @@ typedef struct #define USB_OTG_HS_PERIPH_BASE USB1_OTG_HS_PERIPH_BASE #define USB_OTG_FS_PERIPH_BASE USB2_OTG_FS_PERIPH_BASE - /** * @} */ @@ -4138,7 +4144,6 @@ typedef struct #define VREFBUF_CCR_TRIM_Msk (0x3FU << VREFBUF_CCR_TRIM_Pos) /*!< 0x0000003F */ #define VREFBUF_CCR_TRIM VREFBUF_CCR_TRIM_Msk /*!*/ /***************** Bit definition for DAC_SWTRIGR register ******************/ -#define DAC_SWTRIGR_SWTRIG1 ((uint8_t)0x01) /*!