mirror of
https://github.com/openmv/openmv.git
synced 2025-11-04 14:49:50 +08:00
Merge pull request #2604 from openmv/alif_port
ports/alif: Add Alif port.
This commit is contained in:
commit
a09bd2d4b2
22
.github/workflows/firmware.yml
vendored
22
.github/workflows/firmware.yml
vendored
@ -28,7 +28,19 @@ jobs:
|
||||
runs-on: ubuntu-24.04
|
||||
strategy:
|
||||
matrix:
|
||||
target: [OPENMV2, OPENMV3, OPENMV4, OPENMV4P, OPENMVPT, OPENMV_RT1060, ARDUINO_PORTENTA_H7, ARDUINO_GIGA, ARDUINO_NICLA_VISION, ARDUINO_NANO_RP2040_CONNECT, ARDUINO_NANO_33_BLE_SENSE]
|
||||
target:
|
||||
- OPENMV2
|
||||
- OPENMV3
|
||||
- OPENMV4
|
||||
- OPENMV4P
|
||||
- OPENMVPT
|
||||
- OPENMV_RT1060
|
||||
- OPENMV_AE3
|
||||
- ARDUINO_PORTENTA_H7
|
||||
- ARDUINO_GIGA
|
||||
- ARDUINO_NICLA_VISION
|
||||
- ARDUINO_NANO_RP2040_CONNECT
|
||||
- ARDUINO_NANO_33_BLE_SENSE
|
||||
fail-fast: false
|
||||
steps:
|
||||
- name: '⏳ Checkout repository'
|
||||
@ -53,11 +65,13 @@ jobs:
|
||||
uses: actions/setup-python@v5
|
||||
with:
|
||||
cache: 'pip'
|
||||
python-version: "3.12.4"
|
||||
python-version: "3.12.0"
|
||||
|
||||
- name: '🛠 Install Vela'
|
||||
- name: '🛠 Install dependencies'
|
||||
run: |
|
||||
pip install ethos-u-vela==3.12.0
|
||||
pip install -r .github/workflows/requirements.txt
|
||||
flake8 --version
|
||||
pytest --version
|
||||
vela --version
|
||||
|
||||
- name: '🛠 Install GNU Make '
|
||||
|
||||
3
.github/workflows/requirements.txt
vendored
3
.github/workflows/requirements.txt
vendored
@ -1,4 +1,5 @@
|
||||
flake8==6.0.0
|
||||
pytest==7.4.0
|
||||
ethos-u-vela==3.12.0
|
||||
ethos-u-vela==4.2.0
|
||||
tabulate==0.9.0
|
||||
cryptography==44.0.0
|
||||
|
||||
70
scripts/libraries/alif/he/_boot.py
Normal file
70
scripts/libraries/alif/he/_boot.py
Normal file
@ -0,0 +1,70 @@
|
||||
import os
|
||||
import openamp
|
||||
import asyncio
|
||||
from asyncio import CancelledError
|
||||
import struct
|
||||
import marshal
|
||||
from types import FunctionType
|
||||
|
||||
|
||||
# MicroPython doesn't have this exception
|
||||
class InvalidStateError(Exception):
|
||||
pass
|
||||
|
||||
|
||||
class DoneException(Exception):
|
||||
pass
|
||||
|
||||
|
||||
tasks = {}
|
||||
_epts = {}
|
||||
|
||||
|
||||
def vm_out_callback(src_addr, data):
|
||||
try:
|
||||
nlen, mlen = struct.unpack("II", data[0:8])
|
||||
name, mpy = struct.unpack(f"{nlen}s{mlen}s", data[8:])
|
||||
name = name.decode()
|
||||
g = FunctionType(marshal.loads(mpy), globals())
|
||||
ept = openamp.Endpoint(name)
|
||||
tasks[name] = asyncio.create_task(g(ept))
|
||||
except Exception as e:
|
||||
print(str(e))
|
||||
|
||||
|
||||
async def main():
|
||||
while True:
|
||||
if tasks:
|
||||
task_except = None
|
||||
try:
|
||||
await asyncio.gather(*tasks.values(), return_exceptions=False)
|
||||
except Exception as e:
|
||||
task_except = e
|
||||
|
||||
for name in list(tasks):
|
||||
task = tasks[name]
|
||||
try:
|
||||
if task.done():
|
||||
tasks.pop(name)
|
||||
if not isinstance(task_except, DoneException):
|
||||
print(f'Task "{name}" raised: {task_except}')
|
||||
break # Break after the first task is removed.
|
||||
except (CancelledError, InvalidStateError):
|
||||
pass
|
||||
await asyncio.sleep(0.5)
|
||||
print(f"running tasks:{len(tasks)}")
|
||||
|
||||
|
||||
try:
|
||||
os.chdir("/rom")
|
||||
except:
|
||||
pass
|
||||
|
||||
try:
|
||||
# openamp.new_service_callback(vm_ns_callback)
|
||||
# Create the RPMsg endpoints to communicate with HP core.
|
||||
_epts["vm"] = openamp.Endpoint("vm", callback=vm_out_callback)
|
||||
os.dupterm(openamp.EndpointIO(_epts["vm"]), 0)
|
||||
asyncio.run(main())
|
||||
except Exception as e:
|
||||
print(e)
|
||||
19
scripts/libraries/alif/hp/_boot.py
Normal file
19
scripts/libraries/alif/hp/_boot.py
Normal file
@ -0,0 +1,19 @@
|
||||
import sys
|
||||
import os
|
||||
import alif
|
||||
import vfs
|
||||
|
||||
bdev = alif.Flash()
|
||||
try:
|
||||
fat = vfs.VfsFat(bdev)
|
||||
vfs.mount(fat, "/flash")
|
||||
except:
|
||||
vfs.VfsFat.mkfs(bdev)
|
||||
fat = vfs.VfsFat(bdev)
|
||||
vfs.mount(fat, "/flash")
|
||||
|
||||
sys.path.append("/flash")
|
||||
sys.path.append("/flash/lib")
|
||||
os.chdir("/flash")
|
||||
|
||||
del sys, os, alif, bdev
|
||||
82
scripts/libraries/openamp.py
Normal file
82
scripts/libraries/openamp.py
Normal file
@ -0,0 +1,82 @@
|
||||
import io
|
||||
import struct
|
||||
import marshal
|
||||
from uopenamp import *
|
||||
|
||||
_epts = {}
|
||||
_MP_STREAM_POLL_WR = const(0x04)
|
||||
_MP_STREAM_POLL_RD = const(0x01)
|
||||
_MP_STREAM_POLL_HUP = const(0x10)
|
||||
|
||||
|
||||
async def coro(): # noqa
|
||||
pass
|
||||
|
||||
|
||||
class EndpointIO(io.IOBase):
|
||||
def __init__(self, ept):
|
||||
self.ept = ept
|
||||
|
||||
def write(self, buf):
|
||||
if buf != b"\r\n":
|
||||
self.ept.send(buf, timeout=0)
|
||||
|
||||
def ioctl(self, op, arg):
|
||||
if op == _MP_STREAM_POLL and self.ept.is_ready():
|
||||
return _MP_STREAM_POLL_WR
|
||||
return 0
|
||||
|
||||
|
||||
def vm_out_callback(src_addr, data):
|
||||
print("VM ❯", data.decode())
|
||||
|
||||
|
||||
def vm_ns_callback(src_addr, name):
|
||||
print(f'New service announcement src address: {src_addr} name: "{name}"')
|
||||
if name == "vm":
|
||||
# The "vm" channel is announced. Create our side of the channel
|
||||
# and send the tasks' mpy. The other core will create the tasks,
|
||||
# and their associated endpoints, and announce them.
|
||||
_epts["vm"] = Endpoint("vm", vm_out_callback, dest=src_addr)
|
||||
for name in _epts:
|
||||
if name != "vm":
|
||||
mpy = _epts[name]["mpy"]
|
||||
_epts["vm"].send(
|
||||
struct.pack(
|
||||
f"II{len(name)}s{len(mpy)}s",
|
||||
len(name),
|
||||
len(mpy),
|
||||
bytes(name, "utf-8"),
|
||||
mpy,
|
||||
),
|
||||
timeout=1000,
|
||||
)
|
||||
else:
|
||||
# A task's endpoint is announced. Create our side of the endpoint
|
||||
# using the task's callback as the output callback.
|
||||
_epts[name] = Endpoint(name, callback=_epts[name]["cb"])
|
||||
|
||||
|
||||
def async_remote(callback=None):
|
||||
# Register the new service callback to create endpoints, when the
|
||||
# remote processor announces them.
|
||||
new_service_callback(vm_ns_callback)
|
||||
|
||||
def decorator(func):
|
||||
try:
|
||||
name = func.__name__
|
||||
mpy = marshal.dumps(func.__code__)
|
||||
if len(mpy) + len(name) + 8 > 500:
|
||||
raise ValueError("The maximum mpy size supported is 500 bytes")
|
||||
_epts[name] = {"cb": callback, "mpy": mpy}
|
||||
except Exception as e:
|
||||
print(str(e))
|
||||
|
||||
if isinstance(callback, type(coro)):
|
||||
# The decorator is called without any args.
|
||||
# `callback` is actually the function to be decorated.
|
||||
func = callback
|
||||
callback = None
|
||||
return decorator(func)
|
||||
|
||||
return decorator
|
||||
26
scripts/libraries/romfs.py
Normal file
26
scripts/libraries/romfs.py
Normal file
@ -0,0 +1,26 @@
|
||||
import os
|
||||
import uctypes
|
||||
|
||||
|
||||
def ls_romfs():
|
||||
# Define possible alignment sizes in descending order
|
||||
alignments = [128, 64, 32, 16, 8, 4]
|
||||
|
||||
for fname in os.listdir("/rom"):
|
||||
with open("/rom/" + fname, "rb") as file:
|
||||
address = uctypes.addressof(file) & 0xFFFFFFF
|
||||
size = len(memoryview(file))
|
||||
aligned = False
|
||||
# Check alignment for each size, starting from the highest alignment
|
||||
for alignment in alignments:
|
||||
if address % alignment == 0:
|
||||
print(
|
||||
f"addr: 0x{address:08X} size: {size:<8} alignment: {alignment:<4} name: {fname}"
|
||||
)
|
||||
aligned = True
|
||||
break
|
||||
# If not aligned to any of the specified sizes
|
||||
if not aligned:
|
||||
print(
|
||||
f"addr: 0x{address:08X} size: {size:<8} alignment: NOT aligned name: {fname}"
|
||||
)
|
||||
164
src/boot/src/ports/alif/alif.ld.S
Normal file
164
src/boot/src/ports/alif/alif.ld.S
Normal file
@ -0,0 +1,164 @@
|
||||
/*
|
||||
* Copyright (C) 2023-2024 OpenMV, LLC.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Any redistribution, use, or modification in source or binary form
|
||||
* is done solely for personal benefit and not for any commercial
|
||||
* purpose or for monetary gain. For commercial licensing options,
|
||||
* please contact openmv@openmv.io
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE LICENSOR AND COPYRIGHT OWNER "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
|
||||
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE LICENSOR OR COPYRIGHT
|
||||
* OWNER BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
|
||||
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
|
||||
* OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
*/
|
||||
|
||||
// Entry Point
|
||||
ENTRY(Reset_Handler)
|
||||
|
||||
#include "omv_boardconfig.h"
|
||||
|
||||
MEMORY
|
||||
{
|
||||
FLASH_TEXT (rx) : ORIGIN = OMV_FLASH_ORIGIN, LENGTH = OMV_FLASH_LENGTH
|
||||
ITCM (rx) : ORIGIN = OMV_ITCM_ORIGIN, LENGTH = OMV_ITCM_LENGTH
|
||||
DTCM (rw) : ORIGIN = OMV_DTCM_ORIGIN, LENGTH = OMV_DTCM_LENGTH
|
||||
#if defined(OMV_SRAM0_ORIGIN)
|
||||
SRAM0 (rw) : ORIGIN = OMV_SRAM0_ORIGIN, LENGTH = OMV_SRAM0_LENGTH
|
||||
#endif
|
||||
#if defined(OMV_SRAM1_ORIGIN)
|
||||
SRAM1 (rw) : ORIGIN = OMV_SRAM1_ORIGIN, LENGTH = OMV_SRAM1_LENGTH
|
||||
#endif
|
||||
#if defined(OMV_SRAM6_A_ORIGIN)
|
||||
SRAM6_A (rw) : ORIGIN = OMV_SRAM6_A_ORIGIN, LENGTH = OMV_SRAM6_A_LENGTH
|
||||
#endif
|
||||
#if defined(OMV_SRAM6_B_ORIGIN)
|
||||
SRAM6_B (rw) : ORIGIN = OMV_SRAM6_B_ORIGIN, LENGTH = OMV_SRAM6_B_LENGTH
|
||||
#endif
|
||||
#if defined(OMV_SRAM7_ORIGIN)
|
||||
SRAM7 (rw) : ORIGIN = OMV_SRAM7_ORIGIN, LENGTH = OMV_SRAM7_LENGTH
|
||||
#endif
|
||||
#if defined(OMV_SRAM8_ORIGIN)
|
||||
SRAM8 (rw) : ORIGIN = OMV_SRAM8_ORIGIN, LENGTH = OMV_SRAM8_LENGTH
|
||||
#endif
|
||||
#if defined(OMV_SRAM9_A_ORIGIN)
|
||||
SRAM9_A (rw) : ORIGIN = OMV_SRAM9_A_ORIGIN, LENGTH = OMV_SRAM9_A_LENGTH
|
||||
#endif
|
||||
#if defined(OMV_SRAM9_B_ORIGIN)
|
||||
SRAM9_B (rw) : ORIGIN = OMV_SRAM9_B_ORIGIN, LENGTH = OMV_SRAM9_B_LENGTH
|
||||
#endif
|
||||
}
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
.text : ALIGN(16)
|
||||
{
|
||||
KEEP(*(.vectors))
|
||||
. = ALIGN(4);
|
||||
*(.text*)
|
||||
. = ALIGN(4);
|
||||
*(.rodata*)
|
||||
. = ALIGN(16);
|
||||
} > FLASH_TEXT
|
||||
|
||||
.copy.table : ALIGN(4)
|
||||
{
|
||||
__copy_table_start__ = .;
|
||||
LONG ( LOADADDR(.data) )
|
||||
LONG ( ADDR(.data) )
|
||||
LONG ( SIZEOF(.data)/4 )
|
||||
__copy_table_end__ = .;
|
||||
. = ALIGN(16);
|
||||
} > FLASH_TEXT
|
||||
|
||||
.zero.table : ALIGN(4)
|
||||
{
|
||||
__zero_table_start__ = .;
|
||||
LONG (ADDR(.bss))
|
||||
LONG (SIZEOF(.bss)/4)
|
||||
LONG (ADDR(.bss.sram))
|
||||
LONG (SIZEOF(.bss.sram)/4)
|
||||
__zero_table_end__ = .;
|
||||
. = ALIGN(16);
|
||||
} > FLASH_TEXT
|
||||
|
||||
.data : ALIGN(8)
|
||||
{
|
||||
*(.data)
|
||||
. = ALIGN(8);
|
||||
*(.data.*)
|
||||
. = ALIGN(8);
|
||||
. = ALIGN(16);
|
||||
} > OMV_MAIN_MEMORY AT > FLASH_TEXT
|
||||
|
||||
/* Peripherals in expansion master 0 (such as USB, Ethernet, SD/MMC)
|
||||
are by default configured as non-secure, so they don't have access
|
||||
to DTCMs. This can be fixed in the ToC by allowing access to DTCMs
|
||||
to all bus masters, for now these peripherals should place buffers
|
||||
in regular SRAM */
|
||||
.bss.sram (NOLOAD) : ALIGN(16)
|
||||
{
|
||||
*(.bss.sram*)
|
||||
. = ALIGN(16);
|
||||
} > SRAM1
|
||||
|
||||
.bss : ALIGN(4)
|
||||
{
|
||||
__bss_start__ = .;
|
||||
*(.bss)
|
||||
. = ALIGN(4);
|
||||
*(.bss.*)
|
||||
. = ALIGN(4);
|
||||
*(COMMON)
|
||||
. = ALIGN(4);
|
||||
__bss_end__ = .;
|
||||
} > OMV_MAIN_MEMORY
|
||||
|
||||
.init_fini_arrays : ALIGN(16)
|
||||
{
|
||||
KEEP(*(.init))
|
||||
KEEP(*(.fini))
|
||||
|
||||
. = ALIGN(4);
|
||||
/* preinit data */
|
||||
PROVIDE_HIDDEN (__preinit_array_start = .);
|
||||
KEEP(*(.preinit_array))
|
||||
PROVIDE_HIDDEN (__preinit_array_end = .);
|
||||
|
||||
. = ALIGN(4);
|
||||
/* init data */
|
||||
PROVIDE_HIDDEN (__init_array_start = .);
|
||||
KEEP(*(SORT(.init_array.*)))
|
||||
KEEP(*(.init_array))
|
||||
PROVIDE_HIDDEN (__init_array_end = .);
|
||||
|
||||
. = ALIGN(4);
|
||||
/* finit data */
|
||||
PROVIDE_HIDDEN (__fini_array_start = .);
|
||||
KEEP(*(SORT(.fini_array.*)))
|
||||
KEEP(*(.fini_array))
|
||||
PROVIDE_HIDDEN (__fini_array_end = .);
|
||||
|
||||
KEEP(*(.eh_frame*))
|
||||
. = ALIGN(16);
|
||||
} > FLASH_TEXT
|
||||
|
||||
#include "common.ld.S"
|
||||
}
|
||||
67
src/boot/src/ports/alif/alif_flash.c
Normal file
67
src/boot/src/ports/alif/alif_flash.c
Normal file
@ -0,0 +1,67 @@
|
||||
/*
|
||||
* Copyright (C) 2023-2024 OpenMV, LLC.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Any redistribution, use, or modification in source or binary form
|
||||
* is done solely for personal benefit and not for any commercial
|
||||
* purpose or for monetary gain. For commercial licensing options,
|
||||
* please contact openmv@openmv.io
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE LICENSOR AND COPYRIGHT OWNER "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
|
||||
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE LICENSOR OR COPYRIGHT
|
||||
* OWNER BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
|
||||
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
|
||||
* OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* Alif Flash driver.
|
||||
*/
|
||||
#include <string.h>
|
||||
#include ALIF_CMSIS_H
|
||||
|
||||
#include "omv_boardconfig.h"
|
||||
#include "omv_bootconfig.h"
|
||||
#include "mram.h"
|
||||
|
||||
#if OMV_BOOT_AXI_FLASH_ENABLE
|
||||
|
||||
int axi_flash_read(uint32_t addr, uint8_t *buf, size_t size) {
|
||||
memcpy(buf, (void *) addr, size);
|
||||
return 0;
|
||||
}
|
||||
|
||||
int axi_flash_write(uint32_t addr, const uint8_t *buf, size_t size) {
|
||||
// Note TinyUSB buffers are aligned to a multiple of the MRAM sector size.
|
||||
if ((addr % MRAM_SECTOR_SIZE) || ((uint32_t) buf % MRAM_SECTOR_SIZE)) {
|
||||
return -1;
|
||||
}
|
||||
|
||||
// Round up to multiple of the MRAM sector size.
|
||||
// Note TinyUSB buffers are much bigger than the MRAM sector size, so the
|
||||
// writes can be rounded up, and we can read more than the specified size.
|
||||
if (size % MRAM_SECTOR_SIZE) {
|
||||
size = (size + (MRAM_SECTOR_SIZE - 1)) & ~(MRAM_SECTOR_SIZE - 1);
|
||||
}
|
||||
|
||||
// Note writes must be 16 bytes aligned and a multiple of 16 bytes.
|
||||
for (size_t i = 0; i < size / sizeof(uint64_t); i += 2) {
|
||||
((volatile uint64_t *) addr)[i + 0] = ((volatile uint64_t *) buf)[i + 0];
|
||||
((volatile uint64_t *) addr)[i + 1] = ((volatile uint64_t *) buf)[i + 1];
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
#endif // OMV_BOOT_AXI_FLASH_ENABLE
|
||||
524
src/boot/src/ports/alif/alif_ospi.c
Normal file
524
src/boot/src/ports/alif/alif_ospi.c
Normal file
@ -0,0 +1,524 @@
|
||||
/*
|
||||
* Copyright (C) 2023-2024 OpenMV, LLC.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Any redistribution, use, or modification in source or binary form
|
||||
* is done solely for personal benefit and not for any commercial
|
||||
* purpose or for monetary gain. For commercial licensing options,
|
||||
* please contact openmv@openmv.io
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE LICENSOR AND COPYRIGHT OWNER "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
|
||||
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE LICENSOR OR COPYRIGHT
|
||||
* OWNER BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
|
||||
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
|
||||
* OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* ALif OSPI driver.
|
||||
* Note this driver uses SPI mode, and should support any standard flash.
|
||||
*/
|
||||
#include <stdint.h>
|
||||
#include <string.h>
|
||||
#include ALIF_CMSIS_H
|
||||
#include "omv_boardconfig.h"
|
||||
#include "omv_bootconfig.h"
|
||||
|
||||
#if OMV_BOOT_SPI_FLASH_ENABLE
|
||||
#include "gpio.h"
|
||||
#include "pinconf.h"
|
||||
#include "ospi_private.h"
|
||||
|
||||
#define OSPI_INST_0BIT (0x00U)
|
||||
#define OSPI_INST_4BIT (0x01U)
|
||||
#define OSPI_INST_8BIT (0x02U)
|
||||
#define OSPI_INST_16BIT (0x03U)
|
||||
|
||||
#define OSPI_DFS_8BIT (0x07U)
|
||||
#define OSPI_DFS_16BIT (0x0FU)
|
||||
#define OSPI_DFS_32BIT (0x1FU)
|
||||
|
||||
#define OSPI_FRF_SINGLE (0x00U)
|
||||
#define OSPI_FRF_DUAL (0x01U)
|
||||
#define OSPI_FRF_QUAD (0x02U)
|
||||
#define OSPI_FRF_OCTAL (0x03U)
|
||||
|
||||
#define OSPI_ADDR_0BIT (0x00U)
|
||||
#define OSPI_ADDR_24BIT (0x06U)
|
||||
#define OSPI_ADDR_32BIT (0x08U)
|
||||
|
||||
#define OSPI_FIFO_SIZE (128) // 256 words
|
||||
#define OSPI_PAGE_SIZE (128)
|
||||
#define OSPI_SECTOR_SIZE (4096)
|
||||
#define OSPI_POLL_TIMEOUT (1000000)
|
||||
|
||||
#define OSPI_WRSR_COMMAND (0x01)
|
||||
#define OSPI_RDSR_COMMAND (0x05)
|
||||
#define OSPI_RDSR_DCYCLES (0)
|
||||
|
||||
#define OSPI_WRVL_COMMAND (0x81)
|
||||
#define OSPI_RDVL_COMMAND (0x85)
|
||||
|
||||
#define OSPI_WRNV_COMMAND (0xB1)
|
||||
#define OSPI_RDNV_COMMAND (0xB5)
|
||||
|
||||
#define OSPI_RDID_COMMAND (0x9F)
|
||||
#define OSPI_RDID_DCYCLES (0)
|
||||
|
||||
#define OSPI_READ_COMMAND (0x13)
|
||||
#define OSPI_READ_DCYCLES (0)
|
||||
|
||||
#define OSPI_WREN_COMMAND (0x06)
|
||||
#define OSPI_WRITE_COMMAND (0x12)
|
||||
|
||||
#define OSPI_ERASE_COMMAND (0x21)
|
||||
#define OSPI_ERASE_CHIP_COMMAND (0xC7)
|
||||
|
||||
typedef struct ospi_flash {
|
||||
uint8_t ddr_mode;
|
||||
uint8_t spi_mode;
|
||||
ssi_regs_t *regs;
|
||||
aes_regs_t *aes_regs;
|
||||
volatile void *xip_base;
|
||||
uint8_t initialized;
|
||||
bool bswap16;
|
||||
bool recovered;
|
||||
} ospi_flash_t;
|
||||
|
||||
static ospi_flash_t ospi = { 0 };
|
||||
|
||||
static void port_delay_ns(uint32_t ns) {
|
||||
for (size_t i = 0; i < (ns / 2.5); i++) {
|
||||
}
|
||||
}
|
||||
|
||||
static void ospi_setup(ospi_flash_t *ospi, uint32_t addr_len, uint32_t ndf, uint32_t wait_cycles) {
|
||||
ospi_writel(ospi, ser, 0);
|
||||
spi_disable(ospi);
|
||||
|
||||
uint32_t val = CTRLR0_IS_MST
|
||||
| (OSPI_DFS_8BIT << CTRLR0_DFS_OFFSET)
|
||||
| (OSPI_FRF_SINGLE << CTRLR0_SPI_FRF_OFFSET)
|
||||
| ((ndf ? SPI_TMOD_TR : TMOD_TO) << CTRLR0_TMOD_OFFSET);
|
||||
|
||||
ospi_writel(ospi, ctrlr0, val);
|
||||
ospi_writel(ospi, ctrlr1, (ndf ? (ndf - 1) : 0));
|
||||
|
||||
val = TRANS_TYPE_FRF_DEFINED
|
||||
| (1 << CTRLR0_SPI_RXDS_EN_OFFSET)
|
||||
| (addr_len << CTRLR0_ADDR_L_OFFSET)
|
||||
| (OSPI_INST_8BIT << CTRLR0_INST_L_OFFSET)
|
||||
| (wait_cycles << CTRLR0_WAIT_CYCLES_OFFSET);
|
||||
|
||||
ospi_writel(ospi, spi_ctrlr0, val);
|
||||
spi_enable(ospi);
|
||||
}
|
||||
|
||||
static inline void ospi_push(ospi_flash_t *ospi, uint32_t data) {
|
||||
ospi_writel(ospi, data_reg, data);
|
||||
}
|
||||
|
||||
static int ospi_flash_wait_busy(ospi_flash_t *ospi) {
|
||||
uint32_t timeout = OSPI_POLL_TIMEOUT;
|
||||
while ((ospi_readl(ospi, sr) & (SR_TF_EMPTY | SR_BUSY)) != SR_TF_EMPTY) {
|
||||
if (--timeout == 0) {
|
||||
return -1;
|
||||
}
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int ospi_send(ospi_flash_t *ospi, uint32_t cmd, uint32_t addr_len,
|
||||
uint32_t addr, uint32_t data_len, const uint8_t *data) {
|
||||
ospi_setup(ospi, addr_len, 0, 0);
|
||||
ospi_push(ospi, cmd);
|
||||
|
||||
// Push the address (0, 24, or 32 bits).
|
||||
for (size_t i = 0; i < addr_len / 2; i++) {
|
||||
ospi_push(ospi, addr >> ((addr_len / 2 - 1) * 8 - i * 8));
|
||||
}
|
||||
|
||||
for (size_t i = 0; i < data_len; i++) {
|
||||
ospi_push(ospi, data[i]);
|
||||
}
|
||||
|
||||
ospi_writel(ospi, ser, OMV_BOOT_OSPI_SER);
|
||||
return ospi_flash_wait_busy(ospi);
|
||||
}
|
||||
|
||||
static int ospi_recv(ospi_flash_t *ospi, uint32_t cmd, uint32_t addr_len,
|
||||
uint32_t addr, size_t data_len, uint8_t *data, uint32_t dcycles) {
|
||||
|
||||
ospi_setup(ospi, addr_len, data_len, dcycles);
|
||||
ospi_push(ospi, cmd);
|
||||
|
||||
// Push the address (0, 24, or 32 bits).
|
||||
for (size_t i = 0; i < addr_len / 2; i++) {
|
||||
ospi_push(ospi, addr >> ((addr_len / 2 - 1) * 8 - i * 8));
|
||||
}
|
||||
|
||||
// Push dummy bytes as many as the data size.
|
||||
for (size_t i = 0; i < data_len; i++) {
|
||||
ospi_push(ospi, 0x00);
|
||||
}
|
||||
|
||||
ospi_writel(ospi, ser, OMV_BOOT_OSPI_SER);
|
||||
|
||||
// Skip the command and address high-z bytes.
|
||||
uint32_t skip_len = addr_len / 2 + 1;
|
||||
|
||||
for (size_t i = 0; i < skip_len + data_len; i++) {
|
||||
unsigned int timeout = 100000;
|
||||
|
||||
while (ospi_readl(ospi, rxflr) == 0) {
|
||||
if (--timeout == 0) {
|
||||
return -1;
|
||||
}
|
||||
}
|
||||
|
||||
if (i < skip_len) {
|
||||
(void) ospi_readl(ospi, data_reg);
|
||||
} else {
|
||||
data[i - skip_len] = ospi_readl(ospi, data_reg);
|
||||
}
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int ospi_flash_wait_sr(ospi_flash_t *ospi, uint8_t mask, uint8_t val, uint32_t timeout) {
|
||||
do {
|
||||
uint8_t sr;
|
||||
if (ospi_recv(ospi, OSPI_RDSR_COMMAND, OSPI_ADDR_0BIT, 0, 1, &sr, OSPI_RDSR_DCYCLES) != 0) {
|
||||
return -1;
|
||||
}
|
||||
if ((sr & mask) == val) {
|
||||
return 0; // success
|
||||
}
|
||||
} while (timeout--);
|
||||
|
||||
return -1;
|
||||
}
|
||||
|
||||
static int ospi_flash_wait_wel1(ospi_flash_t *ospi) {
|
||||
return ospi_flash_wait_sr(ospi, 2, 2, OSPI_POLL_TIMEOUT);
|
||||
}
|
||||
|
||||
static int ospi_flash_wait_wip0(ospi_flash_t *ospi) {
|
||||
return ospi_flash_wait_sr(ospi, 1, 0, OSPI_POLL_TIMEOUT);
|
||||
}
|
||||
|
||||
static int ospi_flash_write_enable(ospi_flash_t *ospi) {
|
||||
ospi_send(ospi, OSPI_WREN_COMMAND, OSPI_ADDR_0BIT, 0, 0, NULL);
|
||||
return ospi_flash_wait_wel1(ospi);
|
||||
}
|
||||
|
||||
int ospi_flash_read_reg(ospi_flash_t *ospi, uint32_t cmd, uint32_t addr_len, uint32_t addr) {
|
||||
uint8_t buf;
|
||||
if (ospi_recv(ospi, cmd, addr_len, addr, 1, &buf, 0) != 0) {
|
||||
return -1;
|
||||
}
|
||||
return buf;
|
||||
}
|
||||
|
||||
int ospi_flash_write_reg(ospi_flash_t *ospi, uint32_t cmd, uint32_t addr_len, uint32_t addr, uint8_t buf) {
|
||||
if (ospi_flash_write_enable(ospi) != 0 ||
|
||||
ospi_send(ospi, cmd, addr_len, addr, 1, &buf) != 0 ||
|
||||
ospi_flash_wait_wip0(ospi) != 0) {
|
||||
return -1;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int ospi_flash_chip_erase(ospi_flash_t *ospi, uint32_t value) {
|
||||
// Configure erase value
|
||||
uint32_t nv_reg = 0x7F | ((value & 1) << 7);
|
||||
if (ospi_flash_write_reg(ospi, OSPI_WRVL_COMMAND, OSPI_ADDR_24BIT, 0x08, nv_reg) != 0) {
|
||||
return -1;
|
||||
}
|
||||
if (ospi_flash_write_enable(ospi) != 0 ||
|
||||
ospi_send(ospi, OSPI_ERASE_CHIP_COMMAND, OSPI_ADDR_0BIT, 0, 0, NULL) != 0 ||
|
||||
ospi_flash_wait_sr(ospi, 1, 0, 400000) != 0) {
|
||||
return -1;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int ospi_flash_reset(ospi_flash_t *ospi) {
|
||||
port_pin_write(OMV_BOOT_OSPI_RST_PIN, 0);
|
||||
port_delay_ms(1);
|
||||
port_pin_write(OMV_BOOT_OSPI_RST_PIN, 1);
|
||||
port_delay_ms(1);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int ospi_flash_init(ospi_flash_t *ospi) {
|
||||
if (ospi->initialized) {
|
||||
return 0;
|
||||
}
|
||||
|
||||
// Reset flash.
|
||||
ospi_flash_reset(ospi);
|
||||
|
||||
// Use SPI mode for initialization.
|
||||
ospi->spi_mode = true;
|
||||
ospi->regs = (ssi_regs_t *) OMV_BOOT_OSPI_SSI_BASE;
|
||||
ospi->aes_regs = (aes_regs_t *) OMV_BOOT_OSPI_AES_BASE;
|
||||
ospi->xip_base = (volatile void *) OMV_BOOT_OSPI_XIP_BASE;
|
||||
|
||||
// Initialize OSPI.
|
||||
spi_disable(ospi);
|
||||
ospi_writel(ospi, ser, 0);
|
||||
ospi_writel(ospi, rx_sample_dly, OMV_BOOT_OSPI_RX_DELAY);
|
||||
ospi_writel(ospi, txd_drive_edge, OMV_BOOT_OSPI_DDR_EDGE);
|
||||
ospi->aes_regs->aes_control &= ~AES_CONTROL_XIP_EN;
|
||||
ospi->aes_regs->aes_rxds_delay = OMV_BOOT_OSPI_RXDS_DELAY;
|
||||
spi_set_clk(ospi, (GetSystemAXIClock() / OMV_BOOT_OSPI_CLOCK));
|
||||
spi_enable(ospi);
|
||||
|
||||
// Detect onboard flash based on ID.
|
||||
uint8_t id[3] = { 0 };
|
||||
ospi_recv(ospi, OSPI_RDID_COMMAND, OSPI_ADDR_0BIT, 0, 3, id, OSPI_RDID_DCYCLES);
|
||||
// The byte order of 16-bit words is swapped when written in 1-1-1 and read back
|
||||
// in 8D-8D-8D. The MX chips seems to be the only one that doesn't swap 16-bit words.
|
||||
ospi->bswap16 = id[0] != 0xC2;
|
||||
ospi->initialized = true;
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int ospi_flash_deinit(ospi_flash_t *ospi) {
|
||||
if (ospi->regs) {
|
||||
spi_disable(ospi);
|
||||
spi_set_clk(ospi, 0);
|
||||
}
|
||||
ospi->initialized = false;
|
||||
|
||||
// Reset flash.
|
||||
return ospi_flash_reset(ospi);
|
||||
}
|
||||
|
||||
static int ospi_flash_erase(ospi_flash_t *ospi, uint32_t addr) {
|
||||
if (ospi_flash_write_enable(ospi) != 0) {
|
||||
return -1;
|
||||
}
|
||||
if (ospi_send(ospi, OSPI_ERASE_COMMAND, OSPI_ADDR_32BIT, addr, 0, NULL) != 0) {
|
||||
return -1;
|
||||
}
|
||||
return ospi_flash_wait_wip0(ospi);
|
||||
}
|
||||
|
||||
static int ospi_flash_read_page(ospi_flash_t *ospi, uint32_t addr, uint8_t *buf, uint32_t size) {
|
||||
return ospi_recv(ospi, OSPI_READ_COMMAND, OSPI_ADDR_32BIT, addr, size, buf, OSPI_READ_DCYCLES);
|
||||
}
|
||||
|
||||
static int ospi_flash_write_page(ospi_flash_t *ospi, uint32_t addr, const uint8_t *buf, uint32_t size) {
|
||||
if (ospi_flash_write_enable(ospi) != 0) {
|
||||
return -1;
|
||||
}
|
||||
if (ospi_send(ospi, OSPI_WRITE_COMMAND, OSPI_ADDR_32BIT, addr, size, buf) != 0) {
|
||||
return -1;
|
||||
}
|
||||
return ospi_flash_wait_wip0(ospi);
|
||||
}
|
||||
|
||||
int spi_flash_read(uint32_t addr, uint8_t *buf, uint32_t size) {
|
||||
if (ospi_flash_init(&ospi) != 0) {
|
||||
return -1;
|
||||
}
|
||||
|
||||
for (size_t i = 0; i < size / OSPI_FIFO_SIZE; i++) {
|
||||
if (ospi_flash_read_page(&ospi, addr, buf, OSPI_FIFO_SIZE) != 0) {
|
||||
return -1;
|
||||
}
|
||||
buf += OSPI_FIFO_SIZE;
|
||||
addr += OSPI_FIFO_SIZE;
|
||||
}
|
||||
|
||||
if ((size % OSPI_FIFO_SIZE)) {
|
||||
return ospi_flash_read_page(&ospi, addr, buf, (size % OSPI_FIFO_SIZE));
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
int spi_flash_write(uint32_t addr, const uint8_t *buf, uint32_t size) {
|
||||
if (ospi_flash_init(&ospi) != 0) {
|
||||
return -1;
|
||||
}
|
||||
|
||||
if ((addr % OSPI_SECTOR_SIZE) == 0) {
|
||||
if (ospi_flash_erase(&ospi, addr) != 0) {
|
||||
return -1;
|
||||
}
|
||||
}
|
||||
|
||||
if (ospi.bswap16) {
|
||||
uint16_t *buf16 = (uint16_t *) buf;
|
||||
for (size_t i = 0; i < size / 2; i++) {
|
||||
buf16[i] = __REV16(buf16[i]);
|
||||
}
|
||||
}
|
||||
|
||||
for (size_t i = 0; i < size / OSPI_PAGE_SIZE; i++) {
|
||||
if (ospi_flash_write_page(&ospi, addr, buf, OSPI_PAGE_SIZE) != 0) {
|
||||
return -1;
|
||||
}
|
||||
buf += OSPI_PAGE_SIZE;
|
||||
addr += OSPI_PAGE_SIZE;
|
||||
}
|
||||
|
||||
if ((size % OSPI_PAGE_SIZE)) {
|
||||
return ospi_flash_write_page(&ospi, addr, buf, (size % OSPI_PAGE_SIZE));
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
int spi_flash_recovery(uint32_t addr, const uint8_t *buf, uint32_t size) {
|
||||
static const uint8_t key[] = {
|
||||
0x15, 0x9e, 0x7d, 0x42, 0x96, 0x1a, 0x71, 0xeb,
|
||||
0x73, 0xa3, 0x26, 0x29, 0x2b, 0x08, 0x09, 0x0e,
|
||||
};
|
||||
|
||||
if (ospi.recovered) {
|
||||
return -1;
|
||||
}
|
||||
|
||||
// Check recovery key.
|
||||
if (size < 16 || memcmp(buf, key, sizeof(key))) {
|
||||
return -1;
|
||||
}
|
||||
|
||||
// Init flash.
|
||||
if (ospi_flash_init(&ospi) != 0) {
|
||||
return -1;
|
||||
}
|
||||
|
||||
// 1. Perform JESD reset
|
||||
const pin_t *cs = &omv_boot_pins[OMV_BOOT_OSPI_CS_PIN];
|
||||
pinconf_set(cs->port, cs->pin, OMV_BOOT_ALT_GPIO, cs->pad);
|
||||
port_pin_mode(OMV_BOOT_OSPI_CS_PIN, PIN_MODE_OUTPUT);
|
||||
port_pin_write(OMV_BOOT_OSPI_CS_PIN, 1);
|
||||
|
||||
const pin_t *d0 = &omv_boot_pins[OMV_BOOT_OSPI_D0_PIN];
|
||||
pinconf_set(d0->port, d0->pin, OMV_BOOT_ALT_GPIO, d0->pad);
|
||||
port_pin_mode(OMV_BOOT_OSPI_D0_PIN, PIN_MODE_OUTPUT);
|
||||
port_pin_write(OMV_BOOT_OSPI_D0_PIN, 0);
|
||||
|
||||
// Clock out 0, 1, 0, 1
|
||||
for (size_t i = 0, v = 1; i < 4; v ^= 1, i++) {
|
||||
port_pin_write(OMV_BOOT_OSPI_CS_PIN, 0);
|
||||
port_delay_ns(500);
|
||||
|
||||
port_pin_write(OMV_BOOT_OSPI_D0_PIN, v);
|
||||
|
||||
port_pin_write(OMV_BOOT_OSPI_CS_PIN, 1);
|
||||
port_delay_ns(500);
|
||||
}
|
||||
|
||||
// Revert pin state.
|
||||
pinconf_set(d0->port, d0->pin, d0->alt, d0->pad);
|
||||
pinconf_set(cs->port, cs->pin, cs->alt, cs->pad);
|
||||
|
||||
// 2.Write Enable. Write Opcode 0x06 to set WEL bit to 1
|
||||
if (ospi_flash_write_enable(&ospi) != 0) {
|
||||
return -1;
|
||||
}
|
||||
|
||||
// 4. DFIM entry
|
||||
if (ospi_flash_write_reg(&ospi, OSPI_WRVL_COMMAND, OSPI_ADDR_24BIT, 0x1E, 0x6B) != 0) {
|
||||
return -1;
|
||||
}
|
||||
|
||||
if (ospi_flash_read_reg(&ospi, OSPI_RDVL_COMMAND, OSPI_ADDR_24BIT, 0x1E) != 1) {
|
||||
return -1;
|
||||
}
|
||||
|
||||
for (size_t i = 0; i < 2; i++) {
|
||||
// 5.a Initialize status register to 0xFF
|
||||
if (ospi_flash_write_reg(&ospi, OSPI_WRSR_COMMAND, OSPI_ADDR_0BIT, 0x00, 0xFF) != 0) {
|
||||
return -1;
|
||||
}
|
||||
|
||||
// 5.c Initialize status register to 0x00
|
||||
if (ospi_flash_write_reg(&ospi, OSPI_WRSR_COMMAND, OSPI_ADDR_0BIT, 0x00, 0x00) != 0) {
|
||||
return -1;
|
||||
}
|
||||
|
||||
// 6.a Initialize NCRs (Command=0xB1; Addr=0x00 to 0x0C; Data=0x00)
|
||||
for (size_t addr = 0x00; addr <= 0x0C; addr++) {
|
||||
if (ospi_flash_write_reg(&ospi, 0xB1, OSPI_ADDR_24BIT, addr, 0x00) != 0) {
|
||||
return -1;
|
||||
}
|
||||
}
|
||||
|
||||
// 6.c Initialize NCRs (Command=0xB1; Addr=0x00 to 0x0C; Data=0x00)
|
||||
for (size_t addr = 0x00; addr <= 0x0C; addr++) {
|
||||
if (ospi_flash_write_reg(&ospi, 0xB1, OSPI_ADDR_24BIT, addr, 0xFF) != 0) {
|
||||
return -1;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
for (size_t i = 0; i < 2; i++) {
|
||||
// 7.a Disable lock: Command=0x81; Addr=0x08; Data=0xF9
|
||||
if (ospi_flash_write_reg(&ospi, 0x81, OSPI_ADDR_24BIT, 0x08, 0xF9) != 0) {
|
||||
return -1;
|
||||
}
|
||||
|
||||
// 7.b Write 13: Command=0x42; Addr=0x00 to end (n=257); Data=0xFF
|
||||
for (size_t addr = 0; addr < 256; addr++) {
|
||||
if (ospi_flash_write_reg(&ospi, 0x42, OSPI_ADDR_24BIT, addr, 0xFF) != 0) {
|
||||
return -1;
|
||||
}
|
||||
}
|
||||
|
||||
// 8.a Disable lock: Command=0x81; Addr=0x08; Data=0xF9
|
||||
if (ospi_flash_write_reg(&ospi, 0x81, OSPI_ADDR_24BIT, 0x08, 0xF9) != 0) {
|
||||
return -1;
|
||||
}
|
||||
|
||||
// 8.b Write 03: Command=0x42; Addr=0x00 to end (n=257); Data=0x00
|
||||
for (size_t addr = 0; addr < 256; addr++) {
|
||||
if (ospi_flash_write_reg(&ospi, 0x42, OSPI_ADDR_24BIT, addr, 0x00) != 0) {
|
||||
return -1;
|
||||
}
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
for (size_t i = 0; i < 2; i++) {
|
||||
// 9, 11 Write entire Device to 0
|
||||
if (ospi_flash_chip_erase(&ospi, 0) != 0) {
|
||||
return -1;
|
||||
}
|
||||
|
||||
// 10, 12 Write entire Device to 1
|
||||
if (ospi_flash_chip_erase(&ospi, 1) != 0) {
|
||||
return -1;
|
||||
}
|
||||
}
|
||||
|
||||
// DFIM exit
|
||||
if (ospi_flash_write_reg(&ospi, OSPI_WRVL_COMMAND, OSPI_ADDR_24BIT, 0x1E, 0) != 0) {
|
||||
return -1;
|
||||
}
|
||||
|
||||
ospi.recovered = true;
|
||||
return 0;
|
||||
}
|
||||
|
||||
int spi_flash_deinit() {
|
||||
return ospi_flash_deinit(&ospi);
|
||||
}
|
||||
#endif // OMV_BOOT_SPI_FLASH_ENABLE
|
||||
208
src/boot/src/ports/alif/alif_port.c
Normal file
208
src/boot/src/ports/alif/alif_port.c
Normal file
@ -0,0 +1,208 @@
|
||||
/*
|
||||
* Copyright (C) 2023-2024 OpenMV, LLC.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Any redistribution, use, or modification in source or binary form
|
||||
* is done solely for personal benefit and not for any commercial
|
||||
* purpose or for monetary gain. For commercial licensing options,
|
||||
* please contact openmv@openmv.io
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE LICENSOR AND COPYRIGHT OWNER "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
|
||||
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE LICENSOR OR COPYRIGHT
|
||||
* OWNER BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
|
||||
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
|
||||
* OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* DFU bootloader Alif port.
|
||||
*/
|
||||
#include <stdint.h>
|
||||
#include <string.h>
|
||||
|
||||
#include ALIF_CMSIS_H
|
||||
#include "gpio.h"
|
||||
#include "pinconf.h"
|
||||
|
||||
#include "omv_boardconfig.h"
|
||||
#include "omv_bootconfig.h"
|
||||
#include "flash.h"
|
||||
#include "alif_services.h"
|
||||
|
||||
static volatile uint32_t ticks_ms;
|
||||
|
||||
void SysTick_Handler(void) {
|
||||
ticks_ms += 1;
|
||||
}
|
||||
|
||||
int port_init(void) {
|
||||
// Initialize the MPU and configure
|
||||
// the default attributes and regions.
|
||||
port_mpu_init();
|
||||
|
||||
// Initialize the services API.
|
||||
alif_services_init();
|
||||
|
||||
// Initialize and configure SysTick.
|
||||
SysTick_Config(SystemCoreClock / 1000);
|
||||
|
||||
// Configure pin mux.
|
||||
for (size_t i = 0; i < OMV_BOOT_PINS_COUNT; i++) {
|
||||
const pin_t *pin = &omv_boot_pins[i];
|
||||
pinconf_set(pin->port, pin->pin, pin->alt, pin->pad);
|
||||
}
|
||||
|
||||
// Configure USB MUX GPIO.
|
||||
port_pin_mode(OMV_BOOT_MUX_PIN, PIN_MODE_OUTPUT);
|
||||
port_pin_write(OMV_BOOT_MUX_PIN, 1);
|
||||
|
||||
// Configure LED GPIO.
|
||||
port_pin_mode(OMV_BOOT_LED_PIN, PIN_MODE_OUTPUT);
|
||||
port_pin_write(OMV_BOOT_LED_PIN, 1);
|
||||
|
||||
// Configure OSPI reset GPIO.
|
||||
port_pin_mode(OMV_BOOT_OSPI_RST_PIN, PIN_MODE_OUTPUT);
|
||||
port_pin_write(OMV_BOOT_OSPI_RST_PIN, 0);
|
||||
|
||||
// Configure and enable USB IRQs.
|
||||
NVIC_ClearPendingIRQ(USB_IRQ_IRQn);
|
||||
NVIC_SetPriority(USB_IRQ_IRQn, OMV_BOOT_USB_IRQ_PRI);
|
||||
return 0;
|
||||
}
|
||||
|
||||
int port_deinit(void) {
|
||||
// Deinit DCD and disable USB IRQs.
|
||||
extern void dcd_uninit(void);
|
||||
dcd_uninit();
|
||||
|
||||
// Deinit services API.
|
||||
alif_services_deinit();
|
||||
|
||||
// Deinitialize SPI Flash.
|
||||
#if OMV_BOOT_SPI_FLASH_ENABLE
|
||||
spi_flash_deinit();
|
||||
#endif
|
||||
|
||||
// Disable SysTick and its IRQ.
|
||||
NVIC_DisableIRQ(SysTick_IRQn);
|
||||
NVIC_ClearPendingIRQ(SysTick_IRQn);
|
||||
SysTick->CTRL &= ~(SysTick_CTRL_ENABLE_Msk);
|
||||
|
||||
// Clean/invalidate any cached lines.
|
||||
SCB_CleanInvalidateDCache();
|
||||
|
||||
// Clear default regions and configure XIP regions (if any).
|
||||
port_mpu_deinit();
|
||||
|
||||
// Turn off LED.
|
||||
gpio_set_value_high(omv_boot_pins[OMV_BOOT_LED_PIN].gpio, omv_boot_pins[OMV_BOOT_LED_PIN].pin);
|
||||
return 0;
|
||||
}
|
||||
|
||||
int port_get_uid(uint8_t *buf) {
|
||||
alif_services_get_unique_id(buf, 12);
|
||||
return 0;
|
||||
}
|
||||
|
||||
void port_mpu_protect(const partition_t *p, bool enable) {
|
||||
if (p->region != -1) {
|
||||
ARM_MPU_Disable();
|
||||
MPU->RNR = p->region;
|
||||
MPU->RBAR = ARM_MPU_RBAR(p->start, ARM_MPU_SH_NON, enable & 1, 1, 0); // RO/NP/XN.
|
||||
MPU->RLAR = ARM_MPU_RLAR(p->limit - 1, p->attr);
|
||||
ARM_MPU_Enable(MPU_CTRL_PRIVDEFENA_Msk | MPU_CTRL_HFNMIENA_Msk);
|
||||
}
|
||||
}
|
||||
|
||||
uint32_t port_ticks_ms() {
|
||||
return ticks_ms;
|
||||
}
|
||||
|
||||
void port_delay_ms(uint32_t ms) {
|
||||
uint32_t start_ms = port_ticks_ms();
|
||||
while ((port_ticks_ms() - start_ms) < ms) {
|
||||
__WFI();
|
||||
}
|
||||
}
|
||||
|
||||
void port_pin_mode(uint32_t pin, uint32_t mode) {
|
||||
if (mode == PIN_MODE_OUTPUT) {
|
||||
gpio_set_direction_output(omv_boot_pins[pin].gpio, omv_boot_pins[pin].pin);
|
||||
} else {
|
||||
gpio_set_direction_input(omv_boot_pins[pin].gpio, omv_boot_pins[pin].pin);
|
||||
}
|
||||
}
|
||||
|
||||
void port_pin_write(uint32_t pin, uint32_t state) {
|
||||
if (state) {
|
||||
gpio_set_value_high(omv_boot_pins[pin].gpio, omv_boot_pins[pin].pin);
|
||||
} else {
|
||||
gpio_set_value_low(omv_boot_pins[pin].gpio, omv_boot_pins[pin].pin);
|
||||
}
|
||||
}
|
||||
|
||||
void port_led_blink(uint32_t interval_ms) {
|
||||
static uint32_t start_ms = 0;
|
||||
static uint32_t led_state = 0;
|
||||
|
||||
if ((port_ticks_ms() - start_ms) < interval_ms) {
|
||||
return;
|
||||
}
|
||||
|
||||
led_state ^= 1;
|
||||
port_pin_write(OMV_BOOT_LED_PIN, led_state);
|
||||
start_ms += interval_ms;
|
||||
}
|
||||
|
||||
// Bypass startup MPU defaults.
|
||||
void MPU_Setup(void) {
|
||||
|
||||
}
|
||||
|
||||
// Bypass startup MPU regions.
|
||||
void MPU_Load_Regions(void) {
|
||||
|
||||
}
|
||||
|
||||
void port_mpu_load_defaults() {
|
||||
static const ARM_MPU_Region_t mpu_table[] __STARTUP_RO_DATA_ATTRIBUTE = {
|
||||
{ /* SRAM0 - 4MB : RO-0, NP-1, XN-0 */
|
||||
.RBAR = ARM_MPU_RBAR(0x02000000, ARM_MPU_SH_NON, 0, 1, 0),
|
||||
.RLAR = ARM_MPU_RLAR(0x023FFFFF, MEMATTR_NORMAL_RA)
|
||||
},
|
||||
{ /* SRAM1 - 2.5MB : RO-0, NP-1, XN-0 */
|
||||
.RBAR = ARM_MPU_RBAR(0x08000000, ARM_MPU_SH_NON, 0, 1, 0),
|
||||
.RLAR = ARM_MPU_RLAR(0x0827FFFF, MEMATTR_NORMAL_WB_RA_WA)
|
||||
},
|
||||
{ /* Host Peripherals - 16MB : RO-0, NP-1, XN-1 */
|
||||
.RBAR = ARM_MPU_RBAR(0x1A000000, ARM_MPU_SH_NON, 0, 1, 1),
|
||||
.RLAR = ARM_MPU_RLAR(0x1AFFFFFF, MEMATTR_DEVICE_nGnRE)
|
||||
},
|
||||
{ /* OSPI Regs - 16MB : RO-0, NP-1, XN-1 */
|
||||
.RBAR = ARM_MPU_RBAR(0x83000000, ARM_MPU_SH_NON, 0, 1, 1),
|
||||
.RLAR = ARM_MPU_RLAR(0x83FFFFFF, MEMATTR_DEVICE_nGnRE)
|
||||
},
|
||||
};
|
||||
|
||||
/* Load the regions from the table */
|
||||
ARM_MPU_Load(0, mpu_table, sizeof(mpu_table) / sizeof(ARM_MPU_Region_t));
|
||||
}
|
||||
|
||||
void __attribute__((noreturn)) __fatal_error(const char *msg) {
|
||||
while (1) {
|
||||
port_led_blink(50);
|
||||
}
|
||||
}
|
||||
192
src/boot/src/ports/alif/alif_port.mk
Normal file
192
src/boot/src/ports/alif/alif_port.mk
Normal file
@ -0,0 +1,192 @@
|
||||
# Copyright (C) 2023-2024 OpenMV, LLC.
|
||||
#
|
||||
# Redistribution and use in source and binary forms, with or without
|
||||
# modification, are permitted provided that the following conditions
|
||||
# are met:
|
||||
#
|
||||
# 1. Redistributions of source code must retain the above copyright
|
||||
# notice, this list of conditions and the following disclaimer.
|
||||
# 2. Redistributions in binary form must reproduce the above copyright
|
||||
# notice, this list of conditions and the following disclaimer in
|
||||
# the documentation and/or other materials provided with the
|
||||
# distribution.
|
||||
# 3. Any redistribution, use, or modification in source or binary form
|
||||
# is done solely for personal benefit and not for any commercial
|
||||
# purpose or for monetary gain. For commercial licensing options,
|
||||
# please contact openmv@openmv.io
|
||||
#
|
||||
# THIS SOFTWARE IS PROVIDED BY THE LICENSOR AND COPYRIGHT OWNER "AS IS"
|
||||
# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
|
||||
# THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE LICENSOR OR COPYRIGHT
|
||||
# OWNER BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
|
||||
# PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
# PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
|
||||
# OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
|
||||
# Include OpenMV board config first to set the port.
|
||||
include $(OMV_BOARD_CONFIG_DIR)/omv_boardconfig.mk
|
||||
|
||||
LDSCRIPT ?= alif
|
||||
BUILD := $(BUILD)/bootloader
|
||||
FIRMWARE := bootloader
|
||||
CMSIS_MCU_H := '<system_utils.h>'
|
||||
|
||||
# Compiler Flags
|
||||
CFLAGS += -std=gnu99 \
|
||||
-Wall \
|
||||
-Werror \
|
||||
-Warray-bounds \
|
||||
-nostartfiles \
|
||||
-fdata-sections \
|
||||
-ffunction-sections \
|
||||
-fno-inline-small-functions \
|
||||
-mfloat-abi=hard \
|
||||
-mthumb \
|
||||
-mcpu=$(CPU) \
|
||||
-mtune=$(CPU) \
|
||||
-mfpu=$(FPU) \
|
||||
-march=armv8.1-m.main+fp+mve.fp \
|
||||
-fsingle-precision-constant \
|
||||
-Wdouble-promotion
|
||||
|
||||
CFLAGS += -D__VFP_FP__ \
|
||||
-D$(TARGET) \
|
||||
-D$(MCU_CORE) \
|
||||
-DCORE_$(MCU_CORE)=1 \
|
||||
-D$(ARM_MATH) \
|
||||
-DARM_NN_TRUNCATE \
|
||||
-DETHOS_U \
|
||||
-DPINS_AF_H=$(PINS_AF_H) \
|
||||
-DCMSIS_MCU_H=$(CMSIS_MCU_H) \
|
||||
-DALIF_CMSIS_H=$(CMSIS_MCU_H) \
|
||||
-DBOOTLOADER=1 \
|
||||
-DOMV_NOSYS_STUBS_ENABLE=1 \
|
||||
-DTUSB_ALIF_NO_IRQ_CFG \
|
||||
-DOMV_BOOT_JUMP=$(OMV_FIRM_ADDR) \
|
||||
$(OMV_BOOT_CFLAGS) \
|
||||
$(OMV_BOARD_CFLAGS)
|
||||
|
||||
CFLAGS += -I$(OMV_BOARD_CONFIG_DIR) \
|
||||
-I$(TOP_DIR)/$(BOOT_DIR)/include \
|
||||
-I$(TOP_DIR)/$(BOOT_DIR)/$(PORT_DIR) \
|
||||
-I$(TOP_DIR)/$(CMSIS_DIR)/include \
|
||||
-I$(TOP_DIR)/$(HAL_DIR)/drivers/include \
|
||||
-I$(TOP_DIR)/$(HAL_DIR)/ospi_xip/source/ospi \
|
||||
-I$(TOP_DIR)/$(HAL_DIR)/se_services/include \
|
||||
-I$(TOP_DIR)/$(HAL_DIR)/Device/common/config \
|
||||
-I$(TOP_DIR)/$(HAL_DIR)/Device/common/include \
|
||||
-I$(TOP_DIR)/$(HAL_DIR)/Device/core/$(MCU_CORE)/config \
|
||||
-I$(TOP_DIR)/$(HAL_DIR)/Device/core/$(MCU_CORE)/include \
|
||||
-I$(TOP_DIR)/$(HAL_DIR)/Device/$(MCU_SERIES)/$(MCU_VARIANT) \
|
||||
-I$(TOP_DIR)/$(TINYUSB_DIR)/src
|
||||
|
||||
# Linker Flags
|
||||
LDFLAGS = -mthumb \
|
||||
-mcpu=$(CPU) \
|
||||
-mfpu=$(FPU) \
|
||||
-mfloat-abi=hard \
|
||||
-mabi=aapcs-linux \
|
||||
-Wl,--print-memory-usage \
|
||||
-Wl,--gc-sections \
|
||||
-Wl,--no-warn-rwx-segment \
|
||||
-Wl,-Map=$(BUILD)/$(FIRMWARE).map \
|
||||
-Wl,-T$(BUILD)/$(LDSCRIPT).lds
|
||||
|
||||
SRC_C += $(addprefix src/common/, \
|
||||
dfu.c \
|
||||
mpu.c \
|
||||
desc.c \
|
||||
main.c \
|
||||
)
|
||||
|
||||
SRC_C += $(addprefix $(PORT_DIR)/, \
|
||||
alif_ospi.c \
|
||||
alif_port.c \
|
||||
alif_flash.c \
|
||||
alif_services.c \
|
||||
)
|
||||
|
||||
SRC_C += $(addprefix $(OMV_COMMON_DIR)/, \
|
||||
nosys_stubs.c \
|
||||
)
|
||||
|
||||
SRC_C += $(addprefix $(TINYUSB_DIR)/, \
|
||||
src/tusb.c \
|
||||
src/class/dfu/dfu_device.c \
|
||||
src/common/tusb_fifo.c \
|
||||
src/device/usbd.c \
|
||||
src/device/usbd_control.c \
|
||||
)
|
||||
|
||||
SRC_C += $(addprefix $(HAL_DIR)/, \
|
||||
drivers/source/pinconf.c \
|
||||
drivers/source/mhu_driver.c \
|
||||
drivers/source/mhu_receiver.c \
|
||||
drivers/source/mhu_sender.c \
|
||||
Device/common/source/clk.c \
|
||||
Device/common/source/dcd.c \
|
||||
Device/common/source/mpu_M55.c \
|
||||
Device/common/source/tgu_M55.c \
|
||||
Device/common/source/system_M55.c \
|
||||
Device/common/source/system_utils.c \
|
||||
Device/common/source/tcm_partition.c \
|
||||
Device/core/$(MCU_CORE)/source/startup_$(MCU_CORE).c \
|
||||
se_services/source/services_host_clocks.c \
|
||||
se_services/source/services_host_handler.c \
|
||||
se_services/source/services_host_power.c \
|
||||
se_services/source/services_host_system.c \
|
||||
se_services/source/services_host_maintenance.c \
|
||||
)
|
||||
|
||||
# Firmware objects
|
||||
OBJS += $(addprefix $(BUILD)/, $(SRC_C:.c=.o))
|
||||
OBJS += $(addprefix $(BUILD)/, $(SRC_S:.s=.o))
|
||||
OBJS_DIR = $(sort $(dir $(OBJS)))
|
||||
|
||||
$(BUILD)/$(HAL_DIR)/se_services/source/services_host_boot.o: override CFLAGS += -Wno-stringop-truncation
|
||||
$(BUILD)/$(HAL_DIR)/se_services/source/services_host_system.o: override CFLAGS += -Wno-maybe-uninitialized
|
||||
|
||||
all: $(FIRMWARE)
|
||||
$(SIZE) $(FW_DIR)/$(FIRMWARE).elf
|
||||
|
||||
$(OBJS_DIR):
|
||||
$(MKDIR) -p $@
|
||||
|
||||
$(BUILD)/%.o : %.c
|
||||
$(ECHO) "CC $<"
|
||||
$(CC) $(CFLAGS) -c -o $@ $<
|
||||
|
||||
$(BUILD)/$(HAL_DIR)/%.o : $(TOP_DIR)/$(HAL_DIR)/%.c
|
||||
$(ECHO) "CC $(shell realpath --relative-to=pwd $<)"
|
||||
$(CC) $(CFLAGS) -c -o $@ $<
|
||||
|
||||
$(BUILD)/$(TINYUSB_DIR)/%.o : $(TOP_DIR)/$(TINYUSB_DIR)/%.c
|
||||
$(ECHO) "CC $(shell realpath --relative-to=pwd $<)"
|
||||
$(CC) $(CFLAGS) -c -o $@ $<
|
||||
|
||||
$(BUILD)/$(OMV_COMMON_DIR)/%.o : $(TOP_DIR)/$(OMV_COMMON_DIR)/%.c
|
||||
$(ECHO) "CC $(shell realpath --relative-to=pwd $<)"
|
||||
$(CC) $(CFLAGS) -c -o $@ $<
|
||||
|
||||
$(BUILD)/%.o : %.s
|
||||
$(ECHO) "AS $<"
|
||||
$(AS) $(AFLAGS) $< -o $@
|
||||
|
||||
FIRMWARE_OBJS: | $(OBJS_DIR) $(OBJS)
|
||||
|
||||
$(FIRMWARE): FIRMWARE_OBJS
|
||||
$(CPP) -P -E -DBOOTLOADER -DLINKER_SCRIPT -DCORE_$(MCU_CORE) -I$(OMV_COMMON_DIR) \
|
||||
-I$(OMV_BOARD_CONFIG_DIR) $(PORT_DIR)/$(LDSCRIPT).ld.S > $(BUILD)/$(LDSCRIPT).lds
|
||||
$(CC) $(LDFLAGS) $(OBJS) -o $(FW_DIR)/$(FIRMWARE).elf
|
||||
$(OBJCOPY) -Obinary $(FW_DIR)/$(FIRMWARE).elf $(FW_DIR)/$(FIRMWARE).bin
|
||||
BIN_SIZE=$$(stat -c%s "$(FW_DIR)/$(FIRMWARE).bin"); \
|
||||
PADDED_SIZE=$$(( (BIN_SIZE + 15) / 16 * 16 )); \
|
||||
if [ $$BIN_SIZE -lt $$PADDED_SIZE ]; then \
|
||||
dd if=/dev/zero bs=1 count=$$((PADDED_SIZE - BIN_SIZE)) >> $(FW_DIR)/$(FIRMWARE).bin; \
|
||||
fi
|
||||
|
||||
-include $(OBJS:%.o=%.d)
|
||||
153
src/boot/src/ports/alif/alif_services.c
Normal file
153
src/boot/src/ports/alif/alif_services.c
Normal file
@ -0,0 +1,153 @@
|
||||
/*
|
||||
* Copyright (C) 2023-2025 OpenMV, LLC.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Any redistribution, use, or modification in source or binary form
|
||||
* is done solely for personal benefit and not for any commercial
|
||||
* purpose or for monetary gain. For commercial licensing options,
|
||||
* please contact openmv@openmv.io
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE LICENSOR AND COPYRIGHT OWNER "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
|
||||
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE LICENSOR OR COPYRIGHT
|
||||
* OWNER BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
|
||||
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
|
||||
* OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* SE services helper functions.
|
||||
*/
|
||||
#include <stdio.h>
|
||||
#include <string.h>
|
||||
|
||||
#include ALIF_CMSIS_H
|
||||
#include "alif_services.h"
|
||||
#include "services_lib_bare_metal.h"
|
||||
|
||||
// MHU indices.
|
||||
#define MHU_M55_SE_MHU0 0
|
||||
#define MAX_MHU 1
|
||||
|
||||
extern void __fatal_error(const char *msg);
|
||||
|
||||
static uint32_t se_handle;
|
||||
static uint32_t se_buffer[SERVICES_MAX_PACKET_BUFFER_SIZE / sizeof(uint32_t)];
|
||||
static mhu_driver_out_t mhu_driver_out;
|
||||
|
||||
static const uint32_t mhu_sender_base_address_list[MAX_MHU] = {
|
||||
MHU_SESS_S_TX_BASE,
|
||||
};
|
||||
|
||||
static const uint32_t mhu_receiver_base_address_list[MAX_MHU] = {
|
||||
MHU_SESS_S_RX_BASE,
|
||||
};
|
||||
|
||||
void MHU_SESS_S_TX_IRQHandler(void) {
|
||||
mhu_driver_out.sender_irq_handler(MHU_M55_SE_MHU0);
|
||||
}
|
||||
|
||||
void MHU_SESS_S_RX_IRQHandler(void) {
|
||||
mhu_driver_out.receiver_irq_handler(MHU_M55_SE_MHU0);
|
||||
}
|
||||
|
||||
static int dummy_printf(const char *fmt, ...) {
|
||||
(void) fmt;
|
||||
return 0;
|
||||
}
|
||||
|
||||
void alif_services_init(void) {
|
||||
// Initialize MHU.
|
||||
mhu_driver_in_t mhu_driver_in = {
|
||||
.sender_base_address_list = (uint32_t *) mhu_sender_base_address_list,
|
||||
.receiver_base_address_list = (uint32_t *) mhu_receiver_base_address_list,
|
||||
.mhu_count = MAX_MHU,
|
||||
.send_msg_acked_callback = SERVICES_send_msg_acked_callback,
|
||||
.rx_msg_callback = SERVICES_rx_msg_callback,
|
||||
.debug_print = NULL, // not currently used by MHU_driver_initialize
|
||||
};
|
||||
MHU_driver_initialize(&mhu_driver_in, &mhu_driver_out);
|
||||
|
||||
// Initialize SE services.
|
||||
services_lib_t services_init_params = {
|
||||
.packet_buffer_address = (uint32_t) se_buffer,
|
||||
.fn_send_mhu_message = mhu_driver_out.send_message,
|
||||
.fn_wait_ms = NULL, // not currently used by services_host_handler.c
|
||||
.wait_timeout = 1000000,
|
||||
.fn_print_msg = dummy_printf,
|
||||
};
|
||||
SERVICES_initialize(&services_init_params);
|
||||
|
||||
// Create SE services channel for sending requests.
|
||||
se_handle = SERVICES_register_channel(MHU_M55_SE_MHU0, 0);
|
||||
|
||||
// Enable MHU RX IRQ.
|
||||
NVIC_SetPriority(MHU_SESS_S_RX_IRQ_IRQn, 0);
|
||||
NVIC_ClearPendingIRQ(MHU_SESS_S_RX_IRQ_IRQn);
|
||||
NVIC_EnableIRQ(MHU_SESS_S_RX_IRQ_IRQn);
|
||||
|
||||
// Enable MHU TX IRQ.
|
||||
NVIC_SetPriority(MHU_SESS_S_TX_IRQ_IRQn, 0);
|
||||
NVIC_ClearPendingIRQ(MHU_SESS_S_TX_IRQ_IRQn);
|
||||
NVIC_EnableIRQ(MHU_SESS_S_TX_IRQ_IRQn);
|
||||
|
||||
// Send heartbeat services requests until one succeeds.
|
||||
SERVICES_synchronize_with_se(se_handle);
|
||||
|
||||
// Set default run profile
|
||||
run_profile_t run_profile = {
|
||||
.dcdc_mode = DCDC_MODE_PWM,
|
||||
.dcdc_voltage = DCDC_VOUT_0825,
|
||||
.aon_clk_src = CLK_SRC_LFXO,
|
||||
.run_clk_src = CLK_SRC_PLL,
|
||||
#if CORE_M55_HP
|
||||
.cpu_clk_freq = CLOCK_FREQUENCY_400MHZ,
|
||||
#else
|
||||
.cpu_clk_freq = CLOCK_FREQUENCY_160MHZ,
|
||||
#endif
|
||||
.scaled_clk_freq = SCALED_FREQ_XO_HIGH_DIV_38_4_MHZ,
|
||||
.power_domains = PD_VBAT_AON_MASK | PD_SSE700_AON_MASK | PD_SYST_MASK |
|
||||
PD_DBSS_MASK | PD_SESS_MASK | PD_SRAMS_MASK | PD_SRAM_CTRL_AON_MASK,
|
||||
.memory_blocks = SERAM_MASK | SRAM0_MASK | SRAM1_MASK | MRAM_MASK | BACKUP4K_MASK,
|
||||
.ip_clock_gating = OSPI_1_MASK | USB_MASK | LP_PERIPH_MASK,
|
||||
.phy_pwr_gating = LDO_PHY_MASK | USB_PHY_MASK,
|
||||
.vdd_ioflex_3V3 = IOFLEX_LEVEL_3V3,
|
||||
};
|
||||
|
||||
uint32_t error;
|
||||
SERVICES_set_run_cfg(se_handle, &run_profile, &error);
|
||||
if (error) {
|
||||
__fatal_error("SERVICES_set_run_cfg");
|
||||
}
|
||||
}
|
||||
|
||||
void alif_services_deinit(void) {
|
||||
// Disable MHU RX IRQ.
|
||||
NVIC_DisableIRQ(MHU_SESS_S_RX_IRQ_IRQn);
|
||||
NVIC_ClearPendingIRQ(MHU_SESS_S_RX_IRQ_IRQn);
|
||||
|
||||
// Disable MHU TX IRQ.
|
||||
NVIC_DisableIRQ(MHU_SESS_S_TX_IRQ_IRQn);
|
||||
NVIC_ClearPendingIRQ(MHU_SESS_S_TX_IRQ_IRQn);
|
||||
}
|
||||
|
||||
void alif_services_get_unique_id(uint8_t *id, size_t len) {
|
||||
uint32_t error;
|
||||
SERVICES_version_data_t data = { 0 };
|
||||
SERVICES_system_get_device_data(se_handle, &data, &error);
|
||||
if (error == 0) {
|
||||
memcpy(id, data.MfgData, len);
|
||||
}
|
||||
}
|
||||
38
src/boot/src/ports/alif/alif_services.h
Normal file
38
src/boot/src/ports/alif/alif_services.h
Normal file
@ -0,0 +1,38 @@
|
||||
/*
|
||||
* Copyright (C) 2023-2025 OpenMV, LLC.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Any redistribution, use, or modification in source or binary form
|
||||
* is done solely for personal benefit and not for any commercial
|
||||
* purpose or for monetary gain. For commercial licensing options,
|
||||
* please contact openmv@openmv.io
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE LICENSOR AND COPYRIGHT OWNER "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
|
||||
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE LICENSOR OR COPYRIGHT
|
||||
* OWNER BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
|
||||
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
|
||||
* OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* SE services helper functions.
|
||||
*/
|
||||
#ifndef __ALIF_PORT_SE_H__
|
||||
#define __ALIF_PORT_SE_H__
|
||||
void alif_services_init(void);
|
||||
void alif_services_deinit(void);
|
||||
void alif_services_get_unique_id(uint8_t *id, size_t len);
|
||||
#endif // __ALIF_PORT_SE_H__
|
||||
52
src/boot/src/ports/alif/tusb_config.h
Normal file
52
src/boot/src/ports/alif/tusb_config.h
Normal file
@ -0,0 +1,52 @@
|
||||
/*
|
||||
* Copyright (C) 2023-2024 OpenMV, LLC.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Any redistribution, use, or modification in source or binary form
|
||||
* is done solely for personal benefit and not for any commercial
|
||||
* purpose or for monetary gain. For commercial licensing options,
|
||||
* please contact openmv@openmv.io
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE LICENSOR AND COPYRIGHT OWNER "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
|
||||
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE LICENSOR OR COPYRIGHT
|
||||
* OWNER BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
|
||||
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
|
||||
* OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* TinyUSB config.
|
||||
*/
|
||||
#ifndef __ALIF_TUSB_CONFIG_H__
|
||||
#define __ALIF_TUSB_CONFIG_H__
|
||||
// Common configuration
|
||||
#define CFG_TUSB_OS OPT_OS_NONE
|
||||
#define CFG_TUSB_MCU OPT_MCU_NONE
|
||||
#define CFG_TUSB_RHPORT0_MODE (OPT_MODE_DEVICE | OPT_MODE_HIGH_SPEED)
|
||||
#define TUP_DCD_ENDPOINT_MAX (8)
|
||||
|
||||
// Device stack configuration.
|
||||
#define CFG_TUD_ENABLED (1)
|
||||
#define CFG_TUD_DFU (1)
|
||||
#define CFG_TUD_ENDPOINT0_SIZE (64)
|
||||
#define CFG_TUD_DFU_XFER_BUFSIZE (4096)
|
||||
|
||||
// Peripherals in expansion master 0 (such as USB, Ethernet, SD/MMC)
|
||||
// are by default configured as non-secure, so they don't have access
|
||||
// to DTCMs. These peripherals should place buffers in regular SRAM.
|
||||
#define CFG_TUSB_MEM_SECTION __attribute__((section(".bss.sram0")))
|
||||
#define CFG_TUSB_MEM_ALIGN __attribute__ ((aligned(256)))
|
||||
#endif //__ALIF_TUSB_CONFIG_H__
|
||||
1956
src/hal/alif/AlifSemiconductor.Ensemble.pdsc
Normal file
1956
src/hal/alif/AlifSemiconductor.Ensemble.pdsc
Normal file
File diff suppressed because it is too large
Load Diff
139
src/hal/alif/Alif_CMSIS/Include/Camera_Sensor.h
Normal file
139
src/hal/alif/Alif_CMSIS/Include/Camera_Sensor.h
Normal file
@ -0,0 +1,139 @@
|
||||
/* Copyright (C) 2023 Alif Semiconductor - All Rights Reserved.
|
||||
* Use, distribution and modification of this code is permitted under the
|
||||
* terms stated in the Alif Semiconductor Software License Agreement
|
||||
*
|
||||
* You should have received a copy of the Alif Semiconductor Software
|
||||
* License Agreement with this file. If not, please write to:
|
||||
* contact@alifsemi.com, or visit: https://alifsemi.com/license
|
||||
*
|
||||
*/
|
||||
|
||||
/**************************************************************************//**
|
||||
* @file Camera_Sensor.h
|
||||
* @author Tanay Rami and Chandra Bhushan Singh
|
||||
* @email tanay@alifsemi.com and chandrabhushan.singh@alifsemi.com
|
||||
* @version V1.1.0
|
||||
* -Removed enums for clock source, interface, polarity, hsync mode,
|
||||
* data mode, and data mask.
|
||||
* -Included low level header file 'cpi.h'
|
||||
* -Replaced data types in CAMERA_SENSOR_INFO structure with CPI low
|
||||
* level file data types.
|
||||
* @date 19-April-2023
|
||||
* @brief Camera Sensor Device definitions.
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef CAMERA_SENSOR_H_
|
||||
#define CAMERA_SENSOR_H_
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
#include <stdint.h>
|
||||
#include <stdbool.h>
|
||||
#include "cpi.h"
|
||||
#include "csi.h"
|
||||
|
||||
/****** CAMERA_SENSOR used for registering camera sensor *****/
|
||||
#define CAMERA_SENSOR(sensor) \
|
||||
CAMERA_SENSOR_DEVICE *Get_Camera_Sensor(void) \
|
||||
{ \
|
||||
return &sensor; \
|
||||
} \
|
||||
|
||||
/****** LPCAMERA_SENSOR used for registering low power camera sensor *****/
|
||||
#define LPCAMERA_SENSOR(sensor) \
|
||||
CAMERA_SENSOR_DEVICE *Get_LPCamera_Sensor(void) \
|
||||
{ \
|
||||
return &sensor; \
|
||||
} \
|
||||
|
||||
/**
|
||||
\brief Camera Sensor interface
|
||||
*/
|
||||
typedef enum _CAMERA_SENSOR_INTERFACE {
|
||||
CAMERA_SENSOR_INTERFACE_PARALLEL, /* Camera sensor parallel interface */
|
||||
CAMERA_SENSOR_INTERFACE_MIPI /* Camera sensor serial interface */
|
||||
} CAMERA_SENSOR_INTERFACE;
|
||||
|
||||
/**
|
||||
\brief CPI information structure
|
||||
*/
|
||||
typedef struct _CPI_INFO {
|
||||
CPI_WAIT_VSYNC vsync_wait; /* CPI VSYNC Wait */
|
||||
CPI_CAPTURE_DATA_ENABLE vsync_mode; /* CPI VSYNC Mode */
|
||||
CPI_SIG_POLARITY pixelclk_pol; /* CPI Pixel Clock Polarity */
|
||||
CPI_SIG_POLARITY hsync_pol; /* CPI HSYNC Polarity */
|
||||
CPI_SIG_POLARITY vsync_pol; /* CPI VSYNC Polarity */
|
||||
CPI_DATA_MODE data_mode; /* CPI Data Mode */
|
||||
CPI_DATA_ENDIANNESS data_endianness; /* CPI MSB/LSB */
|
||||
CPI_CODE10ON8_CODING code10on8; /* CPI code10on8 enable/disable */
|
||||
CPI_DATA_MASK data_mask; /* CPI Data Mask */
|
||||
CPI_COLOR_MODE_CONFIG csi_mode; /* CPI CSI Color mode */
|
||||
} CPI_INFO;
|
||||
|
||||
/**
|
||||
\brief CSI override CPI color mode structure
|
||||
*/
|
||||
typedef struct _CSI_OVERRIDE_CPI_COLOR {
|
||||
bool override; /* CPI color mode override by CPI */
|
||||
CPI_COLOR_MODE_CONFIG cpi_color_mode; /* CPI color mode to be override */
|
||||
} CSI_OVERRIDE_CPI_COLOR;
|
||||
|
||||
/**
|
||||
\brief CSI Pkt2PktTime, Time between Packets (includes the duration of the LS
|
||||
Packet + PHY LowPower to High-Speed time + any eventual camera added delay
|
||||
+ PHY HighSpeed to Low-Power time).
|
||||
*/
|
||||
typedef struct _CSI_PKT2PKT_TIME{
|
||||
bool line_sync_pkt_enable; /* LS/LE Packets are enabled */
|
||||
float time_ns; /* Time between Packets in ns */
|
||||
}CSI_PKT2PKT_TIME;
|
||||
|
||||
/**
|
||||
\brief CSI information structure
|
||||
*/
|
||||
typedef struct _CSI_INFO {
|
||||
uint32_t frequency; /* CSI clock frequency */
|
||||
CSI_DATA_TYPE dt; /* CSI data type */
|
||||
uint8_t n_lanes; /* CSI number of data lanes */
|
||||
CSI_VC_ID vc_id; /* CSI virtual channel ID */
|
||||
CSI_OVERRIDE_CPI_COLOR cpi_cfg; /* CSI override CPI color mode */
|
||||
CSI_PKT2PKT_TIME pkt2pkt_time; /* CSI Time between Packets */
|
||||
} CSI_INFO;
|
||||
|
||||
/**
|
||||
\brief CAMERA Sensor Device Operations
|
||||
*/
|
||||
typedef struct _CAMERA_SENSOR_OPERATIONS {
|
||||
int32_t (*Init) (void); /* Initialize Camera Sensor device */
|
||||
int32_t (*Uninit) (void); /* De-initialize Camera Sensor device */
|
||||
int32_t (*Start) (void); /* Start Camera Sensor device */
|
||||
int32_t (*Stop) (void); /* Stop Camera Sensor device */
|
||||
int32_t (*Control) (uint32_t control, uint32_t arg); /* Control Camera Sensor device */
|
||||
} CAMERA_SENSOR_OPERATIONS;
|
||||
|
||||
/**
|
||||
\brief CAMERA Sensor Device
|
||||
*/
|
||||
typedef struct _CAMERA_SENSOR_DEVICE {
|
||||
CAMERA_SENSOR_INTERFACE interface; /* Camera Sensor interface */
|
||||
int width; /* Frame Width */
|
||||
int height; /* Frame Height */
|
||||
CPI_INFO *cpi_info; /* CPI Camera Sensor device Information */
|
||||
CSI_INFO *csi_info; /* CSI Camera Sensor device Information */
|
||||
CAMERA_SENSOR_OPERATIONS *ops; /* Camera Sensor device Operations */
|
||||
} CAMERA_SENSOR_DEVICE;
|
||||
|
||||
/** Get CPI/LPCPI sensor information */
|
||||
CAMERA_SENSOR_DEVICE *Get_Camera_Sensor(void);
|
||||
CAMERA_SENSOR_DEVICE *Get_LPCamera_Sensor(void);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* CAMERA_SENSOR_H_ */
|
||||
|
||||
/************************ (C) COPYRIGHT ALIF SEMICONDUCTOR *****END OF FILE****/
|
||||
67
src/hal/alif/Alif_CMSIS/Include/DMA_Common.h
Normal file
67
src/hal/alif/Alif_CMSIS/Include/DMA_Common.h
Normal file
@ -0,0 +1,67 @@
|
||||
/* Copyright (C) 2022 Alif Semiconductor - All Rights Reserved.
|
||||
* Use, distribution and modification of this code is permitted under the
|
||||
* terms stated in the Alif Semiconductor Software License Agreement
|
||||
*
|
||||
* You should have received a copy of the Alif Semiconductor Software
|
||||
* License Agreement with this file. If not, please write to:
|
||||
* contact@alifsemi.com, or visit: https://alifsemi.com/license
|
||||
*
|
||||
*/
|
||||
|
||||
/**************************************************************************//**
|
||||
* @file DMA_Common.h
|
||||
* @author Sudhir Sreedharan
|
||||
* @email sudhir@alifsemi.com
|
||||
* @version V1.0.0
|
||||
* @date 05-Aug-2022
|
||||
* @brief Common DMA definitions.
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef DMA_COMMON_H_
|
||||
#define DMA_COMMON_H_
|
||||
|
||||
#include <Driver_DMA.h>
|
||||
#include <RTE_Device.h>
|
||||
#include <evtrtr.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
#if RTE_DMA0
|
||||
extern ARM_DRIVER_DMA ARM_Driver_DMA_(0);
|
||||
#endif
|
||||
|
||||
#if RTE_DMA1
|
||||
extern ARM_DRIVER_DMA ARM_Driver_DMA_(1);
|
||||
#endif
|
||||
|
||||
#if RTE_DMA2
|
||||
extern ARM_DRIVER_DMA ARM_Driver_DMA_(2);
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
\brief DMA Peripheral Configuration
|
||||
*/
|
||||
typedef struct _DMA_PERIPHERAL_CONFIG {
|
||||
|
||||
/*!< DMA controller driver */
|
||||
const ARM_DRIVER_DMA *dma_drv;
|
||||
|
||||
/*!< Peripheral request number */
|
||||
const uint8_t dma_periph_req;
|
||||
|
||||
/*!< DMA handle */
|
||||
DMA_Handle_Type dma_handle;
|
||||
|
||||
/*!< Event Router Configuration */
|
||||
EVTRTR_CONFIG evtrtr_cfg;
|
||||
} DMA_PERIPHERAL_CONFIG;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* DMA_COMMON_H_ */
|
||||
167
src/hal/alif/Alif_CMSIS/Include/Driver_ADC.h
Normal file
167
src/hal/alif/Alif_CMSIS/Include/Driver_ADC.h
Normal file
@ -0,0 +1,167 @@
|
||||
/* Copyright (C) 2023 Alif Semiconductor - All Rights Reserved.
|
||||
* Use, distribution and modification of this code is permitted under the
|
||||
* terms stated in the Alif Semiconductor Software License Agreement
|
||||
*
|
||||
* You should have received a copy of the Alif Semiconductor Software
|
||||
* License Agreement with this file. If not, please write to:
|
||||
* contact@alifsemi.com, or visit: https://alifsemi.com/license
|
||||
*
|
||||
*/
|
||||
/****************************************************************************
|
||||
* @file Driver_ADC.h
|
||||
* @author Prabhakar Kumar
|
||||
* @email prabhakar.kumar@alifsemi.com
|
||||
* @version V1.0.0
|
||||
* @date 22-feb-2022
|
||||
* @brief ADC (Analog to digital conversion) Driver Definition.
|
||||
*******************************************************************************/
|
||||
#ifndef DRIVER_ADC_H_
|
||||
#define DRIVER_ADC_H_
|
||||
|
||||
#include"Driver_Common.h"
|
||||
|
||||
#ifdef _cplusplus
|
||||
extern "c"
|
||||
{
|
||||
#endif
|
||||
|
||||
|
||||
#define ARM_ADC_API_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR (1,0) /*API VERSION*/
|
||||
|
||||
/**********ADC CONTROL CODE************/
|
||||
#define ARM_ADC_SHIFT_CTRL (0x01UL) /* ARM ADC SHIFT CONTROL */
|
||||
#define ARM_ADC_SEQUENCER_CTRL (0x02UL) /* ARM ADC SEQUENCER CONTROL */
|
||||
#define ARM_ADC_SEQUENCER_MSK_CH_CTRL (0x03UL) /* ARM ADC SEQUENCER MASK CHANNEL CONTROL */
|
||||
#define ARM_ADC_CHANNEL_INIT_VAL (0x04UL) /* ARM ADC CHANNEL INITIAL CONTROL */
|
||||
#define ARM_ADC_COMPARATOR_A (0x05UL) /* ARM ADC COMPARATOR A CONTROL */
|
||||
#define ARM_ADC_COMPARATOR_B (0x06UL) /* ARM ADC COMPARATOR B CONTROL */
|
||||
#define ARM_ADC_THRESHOLD_COMPARISON (0X07UL) /* ARM ADC THRESHOLD COMPARISON CONTROL */
|
||||
#define ARM_ADC_CONVERSION_MODE_CTRL (0x08UL) /* ARM ADC CONVERSION MODE CONTROL */
|
||||
#define ARM_ADC_EXTERNAL_TRIGGER_ENABLE (0x09UL) /* ARM ADC EXTERNAL TRIGGER ENABLE */
|
||||
#define ARM_ADC_EXTERNAL_TRIGGER_DISABLE (0x0AUL) /* ARM ADC EXTERNAL TRIGGER DISABLE */
|
||||
#define ARM_ADC_HARDWARE_AVERAGING_CTRL (0x0BUL) /* ARM ADC SET HARDWARE AVERAGING */
|
||||
#define ARM_ADC_SAMPLE_WIDTH_CTRL (0x0CUL) /* ARM ADC SAMPLE WIDTH CONTROL */
|
||||
#define ARM_ADC_DIFFERENTIAL_MODE_CTRL (0x0DUL) /* ARM ADC DIFFERENTIAL MODE CONTROL */
|
||||
#define ARM_ADC_INPUT_CLOCK_DIV_CTRL (0x0FUL) /* ARM ADC INPUT CLOCK DIVISOR CONTROL */
|
||||
#define ARM_ADC_SET_PGA_GAIN_CTRL (0x10UL) /* ARM ADC SET PGA GAIN CONTROL */
|
||||
#define ARM_ADC_24_BIAS_CTRL (0x11UL) /* ARM ADC 24 BIAS CONTROL */
|
||||
#define ARM_ADC_24_OUTPUT_RATE_CTRL (0x12UL) /* ARM ADC 24 OUTPUT RATE CONTROL */
|
||||
|
||||
/*********THRESHOLD COMPARSION**********/
|
||||
#define ARM_ADC_ABOVE_A_AND_ABOVE_B (0x00UL) /* ARM ADC THRESHOLD ABOVE A AND ABOVE B */
|
||||
#define ARM_ADC_BELOW_A_AND_BELOW_B (0x01UL) /* ARM ADC THRESHOLD BELOW A AND BELOW B */
|
||||
#define ARM_ADC_BETWEEN_A_B_AND_OUTSIDE_A_B (0x02UL) /* ARM ADC THRESHOLD BETWEEN A_B AND OUTSIDE A_B */
|
||||
|
||||
/**********ADC EVENT********************/
|
||||
#define ARM_ADC_EVENT_CONVERSION_COMPLETE (1 << 0) /* ARM ADC EVENT CONVERSION COMPLETE */
|
||||
#define ARM_ADC_COMPARATOR_THRESHOLD_ABOVE_A (1 << 1) /* ARM ADC COMPARATOR THRESHOLD ABOVE A */
|
||||
#define ARM_ADC_COMPARATOR_THRESHOLD_ABOVE_B (1 << 2) /* ARM ADC COMPARATOR THRESHOLD ABOVE B */
|
||||
#define ARM_ADC_COMPARATOR_THRESHOLD_BELOW_A (1 << 3) /* ARM ADC COMPARATOR THRESHOLD BELOW A */
|
||||
#define ARM_ADC_COMPARATOR_THRESHOLD_BELOW_B (1 << 4) /* ARM ADC COMPARATOR THRESHOLD BELOW B */
|
||||
#define ARM_ADC_COMPARATOR_THRESHOLD_BETWEEN_A_B (1 << 5) /* ARM ADC COMPARATOR THRESHOLD BETWEEN A_B */
|
||||
#define ARM_ADC_COMPARATOR_THRESHOLD_OUTSIDE_A_B (1 << 6) /* ARM ADC COMPARATOR THRESHOLD OUTSIDE A_B */
|
||||
|
||||
/**********ADC CONVERSION OPERATION**********/
|
||||
#define ARM_ADC_CONTINOUS_CH_CONV (0x00) /* ARM ADC CHANNEL CONTINUOUS CONVERSION */
|
||||
#define ARM_ADC_SINGLE_SHOT_CH_CONV (0x01) /* ARM ADC CHANNEL SINGLE CONVERSION */
|
||||
|
||||
/**********ADC SCAN OPERATION**********/
|
||||
#define ARM_ADC_MULTIPLE_CH_SCAN (0x00) /* ARM ADC MULTIPLE CHANNEL SCAN MODE */
|
||||
#define ARM_ADC_SINGLE_CH_SCAN (0x01) /* ARM ADC SINGLE CHANNEL SCAN MODE */
|
||||
|
||||
/**********ADC CHANNELS******/
|
||||
#define ARM_ADC_CHANNEL_0 (0x00) /* ARM ADC CHANNEL 0 */
|
||||
#define ARM_ADC_CHANNEL_1 (0x01) /* ARM ADC CHANNEL 1 */
|
||||
#define ARM_ADC_CHANNEL_2 (0x02) /* ARM ADC CHANNEL 2 */
|
||||
#define ARM_ADC_CHANNEL_3 (0x03) /* ARM ADC CHANNEL 3 */
|
||||
#define ARM_ADC_CHANNEL_4 (0x04) /* ARM ADC CHANNEL 4 */
|
||||
#define ARM_ADC_CHANNEL_5 (0x05) /* ARM ADC CHANNEL 5 */
|
||||
#define ARM_ADC_CHANNEL_6 (0x06) /* ARM ADC CHANNEL 6 */
|
||||
#define ARM_ADC_CHANNEL_7 (0x07) /* ARM ADC CHANNEL 7 */
|
||||
#define ARM_ADC_CHANNEL_8 (0x08) /* ARM ADC CHANNEL 8 */
|
||||
|
||||
/****ADC MASK CHANNEL****/
|
||||
#define ARM_ADC_MASK_CHANNEL_0 (1 << ARM_ADC_CHANNEL_0) /* ARM ADC MASK CHANNEL 0 */
|
||||
#define ARM_ADC_MASK_CHANNEL_1 (1 << ARM_ADC_CHANNEL_1) /* ARM ADC MASK CHANNEL 1 */
|
||||
#define ARM_ADC_MASK_CHANNEL_2 (1 << ARM_ADC_CHANNEL_2) /* ARM ADC MASK CHANNEL 2 */
|
||||
#define ARM_ADC_MASK_CHANNEL_3 (1 << ARM_ADC_CHANNEL_3) /* ARM ADC MASK CHANNEL 3 */
|
||||
#define ARM_ADC_MASK_CHANNEL_4 (1 << ARM_ADC_CHANNEL_4) /* ARM ADC MASK CHANNEL 4 */
|
||||
#define ARM_ADC_MASK_CHANNEL_5 (1 << ARM_ADC_CHANNEL_5) /* ARM ADC MASK CHANNEL 5 */
|
||||
#define ARM_ADC_MASK_CHANNEL_6 (1 << ARM_ADC_CHANNEL_6) /* ARM ADC MASK CHANNEL 6 */
|
||||
#define ARM_ADC_MASK_CHANNEL_7 (1 << ARM_ADC_CHANNEL_7) /* ARM ADC MASK CHANNEL 7 */
|
||||
#define ARM_ADC_MASK_CHANNEL_8 (1 << ARM_ADC_CHANNEL_8) /* ARM ADC MASK CHANNEL 8 */
|
||||
|
||||
/* External trigger macros */
|
||||
#define ARM_ADC_EXTERNAL_TRIGGER_SRC_0 (1UL << 0) /* ARM ADC EXTERNAL TRIGGER SOURCE 0 */
|
||||
#define ARM_ADC_EXTERNAL_TRIGGER_SRC_1 (1UL << 1) /* ARM ADC EXTERNAL TRIGGER SOURCE 1 */
|
||||
#define ARM_ADC_EXTERNAL_TRIGGER_SRC_2 (1UL << 2) /* ARM ADC EXTERNAL TRIGGER SOURCE 2 */
|
||||
#define ARM_ADC_EXTERNAL_TRIGGER_SRC_3 (1UL << 3) /* ARM ADC EXTERNAL TRIGGER SOURCE 3 */
|
||||
#define ARM_ADC_EXTERNAL_TRIGGER_SRC_4 (1UL << 4) /* ARM ADC EXTERNAL TRIGGER SOURCE 4 */
|
||||
#define ARM_ADC_EXTERNAL_TRIGGER_SRC_5 (1UL << 5) /* ARM ADC EXTERNAL TRIGGER SOURCE 5 */
|
||||
|
||||
// Function documentation
|
||||
/**
|
||||
@func : ARM_DRIVER_VERSION GetVersion (void)
|
||||
@brief : Get ADC driver version.
|
||||
@return : \ref ARM_DRIVER_VERSION
|
||||
@func : ARM_ADC_CAPABILITIES GetCapabilities (void)
|
||||
@brief : Get ADC driver capabilities
|
||||
@return : \ref ADC_CAPABILITIES
|
||||
|
||||
@func : int32_t Initialize (ARM_ADC_SignalEvent_t cb_event)
|
||||
@brief : Initialize ADC INterface
|
||||
@parameter[1] : cb_event : Pointer to ADC Event \ref ARM_ADC_Signal_Event
|
||||
@return : Execution status
|
||||
|
||||
@func : int32_t Uninitialize (void)
|
||||
@brief : De-initialize the ADC interface
|
||||
@return : Execution Status
|
||||
|
||||
@func : int32_t start (uint32_t *data, uint32_t num)
|
||||
@brief : Start the ADC and start collecting data
|
||||
@parameter[1] : data : pointer to unsigned int
|
||||
@parameter[2] : num : store the amount data
|
||||
@return : Execution status
|
||||
|
||||
@func : int32_t stop (void)
|
||||
@brief : Stop the ADC interface
|
||||
@PARAMETER : NONE
|
||||
@Return : Execution Status
|
||||
|
||||
@func : intt32_t PowerControl(ARM_Power_status state)
|
||||
@brief : Control ADC interface power
|
||||
@parameter[1] : state :power state
|
||||
@return : execution status
|
||||
|
||||
@func : int32_t control(uint32_t control, uint32_t arg)
|
||||
@brief : control ADC_interface
|
||||
@parameter[1] : control :operation
|
||||
@parameter[2] : arg :Argument of operation (optional)
|
||||
@return : Execution status
|
||||
*/
|
||||
|
||||
typedef void (*ARM_ADC_SignalEvent_t) (uint32_t event, uint8_t channel, uint32_t value); /*Pointer to \ref ADC_SignalEvent : Signal ADC Event*/
|
||||
|
||||
typedef struct _ARM_ADC_CAPABILITIES{
|
||||
uint32_t Resolution :1; /* Resolution 12 or 20 bits*/
|
||||
uint32_t Reserved :31; /* Reserved */
|
||||
}ARM_ADC_CAPABILITIES;
|
||||
|
||||
/* Access Structure Of ADC */
|
||||
typedef struct ARM_DRIVER_ADC{
|
||||
ARM_DRIVER_VERSION (*GetVersion) (void); /* pointer pointing to \ref ADC_get_verion */
|
||||
ARM_ADC_CAPABILITIES (*GetCapabilities) (void); /* Pointer to ADC_get_capabilities */
|
||||
int32_t (*Initialize) (ARM_ADC_SignalEvent_t cb_event); /* Pointer pointing to \ref ADC_intialize */
|
||||
int32_t (*Uninitialize) (void); /* Pointer pointing to \ref ADC_Unintialize */
|
||||
int32_t (*Start) (void); /* Pointer to \ref ADC_Start */
|
||||
int32_t (*Stop) (void); /* pointer to \ref ADC_Stop */
|
||||
int32_t (*PowerControl) (ARM_POWER_STATE state); /* Pointer to \ref ADC_PowerControl : Control ADC Interface Power */
|
||||
int32_t (*Control) (uint32_t Control, uint32_t arg); /* Pointer to \ref ADC_Control : Control ADC Interface */
|
||||
}const ARM_DRIVER_ADC;
|
||||
|
||||
#ifdef _cplusplus
|
||||
}
|
||||
#endif
|
||||
#endif /* DRIVER_ADC_H_ */
|
||||
|
||||
/************************ (C) COPYRIGHT ALIF SEMICONDUCTOR *****END OF FILE****/
|
||||
388
src/hal/alif/Alif_CMSIS/Include/Driver_CAN.h
Normal file
388
src/hal/alif/Alif_CMSIS/Include/Driver_CAN.h
Normal file
@ -0,0 +1,388 @@
|
||||
/*
|
||||
* Copyright (c) 2015-2020 ARM Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* $Date: 31. March 2020
|
||||
* $Revision: V1.3
|
||||
*
|
||||
* Project: CAN (Controller Area Network) Driver definitions
|
||||
*/
|
||||
|
||||
/* History:
|
||||
* Version 1.3
|
||||
* Removed volatile from ARM_CAN_STATUS
|
||||
* Version 1.2
|
||||
* Added ARM_CAN_UNIT_STATE_BUS_OFF unit state and
|
||||
* ARM_CAN_EVENT_UNIT_INACTIVE unit event
|
||||
* Version 1.1
|
||||
* ARM_CAN_STATUS made volatile
|
||||
* Version 1.0
|
||||
* Initial release
|
||||
*/
|
||||
|
||||
#ifndef DRIVER_CAN_H_
|
||||
#define DRIVER_CAN_H_
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
#include "Driver_Common.h"
|
||||
|
||||
#define ARM_CAN_API_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(1,3) /* API version */
|
||||
|
||||
|
||||
#define _ARM_Driver_CAN_(n) Driver_CAN##n
|
||||
#define ARM_Driver_CAN_(n) _ARM_Driver_CAN_(n)
|
||||
|
||||
|
||||
/****** CAN Bitrate selection codes *****/
|
||||
typedef enum _ARM_CAN_BITRATE_SELECT {
|
||||
ARM_CAN_BITRATE_NOMINAL, ///< Select nominal (flexible data-rate arbitration) bitrate
|
||||
ARM_CAN_BITRATE_FD_DATA ///< Select flexible data-rate data bitrate
|
||||
} ARM_CAN_BITRATE_SELECT;
|
||||
|
||||
/****** CAN Bit Propagation Segment codes (PROP_SEG) *****/
|
||||
#define ARM_CAN_BIT_PROP_SEG_Pos 0UL ///< bits 7..0
|
||||
#define ARM_CAN_BIT_PROP_SEG_Msk (0xFFUL << ARM_CAN_BIT_PROP_SEG_Pos)
|
||||
#define ARM_CAN_BIT_PROP_SEG(x) (((x) << ARM_CAN_BIT_PROP_SEG_Pos) & ARM_CAN_BIT_PROP_SEG_Msk)
|
||||
|
||||
/****** CAN Bit Phase Buffer Segment 1 (PHASE_SEG1) codes *****/
|
||||
#define ARM_CAN_BIT_PHASE_SEG1_Pos 8UL ///< bits 15..8
|
||||
#define ARM_CAN_BIT_PHASE_SEG1_Msk (0xFFUL << ARM_CAN_BIT_PHASE_SEG1_Pos)
|
||||
#define ARM_CAN_BIT_PHASE_SEG1(x) (((x) << ARM_CAN_BIT_PHASE_SEG1_Pos) & ARM_CAN_BIT_PHASE_SEG1_Msk)
|
||||
|
||||
/****** CAN Bit Phase Buffer Segment 2 (PHASE_SEG2) codes *****/
|
||||
#define ARM_CAN_BIT_PHASE_SEG2_Pos 16UL ///< bits 23..16
|
||||
#define ARM_CAN_BIT_PHASE_SEG2_Msk (0xFFUL << ARM_CAN_BIT_PHASE_SEG2_Pos)
|
||||
#define ARM_CAN_BIT_PHASE_SEG2(x) (((x) << ARM_CAN_BIT_PHASE_SEG2_Pos) & ARM_CAN_BIT_PHASE_SEG2_Msk)
|
||||
|
||||
/****** CAN Bit (Re)Synchronization Jump Width Segment (SJW) *****/
|
||||
#define ARM_CAN_BIT_SJW_Pos 24UL ///< bits 28..24
|
||||
#define ARM_CAN_BIT_SJW_Msk (0x1FUL << ARM_CAN_BIT_SJW_Pos)
|
||||
#define ARM_CAN_BIT_SJW(x) (((x) << ARM_CAN_BIT_SJW_Pos) & ARM_CAN_BIT_SJW_Msk)
|
||||
|
||||
/****** CAN Mode codes *****/
|
||||
typedef enum _ARM_CAN_MODE {
|
||||
ARM_CAN_MODE_INITIALIZATION, ///< Initialization mode
|
||||
ARM_CAN_MODE_NORMAL, ///< Normal operation mode
|
||||
ARM_CAN_MODE_RESTRICTED, ///< Restricted operation mode
|
||||
ARM_CAN_MODE_MONITOR, ///< Bus monitoring mode
|
||||
ARM_CAN_MODE_LOOPBACK_INTERNAL, ///< Loopback internal mode
|
||||
ARM_CAN_MODE_LOOPBACK_EXTERNAL ///< Loopback external mode
|
||||
} ARM_CAN_MODE;
|
||||
|
||||
/****** CAN Filter Operation codes *****/
|
||||
typedef enum _ARM_CAN_FILTER_OPERATION {
|
||||
ARM_CAN_FILTER_ID_EXACT_ADD, ///< Add exact id filter
|
||||
ARM_CAN_FILTER_ID_EXACT_REMOVE, ///< Remove exact id filter
|
||||
ARM_CAN_FILTER_ID_RANGE_ADD, ///< Add range id filter
|
||||
ARM_CAN_FILTER_ID_RANGE_REMOVE, ///< Remove range id filter
|
||||
ARM_CAN_FILTER_ID_MASKABLE_ADD, ///< Add maskable id filter
|
||||
ARM_CAN_FILTER_ID_MASKABLE_REMOVE ///< Remove maskable id filter
|
||||
} ARM_CAN_FILTER_OPERATION;
|
||||
|
||||
/****** CAN Object Configuration codes *****/
|
||||
typedef enum _ARM_CAN_OBJ_CONFIG {
|
||||
ARM_CAN_OBJ_INACTIVE, ///< CAN object inactive
|
||||
ARM_CAN_OBJ_TX, ///< CAN transmit object
|
||||
ARM_CAN_OBJ_RX, ///< CAN receive object
|
||||
ARM_CAN_OBJ_RX_RTR_TX_DATA, ///< CAN object that on RTR reception automatically transmits Data Frame
|
||||
ARM_CAN_OBJ_TX_RTR_RX_DATA ///< CAN object that transmits RTR and automatically receives Data Frame
|
||||
} ARM_CAN_OBJ_CONFIG;
|
||||
|
||||
/**
|
||||
\brief CAN Object Capabilities
|
||||
*/
|
||||
typedef struct _ARM_CAN_OBJ_CAPABILITIES {
|
||||
uint32_t tx : 1; ///< Object supports transmission
|
||||
uint32_t rx : 1; ///< Object supports reception
|
||||
uint32_t rx_rtr_tx_data : 1; ///< Object supports RTR reception and automatic Data Frame transmission
|
||||
uint32_t tx_rtr_rx_data : 1; ///< Object supports RTR transmission and automatic Data Frame reception
|
||||
uint32_t multiple_filters : 1; ///< Object allows assignment of multiple filters to it
|
||||
uint32_t exact_filtering : 1; ///< Object supports exact identifier filtering
|
||||
uint32_t range_filtering : 1; ///< Object supports range identifier filtering
|
||||
uint32_t mask_filtering : 1; ///< Object supports mask identifier filtering
|
||||
uint32_t message_depth : 8; ///< Number of messages buffers (FIFO) for that object
|
||||
uint32_t reserved : 16; ///< Reserved (must be zero)
|
||||
} ARM_CAN_OBJ_CAPABILITIES;
|
||||
|
||||
/****** CAN Control Function Operation codes *****/
|
||||
#define ARM_CAN_CONTROL_Pos 0UL
|
||||
#define ARM_CAN_CONTROL_Msk (0xFFUL << ARM_CAN_CONTROL_Pos)
|
||||
#define ARM_CAN_SET_FD_MODE (1UL << ARM_CAN_CONTROL_Pos) ///< Set FD operation mode; arg: 0 = disable, 1 = enable
|
||||
#define ARM_CAN_ABORT_MESSAGE_SEND (2UL << ARM_CAN_CONTROL_Pos) ///< Abort sending of CAN message; arg = object
|
||||
#define ARM_CAN_CONTROL_RETRANSMISSION (3UL << ARM_CAN_CONTROL_Pos) ///< Enable/disable automatic retransmission; arg: 0 = disable, 1 = enable (default state)
|
||||
#define ARM_CAN_SET_TRANSCEIVER_DELAY (4UL << ARM_CAN_CONTROL_Pos) ///< Set transceiver delay; arg = delay in time quanta
|
||||
|
||||
/****** CAN ID Frame Format codes *****/
|
||||
#define ARM_CAN_ID_IDE_Pos 31UL
|
||||
#define ARM_CAN_ID_IDE_Msk (1UL << ARM_CAN_ID_IDE_Pos)
|
||||
|
||||
/****** CAN Identifier encoding *****/
|
||||
#define ARM_CAN_STANDARD_ID(id) (id & 0x000007FFUL) ///< CAN identifier in standard format (11-bits)
|
||||
#define ARM_CAN_EXTENDED_ID(id) ((id & 0x1FFFFFFFUL) | ARM_CAN_ID_IDE_Msk)///< CAN identifier in extended format (29-bits)
|
||||
|
||||
/**
|
||||
\brief CAN Message Information
|
||||
*/
|
||||
typedef struct _ARM_CAN_MSG_INFO {
|
||||
uint32_t id; ///< CAN identifier with frame format specifier (bit 31)
|
||||
uint32_t rtr : 1; ///< Remote transmission request frame
|
||||
uint32_t edl : 1; ///< Flexible data-rate format extended data length
|
||||
uint32_t brs : 1; ///< Flexible data-rate format with bitrate switch
|
||||
uint32_t esi : 1; ///< Flexible data-rate format error state indicator
|
||||
uint32_t dlc : 4; ///< Data length code
|
||||
uint32_t reserved : 24;
|
||||
} ARM_CAN_MSG_INFO;
|
||||
|
||||
/****** CAN specific error code *****/
|
||||
#define ARM_CAN_INVALID_BITRATE_SELECT (ARM_DRIVER_ERROR_SPECIFIC - 1) ///< Bitrate selection not supported
|
||||
#define ARM_CAN_INVALID_BITRATE (ARM_DRIVER_ERROR_SPECIFIC - 2) ///< Requested bitrate not supported
|
||||
#define ARM_CAN_INVALID_BIT_PROP_SEG (ARM_DRIVER_ERROR_SPECIFIC - 3) ///< Propagation segment value not supported
|
||||
#define ARM_CAN_INVALID_BIT_PHASE_SEG1 (ARM_DRIVER_ERROR_SPECIFIC - 4) ///< Phase segment 1 value not supported
|
||||
#define ARM_CAN_INVALID_BIT_PHASE_SEG2 (ARM_DRIVER_ERROR_SPECIFIC - 5) ///< Phase segment 2 value not supported
|
||||
#define ARM_CAN_INVALID_BIT_SJW (ARM_DRIVER_ERROR_SPECIFIC - 6) ///< SJW value not supported
|
||||
#define ARM_CAN_NO_MESSAGE_AVAILABLE (ARM_DRIVER_ERROR_SPECIFIC - 7) ///< Message is not available
|
||||
|
||||
/****** CAN Status codes *****/
|
||||
#define ARM_CAN_UNIT_STATE_INACTIVE (0U) ///< Unit state: Not active on bus (initialization)
|
||||
#define ARM_CAN_UNIT_STATE_ACTIVE (1U) ///< Unit state: Active on bus (can generate active error frame)
|
||||
#define ARM_CAN_UNIT_STATE_PASSIVE (2U) ///< Unit state: Error passive (can not generate active error frame)
|
||||
#define ARM_CAN_UNIT_STATE_BUS_OFF (3U) ///< Unit state: Bus-off (can recover to active state)
|
||||
#define ARM_CAN_LEC_NO_ERROR (0U) ///< Last error code: No error
|
||||
#define ARM_CAN_LEC_BIT_ERROR (1U) ///< Last error code: Bit error
|
||||
#define ARM_CAN_LEC_STUFF_ERROR (2U) ///< Last error code: Bit stuffing error
|
||||
#define ARM_CAN_LEC_CRC_ERROR (3U) ///< Last error code: CRC error
|
||||
#define ARM_CAN_LEC_FORM_ERROR (4U) ///< Last error code: Illegal fixed-form bit
|
||||
#define ARM_CAN_LEC_ACK_ERROR (5U) ///< Last error code: Acknowledgment error
|
||||
|
||||
/**
|
||||
\brief CAN Status
|
||||
*/
|
||||
typedef struct _ARM_CAN_STATUS {
|
||||
uint32_t unit_state : 4; ///< Unit bus state
|
||||
uint32_t last_error_code : 4; ///< Last error code
|
||||
uint32_t tx_error_count : 8; ///< Transmitter error count
|
||||
uint32_t rx_error_count : 8; ///< Receiver error count
|
||||
uint32_t reserved : 8;
|
||||
} ARM_CAN_STATUS;
|
||||
|
||||
|
||||
/****** CAN Unit Event *****/
|
||||
#define ARM_CAN_EVENT_UNIT_INACTIVE (0U) ///< Unit entered Inactive state
|
||||
#define ARM_CAN_EVENT_UNIT_ACTIVE (1U) ///< Unit entered Error Active state
|
||||
#define ARM_CAN_EVENT_UNIT_WARNING (2U) ///< Unit entered Error Warning state (one or both error counters >= 96)
|
||||
#define ARM_CAN_EVENT_UNIT_PASSIVE (3U) ///< Unit entered Error Passive state
|
||||
#define ARM_CAN_EVENT_UNIT_BUS_OFF (4U) ///< Unit entered Bus-off state
|
||||
|
||||
/****** CAN Send/Receive Event *****/
|
||||
#define ARM_CAN_EVENT_SEND_COMPLETE (1UL << 0) ///< Send complete
|
||||
#define ARM_CAN_EVENT_RECEIVE (1UL << 1) ///< Message received
|
||||
#define ARM_CAN_EVENT_RECEIVE_OVERRUN (1UL << 2) ///< Received message overrun
|
||||
|
||||
|
||||
// Function documentation
|
||||
/**
|
||||
\fn ARM_DRIVER_VERSION ARM_CAN_GetVersion (void)
|
||||
\brief Get driver version.
|
||||
\return \ref ARM_DRIVER_VERSION
|
||||
|
||||
\fn ARM_CAN_CAPABILITIES ARM_CAN_GetCapabilities (void)
|
||||
\brief Get driver capabilities.
|
||||
\return \ref ARM_CAN_CAPABILITIES
|
||||
|
||||
\fn int32_t ARM_CAN_Initialize (ARM_CAN_SignalUnitEvent_t cb_unit_event,
|
||||
ARM_CAN_SignalObjectEvent_t cb_object_event)
|
||||
\brief Initialize CAN interface and register signal (callback) functions.
|
||||
\param[in] cb_unit_event Pointer to \ref ARM_CAN_SignalUnitEvent callback function
|
||||
\param[in] cb_object_event Pointer to \ref ARM_CAN_SignalObjectEvent callback function
|
||||
\return \ref execution_status
|
||||
|
||||
\fn int32_t ARM_CAN_Uninitialize (void)
|
||||
\brief De-initialize CAN interface.
|
||||
\return \ref execution_status
|
||||
|
||||
\fn int32_t ARM_CAN_PowerControl (ARM_POWER_STATE state)
|
||||
\brief Control CAN interface power.
|
||||
\param[in] state Power state
|
||||
- \ref ARM_POWER_OFF : power off: no operation possible
|
||||
- \ref ARM_POWER_LOW : low power mode: retain state, detect and signal wake-up events
|
||||
- \ref ARM_POWER_FULL : power on: full operation at maximum performance
|
||||
\return \ref execution_status
|
||||
|
||||
\fn uint32_t ARM_CAN_GetClock (void)
|
||||
\brief Retrieve CAN base clock frequency.
|
||||
\return base clock frequency
|
||||
|
||||
\fn int32_t ARM_CAN_SetBitrate (ARM_CAN_BITRATE_SELECT select, uint32_t bitrate, uint32_t bit_segments)
|
||||
\brief Set bitrate for CAN interface.
|
||||
\param[in] select Bitrate selection
|
||||
- \ref ARM_CAN_BITRATE_NOMINAL : nominal (flexible data-rate arbitration) bitrate
|
||||
- \ref ARM_CAN_BITRATE_FD_DATA : flexible data-rate data bitrate
|
||||
\param[in] bitrate Bitrate
|
||||
\param[in] bit_segments Bit segments settings
|
||||
- \ref ARM_CAN_BIT_PROP_SEG(x) : number of time quanta for propagation time segment
|
||||
- \ref ARM_CAN_BIT_PHASE_SEG1(x) : number of time quanta for phase buffer segment 1
|
||||
- \ref ARM_CAN_BIT_PHASE_SEG2(x) : number of time quanta for phase buffer Segment 2
|
||||
- \ref ARM_CAN_BIT_SJW(x) : number of time quanta for (re-)synchronization jump width
|
||||
\return \ref execution_status
|
||||
|
||||
\fn int32_t ARM_CAN_SetMode (ARM_CAN_MODE mode)
|
||||
\brief Set operating mode for CAN interface.
|
||||
\param[in] mode Operating mode
|
||||
- \ref ARM_CAN_MODE_INITIALIZATION : initialization mode
|
||||
- \ref ARM_CAN_MODE_NORMAL : normal operation mode
|
||||
- \ref ARM_CAN_MODE_RESTRICTED : restricted operation mode
|
||||
- \ref ARM_CAN_MODE_MONITOR : bus monitoring mode
|
||||
- \ref ARM_CAN_MODE_LOOPBACK_INTERNAL : loopback internal mode
|
||||
- \ref ARM_CAN_MODE_LOOPBACK_EXTERNAL : loopback external mode
|
||||
\return \ref execution_status
|
||||
|
||||
\fn ARM_CAN_OBJ_CAPABILITIES ARM_CAN_ObjectGetCapabilities (uint32_t obj_idx)
|
||||
\brief Retrieve capabilities of an object.
|
||||
\param[in] obj_idx Object index
|
||||
\return \ref ARM_CAN_OBJ_CAPABILITIES
|
||||
|
||||
\fn int32_t ARM_CAN_ObjectSetFilter (uint32_t obj_idx, ARM_CAN_FILTER_OPERATION operation, uint32_t id, uint32_t arg)
|
||||
\brief Add or remove filter for message reception.
|
||||
\param[in] obj_idx Object index of object that filter should be or is assigned to
|
||||
\param[in] operation Operation on filter
|
||||
- \ref ARM_CAN_FILTER_ID_EXACT_ADD : add exact id filter
|
||||
- \ref ARM_CAN_FILTER_ID_EXACT_REMOVE : remove exact id filter
|
||||
- \ref ARM_CAN_FILTER_ID_RANGE_ADD : add range id filter
|
||||
- \ref ARM_CAN_FILTER_ID_RANGE_REMOVE : remove range id filter
|
||||
- \ref ARM_CAN_FILTER_ID_MASKABLE_ADD : add maskable id filter
|
||||
- \ref ARM_CAN_FILTER_ID_MASKABLE_REMOVE : remove maskable id filter
|
||||
\param[in] id ID or start of ID range (depending on filter type)
|
||||
\param[in] arg Mask or end of ID range (depending on filter type)
|
||||
\return \ref execution_status
|
||||
|
||||
\fn int32_t ARM_CAN_ObjectConfigure (uint32_t obj_idx, ARM_CAN_OBJ_CONFIG obj_cfg)
|
||||
\brief Configure object.
|
||||
\param[in] obj_idx Object index
|
||||
\param[in] obj_cfg Object configuration state
|
||||
- \ref ARM_CAN_OBJ_INACTIVE : deactivate object
|
||||
- \ref ARM_CAN_OBJ_RX : configure object for reception
|
||||
- \ref ARM_CAN_OBJ_TX : configure object for transmission
|
||||
- \ref ARM_CAN_OBJ_RX_RTR_TX_DATA : configure object that on RTR reception automatically transmits Data Frame
|
||||
- \ref ARM_CAN_OBJ_TX_RTR_RX_DATA : configure object that transmits RTR and automatically receives Data Frame
|
||||
\return \ref execution_status
|
||||
|
||||
\fn int32_t ARM_CAN_MessageSend (uint32_t obj_idx, ARM_CAN_MSG_INFO *msg_info, const uint8_t *data, uint8_t size)
|
||||
\brief Send message on CAN bus.
|
||||
\param[in] obj_idx Object index
|
||||
\param[in] msg_info Pointer to CAN message information
|
||||
\param[in] data Pointer to data buffer
|
||||
\param[in] size Number of data bytes to send
|
||||
\return value >= 0 number of data bytes accepted to send
|
||||
\return value < 0 \ref execution_status
|
||||
|
||||
\fn int32_t ARM_CAN_MessageRead (uint32_t obj_idx, ARM_CAN_MSG_INFO *msg_info, uint8_t *data, uint8_t size)
|
||||
\brief Read message received on CAN bus.
|
||||
\param[in] obj_idx Object index
|
||||
\param[out] msg_info Pointer to read CAN message information
|
||||
\param[out] data Pointer to data buffer for read data
|
||||
\param[in] size Maximum number of data bytes to read
|
||||
\return value >= 0 number of data bytes read
|
||||
\return value < 0 \ref execution_status
|
||||
|
||||
\fn int32_t ARM_CAN_Control (uint32_t control, uint32_t arg)
|
||||
\brief Control CAN interface.
|
||||
\param[in] control Operation
|
||||
- \ref ARM_CAN_SET_FD_MODE : set FD operation mode
|
||||
- \ref ARM_CAN_ABORT_MESSAGE_SEND : abort sending of CAN message
|
||||
- \ref ARM_CAN_CONTROL_RETRANSMISSION : enable/disable automatic retransmission
|
||||
- \ref ARM_CAN_SET_TRANSCEIVER_DELAY : set transceiver delay
|
||||
\param[in] arg Argument of operation
|
||||
\return \ref execution_status
|
||||
|
||||
\fn ARM_CAN_STATUS ARM_CAN_GetStatus (void)
|
||||
\brief Get CAN status.
|
||||
\return CAN status \ref ARM_CAN_STATUS
|
||||
|
||||
\fn void ARM_CAN_SignalUnitEvent (uint32_t event)
|
||||
\brief Signal CAN unit event.
|
||||
\param[in] event \ref CAN_unit_events
|
||||
\return none
|
||||
|
||||
\fn void ARM_CAN_SignalObjectEvent (uint32_t obj_idx, uint32_t event)
|
||||
\brief Signal CAN object event.
|
||||
\param[in] obj_idx Object index
|
||||
\param[in] event \ref CAN_events
|
||||
\return none
|
||||
*/
|
||||
|
||||
typedef void (*ARM_CAN_SignalUnitEvent_t) (uint32_t event); ///< Pointer to \ref ARM_CAN_SignalUnitEvent : Signal CAN Unit Event.
|
||||
typedef void (*ARM_CAN_SignalObjectEvent_t) (uint32_t obj_idx, uint32_t event); ///< Pointer to \ref ARM_CAN_SignalObjectEvent : Signal CAN Object Event.
|
||||
|
||||
|
||||
/**
|
||||
\brief CAN Device Driver Capabilities.
|
||||
*/
|
||||
typedef struct _ARM_CAN_CAPABILITIES {
|
||||
uint32_t num_objects : 8; ///< Number of \ref can_objects available
|
||||
uint32_t reentrant_operation : 1; ///< Support for reentrant calls to \ref ARM_CAN_MessageSend, \ref ARM_CAN_MessageRead, \ref ARM_CAN_ObjectConfigure and abort message sending used by \ref ARM_CAN_Control
|
||||
uint32_t fd_mode : 1; ///< Support for CAN with flexible data-rate mode (CAN_FD) (set by \ref ARM_CAN_Control)
|
||||
uint32_t restricted_mode : 1; ///< Support for restricted operation mode (set by \ref ARM_CAN_SetMode)
|
||||
uint32_t monitor_mode : 1; ///< Support for bus monitoring mode (set by \ref ARM_CAN_SetMode)
|
||||
uint32_t internal_loopback : 1; ///< Support for internal loopback mode (set by \ref ARM_CAN_SetMode)
|
||||
uint32_t external_loopback : 1; ///< Support for external loopback mode (set by \ref ARM_CAN_SetMode)
|
||||
uint32_t reserved : 18; ///< Reserved (must be zero)
|
||||
} ARM_CAN_CAPABILITIES;
|
||||
|
||||
|
||||
/**
|
||||
\brief Access structure of the CAN Driver.
|
||||
*/
|
||||
typedef struct _ARM_DRIVER_CAN {
|
||||
ARM_DRIVER_VERSION (*GetVersion) (void); ///< Pointer to \ref ARM_CAN_GetVersion : Get driver version.
|
||||
ARM_CAN_CAPABILITIES (*GetCapabilities) (void); ///< Pointer to \ref ARM_CAN_GetCapabilities : Get driver capabilities.
|
||||
int32_t (*Initialize) (ARM_CAN_SignalUnitEvent_t cb_unit_event,
|
||||
ARM_CAN_SignalObjectEvent_t cb_object_event); ///< Pointer to \ref ARM_CAN_Initialize : Initialize CAN interface.
|
||||
int32_t (*Uninitialize) (void); ///< Pointer to \ref ARM_CAN_Uninitialize : De-initialize CAN interface.
|
||||
int32_t (*PowerControl) (ARM_POWER_STATE state); ///< Pointer to \ref ARM_CAN_PowerControl : Control CAN interface power.
|
||||
uint32_t (*GetClock) (void); ///< Pointer to \ref ARM_CAN_GetClock : Retrieve CAN base clock frequency.
|
||||
int32_t (*SetBitrate) (ARM_CAN_BITRATE_SELECT select,
|
||||
uint32_t bitrate,
|
||||
uint32_t bit_segments); ///< Pointer to \ref ARM_CAN_SetBitrate : Set bitrate for CAN interface.
|
||||
int32_t (*SetMode) (ARM_CAN_MODE mode); ///< Pointer to \ref ARM_CAN_SetMode : Set operating mode for CAN interface.
|
||||
ARM_CAN_OBJ_CAPABILITIES (*ObjectGetCapabilities) (uint32_t obj_idx); ///< Pointer to \ref ARM_CAN_ObjectGetCapabilities : Retrieve capabilities of an object.
|
||||
int32_t (*ObjectSetFilter) (uint32_t obj_idx,
|
||||
ARM_CAN_FILTER_OPERATION operation,
|
||||
uint32_t id,
|
||||
uint32_t arg); ///< Pointer to \ref ARM_CAN_ObjectSetFilter : Add or remove filter for message reception.
|
||||
int32_t (*ObjectConfigure) (uint32_t obj_idx,
|
||||
ARM_CAN_OBJ_CONFIG obj_cfg); ///< Pointer to \ref ARM_CAN_ObjectConfigure : Configure object.
|
||||
int32_t (*MessageSend) (uint32_t obj_idx,
|
||||
ARM_CAN_MSG_INFO *msg_info,
|
||||
const uint8_t *data,
|
||||
uint8_t size); ///< Pointer to \ref ARM_CAN_MessageSend : Send message on CAN bus.
|
||||
int32_t (*MessageRead) (uint32_t obj_idx,
|
||||
ARM_CAN_MSG_INFO *msg_info,
|
||||
uint8_t *data,
|
||||
uint8_t size); ///< Pointer to \ref ARM_CAN_MessageRead : Read message received on CAN bus.
|
||||
int32_t (*Control) (uint32_t control,
|
||||
uint32_t arg); ///< Pointer to \ref ARM_CAN_Control : Control CAN interface.
|
||||
ARM_CAN_STATUS (*GetStatus) (void); ///< Pointer to \ref ARM_CAN_GetStatus : Get CAN status.
|
||||
} const ARM_DRIVER_CAN;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* DRIVER_CAN_H_ */
|
||||
83
src/hal/alif/Alif_CMSIS/Include/Driver_CAN_EX.h
Normal file
83
src/hal/alif/Alif_CMSIS/Include/Driver_CAN_EX.h
Normal file
@ -0,0 +1,83 @@
|
||||
/* Copyright (C) 2023 Alif Semiconductor - All Rights Reserved.
|
||||
* Use, distribution and modification of this code is permitted under the
|
||||
* terms stated in the Alif Semiconductor Software License Agreement
|
||||
*
|
||||
* You should have received a copy of the Alif Semiconductor Software
|
||||
* License Agreement with this file. If not, please write to:
|
||||
* contact@alifsemi.com, or visit: https://alifsemi.com/license
|
||||
*
|
||||
*/
|
||||
|
||||
/******************************************************************************
|
||||
* @file Driver_CAN_EX.h
|
||||
* @author Shreehari H K
|
||||
* @email shreehari.hk@alifsemi.com
|
||||
* @version V1.0.0
|
||||
* @date 29-Jan-2024
|
||||
* @brief Extension of CMSIS Driver_CAN.h
|
||||
* @bug None.
|
||||
* @Note None
|
||||
******************************************************************************/
|
||||
#ifndef DRIVER_CAN_EX_H_
|
||||
#define DRIVER_CAN_EX_H_
|
||||
|
||||
#include "Driver_CAN.h"
|
||||
|
||||
/****** CAN Control Function Operation codes *****/
|
||||
#define ARM_CAN_SET_SPECIFICATION (5UL << ARM_CAN_CONTROL_Pos) ///< Set Spec: ISO/Non-ISO. Default: ISO
|
||||
#define ARM_CAN_SET_RBUF_OVERFLOW_MODE (6UL << ARM_CAN_CONTROL_Pos) ///< Set mode: overwrite old msg or Don't store new msg
|
||||
#define ARM_CAN_SET_RBUF_STORAGE_FORMAT (7UL << ARM_CAN_CONTROL_Pos) ///< Rx buf storage format. Default: Normal msgs
|
||||
#define ARM_CAN_SET_RBUF_ALMOST_FULL_WARN_LIMIT (8UL << ARM_CAN_CONTROL_Pos) ///< Rx buf almost full warning limit arg: 1-15. Default: 15
|
||||
#define ARM_CAN_SET_TRANSMISSION_MODE (9UL << ARM_CAN_CONTROL_Pos) ///< Normal Transmission buffer mode; Fifo/Priority. Not for primary buffer
|
||||
#define ARM_CAN_SET_PRIMARY_TBUF (10UL << ARM_CAN_CONTROL_Pos) ///< Set Primary Tx buffer
|
||||
#define ARM_CAN_ABORT_PRIMARY_TBUF_MESSAGE_SEND (11UL << ARM_CAN_CONTROL_Pos) ///< Abort Primary buffer message transmission
|
||||
#define ARM_CAN_CONTROL_PRIMARY_TBUF_RETRANSMISSION (12UL << ARM_CAN_CONTROL_Pos) ///< Enable/disable primary tbuf's automatic retransmission; arg: 0 = disable, 1 = enable (default state)
|
||||
#define ARM_CAN_SET_TIMER_COUNTER (13UL << ARM_CAN_CONTROL_Pos) ///< Set the initial value Timer counter; arg: value
|
||||
#define ARM_CAN_CONTROL_TIMER_COUNTER (14UL << ARM_CAN_CONTROL_Pos) ///< Manipulate Timer counter; arg: Start, Stop, Clear
|
||||
#define ARM_CAN_ENABLE_TIMESTAMP (15UL << ARM_CAN_CONTROL_Pos) ///< Enable CAN msg timestamp; arg: timestamp position- SOF/EOF
|
||||
#define ARM_CAN_DISABLE_TIMESTAMP (16UL << ARM_CAN_CONTROL_Pos) ///< Disable CAN msg timestamp; arg: NULL
|
||||
#define ARM_CAN_GET_TX_TIMESTAMP (17UL << ARM_CAN_CONTROL_Pos) ///< Get CAN Tx msg timestamp; arg: Address of variable to store it
|
||||
#define ARM_CAN_GET_RX_TIMESTAMP (18UL << ARM_CAN_CONTROL_Pos) ///< Get CAN Rx msg timestamp; arg: Address of variable to store it
|
||||
|
||||
/* CAN Control arguments ISO/Non-ISO modes */
|
||||
#define ARM_CAN_SPECIFICATION_NON_ISO 1U ///< Bosch (Non-ISO) Specification
|
||||
#define ARM_CAN_SPECIFICATION_ISO 2U ///< ISO (11898-1:2015) Specification
|
||||
|
||||
/* Control arguments for RBUF Overflow mode */
|
||||
#define ARM_CAN_RBUF_OVERWRITE_OLD_MSG 1U
|
||||
#define ARM_CAN_RBUF_DISCARD_NEW_MSG 2U
|
||||
|
||||
/* Control arguments for RBUF Storage format */
|
||||
#define ARM_CAN_RBUF_STORAGE_NORMAL_MSG 1U ///< Stores only normal messages
|
||||
#define ARM_CAN_RBUF_STORAGE_ALL_MSG 2U ///< Stores both correct and error data frames
|
||||
|
||||
/* Control arguments for Transmission mode */
|
||||
#define ARM_CAN_SET_TRANSMISSION_MODE_FIFO 1U ///< Fifo mode; only for normal buffer
|
||||
#define ARM_CAN_SET_TRANSMISSION_MODE_PRIORITY 2U ///< Priority mode; only for normal
|
||||
|
||||
/* Object filter configuration arguments decoding.
|
||||
* User doesn't have to use it*/
|
||||
#define ARM_CAN_OBJECT_ID(id) (id & 0x1FFFFFFFUL)
|
||||
|
||||
/* Arguments for Object filter configuration.
|
||||
* These arguments should be added to the
|
||||
* parameter "id" of ObjectSetFilter() api */
|
||||
#define ARM_CAN_OBJECT_FILTER_STD_FRAMES (1U << 30U)
|
||||
#define ARM_CAN_OBJECT_FILTER_EXT_FRAMES (3U << 29U)
|
||||
#define ARM_CAN_OBJECT_FILTER_ALL_FRAMES (0U)
|
||||
|
||||
/* Arguments for Timer Counter Controlling */
|
||||
#define ARM_CAN_TIMER_COUNTER_START (1U << 1U) ///< Start the counter
|
||||
#define ARM_CAN_TIMER_COUNTER_STOP (1U << 2U) ///< Stop the counter
|
||||
#define ARM_CAN_TIMER_COUNTER_CLEAR (1U << 3U) ///< Clear the counter
|
||||
|
||||
/* Arguments for CAN Timestamp position */
|
||||
#define CAN_TIMESTAMP_POSITION_SOF (1U << 1U) ///< Timestamp at start of the frame
|
||||
#define CAN_TIMESTAMP_POSITION_EOF (1U << 2U) ///< Timestamp at end of the frame
|
||||
|
||||
/****** Extended CAN Events *****/
|
||||
#define ARM_CAN_EVENT_RBUF_ALMOST_FULL (1UL << 3) ///< Rx buffer is almost full
|
||||
#define ARM_CAN_EVENT_ARBITRATION_LOST (1UL << 4) ///< Arbitration lost during msg transmission
|
||||
#define ARM_CAN_EVENT_PRIMARY_TBUF_SEND_COMPLETE (1UL << 5) ///< Primary Tx buffer send complete
|
||||
|
||||
#endif /* DRIVER_CAN_EX_H_ */
|
||||
225
src/hal/alif/Alif_CMSIS/Include/Driver_CDC200.h
Normal file
225
src/hal/alif/Alif_CMSIS/Include/Driver_CDC200.h
Normal file
@ -0,0 +1,225 @@
|
||||
/* Copyright (C) 2023 Alif Semiconductor - All Rights Reserved.
|
||||
* Use, distribution and modification of this code is permitted under the
|
||||
* terms stated in the Alif Semiconductor Software License Agreement
|
||||
*
|
||||
* You should have received a copy of the Alif Semiconductor Software
|
||||
* License Agreement with this file. If not, please write to:
|
||||
* contact@alifsemi.com, or visit: https://alifsemi.com/license
|
||||
*
|
||||
*/
|
||||
|
||||
/******************************************************************************
|
||||
* @file Driver_CDC200.h
|
||||
* @author Girish BN and Prasanna Ravi
|
||||
* @email girish.bn@alifsemi.com and prasanna.ravi@alifsemi.com
|
||||
* @version V1.0.0
|
||||
* @date 30-Sep-2021
|
||||
* @brief Display controller driver header.
|
||||
* @bug None.
|
||||
* @Note None.
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef DRIVER_CDC200_H_
|
||||
#define DRIVER_CDC200_H_
|
||||
|
||||
#include "Driver_Common.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
#define ARM_CDC200_API_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(1,0) /* API version */
|
||||
|
||||
/****** CDC200 Background color blue *****/
|
||||
#define ARM_CDC200_BGC_BLUE_Pos 0UL ///< bits 7..0
|
||||
#define ARM_CDC200_BGC_BLUE_Msk (0xFFUL << ARM_CDC200_BGC_BLUE_Pos)
|
||||
#define ARM_CDC200_BGC_BLUE(x) (((x) << ARM_CDC200_BGC_BLUE_Pos) & ARM_CDC200_BGC_BLUE_Msk)
|
||||
|
||||
/****** CDC200 Background color green *****/
|
||||
#define ARM_CDC200_BGC_GREEN_Pos 8UL ///< bits 15..8
|
||||
#define ARM_CDC200_BGC_GREEN_Msk (0xFFUL << ARM_CDC200_BGC_GREEN_Pos)
|
||||
#define ARM_CDC200_BGC_GREEN(x) (((x) << ARM_CDC200_BGC_GREEN_Pos) & ARM_CDC200_BGC_GREEN_Msk)
|
||||
|
||||
/****** CDC200 Background color red *****/
|
||||
#define ARM_CDC200_BGC_RED_Pos 16UL ///< bits 23..16
|
||||
#define ARM_CDC200_BGC_RED_Msk (0xFFUL << ARM_CDC200_BGC_RED_Pos)
|
||||
#define ARM_CDC200_BGC_RED(x) (((x) << ARM_CDC200_BGC_RED_Pos) & ARM_CDC200_BGC_RED_Msk)
|
||||
|
||||
/****** CDC200 Control Function Operation codes *****/
|
||||
#define CDC200_CONFIGURE_DISPLAY (1U << 0) ///< Configure Display
|
||||
#define CDC200_FRAMEBUF_UPDATE (1U << 1) ///< Update layer Frame buffer
|
||||
#define CDC200_FRAMEBUF_UPDATE_VSYNC (1U << 2) ///< Update layer Frame buffer on vertical blanking
|
||||
#define CDC200_SCANLINE0_EVENT (1U << 3) ///< Enable/Disable Scanline0 event
|
||||
#define CDC200_CONFIGURE_LAYER (1U << 4) ///< Configure Layer
|
||||
#define CDC200_LAYER_ON (1U << 5) ///< Turn On the Layer
|
||||
#define CDC200_LAYER_OFF (1U << 6) ///< Turn Off the Layer
|
||||
#define CDC200_CONFIGURE_LAYER_WINDOW (1U << 7) ///< Configure Layer window
|
||||
#define CDC200_CONFIGURE_BG_COLOR (1U << 8) ///< Configure Background color
|
||||
#define CDC200_CONFIGURE_LAYER_BLENDING (1U << 9) ///< Configure Layer blending
|
||||
|
||||
|
||||
/**
|
||||
\brief CDC200 Layer index
|
||||
*/
|
||||
typedef enum _ARM_CDC200_LAYER_INDEX {
|
||||
ARM_CDC200_LAYER_1, ///< CDC200 Layer 1
|
||||
ARM_CDC200_LAYER_2 ///< CDC200 Layer 2
|
||||
} ARM_CDC200_LAYER_INDEX;
|
||||
|
||||
/**
|
||||
\brief CDC200 Layer Pixel format
|
||||
*/
|
||||
typedef enum _ARM_CDC200_LAYER_PIXEL_FORMAT {
|
||||
ARM_CDC200_ARGB8888, ///< 32-bit ARGB
|
||||
ARM_CDC200_RGB888, ///< 24-bit RGB (A = 255)
|
||||
ARM_CDC200_RGB565, ///< 16-bit RGB (A = 255)
|
||||
ARM_CDC200_RGBA8888, ///< 32-bit RGBA
|
||||
ARM_CDC200_AL44, ///< 8-bit alpha + luminance (lower channel on R, G and B)
|
||||
ARM_CDC200_AL8, ///< 8-bit single channel (value on A, R, G and B)
|
||||
ARM_CDC200_ARGB1555, ///< 16-bit ARGB with 1 bit alpha
|
||||
ARM_CDC200_ARGB4444 ///< 16-bit ARGB with 4 bits alpha
|
||||
} ARM_CDC200_LAYER_PIXEL_FORMAT;
|
||||
|
||||
/**
|
||||
\brief CDC200 Selection of layer blending factor
|
||||
*/
|
||||
typedef enum _CDC200_BLEND_FACTOR
|
||||
{
|
||||
CDC200_BLEND_CONST_ALPHA, ///< layer blending factor selected to constant alpha
|
||||
CDC200_BLEND_PIXEL_ALPHA_X_CONST_ALPHA ///< layer blending factor selected to pixel alpha * constant alpha
|
||||
} CDC200_BLEND_FACTOR;
|
||||
|
||||
/**
|
||||
\brief CDC200 Layer window information
|
||||
*/
|
||||
typedef struct _ARM_CDC200_LAYER_WINDOW_INFO {
|
||||
uint16_t v_start_pos; ///< Vertical Start Position
|
||||
uint16_t v_stop_pos; ///< Vertical Stop Position
|
||||
uint16_t h_start_pos; ///< Horizontal Start Position
|
||||
uint16_t h_stop_pos; ///< Horizontal Stop Position
|
||||
} ARM_CDC200_LAYER_WINDOW_INFO;
|
||||
|
||||
/**
|
||||
\brief CDC Layer information
|
||||
*/
|
||||
typedef struct _ARM_CDC200_LAYER_INFO {
|
||||
ARM_CDC200_LAYER_INDEX layer_idx; ///< CDC200 Layer index
|
||||
ARM_CDC200_LAYER_WINDOW_INFO win_info; ///< CDC200 window information
|
||||
ARM_CDC200_LAYER_PIXEL_FORMAT pix_format; ///< CDC200 Layer pixel format
|
||||
uint8_t const_alpha; ///< CDC200 Layer constant alpha
|
||||
CDC200_BLEND_FACTOR blend_factor; ///< CDC200 Selection of Layer blending factor
|
||||
uint32_t fb_addr; ///< CDC200 Layer FB address
|
||||
uint16_t line_length_in_pixels; ///< CDC200 Layer Line length in pixels of color FB
|
||||
uint16_t num_lines; ///< CDC200 Layer number of lines in the color FB
|
||||
} ARM_CDC200_LAYER_INFO;
|
||||
|
||||
/****** CDC200 events *****/
|
||||
#define ARM_CDC_DSI_ERROR_EVENT (1U << 0) ///< DSI error event
|
||||
#define ARM_CDC_SCANLINE0_EVENT (1U << 1) ///< Scanline0 irq event
|
||||
|
||||
// Function documentation
|
||||
/**
|
||||
\fn ARM_DRIVER_VERSION ARM_CDC200_GetVersion (void)
|
||||
\brief Get CDC200 driver version.
|
||||
\return \ref ARM_DRIVER_VERSION.
|
||||
|
||||
\fn ARM_CDC200_CAPABILITIES ARM_CDC200_GetCapabilities (void)
|
||||
\brief Get CDC200 driver capabilities.
|
||||
\return \ref ARM_CDC200_CAPABILITIES.
|
||||
|
||||
\fn int32_t ARM_CDC200_Initialize (ARM_CDC200_SignalEvent_t cb_event)
|
||||
\brief Initialize CDC200 Interface.
|
||||
\param[in] cb_event Pointer to ARM_CDC200_SignalEvent_t.
|
||||
\return \ref execution_status.
|
||||
|
||||
\fn int32_t ARM_CDC200_Uninitialize (void)
|
||||
\brief Uninitialize CDC200 Interface.
|
||||
\return \ref execution_status.
|
||||
|
||||
\fn int32_t ARM_CDC200_PowerControl (ARM_POWER_STATE state)
|
||||
\brief Control CDC200 Interface Power.
|
||||
\param[in] state Power state.
|
||||
\return \ref execution_status.
|
||||
|
||||
\fn int32_t ARM_CDC200_Control (uint32_t control, uint32_t arg)
|
||||
\brief Control the display controller.
|
||||
\param[in] control CDC200 contol code operation.
|
||||
- \ref CDC200_CONFIGURE_DISPLAY : Configure Display
|
||||
- \ref CDC200_FRAMEBUF_UPDATE : Update layer Frame buffer
|
||||
- \ref CDC200_FRAMEBUF_UPDATE_VSYNC : Update layer Frame buffer on vertical blanking
|
||||
- \ref CDC200_SCANLINE0_EVENT : Enable/Disable Scanline0 event
|
||||
- \ref CDC200_CONFIGURE_LAYER : Configure Layer
|
||||
- \ref CDC200_LAYER_ON : Turn On the Layer
|
||||
- \ref CDC200_LAYER_OFF : Turn Off the Layer
|
||||
- \ref CDC200_CONFIGURE_LAYER_WINDOW : Configure Layer window
|
||||
- \ref CDC200_CONFIGURE_BG_COLOR : Configure Background color
|
||||
- \ref CDC200_CONFIGURE_LAYER_BLENDING : Configure Layer blending
|
||||
\param[in] arg Argument of operation.
|
||||
- CDC200_CONFIGURE_DISPLAY : Frame buffer address
|
||||
- CDC200_FRAMEBUF_UPDATE : Frame buffer address
|
||||
- CDC200_FRAMEBUF_UPDATE_VSYNC : Frame buffer address
|
||||
- CDC200_SCANLINE0_EVENT : ENABLE/DISABLE
|
||||
- CDC200_CONFIGURE_LAYER : Pointer to layer info \ref ARM_CDC200_LAYER_INFO
|
||||
- CDC200_LAYER_ON : layer index /ref ARM_CDC200_LAYER_INDEX
|
||||
- CDC200_LAYER_OFF : layer index /ref ARM_CDC200_LAYER_INDEX
|
||||
- CDC200_CONFIGURE_LAYER_WINDOW : Pointer to layer info \ref ARM_CDC200_LAYER_INFO
|
||||
- CDC200_CONFIGURE_BG_COLOR : Background color setting
|
||||
- /ref ARM_CDC200_BGC_BLUE(x)
|
||||
- /ref ARM_CDC200_BGC_GREEN(x)
|
||||
- /ref ARM_CDC200_BGC_RED(x)
|
||||
- CDC200_CONFIGURE_LAYER_BLENDING : Pointer to layer info \ref ARM_CDC200_LAYER_INFO
|
||||
\return \ref execution_status.
|
||||
|
||||
\fn int32_t ARM_CDC200_GetVerticalPosition (void)
|
||||
\brief Get current vertical position count.
|
||||
\return return current vertical position.
|
||||
|
||||
\fn int32_t ARM_CDC200_StartDisplay (void)
|
||||
\brief Start the display controller.
|
||||
\return \ref execution_status.
|
||||
|
||||
\fn int32_t ARM_CDC200_StopDisplay (void)
|
||||
\brief Stop the display controller.
|
||||
\return \ref execution_status.
|
||||
|
||||
\fn void ARM_CDC200_SignalEvent (uint32_t int_event)
|
||||
\brief Signal CDC200 Events.
|
||||
\param[in] int_event \ref CDC200 event types.
|
||||
\return none.
|
||||
*/
|
||||
|
||||
/**
|
||||
\brief CDC200 signal event.
|
||||
*/
|
||||
typedef void (*ARM_CDC200_SignalEvent_t) (uint32_t int_event); ///< Pointer to \ref ARM_CDC200_SignalEvent : Signal CDC200 Event.
|
||||
|
||||
/**
|
||||
\brief CDC200 driver capabilities.
|
||||
*/
|
||||
typedef struct _ARM_CDC200_CAPABILITIES {
|
||||
uint32_t reentrant_operation :1; ///< Support for reentrant calls
|
||||
uint32_t dpi_interface :1; ///< Support video mode Interface
|
||||
uint32_t reserved :30; ///< Reserved (must be zero)
|
||||
} ARM_CDC200_CAPABILITIES;
|
||||
|
||||
/**
|
||||
\brief Access structure of the CDC200 Driver.
|
||||
*/
|
||||
typedef struct _ARM_DRIVER_CDC200 {
|
||||
ARM_DRIVER_VERSION (*GetVersion) (void); ///< Pointer to \ref ARM_CDC200_GetVersion : Get driver version.
|
||||
ARM_CDC200_CAPABILITIES (*GetCapabilities) (void); ///< Pointer to \ref ARM_CDC200_GetCapabilities : Get CDC200 driver capabilities.
|
||||
int32_t (*Initialize) (ARM_CDC200_SignalEvent_t cb_event); ///< Pointer to \ref ARM_CDC200_Initialize : Initialize CDC200 Interface.
|
||||
int32_t (*Uninitialize) (void); ///< Pointer to \ref ARM_CDC200_Uninitialize : Uninitialize CDC200 Interface.
|
||||
int32_t (*PowerControl) (ARM_POWER_STATE state); ///< Pointer to \ref ARM_CDC200_PowerControl : Control CDC200 Interface Power.
|
||||
int32_t (*Control) (uint32_t control, uint32_t arg); ///< Pointer to \ref ARM_CDC200_Control: Control CDC200 Interface.
|
||||
int32_t (*GetVerticalPosition) (void); ///< Pointer to \ref ARM_CDC200_GetVerticalPosition: Get current vertical position count.
|
||||
int32_t (*Start) (void); ///< Pointer to \ref ARM_CDC200_StartDisplay : Configure CDC200 to start Displaying.
|
||||
int32_t (*Stop) (void); ///< Pointer to \ref ARM_CDC200_StopDisplay : Configure CDC200 to stop Displaying.
|
||||
} ARM_DRIVER_CDC200;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* DRIVER_CDC200_H_ */
|
||||
117
src/hal/alif/Alif_CMSIS/Include/Driver_CMP.h
Normal file
117
src/hal/alif/Alif_CMSIS/Include/Driver_CMP.h
Normal file
@ -0,0 +1,117 @@
|
||||
/* Copyright (C) 2022 Alif Semiconductor - All Rights Reserved.
|
||||
* Use, distribution and modification of this code is permitted under the
|
||||
* terms stated in the Alif Semiconductor Software License Agreement
|
||||
*
|
||||
* You should have received a copy of the Alif Semiconductor Software
|
||||
* License Agreement with this file. If not, please write to:
|
||||
* contact@alifsemi.com, or visit: https://alifsemi.com/license
|
||||
*
|
||||
*/
|
||||
|
||||
/**************************************************************************//**
|
||||
* @file Driver_CMP.h
|
||||
* @author Nisarga A M
|
||||
* @email nisarga.am@alifsemi.com
|
||||
* @version V1.0.0
|
||||
* @date 20-June-2022
|
||||
* @brief Analog Comparator driver definitions.
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef DRIVER_CMP_H_
|
||||
#define DRIVER_CMP_H_
|
||||
|
||||
#include"Driver_Common.h"
|
||||
|
||||
#ifdef _cplusplus
|
||||
extern "c"
|
||||
{
|
||||
#endif
|
||||
|
||||
#define ARM_CMP_API_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(1,0) /* API version */
|
||||
|
||||
/* Control code for Analog Comparator */
|
||||
#define ARM_CMP_POLARITY_CONTROL (0X01UL) /* Used to invert the comparator input signal before processing */
|
||||
#define ARM_CMP_WINDOW_CONTROL_ENABLE (0X02UL) /* Window control used to define when to look at the comparator input */
|
||||
#define ARM_CMP_WINDOW_CONTROL_DISABLE (0X03UL) /* Disable the window control */
|
||||
#define ARM_CMP_FILTER_CONTROL (0X04UL) /* Used to define how many times the comparator input must be sampled */
|
||||
#define ARM_CMP_PRESCALER_CONTROL (0X05UL) /* comparator input will be sampled for every prescaler value */
|
||||
|
||||
/* Comparator event */
|
||||
#define ARM_CMP_FILTER_EVENT_OCCURRED (0x01UL) /* Filter event occurred */
|
||||
|
||||
/* CMP window control macros */
|
||||
#define ARM_CMP_WINDOW_CONTROL_SRC_0 (0x0UL) /* ARM CMP Window control SOURCE 0 */
|
||||
#define ARM_CMP_WINDOW_CONTROL_SRC_1 (0x01UL) /* ARM CMP Window control SOURCE 1 */
|
||||
#define ARM_CMP_WINDOW_CONTROL_SRC_2 (0x02UL) /* ARM CMP Window control SOURCE 2 */
|
||||
#define ARM_CMP_WINDOW_CONTROL_SRC_3 (0x03UL) /* ARM CMP Window control SOURCE 3 */
|
||||
|
||||
/* Function documentation */
|
||||
/**
|
||||
@fn ARM_DRIVER_VERSION GetVersion (void)
|
||||
@brief Get CMP driver version.
|
||||
@return @ref CMP_DRIVER_VERSION
|
||||
|
||||
@fn ARM_CMP_CAPABILITIES GetCapabilities (void)
|
||||
@brief Get CMP driver capabilities
|
||||
@return @ref CMP_CAPABILITIES
|
||||
|
||||
@func int32_t CMP_Initialize (ARM_CMP_SignalEvent_t cb_event)
|
||||
@brief Initialize CMP interface
|
||||
@parameter[1] cb_event : Pointer Comparator Event \ref ARM_CMP_Signal_Event
|
||||
@return \ref execution_status
|
||||
|
||||
@fn int32_t CMP_Uninitialize (void)
|
||||
@brief UnInitialize the CMP interface
|
||||
@param[in] None
|
||||
@return \ref execution_status
|
||||
|
||||
@fn int32_t CMP_PowerControl (ARM_POWER_STATE state)
|
||||
@brief CMSIS-DRIVER CMP power control
|
||||
@param[in] state : Power state
|
||||
@param[in] CMP : Pointer to CMP_resources_t
|
||||
@return \ref execution_status
|
||||
|
||||
@fn int32_t CMP_Control (uint32_t control,uint32_t arg)
|
||||
@brief CMSIS-Driver CMP control
|
||||
@param[in] control : Operation \ref Driver_Comparator.h :Comparator control codes
|
||||
@param[in] arg : Argument of operation (optional)
|
||||
@param[in] cmp : Pointer to CMP_resources_t
|
||||
@return \ref execution_status
|
||||
|
||||
@fn int32_t CMP_Start (void)
|
||||
@brief Start the Analog comparator Interface
|
||||
@param[in] None
|
||||
@return \ref execution_status
|
||||
|
||||
@fn int32_t CMP_Stop (void)
|
||||
@brief Stop the Analog Comparator Interface
|
||||
@param[in] None
|
||||
@return \ref execution_status
|
||||
*/
|
||||
|
||||
typedef void (*ARM_Comparator_SignalEvent_t) (uint32_t event); /*Pointer to \ref Comparator_SignalEvent : Signal Comparator Event*/
|
||||
|
||||
typedef struct _ARM_COMPARATOR_CAPABILITIES{
|
||||
uint32_t Polarity_invert :1; /* Ability to invert the input signal */
|
||||
uint32_t Windowing :1; /* Used to define when to look at the comparator input */
|
||||
uint32_t Filter_Control :1; /* Supports Filter function */
|
||||
uint32_t Prescaler :1; /* Supports Prescaler function */
|
||||
uint32_t Reserved :28; /* Reserved */
|
||||
}ARM_COMPARATOR_CAPABILITIES;
|
||||
|
||||
/**
|
||||
@brief Access Structure of Analog Comparator Driver
|
||||
*/
|
||||
typedef struct ARM_DRIVER_COMPARATOR{
|
||||
ARM_DRIVER_VERSION (*GetVersion) (void); /* pointer is pointing to CMP_GetVersion : used to get the driver version */
|
||||
ARM_COMPARATOR_CAPABILITIES (*GetCapabilities) (void); /* pointer is pointing to CMP_Capabilities : used to get the driver capabilities */
|
||||
int32_t (*Initialize) (ARM_Comparator_SignalEvent_t cb_event); /* Pointer pointing to \ref CMP_intialize */
|
||||
int32_t (*Uninitialize) (void); /* Pointer to CMP_Uninitialize : Un-initialize comparator Interface */
|
||||
int32_t (*PowerControl) (ARM_POWER_STATE state); /* Pointer to CMP_PowerControl : Control Comparator Interface Power */
|
||||
int32_t (*Control) (uint32_t control, uint32_t arg); /* Pointer to CMP_Control : Control Comparator Interface */
|
||||
int32_t (*Start) (void); /* Pointer to start Comparator */
|
||||
int32_t (*Stop) (void); /* Pointer to Stop the Comparator */
|
||||
}const ARM_DRIVER_CMP;
|
||||
|
||||
|
||||
#endif /* DRIVER_CMP_H_ */
|
||||
132
src/hal/alif/Alif_CMSIS/Include/Driver_CPI.h
Normal file
132
src/hal/alif/Alif_CMSIS/Include/Driver_CPI.h
Normal file
@ -0,0 +1,132 @@
|
||||
/* Copyright (C) 2023 Alif Semiconductor - All Rights Reserved.
|
||||
* Use, distribution and modification of this code is permitted under the
|
||||
* terms stated in the Alif Semiconductor Software License Agreement
|
||||
*
|
||||
* You should have received a copy of the Alif Semiconductor Software
|
||||
* License Agreement with this file. If not, please write to:
|
||||
* contact@alifsemi.com, or visit: https://alifsemi.com/license
|
||||
*
|
||||
*/
|
||||
|
||||
/**************************************************************************//**
|
||||
* @file Driver_CPI.h
|
||||
* @author Tanay Rami
|
||||
* @email tanay@alifsemi.com
|
||||
* @version V1.0.0
|
||||
* @date 03-May-2023
|
||||
* @brief Camera Controller Driver definitions.
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef DRIVER_CPI_H_
|
||||
#define DRIVER_CPI_H_
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
#include "Driver_Common.h"
|
||||
|
||||
#define ARM_CPI_API_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(1,0) /* API version */
|
||||
|
||||
/****** CPI Control Codes *****/
|
||||
#define CPI_SOFTRESET (0x01UL) ///< CPI Software Reset; arg: 0=disable, 1=enable
|
||||
#define CPI_CAMERA_SENSOR_CONFIGURE (0x02UL) ///< CAMERA SENSOR configure; arg: 0=disable, 1=enable
|
||||
#define CPI_EVENTS_CONFIGURE (0x03UL) ///< CAMERA EVENTS configure; arg: list of events to enable (ARM_CPI_EVENT_*)
|
||||
#define CPI_CAMERA_SENSOR_GAIN (0x04UL) ///< CAMERA SENSOR gain set; arg: 0x10000 * gain, 0=read only. Returns current/updated gain if no error.
|
||||
#define CPI_CONFIGURE (0x05UL) ///< CPI configure
|
||||
#define CPI_CAMERA_SENSOR_AE (0x06UL) ///< CAMERA SENSOR AE; arg: 0=disable, 1=enable
|
||||
#define CPI_CAMERA_SENSOR_AE_TARGET_LUMA (0x07UL) ///< CAMERA SENSOR AE Tagret LUMA; arg: Value for target luminance
|
||||
|
||||
/****** CPI Events *****/
|
||||
#define ARM_CPI_EVENT_CAMERA_CAPTURE_STOPPED (1UL << 0) ///< Camera Capture Stopped
|
||||
#define ARM_CPI_EVENT_CAMERA_FRAME_HSYNC_DETECTED (1UL << 1) ///< Camera Frame VSYNC Detected for incoming frame
|
||||
#define ARM_CPI_EVENT_CAMERA_FRAME_VSYNC_DETECTED (1UL << 2) ///< Camera Frame VSYNC Detected for incoming frame
|
||||
#define ARM_CPI_EVENT_ERR_CAMERA_INPUT_FIFO_OVERRUN (1UL << 3) ///< Camera FIFO over run Error
|
||||
#define ARM_CPI_EVENT_ERR_CAMERA_OUTPUT_FIFO_OVERRUN (1UL << 4) ///< Camera FIFO under run Error
|
||||
#define ARM_CPI_EVENT_ERR_HARDWARE (1UL << 5) ///< Hardware Bus Error
|
||||
#define ARM_CPI_EVENT_MIPI_CSI2_ERROR (1UL << 6) ///< MIPI CSI2 Error
|
||||
|
||||
// Function documentation
|
||||
/**
|
||||
\fn ARM_DRIVER_VERSION GetVersion (void)
|
||||
\brief Get CPI driver version.
|
||||
\return \ref ARM_DRIVER_VERSION
|
||||
|
||||
\fn ARM_CPI_CAPABILITIES GetCapabilities (void)
|
||||
\brief Get CPI driver capabilities
|
||||
\return \ref ARM_CPI_CAPABILITIES
|
||||
|
||||
\fn int32_t Initialize (CAMERA_RESOLUTION camera_resolution,
|
||||
ARM_CPI_SignalEvent_t cb_event)
|
||||
\brief Initialize CPI and Camera Sensor Device Interface.
|
||||
\param[in] cb_event : Pointer to \ref ARM_CPI_SignalEvent_t
|
||||
\return \ref execution_status
|
||||
|
||||
\fn int32_t Uninitialize (void)
|
||||
\brief De-initialize CPI and Camera Sensor Device Interface.
|
||||
\return \ref execution_status
|
||||
|
||||
\fn int32_t PowerControl (ARM_POWER_STATE state)
|
||||
\brief Control CPI Interface Power.
|
||||
\param[in] state : Power state
|
||||
\return \ref execution_status
|
||||
|
||||
\fn int32_t CaptureFrame (void *framebuffer_startaddr)
|
||||
\brief Start CPI in Snapshot mode and Camera Sensor Device Interface.
|
||||
In Snapshot mode, CPI will capture one frame then it gets stop.
|
||||
\param[in] framebuffer_startaddr : Pointer to frame buffer start address, where camera captured image will be stored.
|
||||
\return \ref execution_status
|
||||
|
||||
\fn int32_t CaptureVideo (void *framebuffer_startaddr)
|
||||
\brief Start CPI in Video mode and Camera Sensor Device Interface.
|
||||
In Video mode, CPI will capture video data continuously.
|
||||
\param[in] framebuffer_startaddr : Pointer to frame buffer start address, where camera captured video data will be stored.
|
||||
\return \ref execution_status
|
||||
|
||||
|
||||
\fn int32_t Stop (void)
|
||||
\brief Stop CPI and Camera Sensor Device Interface.
|
||||
\return \ref execution_status
|
||||
|
||||
\fn int32_t Control (uint32_t control, uint32_t arg)
|
||||
\brief Control CPI and Camera Sensor Device Interface.
|
||||
\param[in] control : Operation
|
||||
\param[in] arg : Argument of operation (optional)
|
||||
\return common \ref execution_status
|
||||
*/
|
||||
|
||||
typedef void (*ARM_CPI_SignalEvent_t) (uint32_t event); ///< Pointer to \ref ARM_CPI_SignalEvent_t : Signal CPI Event.
|
||||
|
||||
/**
|
||||
\brief CPI Driver Capabilities.
|
||||
*/
|
||||
typedef struct _ARM_CPI_CAPABILITIES {
|
||||
uint32_t snapshot : 1; ///< Supports CPI Snapshot mode, In this mode CPI will capture one frame then it gets stop.
|
||||
uint32_t video : 1; ///< Supports CPI video mode
|
||||
uint32_t reserved : 30; ///< Reserved (must be zero)
|
||||
} ARM_CPI_CAPABILITIES;
|
||||
|
||||
|
||||
/**
|
||||
\brief Access structure of the CPI Driver.
|
||||
*/
|
||||
typedef struct _ARM_DRIVER_CPI{
|
||||
ARM_DRIVER_VERSION (*GetVersion) (void); ///< Pointer to \ref CPI_GetVersion : Get driver version.
|
||||
ARM_CPI_CAPABILITIES (*GetCapabilities) (void); ///< Pointer to \ref CPI_GetCapabilities : Get driver capabilities.
|
||||
int32_t (*Initialize) (ARM_CPI_SignalEvent_t cb_event); ///< Pointer to \ref CPI_Initialize : Initialize CPI Interface.
|
||||
int32_t (*Uninitialize) (void); ///< Pointer to \ref CPI_Uninitialize : De-initialize CPI Interface.
|
||||
int32_t (*PowerControl) (ARM_POWER_STATE state); ///< Pointer to \ref CPI_PowerControl : Control CPI Interface Power.
|
||||
int32_t (*CaptureFrame) (void *framebuffer_startaddr); ///< Pointer to \ref CPI_StartSnapshot : Start CPI Interface in Snapshot mode.
|
||||
int32_t (*CaptureVideo) (void *framebuffer_startaddr); ///< Pointer to \ref CPI_CaptureVideo : Start CPI Interface in Video mode.
|
||||
int32_t (*Stop) (void); ///< Pointer to \ref CPI_Stop : Stop CPI Interface.
|
||||
int32_t (*Control) (uint32_t control, uint32_t arg); ///< Pointer to \ref CPI_Control : Control CPI Interface.
|
||||
} const ARM_DRIVER_CPI;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* DRIVER_CPI_H_ */
|
||||
|
||||
/************************ (C) COPYRIGHT ALIF SEMICONDUCTOR *****END OF FILE****/
|
||||
140
src/hal/alif/Alif_CMSIS/Include/Driver_CRC.h
Normal file
140
src/hal/alif/Alif_CMSIS/Include/Driver_CRC.h
Normal file
@ -0,0 +1,140 @@
|
||||
/* Copyright (C) 2022 Alif Semiconductor - All Rights Reserved.
|
||||
* Use, distribution and modification of this code is permitted under the
|
||||
* terms stated in the Alif Semiconductor Software License Agreement
|
||||
*
|
||||
* You should have received a copy of the Alif Semiconductor Software
|
||||
* License Agreement with this file. If not, please write to:
|
||||
* contact@alifsemi.com, or visit: https://alifsemi.com/license
|
||||
*
|
||||
*/
|
||||
|
||||
/**************************************************************************//**
|
||||
* @file Driver_CRC.h
|
||||
* @author Nisarga A M
|
||||
* @email nisarga.am@alifsemi.com
|
||||
* @version V1.0.0
|
||||
* @date 18-April-2022
|
||||
* @brief CRC(Cyclic Redundancy Check) driver definitions.
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef DRIVER_CRC_H
|
||||
#define DRIVER_CRC_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
#include "Driver_Common.h"
|
||||
|
||||
#define ARM_CRC_API_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(1,0) /* API version */
|
||||
|
||||
#define ARM_CRC_COMPUTE_EVENT_DONE (1 << 0) /* ARM CRC COMPUTE EVENT DONE */
|
||||
|
||||
#define ARM_CRC_CONTROL_POS 0
|
||||
#define ARM_CRC_CONTROL_MASK (0x1F << ARM_CRC_CONTROL_POS) /* To select the Reflect, Invert, Bit, Byte, Custom polynomial bit of CRC */
|
||||
|
||||
#define ARM_CRC_ENABLE_BYTE_SWAP (0x1UL << 0) /* Byte swap CRC Enale = 1 and Disable =0 */
|
||||
#define ARM_CRC_ENABLE_BIT_SWAP (0x1UL << 1) /* Bit swap CRC Enable = 1 and Disable = 0 */
|
||||
#define ARM_CRC_ENABLE_CUSTOM_POLY (0x1UL << 2) /* Custom poly CRC Enable = 1 and Disable = 0 */
|
||||
#define ARM_CRC_ENABLE_INVERT_OUTPUT (0x1UL << 3) /* Invert CRC Enable = 1 and Disable = 0 */
|
||||
#define ARM_CRC_ENABLE_REFLECT_OUTPUT (0x1UL << 4) /* Reflect CRC Enable = 1 and Disable = 0 */
|
||||
|
||||
/* CRC algorithm select */
|
||||
#define ARM_CRC_ALGORITHM_SEL (0x01UL << 5) /* To select the below particular algorithm */
|
||||
|
||||
#define ARM_CRC_ALGORITHM_SEL_8_BIT_CCITT (0x01UL) /* To select CRC_8_CCITT algorithm give value as 0 */
|
||||
#define ARM_CRC_ALGORITHM_SEL_16_BIT (0x02UL) /* To select CRC_16 algorithm give value as 2 */
|
||||
#define ARM_CRC_ALGORITHM_SEL_16_BIT_CCITT (0x03UL) /* To select CRC_16_CCITT algorithm give value as 3 */
|
||||
#define ARM_CRC_ALGORITHM_SEL_32_BIT (0x04UL) /* To select CRC_32 algorithm give value as 4 */
|
||||
#define ARM_CRC_ALGORITHM_SEL_32_BIT_CUSTOM_POLY (0x05UL) /* To select CRC_32C algorithm give value as 5 */
|
||||
|
||||
/* Function documentation */
|
||||
/**
|
||||
@fn ARM_DRIVER_VERSION GetVersion (void)
|
||||
@brief Get CRC driver version.
|
||||
@return @ref CRC_DRIVER_VERSION
|
||||
|
||||
@fn ARM_CRC_CAPABILITIES GetCapabilities (void)
|
||||
@brief Get CRC driver capabilities
|
||||
@return @ref CRC_CAPABILITIES
|
||||
|
||||
@fn int32_t CRC_Initialize (ARM_CRC_SignalEvent_t cb_event)
|
||||
@brief Initialize the CRC interface
|
||||
@param[in] crc : Pointer to CRC resources
|
||||
@return \ref execution_status
|
||||
|
||||
@fn int32_t CRC_Uninitialize (CRC_resources_t *crc)
|
||||
@brief UnInitialize the CRC interface
|
||||
@param[in] crc : Pointer to CRC resources
|
||||
@return \ref execution_status
|
||||
|
||||
@fn int32_t CRC_PowerControl (ARM_POWER_STATE state)
|
||||
@brief CMSIS-DRIVER CRC power control
|
||||
@param[in] state : Power state
|
||||
@param[in] crc : Pointer to CRC resources
|
||||
@return \ref execution_status
|
||||
|
||||
@fn int32_t CRC_Control (uint32_t control,uint32_t arg,CRC_resources_t *crc)
|
||||
@brief CMSIS-Driver CRC control
|
||||
@param[in] control : Operation \ref Driver_CRC.h :CRC control codes
|
||||
@param[in] arg : Argument of operation (optional)
|
||||
@param[in] crc : Pointer to CRC resources
|
||||
@return common \ref execution_status
|
||||
|
||||
@fn int32_t CRC_Seed (uint32_t value ,CRC_resources_t *crc)
|
||||
@brief CMSIS-DRIVER CRC Seed value
|
||||
@param[in] seed_value : Seed value depending on whether the data is 8 bit or 16 or 32 bit
|
||||
@param[in] crc : pointer to CRC resources
|
||||
@return \ref execution_status
|
||||
|
||||
@fn int32_t CRC_PolyCustom (uint32_t polynomial,CRC_resources_t *crc)
|
||||
@brief CMSIS-DRIVER CRC custom polynomial
|
||||
@param[in] polynomial : Polynomial data for 8 bit or 16 or 32 bit
|
||||
@param[in] crc : pointer to CRC resources
|
||||
@return \ref execution_status
|
||||
|
||||
@fn int32_t CRC_Compute (void *data_in,uint32_t len,uint32_t *data_out,CRC_resources_t *crc)
|
||||
@brief CMSIS-DRIVER CRC Input data and getting the output
|
||||
@param[in] data_in : 8 bit or 16 bit or 32 bit input data
|
||||
@param[in] len : length of the data
|
||||
@param[in] data_out : to get the output data of 8 bit or 16 bit or 32 bit output data
|
||||
@param[in] crc : pointer to CRC resources
|
||||
@return \ref execution_status
|
||||
*/
|
||||
|
||||
/**
|
||||
@brief CRC Device Driver Capabilities.
|
||||
*/
|
||||
typedef struct ARM_CRC_CAPABILITIES {
|
||||
uint32_t CRC_8_CCITT_ALGORITHM : 1; /* Supports CRC_8_CCITT */
|
||||
uint32_t CRC_16_ALGORITHM : 1; /* Supports CRC_16 */
|
||||
uint32_t CRC_16_CCITT_ALGORITHM : 1; /* Supports CRC_16_CCITT */
|
||||
uint32_t CRC_32_ALGORITHM : 1; /* Supports CRC_32 */
|
||||
uint32_t CRC_32C_ALGORITHM : 1; /* Supports CRC_32C */
|
||||
uint32_t reserved : 27; /* Reserved (must be Zero) */
|
||||
}ARM_CRC_CAPABILITIES;
|
||||
|
||||
typedef void (*ARM_CRC_SignalEvent_t) (uint32_t event); /*Pointer to \ref CRC_SignalEvent : Signal CRC Event*/
|
||||
|
||||
/**
|
||||
@brief Access structure of the CRC Driver.
|
||||
*/
|
||||
typedef struct ARM_Driver_CRC
|
||||
{
|
||||
ARM_DRIVER_VERSION (*GetVersion) (void); /* pointer is pointing to CRC_GetVersion : used to get the driver version */
|
||||
ARM_CRC_CAPABILITIES (*GetCapabilities) (void); /* pointer is pointing to CRC_Capabilities : used to get the driver capabilities */
|
||||
int32_t (*Initialize) (ARM_CRC_SignalEvent_t cb_event); /* Initialize the CRC Interface */
|
||||
int32_t (*Uninitialize) (void); /* Pointer to CRC_Uninitialize : De-initialize CRC Interface */
|
||||
int32_t (*PowerControl) (ARM_POWER_STATE state); /* Pointer to CRC_PowerControl : Control CRC Interface Power */
|
||||
int32_t (*Control) (uint32_t control, uint32_t arg); /* Pointer to CRC_Control : Control CRC Interface */
|
||||
int32_t (*Seed) (uint32_t seed_value); /* Pointer to CRC_Seed : used to give the seed value*/
|
||||
int32_t (*PolyCustom) (uint32_t polynomial); /* Pointer to CRC_PolyCustom : used to give the poly custom value*/
|
||||
int32_t (*Compute) (const void *data_in, uint32_t len, uint32_t *data_out); /* Pointer to CRC_Compute : used to give the input data and output data */
|
||||
}const ARM_DRIVER_CRC;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* DRIVER_CRC_H_ */
|
||||
69
src/hal/alif/Alif_CMSIS/Include/Driver_Common.h
Normal file
69
src/hal/alif/Alif_CMSIS/Include/Driver_Common.h
Normal file
@ -0,0 +1,69 @@
|
||||
/*
|
||||
* Copyright (c) 2013-2017 ARM Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* $Date: 2. Feb 2017
|
||||
* $Revision: V2.0
|
||||
*
|
||||
* Project: Common Driver definitions
|
||||
*/
|
||||
|
||||
/* History:
|
||||
* Version 2.0
|
||||
* Changed prefix ARM_DRV -> ARM_DRIVER
|
||||
* Added General return codes definitions
|
||||
* Version 1.10
|
||||
* Namespace prefix ARM_ added
|
||||
* Version 1.00
|
||||
* Initial release
|
||||
*/
|
||||
|
||||
#ifndef DRIVER_COMMON_H_
|
||||
#define DRIVER_COMMON_H_
|
||||
|
||||
#include <stddef.h>
|
||||
#include <stdint.h>
|
||||
#include <stdbool.h>
|
||||
|
||||
#define ARM_DRIVER_VERSION_MAJOR_MINOR(major,minor) (((major) << 8) | (minor))
|
||||
|
||||
/**
|
||||
\brief Driver Version
|
||||
*/
|
||||
typedef struct _ARM_DRIVER_VERSION {
|
||||
uint16_t api; ///< API version
|
||||
uint16_t drv; ///< Driver version
|
||||
} ARM_DRIVER_VERSION;
|
||||
|
||||
/* General return codes */
|
||||
#define ARM_DRIVER_OK 0 ///< Operation succeeded
|
||||
#define ARM_DRIVER_ERROR -1 ///< Unspecified error
|
||||
#define ARM_DRIVER_ERROR_BUSY -2 ///< Driver is busy
|
||||
#define ARM_DRIVER_ERROR_TIMEOUT -3 ///< Timeout occurred
|
||||
#define ARM_DRIVER_ERROR_UNSUPPORTED -4 ///< Operation not supported
|
||||
#define ARM_DRIVER_ERROR_PARAMETER -5 ///< Parameter error
|
||||
#define ARM_DRIVER_ERROR_SPECIFIC -6 ///< Start of driver specific errors
|
||||
|
||||
/**
|
||||
\brief General power states
|
||||
*/
|
||||
typedef enum _ARM_POWER_STATE {
|
||||
ARM_POWER_OFF, ///< Power off: no operation possible
|
||||
ARM_POWER_LOW, ///< Low Power mode: retain state, detect and signal wake-up events
|
||||
ARM_POWER_FULL ///< Power on: full operation at maximum performance
|
||||
} ARM_POWER_STATE;
|
||||
|
||||
#endif /* DRIVER_COMMON_H_ */
|
||||
141
src/hal/alif/Alif_CMSIS/Include/Driver_DAC.h
Normal file
141
src/hal/alif/Alif_CMSIS/Include/Driver_DAC.h
Normal file
@ -0,0 +1,141 @@
|
||||
/* Copyright (C) 2022 Alif Semiconductor - All Rights Reserved.
|
||||
* Use, distribution and modification of this code is permitted under the
|
||||
* terms stated in the Alif Semiconductor Software License Agreement
|
||||
*
|
||||
* You should have received a copy of the Alif Semiconductor Software
|
||||
* License Agreement with this file. If not, please write to:
|
||||
* contact@alifsemi.com, or visit: https://alifsemi.com/license
|
||||
*
|
||||
*/
|
||||
|
||||
/**************************************************************************//**
|
||||
* @file Driver_DAC.h
|
||||
* @author Nisarga A M
|
||||
* @email nisarga.am@alifsemi.com
|
||||
* @version V1.0.0
|
||||
* @date 22-Feb-2022
|
||||
* @brief DAC(Digital to Analog Converter) driver definitions.
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef DRIVER_DAC_H
|
||||
#define DRIVER_DAC_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
#include "Driver_Common.h"
|
||||
|
||||
#define ARM_DAC_API_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(1,0) /* API version */
|
||||
|
||||
/* DAC Control Code */
|
||||
#define ARM_DAC_RESET (0x01UL) /* To reset the DAC */
|
||||
#define ARM_DAC_INPUT_BYPASS_MODE (0x02UL) /* Pass input through bypass mode */
|
||||
#define ARM_DAC_CAPACITANCE_HP_MODE (0x03UL) /* Set DAC capacitance */
|
||||
#define ARM_DAC_SELECT_IBIAS_OUTPUT (0x04UL) /* Set DAC output current */
|
||||
|
||||
/* Select the DAC output current */
|
||||
#define ARM_DAC_0UA_OUT_CUR (0x0UL) /* Set DAC output current to 0 micro amps */
|
||||
#define ARM_DAC_100UA_OUT_CUR (0x1UL) /* Set DAC output current to 100 micro amps */
|
||||
#define ARM_DAC_200UA_OUT_CUR (0x2UL) /* Set DAC output current to 200 micro amps */
|
||||
#define ARM_DAC_300UA_OUT_CUR (0x3UL) /* Set DAC output current to 300 micro amps */
|
||||
#define ARM_DAC_400UA_OUT_CUR (0x4UL) /* Set DAC output current to 400 micro amps */
|
||||
#define ARM_DAC_500UA_OUT_CUR (0x5UL) /* Set DAC output current to 500 micro amps */
|
||||
#define ARM_DAC_600UA_OUT_CUR (0x6UL) /* Set DAC output current to 600 micro amps */
|
||||
#define ARM_DAC_700UA_OUT_CUR (0x7UL) /* Set DAC output current to 700 micro amps */
|
||||
#define ARM_DAC_800UA_OUT_CUR (0x8UL) /* Set DAC output current to 800 micro amps */
|
||||
#define ARM_DAC_900UA_OUT_CUR (0x9UL) /* Set DAC output current to 900 micro amps */
|
||||
#define ARM_DAC_1000UA_OUT_CUR (0xAUL) /* Set DAC output current to 1000 micro amps */
|
||||
#define ARM_DAC_1100UA_OUT_CUR (0xBUL) /* Set DAC output current to 1100 micro amps */
|
||||
#define ARM_DAC_1200UA_OUT_CUR (0xCUL) /* Set DAC output current to 1200 micro amps */
|
||||
#define ARM_DAC_1300UA_OUT_CUR (0xDUL) /* Set DAC output current to 1300 micro amps */
|
||||
#define ARM_DAC_1400UA_OUT_CUR (0xEUL) /* Set DAC output current to 1400 micro amps */
|
||||
#define ARM_DAC_1500UA_OUT_CUR (0xFUL) /* Set DAC output current to 1500 micro amps */
|
||||
|
||||
/* Select the DAC capacitance */
|
||||
#define ARM_DAC_2PF_CAPACITANCE (0x0UL) /* Set DAC capacitance to 2PF */
|
||||
#define ARM_DAC_4PF_CAPACITANCE (0x1UL) /* Set DAC capacitance to 4PF */
|
||||
#define ARM_DAC_6PF_CAPACITANCE (0x2UL) /* Set DAC capacitance to 6PF */
|
||||
#define ARM_DAC_8PF_CAPACITANCE (0x3UL) /* Set DAC capacitance to 8PF */
|
||||
|
||||
/* Function documentation */
|
||||
/**
|
||||
@fn ARM_DRIVER_VERSION GetVersion (void)
|
||||
@brief Get DAC driver version.
|
||||
@return @ref DAC_DRIVER_VERSION
|
||||
|
||||
@fn ARM_DAC_CAPABILITIES GetCapabilities (void)
|
||||
@brief Get DAC driver capabilities
|
||||
@return @ref DAC_CAPABILITIES
|
||||
|
||||
@fn int32_t DAC_Initialize (DAC_DRV_INFO *dac)
|
||||
@brief Initialize the DAC interface
|
||||
@param[in] dac : Pointer to dac resources
|
||||
@return \ref execution_status
|
||||
|
||||
@fn int32_t DAC_Uninitialize (DAC_DRV_INFO *dac)
|
||||
@brief De-Initialize the DAC interface
|
||||
@param[in] dac : Pointer to dac resources
|
||||
@return \ref execution_status
|
||||
|
||||
@fn int32_t DAC_PowerControl (ARM_POWER_STATE state)
|
||||
@brief CMSIS-DRIVER DAC power control
|
||||
@param[in] state : Power state
|
||||
@param[in] DAC : Pointer to DAC resources
|
||||
@return \ref execution_status
|
||||
|
||||
@fn int32_t DAC_Control (uint32_t control,uint32_t arg,DAC_resources_t *dac)
|
||||
@brief CMSIS-Driver dac control
|
||||
@param[in] control : Operation \ref Driver_DAC.h : DAC control codes
|
||||
@param[in] arg : Argument of operation (optional)
|
||||
@param[in] dac : Pointer to dac resources
|
||||
@return common \ref execution_status
|
||||
|
||||
@fn DAC_Start (DAC_resources_t *dac)
|
||||
@brief CMSIS-Driver DAC Start
|
||||
@param[in] dac : Pointer to dac resources
|
||||
@return \ref execution_status
|
||||
|
||||
@fn DAC_Stop (DAC_resources_t *dac)
|
||||
@brief CMSIS-Driver DAC Stop
|
||||
@param[in] dac : Pointer to dac resources
|
||||
@return \ref execution_status
|
||||
|
||||
@fn DAC_SetInput(uint32_t num, DAC_resources_t *dac)
|
||||
@brief CMSIS-Driver to set the DAC input and output will be in GPIO pins
|
||||
@param[in] Input : Operation
|
||||
@param[in] value : DAC input
|
||||
@param[in] dac : Pointer to dac device resources
|
||||
@return \ref execution_status
|
||||
*/
|
||||
|
||||
/**
|
||||
@brief DAC Device Driver Capabilities.
|
||||
*/
|
||||
typedef struct ARM_DAC_CAPABILITIES {
|
||||
uint32_t resolution : 1; /* DAC Resolution */
|
||||
uint32_t reserved : 31; /* Reserved (must be Zero) */
|
||||
}ARM_DAC_CAPABILITIES;
|
||||
|
||||
/**
|
||||
@brief Access structure of the DAC Driver.
|
||||
*/
|
||||
typedef struct ARM_Driver_DAC
|
||||
{
|
||||
ARM_DRIVER_VERSION (*GetVersion) (void); /* pointer is pointing to DAC_GetVersion : used to get the driver version */
|
||||
ARM_DAC_CAPABILITIES (*GetCapabilities) (void); /* pointer is pointing to DAC_Capabilities : used to get the driver capabilities */
|
||||
int32_t (*Initialize) (void); /* Initialize the DAC Interface */
|
||||
int32_t (*Uninitialize) (void); /* Pointer to DAC_Uninitialize : De-initialize DAC Interface */
|
||||
int32_t (*PowerControl) (ARM_POWER_STATE state); /* Pointer to DAC_PowerControl : Control DAC Interface Power */
|
||||
int32_t (*Control) (uint32_t control, uint32_t arg); /* Pointer to DAC_Control : Control DAC Interface */
|
||||
int32_t (*Start) (void); /* Pointer to start DAC */
|
||||
int32_t (*Stop) (void); /* Pointer to stop the DAC */
|
||||
int32_t (*SetInput) (uint32_t value); /* Pointer to Set_input */
|
||||
}const ARM_DRIVER_DAC;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* DRIVER_DAC_H_ */
|
||||
199
src/hal/alif/Alif_CMSIS/Include/Driver_DMA.h
Normal file
199
src/hal/alif/Alif_CMSIS/Include/Driver_DMA.h
Normal file
@ -0,0 +1,199 @@
|
||||
/* Copyright (C) 2022 Alif Semiconductor - All Rights Reserved.
|
||||
* Use, distribution and modification of this code is permitted under the
|
||||
* terms stated in the Alif Semiconductor Software License Agreement
|
||||
*
|
||||
* You should have received a copy of the Alif Semiconductor Software
|
||||
* License Agreement with this file. If not, please write to:
|
||||
* contact@alifsemi.com, or visit: https://alifsemi.com/license
|
||||
*
|
||||
*/
|
||||
#ifndef DRIVER_DMA_H_
|
||||
#define DRIVER_DMA_H_
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
#include "Driver_Common.h"
|
||||
|
||||
#define ARM_DMA_API_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(4,0) /* API version */
|
||||
|
||||
|
||||
#define _ARM_Driver_DMA_(n) Driver_DMA##n
|
||||
#define ARM_Driver_DMA_(n) _ARM_Driver_DMA_(n)
|
||||
|
||||
/****** DMA Control Codes *****/
|
||||
|
||||
#define ARM_DMA_CONTROL_Msk (0xFFUL)
|
||||
#define ARM_DMA_USER_PROVIDED_MCODE (0x01UL) ///< Use User provided microcode; arg = microcode address in memory
|
||||
#define ARM_DMA_I2S_MONO_MODE (0x02UL) ///< Support for I2S mono mode;
|
||||
#define ARM_DMA_CRC_MODE (0x03UL) ///< Support for CRC which doesn't require handshaking
|
||||
#define ARM_DMA_ENDIAN_SWAP_SIZE (0x04UL) ///< Set the Endian Swap Size
|
||||
|
||||
/**
|
||||
\brief DMA Data Direction
|
||||
*/
|
||||
typedef enum _ARM_DMA_DATA_DIR {
|
||||
ARM_DMA_MEM_TO_MEM,
|
||||
ARM_DMA_MEM_TO_DEV,
|
||||
ARM_DMA_DEV_TO_MEM,
|
||||
ARM_DMA_DIR_NOT_SET,
|
||||
} ARM_DMA_DATA_DIR;
|
||||
|
||||
/**
|
||||
\brief DMA Burst Size
|
||||
*/
|
||||
typedef enum {
|
||||
BS_BYTE_1,
|
||||
BS_BYTE_2,
|
||||
BS_BYTE_4,
|
||||
BS_BYTE_8,
|
||||
BS_BYTE_16,
|
||||
} ARM_DMA_BS_Type;
|
||||
|
||||
/**
|
||||
\brief DMA Endian Swap Size
|
||||
*/
|
||||
typedef enum {
|
||||
ESS_SWAP_NONE,
|
||||
ESS_SWAP_16BIT,
|
||||
ESS_SWAP_32BIT,
|
||||
ESS_SWAP_64BIT,
|
||||
ESS_SWAP_128BIT,
|
||||
} ARM_DMA_ESS_Type;
|
||||
|
||||
/****** DMA specific error codes *****/
|
||||
#define ARM_DMA_ERROR_HANDLE (ARM_DRIVER_ERROR_SPECIFIC - 1) ///< Handle error
|
||||
#define ARM_DMA_ERROR_EVENT (ARM_DRIVER_ERROR_SPECIFIC - 2) ///< Event not available
|
||||
#define ARM_DMA_ERROR_BUFFER (ARM_DRIVER_ERROR_SPECIFIC - 3) ///< Buffer overrun
|
||||
#define ARM_DMA_ERROR_MAX_TRANSFER (ARM_DRIVER_ERROR_SPECIFIC - 4) ///< Max transfer length per req
|
||||
#define ARM_DMA_ERROR_BUSY (ARM_DRIVER_ERROR_SPECIFIC - 5) ///< Busy
|
||||
#define ARM_DMA_ERROR_FAULT (ARM_DRIVER_ERROR_SPECIFIC - 6) ///< Fault Occurred
|
||||
#define ARM_DMA_ERROR_UNALIGNED (ARM_DRIVER_ERROR_SPECIFIC - 7) ///< Unaligned address or bytes
|
||||
|
||||
/**
|
||||
\brief DMA Status
|
||||
*/
|
||||
typedef struct _ARM_DMA_STATUS {
|
||||
uint32_t busy : 1; ///< DMA busy flag
|
||||
uint32_t reserved : 31;
|
||||
} ARM_DMA_STATUS;
|
||||
|
||||
typedef void (*ARM_DMA_SignalEvent_t) (uint32_t event, int8_t peri_num); ///< Pointer to \ref ARM_DMA_SignalEvent : Signal DMA Event.
|
||||
typedef int32_t DMA_Handle_Type; ///< Pointer to \ref DMA_Handle_Type : DMA handle number.
|
||||
|
||||
/**
|
||||
\brief DMA Configuration
|
||||
*/
|
||||
typedef struct _ARM_DMA_PARAMS {
|
||||
int8_t peri_reqno;
|
||||
uint8_t burst_len;
|
||||
ARM_DMA_BS_Type burst_size;
|
||||
ARM_DMA_DATA_DIR dir;
|
||||
volatile const void *src_addr;
|
||||
volatile void *dst_addr;
|
||||
uint32_t num_bytes;
|
||||
uint32_t irq_priority;
|
||||
ARM_DMA_SignalEvent_t cb_event;
|
||||
} ARM_DMA_PARAMS;
|
||||
|
||||
/****** DMA Event *****/
|
||||
#define ARM_DMA_EVENT_COMPLETE (1UL << 0) ///< Transfer completed
|
||||
#define ARM_DMA_EVENT_ABORT (1UL << 1) ///< Operation Aborted
|
||||
|
||||
|
||||
|
||||
// Function documentation
|
||||
/**
|
||||
\fn ARM_DRIVER_VERSION ARM_DMA_GetVersion (void)
|
||||
\brief Get driver version.
|
||||
\return \ref ARM_DRIVER_VERSION
|
||||
|
||||
\fn ARM_DMA_CAPABILITIES ARM_DMA_GetCapabilities (void)
|
||||
\brief Get driver capabilities.
|
||||
\return \ref ARM_DMA_CAPABILITIES
|
||||
|
||||
\fn int32_t ARM_DMA_Initialize (ARM_DMA_SignalEvent_t cb_event)
|
||||
\brief Initialize DMA Interface.
|
||||
\param[in] cb_event Pointer to \ref ARM_DMA_SignalEvent
|
||||
\return \ref execution_status
|
||||
|
||||
\fn int32_t ARM_DMA_Uninitialize (void)
|
||||
\brief De-initialize DMA Interface.
|
||||
\return \ref execution_status
|
||||
|
||||
\fn int32_t ARM_DMA_Allocate (DMA_Handle_Type *handle)
|
||||
\brief Allocate a DMA handle for the transfer operation
|
||||
\param[in] handle Pointer to store the handle provided by the DMA driver
|
||||
\return \ref execution_status
|
||||
|
||||
\fn int32_t ARM_DMA_Start (DMA_Handle_Type *handle, ARM_DMA_PARAMS *params)
|
||||
\brief Start the DMA transfer operation using the params
|
||||
\param[in] handle DMA handle for which the transfer operation is requested
|
||||
\param[in] params DMA parameters required for this transfer operation
|
||||
\return \ref execution_status
|
||||
|
||||
\fn int32_t ARM_DMA_Stop (DMA_Handle_Type *handle)
|
||||
\brief Stop the DMA transfer operation
|
||||
\param[in] handle DMA handle for which the transfer operation is requested
|
||||
\return \ref execution_status
|
||||
|
||||
\fn int32_t ARM_DMA_Control (DMA_Handle_Type *handle, uint32_t control, uint32_t arg)
|
||||
\brief Control DMA Interface.
|
||||
\param[in] handle DMA handle for which the transfer operation is requested
|
||||
\param[in] control Operation
|
||||
\param[in] arg Argument of operation (optional)
|
||||
\return common \ref execution_status and driver specific \ref dma_execution_status
|
||||
|
||||
\fn ARM_DMA_STATUS ARM_DMA_GetStatus (DMA_Handle_Type *handle, uint32_t *count)
|
||||
\brief Get DMA status.
|
||||
\param[in] handle DMA handle
|
||||
\param[in] count Return the number of items transmitted
|
||||
\return DMA status \ref ARM_DMA_STATUS
|
||||
|
||||
\fn int32_t ARM_DMA_DeAllocate (DMA_Handle_Type *handle)
|
||||
\brief DeAllocate a DMA handle
|
||||
\param[in] handle Pointer to the handle provided by the DMA driver
|
||||
\return \ref execution_status
|
||||
|
||||
\fn void ARM_DMA_SignalEvent (uint32_t event)
|
||||
\brief Signal DMA Events.
|
||||
\param[in] event \ref DMA_events notification mask
|
||||
\return none
|
||||
*/
|
||||
|
||||
/**
|
||||
\brief DMA Driver Capabilities.
|
||||
*/
|
||||
typedef struct _ARM_DMA_CAPABILITIES {
|
||||
uint32_t mem_to_mem : 1; ///< supports memory to memory operation
|
||||
uint32_t mem_to_peri : 1; ///< supports memory to peripheral operation
|
||||
uint32_t peri_to_mem : 1; ///< supports peripheral to memory operation
|
||||
uint32_t sg : 1; ///< supports Scatter Gather
|
||||
uint32_t secure_mode : 1; ///< supports Secure/Non-Secure mode operation
|
||||
uint32_t reserved : 26; ///< Reserved (must be zero)
|
||||
} ARM_DMA_CAPABILITIES;
|
||||
|
||||
/**
|
||||
\brief Access structure of the DMA Driver.
|
||||
*/
|
||||
typedef struct _ARM_DRIVER_DMA {
|
||||
ARM_DRIVER_VERSION (*GetVersion) (void); ///< Pointer to \ref ARM_DMA_GetVersion : Get driver version.
|
||||
ARM_DMA_CAPABILITIES (*GetCapabilities) (void); ///< Pointer to \ref ARM_DMA_GetCapabilities : Get driver capabilities.
|
||||
int32_t (*Initialize) (void); ///< Pointer to \ref ARM_DMA_Initialize : Initialize DMA Interface.
|
||||
int32_t (*Uninitialize) (void); ///< Pointer to \ref ARM_DMA_Uninitialize : De-initialize DMA Interface.
|
||||
int32_t (*PowerControl) (ARM_POWER_STATE state); ///< Pointer to \ref ARM_DMA_PowerControl : Control DMA Interface Power.
|
||||
int32_t (*Allocate) (DMA_Handle_Type *handle); ///< Pointer to \ref ARM_DMA_Allocate : Allocate a DMA handle
|
||||
int32_t (*Control) (DMA_Handle_Type *handle, uint32_t control, uint32_t arg); ///< Pointer to \ref ARM_DMA_Control : Control DMA operation
|
||||
int32_t (*Start) (DMA_Handle_Type *handle, ARM_DMA_PARAMS *params); ///< Pointer to \ref ARM_DMA_Start : Start DMA operation
|
||||
int32_t (*Stop) (DMA_Handle_Type *handle); ///< Pointer to \ref ARM_DMA_Stop : Stop DMA operation
|
||||
int32_t (*GetStatus) (DMA_Handle_Type *handle, uint32_t *count); ///< Pointer to \ref ARM_DMA_GetStatus : Get DMA status.
|
||||
int32_t (*DeAllocate) (DMA_Handle_Type *handle); ///< Pointer to \ref ARM_DMA_DeAllocate : De-Allocate a DMA handle
|
||||
} const ARM_DRIVER_DMA;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* DRIVER_DMA_H_ */
|
||||
87
src/hal/alif/Alif_CMSIS/Include/Driver_ETH.h
Normal file
87
src/hal/alif/Alif_CMSIS/Include/Driver_ETH.h
Normal file
@ -0,0 +1,87 @@
|
||||
/*
|
||||
* Copyright (c) 2013-2020 ARM Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* $Date: 24. January 2020
|
||||
* $Revision: V2.2
|
||||
*
|
||||
* Project: Ethernet PHY and MAC Driver common definitions
|
||||
*/
|
||||
|
||||
/* History:
|
||||
* Version 2.2
|
||||
* Removed volatile from ARM_ETH_LINK_INFO
|
||||
* Version 2.1
|
||||
* ARM_ETH_LINK_INFO made volatile
|
||||
* Version 2.0
|
||||
* Removed ARM_ETH_STATUS enumerator
|
||||
* Removed ARM_ETH_MODE enumerator
|
||||
* Version 1.10
|
||||
* Namespace prefix ARM_ added
|
||||
* Version 1.00
|
||||
* Initial release
|
||||
*/
|
||||
|
||||
#ifndef DRIVER_ETH_H_
|
||||
#define DRIVER_ETH_H_
|
||||
|
||||
#include "Driver_Common.h"
|
||||
|
||||
/**
|
||||
\brief Ethernet Media Interface type
|
||||
*/
|
||||
#define ARM_ETH_INTERFACE_MII (0U) ///< Media Independent Interface (MII)
|
||||
#define ARM_ETH_INTERFACE_RMII (1U) ///< Reduced Media Independent Interface (RMII)
|
||||
#define ARM_ETH_INTERFACE_SMII (2U) ///< Serial Media Independent Interface (SMII)
|
||||
|
||||
/**
|
||||
\brief Ethernet link speed
|
||||
*/
|
||||
#define ARM_ETH_SPEED_10M (0U) ///< 10 Mbps link speed
|
||||
#define ARM_ETH_SPEED_100M (1U) ///< 100 Mbps link speed
|
||||
#define ARM_ETH_SPEED_1G (2U) ///< 1 Gpbs link speed
|
||||
|
||||
/**
|
||||
\brief Ethernet duplex mode
|
||||
*/
|
||||
#define ARM_ETH_DUPLEX_HALF (0U) ///< Half duplex link
|
||||
#define ARM_ETH_DUPLEX_FULL (1U) ///< Full duplex link
|
||||
|
||||
/**
|
||||
\brief Ethernet link state
|
||||
*/
|
||||
typedef enum _ARM_ETH_LINK_STATE {
|
||||
ARM_ETH_LINK_DOWN, ///< Link is down
|
||||
ARM_ETH_LINK_UP ///< Link is up
|
||||
} ARM_ETH_LINK_STATE;
|
||||
|
||||
/**
|
||||
\brief Ethernet link information
|
||||
*/
|
||||
typedef struct _ARM_ETH_LINK_INFO {
|
||||
uint32_t speed : 2; ///< Link speed: 0= 10 MBit, 1= 100 MBit, 2= 1 GBit
|
||||
uint32_t duplex : 1; ///< Duplex mode: 0= Half, 1= Full
|
||||
uint32_t reserved : 29;
|
||||
} ARM_ETH_LINK_INFO;
|
||||
|
||||
/**
|
||||
\brief Ethernet MAC Address
|
||||
*/
|
||||
typedef struct _ARM_ETH_MAC_ADDR {
|
||||
uint8_t b[6]; ///< MAC Address (6 bytes), MSB first
|
||||
} ARM_ETH_MAC_ADDR;
|
||||
|
||||
#endif /* DRIVER_ETH_H_ */
|
||||
310
src/hal/alif/Alif_CMSIS/Include/Driver_ETH_MAC.h
Normal file
310
src/hal/alif/Alif_CMSIS/Include/Driver_ETH_MAC.h
Normal file
@ -0,0 +1,310 @@
|
||||
/*
|
||||
* Copyright (c) 2013-2020 ARM Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* $Date: 24. January 2020
|
||||
* $Revision: V2.2
|
||||
*
|
||||
* Project: Ethernet MAC (Media Access Control) Driver definitions
|
||||
*/
|
||||
|
||||
/* History:
|
||||
* Version 2.2
|
||||
* Removed volatile from ARM_ETH_LINK_INFO
|
||||
* Version 2.1
|
||||
* Added ARM_ETH_MAC_SLEEP Control
|
||||
* Version 2.0
|
||||
* Changed MAC Address handling:
|
||||
* moved from ARM_ETH_MAC_Initialize
|
||||
* to new functions ARM_ETH_MAC_GetMacAddress and ARM_ETH_MAC_SetMacAddress
|
||||
* Replaced ARM_ETH_MAC_SetMulticastAddr function with ARM_ETH_MAC_SetAddressFilter
|
||||
* Extended ARM_ETH_MAC_SendFrame function with flags
|
||||
* Added ARM_ETH_MAC_Control function:
|
||||
* more control options (Broadcast, Multicast, Checksum offload, VLAN, ...)
|
||||
* replaces ARM_ETH_MAC_SetMode
|
||||
* replaces ARM_ETH_MAC_EnableTx, ARM_ETH_MAC_EnableRx
|
||||
* Added optional event on transmitted frame
|
||||
* Added support for PTP (Precision Time Protocol) through new functions:
|
||||
* ARM_ETH_MAC_ControlTimer
|
||||
* ARM_ETH_MAC_GetRxFrameTime
|
||||
* ARM_ETH_MAC_GetTxFrameTime
|
||||
* Changed prefix ARM_DRV -> ARM_DRIVER
|
||||
* Changed return values of some functions to int32_t
|
||||
* Version 1.10
|
||||
* Name space prefix ARM_ added
|
||||
* Version 1.01
|
||||
* Renamed capabilities items for checksum offload
|
||||
* Version 1.00
|
||||
* Initial release
|
||||
*/
|
||||
|
||||
#ifndef DRIVER_ETH_MAC_H_
|
||||
#define DRIVER_ETH_MAC_H_
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
#include "Driver_ETH.h"
|
||||
|
||||
#define ARM_ETH_MAC_API_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(2,2) /* API version */
|
||||
|
||||
|
||||
#define _ARM_Driver_ETH_MAC_(n) Driver_ETH_MAC##n
|
||||
#define ARM_Driver_ETH_MAC_(n) _ARM_Driver_ETH_MAC_(n)
|
||||
|
||||
|
||||
/****** Ethernet MAC Control Codes *****/
|
||||
|
||||
#define ARM_ETH_MAC_CONFIGURE (0x01UL) ///< Configure MAC; arg = configuration
|
||||
#define ARM_ETH_MAC_CONTROL_TX (0x02UL) ///< Transmitter; arg: 0=disabled (default), 1=enabled
|
||||
#define ARM_ETH_MAC_CONTROL_RX (0x03UL) ///< Receiver; arg: 0=disabled (default), 1=enabled
|
||||
#define ARM_ETH_MAC_FLUSH (0x04UL) ///< Flush buffer; arg = ARM_ETH_MAC_FLUSH_...
|
||||
#define ARM_ETH_MAC_SLEEP (0x05UL) ///< Sleep mode; arg: 1=enter and wait for Magic packet, 0=exit
|
||||
#define ARM_ETH_MAC_VLAN_FILTER (0x06UL) ///< VLAN Filter for received frames; arg15..0: VLAN Tag; arg16: optional ARM_ETH_MAC_VLAN_FILTER_ID_ONLY; 0=disabled (default)
|
||||
|
||||
/*----- Ethernet MAC Configuration -----*/
|
||||
#define ARM_ETH_MAC_SPEED_Pos 0
|
||||
#define ARM_ETH_MAC_SPEED_Msk (3UL << ARM_ETH_MAC_SPEED_Pos)
|
||||
#define ARM_ETH_MAC_SPEED_10M (ARM_ETH_SPEED_10M << ARM_ETH_MAC_SPEED_Pos) ///< 10 Mbps link speed
|
||||
#define ARM_ETH_MAC_SPEED_100M (ARM_ETH_SPEED_100M << ARM_ETH_MAC_SPEED_Pos) ///< 100 Mbps link speed
|
||||
#define ARM_ETH_MAC_SPEED_1G (ARM_ETH_SPEED_1G << ARM_ETH_MAC_SPEED_Pos) ///< 1 Gpbs link speed
|
||||
#define ARM_ETH_MAC_DUPLEX_Pos 2
|
||||
#define ARM_ETH_MAC_DUPLEX_Msk (1UL << ARM_ETH_MAC_DUPLEX_Pos)
|
||||
#define ARM_ETH_MAC_DUPLEX_HALF (ARM_ETH_DUPLEX_HALF << ARM_ETH_MAC_DUPLEX_Pos) ///< Half duplex link
|
||||
#define ARM_ETH_MAC_DUPLEX_FULL (ARM_ETH_DUPLEX_FULL << ARM_ETH_MAC_DUPLEX_Pos) ///< Full duplex link
|
||||
#define ARM_ETH_MAC_LOOPBACK (1UL << 4) ///< Loop-back test mode
|
||||
#define ARM_ETH_MAC_CHECKSUM_OFFLOAD_RX (1UL << 5) ///< Receiver Checksum offload
|
||||
#define ARM_ETH_MAC_CHECKSUM_OFFLOAD_TX (1UL << 6) ///< Transmitter Checksum offload
|
||||
#define ARM_ETH_MAC_ADDRESS_BROADCAST (1UL << 7) ///< Accept frames with Broadcast address
|
||||
#define ARM_ETH_MAC_ADDRESS_MULTICAST (1UL << 8) ///< Accept frames with any Multicast address
|
||||
#define ARM_ETH_MAC_ADDRESS_ALL (1UL << 9) ///< Accept frames with any address (Promiscuous Mode)
|
||||
|
||||
/*----- Ethernet MAC Flush Flags -----*/
|
||||
#define ARM_ETH_MAC_FLUSH_RX (1UL << 0) ///< Flush Receive buffer
|
||||
#define ARM_ETH_MAC_FLUSH_TX (1UL << 1) ///< Flush Transmit buffer
|
||||
|
||||
/*----- Ethernet MAC VLAN Filter Flag -----*/
|
||||
#define ARM_ETH_MAC_VLAN_FILTER_ID_ONLY (1UL << 16) ///< Compare only the VLAN Identifier (12-bit)
|
||||
|
||||
|
||||
/****** Ethernet MAC Frame Transmit Flags *****/
|
||||
#define ARM_ETH_MAC_TX_FRAME_FRAGMENT (1UL << 0) ///< Indicate frame fragment
|
||||
#define ARM_ETH_MAC_TX_FRAME_EVENT (1UL << 1) ///< Generate event when frame is transmitted
|
||||
#define ARM_ETH_MAC_TX_FRAME_TIMESTAMP (1UL << 2) ///< Capture frame time stamp
|
||||
|
||||
|
||||
/****** Ethernet MAC Timer Control Codes *****/
|
||||
#define ARM_ETH_MAC_TIMER_GET_TIME (0x01UL) ///< Get current time
|
||||
#define ARM_ETH_MAC_TIMER_SET_TIME (0x02UL) ///< Set new time
|
||||
#define ARM_ETH_MAC_TIMER_INC_TIME (0x03UL) ///< Increment current time
|
||||
#define ARM_ETH_MAC_TIMER_DEC_TIME (0x04UL) ///< Decrement current time
|
||||
#define ARM_ETH_MAC_TIMER_SET_ALARM (0x05UL) ///< Set alarm time
|
||||
#define ARM_ETH_MAC_TIMER_ADJUST_CLOCK (0x06UL) ///< Adjust clock frequency; time->ns: correction factor * 2^31
|
||||
|
||||
|
||||
/**
|
||||
\brief Ethernet MAC Time
|
||||
*/
|
||||
typedef struct _ARM_ETH_MAC_TIME {
|
||||
uint32_t ns; ///< Nano seconds
|
||||
uint32_t sec; ///< Seconds
|
||||
} ARM_ETH_MAC_TIME;
|
||||
|
||||
|
||||
/****** Ethernet MAC Event *****/
|
||||
#define ARM_ETH_MAC_EVENT_RX_FRAME (1UL << 0) ///< Frame Received
|
||||
#define ARM_ETH_MAC_EVENT_TX_FRAME (1UL << 1) ///< Frame Transmitted
|
||||
#define ARM_ETH_MAC_EVENT_WAKEUP (1UL << 2) ///< Wake-up (on Magic Packet)
|
||||
#define ARM_ETH_MAC_EVENT_TIMER_ALARM (1UL << 3) ///< Timer Alarm
|
||||
|
||||
|
||||
// Function documentation
|
||||
/**
|
||||
\fn ARM_DRIVER_VERSION ARM_ETH_MAC_GetVersion (void)
|
||||
\brief Get driver version.
|
||||
\return \ref ARM_DRIVER_VERSION
|
||||
*/
|
||||
/**
|
||||
\fn ARM_ETH_MAC_CAPABILITIES ARM_ETH_MAC_GetCapabilities (void)
|
||||
\brief Get driver capabilities.
|
||||
\return \ref ARM_ETH_MAC_CAPABILITIES
|
||||
*/
|
||||
/**
|
||||
\fn int32_t ARM_ETH_MAC_Initialize (ARM_ETH_MAC_SignalEvent_t cb_event)
|
||||
\brief Initialize Ethernet MAC Device.
|
||||
\param[in] cb_event Pointer to \ref ARM_ETH_MAC_SignalEvent
|
||||
\return \ref execution_status
|
||||
*/
|
||||
/**
|
||||
\fn int32_t ARM_ETH_MAC_Uninitialize (void)
|
||||
\brief De-initialize Ethernet MAC Device.
|
||||
\return \ref execution_status
|
||||
*/
|
||||
/**
|
||||
\fn int32_t ARM_ETH_MAC_PowerControl (ARM_POWER_STATE state)
|
||||
\brief Control Ethernet MAC Device Power.
|
||||
\param[in] state Power state
|
||||
\return \ref execution_status
|
||||
*/
|
||||
/**
|
||||
\fn int32_t ARM_ETH_MAC_GetMacAddress (ARM_ETH_MAC_ADDR *ptr_addr)
|
||||
\brief Get Ethernet MAC Address.
|
||||
\param[in] ptr_addr Pointer to address
|
||||
\return \ref execution_status
|
||||
*/
|
||||
/**
|
||||
\fn int32_t ARM_ETH_MAC_SetMacAddress (const ARM_ETH_MAC_ADDR *ptr_addr)
|
||||
\brief Set Ethernet MAC Address.
|
||||
\param[in] ptr_addr Pointer to address
|
||||
\return \ref execution_status
|
||||
*/
|
||||
/**
|
||||
\fn int32_t ARM_ETH_MAC_SetAddressFilter (const ARM_ETH_MAC_ADDR *ptr_addr,
|
||||
uint32_t num_addr)
|
||||
\brief Configure Address Filter.
|
||||
\param[in] ptr_addr Pointer to addresses
|
||||
\param[in] num_addr Number of addresses to configure
|
||||
\return \ref execution_status
|
||||
*/
|
||||
/**
|
||||
\fn int32_t ARM_ETH_MAC_SendFrame (const uint8_t *frame, uint32_t len, uint32_t flags)
|
||||
\brief Send Ethernet frame.
|
||||
\param[in] frame Pointer to frame buffer with data to send
|
||||
\param[in] len Frame buffer length in bytes
|
||||
\param[in] flags Frame transmit flags (see ARM_ETH_MAC_TX_FRAME_...)
|
||||
\return \ref execution_status
|
||||
*/
|
||||
/**
|
||||
\fn int32_t ARM_ETH_MAC_ReadFrame (uint8_t *frame, uint32_t len)
|
||||
\brief Read data of received Ethernet frame.
|
||||
\param[in] frame Pointer to frame buffer for data to read into
|
||||
\param[in] len Frame buffer length in bytes
|
||||
\return number of data bytes read or execution status
|
||||
- value >= 0: number of data bytes read
|
||||
- value < 0: error occurred, value is execution status as defined with \ref execution_status
|
||||
*/
|
||||
/**
|
||||
\fn uint32_t ARM_ETH_MAC_GetRxFrameSize (void)
|
||||
\brief Get size of received Ethernet frame.
|
||||
\return number of bytes in received frame
|
||||
*/
|
||||
/**
|
||||
\fn int32_t ARM_ETH_MAC_GetRxFrameTime (ARM_ETH_MAC_TIME *time)
|
||||
\brief Get time of received Ethernet frame.
|
||||
\param[in] time Pointer to time structure for data to read into
|
||||
\return \ref execution_status
|
||||
*/
|
||||
/**
|
||||
\fn int32_t ARM_ETH_MAC_GetTxFrameTime (ARM_ETH_MAC_TIME *time)
|
||||
\brief Get time of transmitted Ethernet frame.
|
||||
\param[in] time Pointer to time structure for data to read into
|
||||
\return \ref execution_status
|
||||
*/
|
||||
/**
|
||||
\fn int32_t ARM_ETH_MAC_Control (uint32_t control, uint32_t arg)
|
||||
\brief Control Ethernet Interface.
|
||||
\param[in] control Operation
|
||||
\param[in] arg Argument of operation (optional)
|
||||
\return \ref execution_status
|
||||
*/
|
||||
/**
|
||||
\fn int32_t ARM_ETH_MAC_ControlTimer (uint32_t control, ARM_ETH_MAC_TIME *time)
|
||||
\brief Control Precision Timer.
|
||||
\param[in] control Operation
|
||||
\param[in] time Pointer to time structure
|
||||
\return \ref execution_status
|
||||
*/
|
||||
/**
|
||||
\fn int32_t ARM_ETH_MAC_PHY_Read (uint8_t phy_addr, uint8_t reg_addr, uint16_t *data)
|
||||
\brief Read Ethernet PHY Register through Management Interface.
|
||||
\param[in] phy_addr 5-bit device address
|
||||
\param[in] reg_addr 5-bit register address
|
||||
\param[out] data Pointer where the result is written to
|
||||
\return \ref execution_status
|
||||
*/
|
||||
/**
|
||||
\fn int32_t ARM_ETH_MAC_PHY_Write (uint8_t phy_addr, uint8_t reg_addr, uint16_t data)
|
||||
\brief Write Ethernet PHY Register through Management Interface.
|
||||
\param[in] phy_addr 5-bit device address
|
||||
\param[in] reg_addr 5-bit register address
|
||||
\param[in] data 16-bit data to write
|
||||
\return \ref execution_status
|
||||
*/
|
||||
|
||||
/**
|
||||
\fn void ARM_ETH_MAC_SignalEvent (uint32_t event)
|
||||
\brief Callback function that signals a Ethernet Event.
|
||||
\param[in] event event notification mask
|
||||
\return none
|
||||
*/
|
||||
|
||||
typedef void (*ARM_ETH_MAC_SignalEvent_t) (uint32_t event); ///< Pointer to \ref ARM_ETH_MAC_SignalEvent : Signal Ethernet Event.
|
||||
|
||||
|
||||
/**
|
||||
\brief Ethernet MAC Capabilities
|
||||
*/
|
||||
typedef struct _ARM_ETH_MAC_CAPABILITIES {
|
||||
uint32_t checksum_offload_rx_ip4 : 1; ///< 1 = IPv4 header checksum verified on receive
|
||||
uint32_t checksum_offload_rx_ip6 : 1; ///< 1 = IPv6 checksum verification supported on receive
|
||||
uint32_t checksum_offload_rx_udp : 1; ///< 1 = UDP payload checksum verified on receive
|
||||
uint32_t checksum_offload_rx_tcp : 1; ///< 1 = TCP payload checksum verified on receive
|
||||
uint32_t checksum_offload_rx_icmp : 1; ///< 1 = ICMP payload checksum verified on receive
|
||||
uint32_t checksum_offload_tx_ip4 : 1; ///< 1 = IPv4 header checksum generated on transmit
|
||||
uint32_t checksum_offload_tx_ip6 : 1; ///< 1 = IPv6 checksum generation supported on transmit
|
||||
uint32_t checksum_offload_tx_udp : 1; ///< 1 = UDP payload checksum generated on transmit
|
||||
uint32_t checksum_offload_tx_tcp : 1; ///< 1 = TCP payload checksum generated on transmit
|
||||
uint32_t checksum_offload_tx_icmp : 1; ///< 1 = ICMP payload checksum generated on transmit
|
||||
uint32_t media_interface : 2; ///< Ethernet Media Interface type
|
||||
uint32_t mac_address : 1; ///< 1 = driver provides initial valid MAC address
|
||||
uint32_t event_rx_frame : 1; ///< 1 = callback event \ref ARM_ETH_MAC_EVENT_RX_FRAME generated
|
||||
uint32_t event_tx_frame : 1; ///< 1 = callback event \ref ARM_ETH_MAC_EVENT_TX_FRAME generated
|
||||
uint32_t event_wakeup : 1; ///< 1 = wakeup event \ref ARM_ETH_MAC_EVENT_WAKEUP generated
|
||||
uint32_t precision_timer : 1; ///< 1 = Precision Timer supported
|
||||
uint32_t reserved : 15; ///< Reserved (must be zero)
|
||||
} ARM_ETH_MAC_CAPABILITIES;
|
||||
|
||||
|
||||
/**
|
||||
\brief Access structure of the Ethernet MAC Driver
|
||||
*/
|
||||
typedef struct _ARM_DRIVER_ETH_MAC {
|
||||
ARM_DRIVER_VERSION (*GetVersion) (void); ///< Pointer to \ref ARM_ETH_MAC_GetVersion : Get driver version.
|
||||
ARM_ETH_MAC_CAPABILITIES (*GetCapabilities) (void); ///< Pointer to \ref ARM_ETH_MAC_GetCapabilities : Get driver capabilities.
|
||||
int32_t (*Initialize) (ARM_ETH_MAC_SignalEvent_t cb_event); ///< Pointer to \ref ARM_ETH_MAC_Initialize : Initialize Ethernet MAC Device.
|
||||
int32_t (*Uninitialize) (void); ///< Pointer to \ref ARM_ETH_MAC_Uninitialize : De-initialize Ethernet MAC Device.
|
||||
int32_t (*PowerControl) (ARM_POWER_STATE state); ///< Pointer to \ref ARM_ETH_MAC_PowerControl : Control Ethernet MAC Device Power.
|
||||
int32_t (*GetMacAddress) ( ARM_ETH_MAC_ADDR *ptr_addr); ///< Pointer to \ref ARM_ETH_MAC_GetMacAddress : Get Ethernet MAC Address.
|
||||
int32_t (*SetMacAddress) (const ARM_ETH_MAC_ADDR *ptr_addr); ///< Pointer to \ref ARM_ETH_MAC_SetMacAddress : Set Ethernet MAC Address.
|
||||
int32_t (*SetAddressFilter)(const ARM_ETH_MAC_ADDR *ptr_addr, uint32_t num_addr); ///< Pointer to \ref ARM_ETH_MAC_SetAddressFilter : Configure Address Filter.
|
||||
int32_t (*SendFrame) (const uint8_t *frame, uint32_t len, uint32_t flags); ///< Pointer to \ref ARM_ETH_MAC_SendFrame : Send Ethernet frame.
|
||||
int32_t (*ReadFrame) ( uint8_t *frame, uint32_t len); ///< Pointer to \ref ARM_ETH_MAC_ReadFrame : Read data of received Ethernet frame.
|
||||
uint32_t (*GetRxFrameSize) (void); ///< Pointer to \ref ARM_ETH_MAC_GetRxFrameSize : Get size of received Ethernet frame.
|
||||
int32_t (*GetRxFrameTime) (ARM_ETH_MAC_TIME *time); ///< Pointer to \ref ARM_ETH_MAC_GetRxFrameTime : Get time of received Ethernet frame.
|
||||
int32_t (*GetTxFrameTime) (ARM_ETH_MAC_TIME *time); ///< Pointer to \ref ARM_ETH_MAC_GetTxFrameTime : Get time of transmitted Ethernet frame.
|
||||
int32_t (*ControlTimer) (uint32_t control, ARM_ETH_MAC_TIME *time); ///< Pointer to \ref ARM_ETH_MAC_ControlTimer : Control Precision Timer.
|
||||
int32_t (*Control) (uint32_t control, uint32_t arg); ///< Pointer to \ref ARM_ETH_MAC_Control : Control Ethernet Interface.
|
||||
int32_t (*PHY_Read) (uint8_t phy_addr, uint8_t reg_addr, uint16_t *data); ///< Pointer to \ref ARM_ETH_MAC_PHY_Read : Read Ethernet PHY Register through Management Interface.
|
||||
int32_t (*PHY_Write) (uint8_t phy_addr, uint8_t reg_addr, uint16_t data); ///< Pointer to \ref ARM_ETH_MAC_PHY_Write : Write Ethernet PHY Register through Management Interface.
|
||||
} const ARM_DRIVER_ETH_MAC;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* DRIVER_ETH_MAC_H_ */
|
||||
143
src/hal/alif/Alif_CMSIS/Include/Driver_ETH_PHY.h
Normal file
143
src/hal/alif/Alif_CMSIS/Include/Driver_ETH_PHY.h
Normal file
@ -0,0 +1,143 @@
|
||||
/*
|
||||
* Copyright (c) 2013-2020 ARM Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* $Date: 24. January 2020
|
||||
* $Revision: V2.2
|
||||
*
|
||||
* Project: Ethernet PHY (Physical Transceiver) Driver definitions
|
||||
*/
|
||||
|
||||
/* History:
|
||||
* Version 2.2
|
||||
* Removed volatile from ARM_ETH_LINK_INFO
|
||||
* Version 2.1
|
||||
* ARM_ETH_LINK_INFO made volatile
|
||||
* Version 2.0
|
||||
* changed parameter "mode" in function ARM_ETH_PHY_SetMode
|
||||
* Changed prefix ARM_DRV -> ARM_DRIVER
|
||||
* Changed return values of some functions to int32_t
|
||||
* Version 1.10
|
||||
* Namespace prefix ARM_ added
|
||||
* Version 1.00
|
||||
* Initial release
|
||||
*/
|
||||
|
||||
#ifndef DRIVER_ETH_PHY_H_
|
||||
#define DRIVER_ETH_PHY_H_
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
#include "Driver_ETH.h"
|
||||
|
||||
#define ARM_ETH_PHY_API_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(2,2) /* API version */
|
||||
|
||||
|
||||
#define _ARM_Driver_ETH_PHY_(n) Driver_ETH_PHY##n
|
||||
#define ARM_Driver_ETH_PHY_(n) _ARM_Driver_ETH_PHY_(n)
|
||||
|
||||
|
||||
/****** Ethernet PHY Mode *****/
|
||||
#define ARM_ETH_PHY_SPEED_Pos 0
|
||||
#define ARM_ETH_PHY_SPEED_Msk (3UL << ARM_ETH_PHY_SPEED_Pos)
|
||||
#define ARM_ETH_PHY_SPEED_10M (ARM_ETH_SPEED_10M << ARM_ETH_PHY_SPEED_Pos) ///< 10 Mbps link speed
|
||||
#define ARM_ETH_PHY_SPEED_100M (ARM_ETH_SPEED_100M << ARM_ETH_PHY_SPEED_Pos) ///< 100 Mbps link speed
|
||||
#define ARM_ETH_PHY_SPEED_1G (ARM_ETH_SPEED_1G << ARM_ETH_PHY_SPEED_Pos) ///< 1 Gpbs link speed
|
||||
#define ARM_ETH_PHY_DUPLEX_Pos 2
|
||||
#define ARM_ETH_PHY_DUPLEX_Msk (1UL << ARM_ETH_PHY_DUPLEX_Pos)
|
||||
#define ARM_ETH_PHY_DUPLEX_HALF (ARM_ETH_DUPLEX_HALF << ARM_ETH_PHY_DUPLEX_Pos) ///< Half duplex link
|
||||
#define ARM_ETH_PHY_DUPLEX_FULL (ARM_ETH_DUPLEX_FULL << ARM_ETH_PHY_DUPLEX_Pos) ///< Full duplex link
|
||||
#define ARM_ETH_PHY_AUTO_NEGOTIATE (1UL << 3) ///< Auto Negotiation mode
|
||||
#define ARM_ETH_PHY_LOOPBACK (1UL << 4) ///< Loop-back test mode
|
||||
#define ARM_ETH_PHY_ISOLATE (1UL << 5) ///< Isolate PHY from MII/RMII interface
|
||||
|
||||
|
||||
// Function documentation
|
||||
/**
|
||||
\fn ARM_DRIVER_VERSION ARM_ETH_PHY_GetVersion (void)
|
||||
\brief Get driver version.
|
||||
\return \ref ARM_DRIVER_VERSION
|
||||
*/
|
||||
/**
|
||||
\fn int32_t ARM_ETH_PHY_Initialize (ARM_ETH_PHY_Read_t fn_read,
|
||||
ARM_ETH_PHY_Write_t fn_write)
|
||||
\brief Initialize Ethernet PHY Device.
|
||||
\param[in] fn_read Pointer to \ref ARM_ETH_MAC_PHY_Read
|
||||
\param[in] fn_write Pointer to \ref ARM_ETH_MAC_PHY_Write
|
||||
\return \ref execution_status
|
||||
*/
|
||||
/**
|
||||
\fn int32_t ARM_ETH_PHY_Uninitialize (void)
|
||||
\brief De-initialize Ethernet PHY Device.
|
||||
\return \ref execution_status
|
||||
*/
|
||||
/**
|
||||
\fn int32_t ARM_ETH_PHY_PowerControl (ARM_POWER_STATE state)
|
||||
\brief Control Ethernet PHY Device Power.
|
||||
\param[in] state Power state
|
||||
\return \ref execution_status
|
||||
*/
|
||||
/**
|
||||
\fn int32_t ARM_ETH_PHY_SetInterface (uint32_t interface)
|
||||
\brief Set Ethernet Media Interface.
|
||||
\param[in] interface Media Interface type
|
||||
\return \ref execution_status
|
||||
*/
|
||||
/**
|
||||
\fn int32_t ARM_ETH_PHY_SetMode (uint32_t mode)
|
||||
\brief Set Ethernet PHY Device Operation mode.
|
||||
\param[in] mode Operation Mode
|
||||
\return \ref execution_status
|
||||
*/
|
||||
/**
|
||||
\fn ARM_ETH_LINK_STATE ARM_ETH_PHY_GetLinkState (void)
|
||||
\brief Get Ethernet PHY Device Link state.
|
||||
\return current link status \ref ARM_ETH_LINK_STATE
|
||||
*/
|
||||
/**
|
||||
\fn ARM_ETH_LINK_INFO ARM_ETH_PHY_GetLinkInfo (void)
|
||||
\brief Get Ethernet PHY Device Link information.
|
||||
\return current link parameters \ref ARM_ETH_LINK_INFO
|
||||
*/
|
||||
|
||||
|
||||
typedef int32_t (*ARM_ETH_PHY_Read_t) (uint8_t phy_addr, uint8_t reg_addr, uint16_t *data); ///< Pointer to \ref ARM_ETH_MAC_PHY_Read : Read Ethernet PHY Register.
|
||||
typedef int32_t (*ARM_ETH_PHY_Write_t) (uint8_t phy_addr, uint8_t reg_addr, uint16_t data); ///< Pointer to \ref ARM_ETH_MAC_PHY_Write : Write Ethernet PHY Register.
|
||||
|
||||
|
||||
/**
|
||||
\brief Access structure of the Ethernet PHY Driver
|
||||
*/
|
||||
typedef struct _ARM_DRIVER_ETH_PHY {
|
||||
ARM_DRIVER_VERSION (*GetVersion) (void); ///< Pointer to \ref ARM_ETH_PHY_GetVersion : Get driver version.
|
||||
int32_t (*Initialize) (ARM_ETH_PHY_Read_t fn_read,
|
||||
ARM_ETH_PHY_Write_t fn_write); ///< Pointer to \ref ARM_ETH_PHY_Initialize : Initialize PHY Device.
|
||||
int32_t (*Uninitialize) (void); ///< Pointer to \ref ARM_ETH_PHY_Uninitialize : De-initialize PHY Device.
|
||||
int32_t (*PowerControl) (ARM_POWER_STATE state); ///< Pointer to \ref ARM_ETH_PHY_PowerControl : Control PHY Device Power.
|
||||
int32_t (*SetInterface) (uint32_t interface); ///< Pointer to \ref ARM_ETH_PHY_SetInterface : Set Ethernet Media Interface.
|
||||
int32_t (*SetMode) (uint32_t mode); ///< Pointer to \ref ARM_ETH_PHY_SetMode : Set Ethernet PHY Device Operation mode.
|
||||
ARM_ETH_LINK_STATE (*GetLinkState) (void); ///< Pointer to \ref ARM_ETH_PHY_GetLinkState : Get Ethernet PHY Device Link state.
|
||||
ARM_ETH_LINK_INFO (*GetLinkInfo) (void); ///< Pointer to \ref ARM_ETH_PHY_GetLinkInfo : Get Ethernet PHY Device Link information.
|
||||
} const ARM_DRIVER_ETH_PHY;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* DRIVER_ETH_PHY_H_ */
|
||||
209
src/hal/alif/Alif_CMSIS/Include/Driver_Flash.h
Normal file
209
src/hal/alif/Alif_CMSIS/Include/Driver_Flash.h
Normal file
@ -0,0 +1,209 @@
|
||||
/*
|
||||
* Copyright (c) 2013-2020 ARM Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* $Date: 24. January 2020
|
||||
* $Revision: V2.3
|
||||
*
|
||||
* Project: Flash Driver definitions
|
||||
*/
|
||||
|
||||
/* History:
|
||||
* Version 2.3
|
||||
* Removed volatile from ARM_FLASH_STATUS
|
||||
* Version 2.2
|
||||
* Padding bytes added to ARM_FLASH_INFO
|
||||
* Version 2.1
|
||||
* ARM_FLASH_STATUS made volatile
|
||||
* Version 2.0
|
||||
* Renamed driver NOR -> Flash (more generic)
|
||||
* Non-blocking operation
|
||||
* Added Events, Status and Capabilities
|
||||
* Linked Flash information (GetInfo)
|
||||
* Version 1.11
|
||||
* Changed prefix ARM_DRV -> ARM_DRIVER
|
||||
* Version 1.10
|
||||
* Namespace prefix ARM_ added
|
||||
* Version 1.00
|
||||
* Initial release
|
||||
*/
|
||||
|
||||
#ifndef DRIVER_FLASH_H_
|
||||
#define DRIVER_FLASH_H_
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
#include "Driver_Common.h"
|
||||
|
||||
#define ARM_FLASH_API_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(2,3) /* API version */
|
||||
|
||||
|
||||
#define _ARM_Driver_Flash_(n) Driver_Flash##n
|
||||
#define ARM_Driver_Flash_(n) _ARM_Driver_Flash_(n)
|
||||
|
||||
|
||||
#define ARM_FLASH_SECTOR_INFO(addr,size) { (addr), (addr)+(size)-1 }
|
||||
|
||||
/**
|
||||
\brief Flash Sector information
|
||||
*/
|
||||
typedef struct _ARM_FLASH_SECTOR {
|
||||
uint32_t start; ///< Sector Start address
|
||||
uint32_t end; ///< Sector End address (start+size-1)
|
||||
} const ARM_FLASH_SECTOR;
|
||||
|
||||
/**
|
||||
\brief Flash information
|
||||
*/
|
||||
typedef struct _ARM_FLASH_INFO {
|
||||
ARM_FLASH_SECTOR *sector_info; ///< Sector layout information (NULL=Uniform sectors)
|
||||
uint32_t sector_count; ///< Number of sectors
|
||||
uint32_t sector_size; ///< Uniform sector size in bytes (0=sector_info used)
|
||||
uint32_t page_size; ///< Optimal programming page size in bytes
|
||||
uint32_t program_unit; ///< Smallest programmable unit in bytes
|
||||
uint8_t erased_value; ///< Contents of erased memory (usually 0xFF)
|
||||
uint8_t reserved[3]; ///< Reserved (must be zero)
|
||||
} const ARM_FLASH_INFO;
|
||||
|
||||
|
||||
/**
|
||||
\brief Flash Status
|
||||
*/
|
||||
typedef struct _ARM_FLASH_STATUS {
|
||||
uint32_t busy : 1; ///< Flash busy flag
|
||||
uint32_t error : 1; ///< Read/Program/Erase error flag (cleared on start of next operation)
|
||||
uint32_t reserved : 30;
|
||||
} ARM_FLASH_STATUS;
|
||||
|
||||
|
||||
/****** Flash Event *****/
|
||||
#define ARM_FLASH_EVENT_READY (1UL << 0) ///< Flash Ready
|
||||
#define ARM_FLASH_EVENT_ERROR (1UL << 1) ///< Read/Program/Erase Error
|
||||
|
||||
|
||||
// Function documentation
|
||||
/**
|
||||
\fn ARM_DRIVER_VERSION ARM_Flash_GetVersion (void)
|
||||
\brief Get driver version.
|
||||
\return \ref ARM_DRIVER_VERSION
|
||||
*/
|
||||
/**
|
||||
\fn ARM_FLASH_CAPABILITIES ARM_Flash_GetCapabilities (void)
|
||||
\brief Get driver capabilities.
|
||||
\return \ref ARM_FLASH_CAPABILITIES
|
||||
*/
|
||||
/**
|
||||
\fn int32_t ARM_Flash_Initialize (ARM_Flash_SignalEvent_t cb_event)
|
||||
\brief Initialize the Flash Interface.
|
||||
\param[in] cb_event Pointer to \ref ARM_Flash_SignalEvent
|
||||
\return \ref execution_status
|
||||
*/
|
||||
/**
|
||||
\fn int32_t ARM_Flash_Uninitialize (void)
|
||||
\brief De-initialize the Flash Interface.
|
||||
\return \ref execution_status
|
||||
*/
|
||||
/**
|
||||
\fn int32_t ARM_Flash_PowerControl (ARM_POWER_STATE state)
|
||||
\brief Control the Flash interface power.
|
||||
\param[in] state Power state
|
||||
\return \ref execution_status
|
||||
*/
|
||||
/**
|
||||
\fn int32_t ARM_Flash_ReadData (uint32_t addr, void *data, uint32_t cnt)
|
||||
\brief Read data from Flash.
|
||||
\param[in] addr Data address.
|
||||
\param[out] data Pointer to a buffer storing the data read from Flash.
|
||||
\param[in] cnt Number of data items to read.
|
||||
\return number of data items read or \ref execution_status
|
||||
*/
|
||||
/**
|
||||
\fn int32_t ARM_Flash_ProgramData (uint32_t addr, const void *data, uint32_t cnt)
|
||||
\brief Program data to Flash.
|
||||
\param[in] addr Data address.
|
||||
\param[in] data Pointer to a buffer containing the data to be programmed to Flash.
|
||||
\param[in] cnt Number of data items to program.
|
||||
\return number of data items programmed or \ref execution_status
|
||||
*/
|
||||
/**
|
||||
\fn int32_t ARM_Flash_EraseSector (uint32_t addr)
|
||||
\brief Erase Flash Sector.
|
||||
\param[in] addr Sector address
|
||||
\return \ref execution_status
|
||||
*/
|
||||
/**
|
||||
\fn int32_t ARM_Flash_EraseChip (void)
|
||||
\brief Erase complete Flash.
|
||||
Optional function for faster full chip erase.
|
||||
\return \ref execution_status
|
||||
*/
|
||||
/**
|
||||
\fn ARM_FLASH_STATUS ARM_Flash_GetStatus (void)
|
||||
\brief Get Flash status.
|
||||
\return Flash status \ref ARM_FLASH_STATUS
|
||||
*/
|
||||
/**
|
||||
\fn ARM_FLASH_INFO * ARM_Flash_GetInfo (void)
|
||||
\brief Get Flash information.
|
||||
\return Pointer to Flash information \ref ARM_FLASH_INFO
|
||||
*/
|
||||
|
||||
/**
|
||||
\fn void ARM_Flash_SignalEvent (uint32_t event)
|
||||
\brief Signal Flash event.
|
||||
\param[in] event Event notification mask
|
||||
\return none
|
||||
*/
|
||||
|
||||
typedef void (*ARM_Flash_SignalEvent_t) (uint32_t event); ///< Pointer to \ref ARM_Flash_SignalEvent : Signal Flash Event.
|
||||
|
||||
|
||||
/**
|
||||
\brief Flash Driver Capabilities.
|
||||
*/
|
||||
typedef struct _ARM_FLASH_CAPABILITIES {
|
||||
uint32_t event_ready : 1; ///< Signal Flash Ready event
|
||||
uint32_t data_width : 2; ///< Data width: 0=8-bit, 1=16-bit, 2=32-bit
|
||||
uint32_t erase_chip : 1; ///< Supports EraseChip operation
|
||||
uint32_t reserved : 28; ///< Reserved (must be zero)
|
||||
} ARM_FLASH_CAPABILITIES;
|
||||
|
||||
|
||||
/**
|
||||
\brief Access structure of the Flash Driver
|
||||
*/
|
||||
typedef struct _ARM_DRIVER_FLASH {
|
||||
ARM_DRIVER_VERSION (*GetVersion) (void); ///< Pointer to \ref ARM_Flash_GetVersion : Get driver version.
|
||||
ARM_FLASH_CAPABILITIES (*GetCapabilities)(void); ///< Pointer to \ref ARM_Flash_GetCapabilities : Get driver capabilities.
|
||||
int32_t (*Initialize) (ARM_Flash_SignalEvent_t cb_event); ///< Pointer to \ref ARM_Flash_Initialize : Initialize Flash Interface.
|
||||
int32_t (*Uninitialize) (void); ///< Pointer to \ref ARM_Flash_Uninitialize : De-initialize Flash Interface.
|
||||
int32_t (*PowerControl) (ARM_POWER_STATE state); ///< Pointer to \ref ARM_Flash_PowerControl : Control Flash Interface Power.
|
||||
int32_t (*ReadData) (uint32_t addr, void *data, uint32_t cnt); ///< Pointer to \ref ARM_Flash_ReadData : Read data from Flash.
|
||||
int32_t (*ProgramData) (uint32_t addr, const void *data, uint32_t cnt); ///< Pointer to \ref ARM_Flash_ProgramData : Program data to Flash.
|
||||
int32_t (*EraseSector) (uint32_t addr); ///< Pointer to \ref ARM_Flash_EraseSector : Erase Flash Sector.
|
||||
int32_t (*EraseChip) (void); ///< Pointer to \ref ARM_Flash_EraseChip : Erase complete Flash.
|
||||
ARM_FLASH_STATUS (*GetStatus) (void); ///< Pointer to \ref ARM_Flash_GetStatus : Get Flash status.
|
||||
ARM_FLASH_INFO * (*GetInfo) (void); ///< Pointer to \ref ARM_Flash_GetInfo : Get Flash information.
|
||||
} const ARM_DRIVER_FLASH;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* DRIVER_FLASH_H_ */
|
||||
157
src/hal/alif/Alif_CMSIS/Include/Driver_GPIO.h
Normal file
157
src/hal/alif/Alif_CMSIS/Include/Driver_GPIO.h
Normal file
@ -0,0 +1,157 @@
|
||||
/* Copyright (C) 2022 Alif Semiconductor - All Rights Reserved.
|
||||
* Use, distribution and modification of this code is permitted under the
|
||||
* terms stated in the Alif Semiconductor Software License Agreement
|
||||
*
|
||||
* You should have received a copy of the Alif Semiconductor Software
|
||||
* License Agreement with this file. If not, please write to:
|
||||
* contact@alifsemi.com, or visit: https://alifsemi.com/license
|
||||
*
|
||||
*/
|
||||
|
||||
/**************************************************************************//**
|
||||
* @file Driver_GPIO.h
|
||||
* @author Girish BN
|
||||
* @email girish.bn@alifsemi.com
|
||||
* @version V1.0.0
|
||||
* @date 21-Aug-2020
|
||||
* @brief CMSIS-Driver for GPIO.
|
||||
* @bug None.
|
||||
* @Note None
|
||||
******************************************************************************/
|
||||
#ifndef __DRIVER_GPIO_H__
|
||||
#define __DRIVER_GPIO_H__
|
||||
|
||||
#include "Driver_Common.h"
|
||||
|
||||
#define _ARM_Driver_GPIO_(n) Driver_GPIO##n
|
||||
#define ARM_Driver_GPIO_(n) _ARM_Driver_GPIO_(n)
|
||||
|
||||
#define GPIO_PIN_SOFTWARE_MODE (1)
|
||||
#define GPIO_PIN_HARDWARE_MODE (2)
|
||||
|
||||
/****** GPIO Control code : ARM_GPIO_ENABLE_INTERRUPT arg definition *****/
|
||||
#define ARM_GPIO_IRQ_POLARITY_LOW 0x00000000
|
||||
#define ARM_GPIO_IRQ_POLARITY_HIGH 0x00000001
|
||||
|
||||
#define ARM_GPIO_IRQ_EDGE_SENSITIVE_SINGLE 0x00000000
|
||||
#define ARM_GPIO_IRQ_EDGE_SENSITIVE_BOTH 0x00000002
|
||||
|
||||
#define ARM_GPIO_IRQ_SENSITIVE_LEVEL 0x00000000
|
||||
#define ARM_GPIO_IRQ_SENSITIVE_EDGE 0x00000004
|
||||
|
||||
/****** GPIO Control code : ARM_GPIO_CONFIG_FLEXIO arg definition *****/
|
||||
#define ARM_GPIO_FLEXIO_VOLT_3V3 0x0
|
||||
#define ARM_GPIO_FLEXIO_VOLT_1V8 0x1
|
||||
|
||||
/****** GPIO Control code : ARM_GPIO_CONFIG_MODE arg definition *****/
|
||||
#define ARM_GPIO_MODE_SOFTWARE 0x0
|
||||
#define ARM_GPIO_MODE_HARDWARE 0x1
|
||||
|
||||
/****** GPIO Interrupt events *****/
|
||||
#define ARM_GPIO_IRQ_EVENT_EXTERNAL (1)
|
||||
|
||||
/**< Initialization GPIO call back function declaration >*/
|
||||
typedef void (*ARM_GPIO_SignalEvent_t) (uint32_t event);
|
||||
|
||||
/**< GPIO Control codes >*/
|
||||
typedef enum _GPIO_OPERATION {
|
||||
ARM_GPIO_CONFIG_DEBOUNCE, /**<GPIO DEBOUNCE configuration operation>*/
|
||||
ARM_GPIO_ENABLE_INTERRUPT, /**<GPIO ENABLE interrupt configuration>*/
|
||||
ARM_GPIO_DISABLE_INTERRUPT, /**<GPIO DISABLE interrupt configuration>*/
|
||||
ARM_GPIO_GET_CONFIG_VALUE1, /**<GPIO GET Config reg-1 value operation>*/
|
||||
ARM_GPIO_GET_CONFIG_VALUE2, /**<GPIO GET Config reg-2 value operation>*/
|
||||
ARM_GPIO_CONFIG_FLEXIO, /**<GPIO Config voltage flexio>*/
|
||||
ARM_GPIO_CONFIG_MODE /**<GPIO Config data source mode>*/
|
||||
} GPIO_OPERATION;
|
||||
|
||||
typedef enum _GPIO_PIN_DIRECTION {
|
||||
GPIO_PIN_DIRECTION_INPUT, /**<GPIO PIN direction to input>*/
|
||||
GPIO_PIN_DIRECTION_OUTPUT, /**<GPIO PIN direction to output>*/
|
||||
} GPIO_PIN_DIRECTION;
|
||||
|
||||
typedef enum _GPIO_PIN_OUTPUT_STATE {
|
||||
GPIO_PIN_OUTPUT_STATE_LOW, /**<GPIO PIN state to LOW>*/
|
||||
GPIO_PIN_OUTPUT_STATE_HIGH, /**<GPIO PIN state to HIGH>*/
|
||||
GPIO_PIN_OUTPUT_STATE_TOGGLE, /**<GPIO PIN state Toggle>*/
|
||||
} GPIO_PIN_OUTPUT_STATE;
|
||||
|
||||
typedef enum _GPIO_PIN_STATE {
|
||||
GPIO_PIN_STATE_LOW, /**<GPIO PIN state to LOW>*/
|
||||
GPIO_PIN_STATE_HIGH, /**<GPIO PIN state to HIGH>*/
|
||||
} GPIO_PIN_STATE;
|
||||
|
||||
/**
|
||||
\fn int32_t ARM_GPIO_Initialize (uint8_t pin_no, ARM_GPIO_SignalEvent_t cb_event);
|
||||
\brief Initialize GPIO interface and register signal (callback) functions.
|
||||
\param[in] pin_no: GPIO Pin number
|
||||
\param[in] cb_event: Pointer to \ref ARM_GPIO_SignalEvent_t callback function
|
||||
\param[out] int32_t: execution_status
|
||||
|
||||
\fn int32_t ARM_GPIO_PowerControl (uint8_t pin_no, ARM_POWER_STATE state);
|
||||
\brief Control GPIO interface power.
|
||||
\param[in] pin_no: GPIO Pin number
|
||||
\param[in] state: Power state
|
||||
- ARM_POWER_OFF : power off: no operation possible
|
||||
- ARM_POWER_LOW : low power mode: retain state, detect and signal wake-up events
|
||||
- ARM_POWER_FULL: power on: full operation at maximum performance
|
||||
\param[out] int32_t: execution_status
|
||||
|
||||
\fn int32_t ARM_GPIO_SetDirection (uint32_t pin_no, GPIO_PIN_DIRECTION dir);
|
||||
\brief Function Configure the GPIO to Input or Output operation .
|
||||
\param[in] pin_no: GPIO Pin number.
|
||||
\param[in] dir: GPIO direction.
|
||||
\param[out] int32_t: execution status.
|
||||
|
||||
\fn int32_t ARM_GPIO_GetDirection (uint32_t pin_no, uint32_t *dir);
|
||||
\brief Function to get the GPIO direction .
|
||||
\param[in] pin_no: GPIO Pin number.
|
||||
\param[in] *dir: pointer to get the status of GPIO direction.
|
||||
\param[out] int32_t: execution status.
|
||||
|
||||
\fn int32_t ARM_GPIO_SetValue (uint32_t pin_no, GPIO_PIN_OUTPUT_STATE value);
|
||||
\brief Function Configure the GPIO pin Output state.
|
||||
\param[in] pin_no: GPIO Pin number.
|
||||
\param[in] value: Set the output pin status.
|
||||
\param[out] int32_t: execution status.
|
||||
|
||||
\fn int32_t ARM_GPIO_GetValue (uint32_t pin_no, uint32_t *value);
|
||||
\brief Function read the input GPIO status .
|
||||
\param[in] pin_no: GPIO Pin number.
|
||||
\param[in] *value: pointer to get the input pin status.
|
||||
\param[out] int32_t: execution status.
|
||||
|
||||
\fn int32_t ARM_GPIO_Control (uint8_t pin_no, uint32_t control_code, uint32_t *arg);
|
||||
\brief Control GPIO interface.
|
||||
\param[in] pin_no: GPIO Pin number
|
||||
\param[in] control_code: control operation
|
||||
- ARM_GPIO_CONFIG_DEBOUNCE: Perform the GPIO De-bounce configuration.
|
||||
- ARM_GPIO_ENABLE_INTERRUPT: GPIO ENABLE interrupt configuration.
|
||||
- ARM_GPIO_DISABLE_INTERRUPT: GPIO DISABLE interrupt configuration.
|
||||
- ARM_GPIO_GET_CONFIG_VALUE1: get Config reg-1 value.
|
||||
- ARM_GPIO_GET_CONFIG_VALUE2: get Config reg-2 value.
|
||||
- ARM_GPIO_CONFIG_FLEXIO: Voltage config for FLEXIO GPIO.
|
||||
- ARM_GPIO_CONFIG_MODE: GPIO config for GPIO Data Source Mode.
|
||||
\param[in] *arg: pointer to operation parameters
|
||||
\param[out] int32_t : execution_status
|
||||
|
||||
\fn int32_t ARM_GPIO_Uninitialize (uint32_t pin_no);
|
||||
\brief UnInitialize GPIO interface and register signal (callback) functions.
|
||||
\param[in] pin_no: GPIO Pin number.
|
||||
\param[out] int32_t: execution status.
|
||||
*/
|
||||
|
||||
/**
|
||||
* \brief Access structure of Gpio module.
|
||||
*/
|
||||
typedef struct _ARM_DRIVER_GPIO {
|
||||
int32_t (*Initialize) (uint8_t pin_no, ARM_GPIO_SignalEvent_t cb_event); /**< Pointer to \ref ARM_GPIO_Initialize : Initialize GPIO interface >*/
|
||||
int32_t (*PowerControl) (uint8_t pin_no, ARM_POWER_STATE state); /**< Pointer to \ref ARM_GPIO_PowerControl : Control GPIO interface power. >*/
|
||||
int32_t (*SetDirection) (uint8_t pin_no, GPIO_PIN_DIRECTION dir); /**< Pointer to \ref ARM_GPIO_SetDirection : Set GPIO direction. >*/
|
||||
int32_t (*GetDirection) (uint8_t pin_no, uint32_t *dir); /**< Pointer to \ref ARM_GPIO_GetDirection : Get GPIO direction. >*/
|
||||
int32_t (*SetValue) (uint8_t pin_no, GPIO_PIN_OUTPUT_STATE value); /**< Pointer to \ref ARM_GPIO_SetValue : Set GPIO Output pin status>*/
|
||||
int32_t (*GetValue) (uint8_t pin_no, uint32_t *value); /**< Pointer to \ref ARM_GPIO_GetValue : Get GPIO input pin status>*/
|
||||
int32_t (*Control) (uint8_t pin_no, GPIO_OPERATION control_code, uint32_t *arg); /**< Pointer to \ref ARM_GPIO_Control : Control GPIO interface.>*/
|
||||
int32_t (*Uninitialize) (uint8_t pin_no); /**< Pointer to \ref ARM_GPIO_Uninitialize : Un-initialize the GPIO Pin configuration >*/
|
||||
} ARM_DRIVER_GPIO;
|
||||
|
||||
#endif /* __DRIVER_GPIO_H__ */
|
||||
137
src/hal/alif/Alif_CMSIS/Include/Driver_HWSEM.h
Normal file
137
src/hal/alif/Alif_CMSIS/Include/Driver_HWSEM.h
Normal file
@ -0,0 +1,137 @@
|
||||
/* Copyright (C) 2022 Alif Semiconductor - All Rights Reserved.
|
||||
* Use, distribution and modification of this code is permitted under the
|
||||
* terms stated in the Alif Semiconductor Software License Agreement
|
||||
*
|
||||
* You should have received a copy of the Alif Semiconductor Software
|
||||
* License Agreement with this file. If not, please write to:
|
||||
* contact@alifsemi.com, or visit: https://alifsemi.com/license
|
||||
*
|
||||
*/
|
||||
|
||||
/**************************************************************************//**
|
||||
* @file Driver_HWSEM.h
|
||||
* @author Khushboo Singh
|
||||
* @email khushboo.singh@alifsemi.com
|
||||
* @version V1.0.0
|
||||
* @date 16-June-2022
|
||||
* @brief Header file for hardware semaphore driver.
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef DRIVER_HWSEM_H_
|
||||
#define DRIVER_HWSEM_H_
|
||||
|
||||
/* Driver Includes */
|
||||
#include "Driver_Common.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
#define ARM_HWSEM_API_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(1, 0) /* API version */
|
||||
|
||||
#define _ARM_Driver_HWSEM_(n) DRIVER_HWSEM##n
|
||||
#define ARM_Driver_HWSEM_(n) _ARM_Driver_HWSEM_(n)
|
||||
|
||||
/* HWSEM Event */
|
||||
#define HWSEM_AVAILABLE_CB_EVENT (1U << 0) ///< HWSEM Available
|
||||
|
||||
// Function Documentation
|
||||
/**
|
||||
\fn ARM_DRIVER_VERSION ARM_HWSEM_GetVersion(void)
|
||||
\brief Returns the Driver Version
|
||||
\param[in] void
|
||||
\return ARM_DRIVER_VERSION : Driver version
|
||||
*/
|
||||
|
||||
/**
|
||||
\fn ARM_HWSEM_CAPABILITIES ARM_HWSEM_GetCapabilities(void)
|
||||
\brief Returns the Driver Capabilities
|
||||
\param[in] void
|
||||
\return ARM_HWSEM_CAPABILITIES : Driver Capabilities
|
||||
*/
|
||||
|
||||
/**
|
||||
\fn int32_t ARM_HWSEM_Initialize(ARM_HWSEM_SignalEvent_t cb_event)
|
||||
\brief Initializes the driver instance with a call back function. The
|
||||
(optional) callback function will be invoked (with HWSEM_AVAILABLE_CB_EVENT)
|
||||
when the hwsem instance becomes available again after an unsuccessful
|
||||
TryLock attempt.
|
||||
\param[in] cb_event : Optional call back function provided by the user.
|
||||
\return ARM_DRIVER_OK : On successful initialization.
|
||||
\ ARM_DRIVER_ERROR_BUSY : Driver has already been initialized.
|
||||
*/
|
||||
|
||||
/**
|
||||
\fn int32_t ARM_HWSEM_Uninitialize(void)
|
||||
\brief Uninitializes the driver instance.
|
||||
\return ARM_DRIVER_OK : On success.
|
||||
\ ARM_DRIVER_ERROR : If the driver instance has not been initialized before.
|
||||
*/
|
||||
|
||||
/**
|
||||
\fn int32_t ARM_HWSEM_Lock(void)
|
||||
\brief Acquire the hw semaphore. If the semaphore is not available, spin until
|
||||
it becomes available.
|
||||
\return ARM_DRIVER_OK : If the hwsem is acquired successfully.
|
||||
\ ARM_DRIVER_ERROR : If the driver is not initialized.
|
||||
*/
|
||||
|
||||
/**
|
||||
\fn int32_t ARM_HWSEM_TryLock(void)
|
||||
\brief Try to acquire the hw semaphore. If the semaphore is not available, return an error
|
||||
code indicating the lock is busy.
|
||||
\return ARM_DRIVER_OK : If the semaphore is acquired successfully.
|
||||
\ ARM_DRIVER_ERROR_BUSY : If the semaphore is not available.
|
||||
\ ARM_DRIVER_ERROR : If the driver is not initialized.
|
||||
*/
|
||||
|
||||
/**
|
||||
\fn int32_t ARM_HWSEM_Unlock(void)
|
||||
\brief Release the hw semaphore
|
||||
\return ARM_DRIVER_OK : On a successful unlock.
|
||||
\ ARM_DRIVER_ERROR : If the driver is not initialized or the hwsem
|
||||
has not been locked before.
|
||||
*/
|
||||
|
||||
/**
|
||||
\fn int32_t ARM_HWSEM_GetCount(void)
|
||||
\brief Get the semaphore lock count.
|
||||
\return The current lock count of the semaphore instance.
|
||||
\ ARM_DRIVER_ERROR : if driver is not initialized
|
||||
*/
|
||||
|
||||
/**
|
||||
\fn void ARM_HWSEM_SignalEvent(int32_t event, uint8_t sem_id)
|
||||
\brief Callback function that signals an HW semaphore event.
|
||||
\param[in] event event notification mask
|
||||
\return none
|
||||
*/
|
||||
typedef void (*ARM_HWSEM_SignalEvent_t) (int32_t event, uint8_t sem_id);
|
||||
|
||||
/**
|
||||
\brief HW Semaphore Device Driver Capabilities.
|
||||
*/
|
||||
typedef struct _ARM_HWSEM_CAPABILITIES {
|
||||
uint32_t event_device_available : 1; ///< supports HWSEM Event Callback
|
||||
uint32_t reserved : 31; ///< Reserved (must be zero)
|
||||
} ARM_HWSEM_CAPABILITIES;
|
||||
|
||||
/**
|
||||
\brief Access structure of the Hardware Semaphore Driver
|
||||
*/
|
||||
typedef struct _ARM_DRIVER_HWSEM {
|
||||
ARM_DRIVER_VERSION (*GetVersion) (void); ///< Pointer to \ref ARM_HWSEM_GetVersion : Get driver version.
|
||||
ARM_HWSEM_CAPABILITIES (*GetCapabilities) (void); ///< Pointer to \ref ARM_HWSEM_GetCapabilities : Get driver capabilities.
|
||||
int32_t (*Initialize) (ARM_HWSEM_SignalEvent_t cb_event); ///< Pointer to \ref ARM_HWSEM_Initialize : Initialize HW semaphore Device.
|
||||
int32_t (*Uninitialize) (void); ///< Pointer to \ref ARM_HWSEM_Uninitialize : De-initialize HW Semaphore Device.
|
||||
int32_t (*Lock) (void); ///< Pointer to \ref ARM_HWSEM_Lock : Spin until the semaphore is successfully locked.
|
||||
int32_t (*TryLock) (void); ///< Pointer to \ref ARM_HWSEM_TryLock : Try to lock the semaphore.
|
||||
int32_t (*Unlock) (void); ///< Pointer to \ref ARM_HWSEM_Unlock : Unlock the semaphore.
|
||||
int32_t (*GetCount) (void); ///< Pointer to \ref ARM_HWSEM_GetCount : Get the semaphore lock count.
|
||||
}const ARM_DRIVER_HWSEM;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
#endif /* DRIVER_HWSEM_H_ */
|
||||
223
src/hal/alif/Alif_CMSIS/Include/Driver_I2C.h
Normal file
223
src/hal/alif/Alif_CMSIS/Include/Driver_I2C.h
Normal file
@ -0,0 +1,223 @@
|
||||
/*
|
||||
* Copyright (c) 2013-2020 ARM Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* $Date: 31. March 2020
|
||||
* $Revision: V2.4
|
||||
*
|
||||
* Project: I2C (Inter-Integrated Circuit) Driver definitions
|
||||
*/
|
||||
|
||||
/* History:
|
||||
* Version 2.4
|
||||
* Removed volatile from ARM_I2C_STATUS
|
||||
* Version 2.3
|
||||
* ARM_I2C_STATUS made volatile
|
||||
* Version 2.2
|
||||
* Removed function ARM_I2C_MasterTransfer in order to simplify drivers
|
||||
* and added back parameter "xfer_pending" to functions
|
||||
* ARM_I2C_MasterTransmit and ARM_I2C_MasterReceive
|
||||
* Version 2.1
|
||||
* Added function ARM_I2C_MasterTransfer and removed parameter "xfer_pending"
|
||||
* from functions ARM_I2C_MasterTransmit and ARM_I2C_MasterReceive
|
||||
* Added function ARM_I2C_GetDataCount
|
||||
* Removed flag "address_nack" from ARM_I2C_STATUS
|
||||
* Replaced events ARM_I2C_EVENT_MASTER_DONE and ARM_I2C_EVENT_SLAVE_DONE
|
||||
* with event ARM_I2C_EVENT_TRANSFER_DONE
|
||||
* Added event ARM_I2C_EVENT_TRANSFER_INCOMPLETE
|
||||
* Removed parameter "arg" from function ARM_I2C_SignalEvent
|
||||
* Version 2.0
|
||||
* New simplified driver:
|
||||
* complexity moved to upper layer (especially data handling)
|
||||
* more unified API for different communication interfaces
|
||||
* Added:
|
||||
* Slave Mode
|
||||
* Changed prefix ARM_DRV -> ARM_DRIVER
|
||||
* Version 1.10
|
||||
* Namespace prefix ARM_ added
|
||||
* Version 1.00
|
||||
* Initial release
|
||||
*/
|
||||
|
||||
#ifndef DRIVER_I2C_H_
|
||||
#define DRIVER_I2C_H_
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
#include "Driver_Common.h"
|
||||
|
||||
#define ARM_I2C_API_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(2,4) /* API version */
|
||||
|
||||
|
||||
#define _ARM_Driver_I2C_(n) Driver_I2C##n
|
||||
#define ARM_Driver_I2C_(n) _ARM_Driver_I2C_(n)
|
||||
|
||||
|
||||
/****** I2C Control Codes *****/
|
||||
|
||||
#define ARM_I2C_OWN_ADDRESS (0x01UL) ///< Set Own Slave Address; arg = address
|
||||
#define ARM_I2C_BUS_SPEED (0x02UL) ///< Set Bus Speed; arg = speed
|
||||
#define ARM_I2C_BUS_CLEAR (0x03UL) ///< Execute Bus clear: send nine clock pulses
|
||||
#define ARM_I2C_ABORT_TRANSFER (0x04UL) ///< Abort Master/Slave Transmit/Receive
|
||||
|
||||
/*----- I2C Bus Speed -----*/
|
||||
#define ARM_I2C_BUS_SPEED_STANDARD (0x01UL) ///< Standard Speed (100kHz)
|
||||
#define ARM_I2C_BUS_SPEED_FAST (0x02UL) ///< Fast Speed (400kHz)
|
||||
#define ARM_I2C_BUS_SPEED_FAST_PLUS (0x03UL) ///< Fast+ Speed ( 1MHz)
|
||||
#define ARM_I2C_BUS_SPEED_HIGH (0x04UL) ///< High Speed (3.4MHz)
|
||||
|
||||
|
||||
/****** I2C Address Flags *****/
|
||||
|
||||
#define ARM_I2C_ADDRESS_10BIT (0x0400UL) ///< 10-bit address flag
|
||||
#define ARM_I2C_ADDRESS_GC (0x8000UL) ///< General Call flag
|
||||
|
||||
|
||||
/**
|
||||
\brief I2C Status
|
||||
*/
|
||||
typedef struct _ARM_I2C_STATUS {
|
||||
uint32_t busy : 1; ///< Busy flag
|
||||
uint32_t mode : 1; ///< Mode: 0=Slave, 1=Master
|
||||
uint32_t direction : 1; ///< Direction: 0=Transmitter, 1=Receiver
|
||||
uint32_t general_call : 1; ///< General Call indication (cleared on start of next Slave operation)
|
||||
uint32_t arbitration_lost : 1; ///< Master lost arbitration (cleared on start of next Master operation)
|
||||
uint32_t bus_error : 1; ///< Bus error detected (cleared on start of next Master/Slave operation)
|
||||
uint32_t reserved : 26;
|
||||
} ARM_I2C_STATUS;
|
||||
|
||||
|
||||
/****** I2C Event *****/
|
||||
#define ARM_I2C_EVENT_TRANSFER_DONE (1UL << 0) ///< Master/Slave Transmit/Receive finished
|
||||
#define ARM_I2C_EVENT_TRANSFER_INCOMPLETE (1UL << 1) ///< Master/Slave Transmit/Receive incomplete transfer
|
||||
#define ARM_I2C_EVENT_SLAVE_TRANSMIT (1UL << 2) ///< Addressed as Slave Transmitter but transmit operation is not set.
|
||||
#define ARM_I2C_EVENT_SLAVE_RECEIVE (1UL << 3) ///< Addressed as Slave Receiver but receive operation is not set.
|
||||
#define ARM_I2C_EVENT_ADDRESS_NACK (1UL << 4) ///< Address not acknowledged from Slave
|
||||
#define ARM_I2C_EVENT_GENERAL_CALL (1UL << 5) ///< Slave addressed with general call address
|
||||
#define ARM_I2C_EVENT_ARBITRATION_LOST (1UL << 6) ///< Master lost arbitration
|
||||
#define ARM_I2C_EVENT_BUS_ERROR (1UL << 7) ///< Bus error detected (START/STOP at illegal position)
|
||||
#define ARM_I2C_EVENT_BUS_CLEAR (1UL << 8) ///< Bus clear finished
|
||||
|
||||
|
||||
// Function documentation
|
||||
/**
|
||||
\fn ARM_DRIVER_VERSION ARM_I2C_GetVersion (void)
|
||||
\brief Get driver version.
|
||||
\return \ref ARM_DRIVER_VERSION
|
||||
|
||||
\fn ARM_I2C_CAPABILITIES ARM_I2C_GetCapabilities (void)
|
||||
\brief Get driver capabilities.
|
||||
\return \ref ARM_I2C_CAPABILITIES
|
||||
|
||||
\fn int32_t ARM_I2C_Initialize (ARM_I2C_SignalEvent_t cb_event)
|
||||
\brief Initialize I2C Interface.
|
||||
\param[in] cb_event Pointer to \ref ARM_I2C_SignalEvent
|
||||
\return \ref execution_status
|
||||
|
||||
\fn int32_t ARM_I2C_Uninitialize (void)
|
||||
\brief De-initialize I2C Interface.
|
||||
\return \ref execution_status
|
||||
|
||||
\fn int32_t ARM_I2C_PowerControl (ARM_POWER_STATE state)
|
||||
\brief Control I2C Interface Power.
|
||||
\param[in] state Power state
|
||||
\return \ref execution_status
|
||||
|
||||
\fn int32_t ARM_I2C_MasterTransmit (uint32_t addr, const uint8_t *data, uint32_t num, bool xfer_pending)
|
||||
\brief Start transmitting data as I2C Master.
|
||||
\param[in] addr Slave address (7-bit or 10-bit)
|
||||
\param[in] data Pointer to buffer with data to transmit to I2C Slave
|
||||
\param[in] num Number of data bytes to transmit
|
||||
\param[in] xfer_pending Transfer operation is pending - Stop condition will not be generated
|
||||
\return \ref execution_status
|
||||
|
||||
\fn int32_t ARM_I2C_MasterReceive (uint32_t addr, uint8_t *data, uint32_t num, bool xfer_pending)
|
||||
\brief Start receiving data as I2C Master.
|
||||
\param[in] addr Slave address (7-bit or 10-bit)
|
||||
\param[out] data Pointer to buffer for data to receive from I2C Slave
|
||||
\param[in] num Number of data bytes to receive
|
||||
\param[in] xfer_pending Transfer operation is pending - Stop condition will not be generated
|
||||
\return \ref execution_status
|
||||
|
||||
\fn int32_t ARM_I2C_SlaveTransmit (const uint8_t *data, uint32_t num)
|
||||
\brief Start transmitting data as I2C Slave.
|
||||
\param[in] data Pointer to buffer with data to transmit to I2C Master
|
||||
\param[in] num Number of data bytes to transmit
|
||||
\return \ref execution_status
|
||||
|
||||
\fn int32_t ARM_I2C_SlaveReceive (uint8_t *data, uint32_t num)
|
||||
\brief Start receiving data as I2C Slave.
|
||||
\param[out] data Pointer to buffer for data to receive from I2C Master
|
||||
\param[in] num Number of data bytes to receive
|
||||
\return \ref execution_status
|
||||
|
||||
\fn int32_t ARM_I2C_GetDataCount (void)
|
||||
\brief Get transferred data count.
|
||||
\return number of data bytes transferred; -1 when Slave is not addressed by Master
|
||||
|
||||
\fn int32_t ARM_I2C_Control (uint32_t control, uint32_t arg)
|
||||
\brief Control I2C Interface.
|
||||
\param[in] control Operation
|
||||
\param[in] arg Argument of operation (optional)
|
||||
\return \ref execution_status
|
||||
|
||||
\fn ARM_I2C_STATUS ARM_I2C_GetStatus (void)
|
||||
\brief Get I2C status.
|
||||
\return I2C status \ref ARM_I2C_STATUS
|
||||
|
||||
\fn void ARM_I2C_SignalEvent (uint32_t event)
|
||||
\brief Signal I2C Events.
|
||||
\param[in] event \ref I2C_events notification mask
|
||||
*/
|
||||
|
||||
typedef void (*ARM_I2C_SignalEvent_t) (uint32_t event); ///< Pointer to \ref ARM_I2C_SignalEvent : Signal I2C Event.
|
||||
|
||||
|
||||
/**
|
||||
\brief I2C Driver Capabilities.
|
||||
*/
|
||||
typedef struct _ARM_I2C_CAPABILITIES {
|
||||
uint32_t address_10_bit : 1; ///< supports 10-bit addressing
|
||||
uint32_t reserved : 31; ///< Reserved (must be zero)
|
||||
} ARM_I2C_CAPABILITIES;
|
||||
|
||||
|
||||
/**
|
||||
\brief Access structure of the I2C Driver.
|
||||
*/
|
||||
typedef struct _ARM_DRIVER_I2C {
|
||||
ARM_DRIVER_VERSION (*GetVersion) (void); ///< Pointer to \ref ARM_I2C_GetVersion : Get driver version.
|
||||
ARM_I2C_CAPABILITIES (*GetCapabilities)(void); ///< Pointer to \ref ARM_I2C_GetCapabilities : Get driver capabilities.
|
||||
int32_t (*Initialize) (ARM_I2C_SignalEvent_t cb_event); ///< Pointer to \ref ARM_I2C_Initialize : Initialize I2C Interface.
|
||||
int32_t (*Uninitialize) (void); ///< Pointer to \ref ARM_I2C_Uninitialize : De-initialize I2C Interface.
|
||||
int32_t (*PowerControl) (ARM_POWER_STATE state); ///< Pointer to \ref ARM_I2C_PowerControl : Control I2C Interface Power.
|
||||
int32_t (*MasterTransmit) (uint32_t addr, const uint8_t *data, uint32_t num, bool xfer_pending); ///< Pointer to \ref ARM_I2C_MasterTransmit : Start transmitting data as I2C Master.
|
||||
int32_t (*MasterReceive) (uint32_t addr, uint8_t *data, uint32_t num, bool xfer_pending); ///< Pointer to \ref ARM_I2C_MasterReceive : Start receiving data as I2C Master.
|
||||
int32_t (*SlaveTransmit) ( const uint8_t *data, uint32_t num); ///< Pointer to \ref ARM_I2C_SlaveTransmit : Start transmitting data as I2C Slave.
|
||||
int32_t (*SlaveReceive) ( uint8_t *data, uint32_t num); ///< Pointer to \ref ARM_I2C_SlaveReceive : Start receiving data as I2C Slave.
|
||||
int32_t (*GetDataCount) (void); ///< Pointer to \ref ARM_I2C_GetDataCount : Get transferred data count.
|
||||
int32_t (*Control) (uint32_t control, uint32_t arg); ///< Pointer to \ref ARM_I2C_Control : Control I2C Interface.
|
||||
ARM_I2C_STATUS (*GetStatus) (void); ///< Pointer to \ref ARM_I2C_GetStatus : Get I2C status.
|
||||
} const ARM_DRIVER_I2C;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* DRIVER_I2C_H_ */
|
||||
363
src/hal/alif/Alif_CMSIS/Include/Driver_I3C.h
Normal file
363
src/hal/alif/Alif_CMSIS/Include/Driver_I3C.h
Normal file
@ -0,0 +1,363 @@
|
||||
/* Copyright (C) 2023 Alif Semiconductor - All Rights Reserved.
|
||||
* Use, distribution and modification of this code is permitted under the
|
||||
* terms stated in the Alif Semiconductor Software License Agreement
|
||||
*
|
||||
* You should have received a copy of the Alif Semiconductor Software
|
||||
* License Agreement with this file. If not, please write to:
|
||||
* contact@alifsemi.com, or visit: https://alifsemi.com/license
|
||||
*/
|
||||
|
||||
#ifndef DRIVER_I3C_H_
|
||||
#define DRIVER_I3C_H_
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
#include "Driver_Common.h"
|
||||
|
||||
#define ARM_I3C_API_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(7,2) /* API version */
|
||||
|
||||
/****** I3C Control Codes *****/
|
||||
|
||||
/* I3C Control Codes: Bus mode */
|
||||
#define I3C_MASTER_SET_BUS_MODE (1UL << 0) ///< Set bus mode to pure i3c, mixed i3c + i2c fast etc.
|
||||
#define I3C_SLAVE_SET_ADDR (1UL << 1) ///< Set slave addr and initialize slave; arg: slave address
|
||||
#define I3C_MASTER_SET_SLAVE_NACK_RETRY_COUNT (1UL << 2) ///< Set retry count to communicate to the slave that nacked the comm. Ref: Slave Nack retry count Control arguments
|
||||
#define I3C_SET_SDA_TX_HOLD_TIME (1UL << 3) ///< Set SDA Hold time(in terms of the CORE_CLK periods) for FM, FM+, SDR and DDR mode of operations; arg:<1-7>
|
||||
#define I3C_MASTER_ABORT_MESSAGE_TRANSFER (1UL << 4) ///< Abort the current Message transfer
|
||||
#define I3C_MASTER_SETUP_HOT_JOIN_ACCEPTANCE (1UL << 5) ///< Accept/Reject the Hot Join request from slaves; arg: 1-Accept, 0-Reject
|
||||
#define I3C_MASTER_SETUP_MR_ACCEPTANCE (1UL << 6) ///< Accept/Reject the Master request from slaves; arg: 1-Accept, 0-Reject
|
||||
#define I3C_SLAVE_REQUEST_IBI_BUS_MASTERSHIP (1UL << 7) ///< Request for Bus Mastership
|
||||
#define I3C_SET_DEVICE_CHARACTERISTICS (1UL << 8) ///< Set Device Characteristics (DCR) value; arg: 0-255
|
||||
#define I3C_MASTER_INIT (1UL << 9) ///< Initialises the device as master
|
||||
#define I3C_MASTER_SETUP_SIR_ACCEPTANCE (1UL << 10) ///< Accept/Reject the SIR from slaves; arg: 1-Accept, 0-Reject
|
||||
#define I3C_SLAVE_SET_IBI_SIR (1UL << 11) ///< Set IBI Slave interrupt Request
|
||||
#define I3C_SLAVE_SET_PID (1UL << 12) ///< Set MIPI I3C Slave's 48-bit Provisional ID
|
||||
|
||||
/* I3C Control Codes: Bus mode arguments */
|
||||
#define I3C_BUS_SLOW_MODE (0x00UL) ///< Slow bus mode for pure i3c devices - For slave addressing
|
||||
#define I3C_BUS_MODE_MIXED_FAST_I2C_FMP_SPEED_1_MBPS (0x01UL) ///< Mixed i3c + i2c device, Speed: Fast Mode Plus 1 MBPS
|
||||
#define I3C_BUS_MODE_MIXED_FAST_I2C_FM_SPEED_400_KBPS (0x02UL) ///< Mixed i3c + i2c device, Speed: Fast Mode 400 KBPS
|
||||
#define I3C_BUS_MODE_MIXED_SLOW_I2C_SS_SPEED_100_KBPS (0x03UL) ///< Mixed i3c + i2c device, Speed: Standard Mode 100 KBPS
|
||||
#define I3C_BUS_MODE_MIXED_LIMITED (0x04UL)
|
||||
#define I3C_BUS_NORMAL_MODE (0x05UL) ///< Normal bus mode for pure i3c devices - For actual data comm
|
||||
|
||||
/* I3C Control arguments: For Slave Nack retry count */
|
||||
#define I3C_SLAVE_NACK_RETRY_COUNT_Pos 8U
|
||||
#define I3C_SLAVE_NACK_RETRY_COUNT_Msk (3U << I3C_SLAVE_NACK_RETRY_COUNT_Pos)
|
||||
#define I3C_SLAVE_NACK_RETRY_COUNT(x) ((x << I3C_SLAVE_NACK_RETRY_COUNT_Pos) & I3C_SLAVE_NACK_RETRY_COUNT_Msk) ///< x: 0-3
|
||||
#define I3C_SLAVE_ADDR(x) (x & (0x7FU))
|
||||
|
||||
#define I3C_BUS_MAX_DEVS 0x8
|
||||
|
||||
/****** I3C Event *****/
|
||||
#define ARM_I3C_EVENT_TRANSFER_DONE (1UL << 0) ///< Event Success
|
||||
#define ARM_I3C_EVENT_TRANSFER_ERROR (1UL << 1) ///< Master and slave Transmit/Receive Error
|
||||
#define ARM_I3C_EVENT_SLV_DYN_ADDR_ASSGN (1UL << 2) ///< Slave Dynamic Address Assigned(only for Slave mode)
|
||||
#define ARM_I3C_EVENT_MESSAGE_TRANSFER_ABORT (1UL << 3) ///< Message transfer is aborted
|
||||
#define ARM_I3C_EVENT_IBI_HOT_JOIN_REQ (1UL << 4) ///< Hot-Join request received from new slave
|
||||
#define ARM_I3C_EVENT_IBI_MASTERSHIP_REQ (1UL << 5) ///< Slave requested to become bus Master
|
||||
#define ARM_I3C_EVENT_BUSOWNER_UPDATED (1UL << 6) ///< Bus Owner (Master) updated
|
||||
#define ARM_I3C_EVENT_SLAVE_CCC_UPDATED (1UL << 7) ///< Slave CCC updated by master
|
||||
#define ARM_I3C_EVENT_IBI_SLV_INTR_REQ (1UL << 8) ///< Slave requested through SIR
|
||||
#define ARM_I3C_EVENT_SLAVE_LIST (1UL << 9) ///< Targets info rcvd through DEFSLVS CCC. Applicable only for secondary masters
|
||||
|
||||
/****** I3C Error Status codes *****/
|
||||
#define ARM_I3C_LEC_NO_ERROR (0U) ///< Last error code: No error
|
||||
#define ARM_I3C_LEC_CRC_ERROR (1U) ///< Last error code: CRC error
|
||||
#define ARM_I3C_LEC_PARITY_ERROR (2U) ///< Last error code: Parity error
|
||||
#define ARM_I3C_LEC_FRAME_ERROR (3U) ///< Last error code: Frame error
|
||||
#define ARM_I3C_LEC_IBA_NACK_ERROR (4U) ///< Last error code: Nack for I3C broadcast address error
|
||||
#define ARM_I3C_LEC_ADDR_NACK_ERROR (5U) ///< Last error code: Nack for I3C slave address error
|
||||
#define ARM_I3C_LEC_BUF_UNDER_OVERFLOW_ERROR (6U) ///< Last error code: Buffer Overflow/underflow error
|
||||
#define ARM_I3C_LEC_TRANSFER_ABORT_ERROR (7U) ///< Last error code: Transfer abort error
|
||||
#define ARM_I3C_LEC_I2C_SLAVE_NACK_ERROR (8U) ///< Last error code: I2C slave NACK for current write transfer error
|
||||
#define ARM_I3C_LEC_PEC_BYTE_ERROR (9U) ///< Last error code: PEC byte check error
|
||||
#define ARM_I3C_LEC_EARLY_TERMINATION_ERROR (10U) ///< Last error code: Master early termination error
|
||||
|
||||
/* I3C CCC (Common Command Codes) related definitions */
|
||||
#define I3C_CCC_DIRECT BIT(7)
|
||||
|
||||
#define I3C_CCC_ID(id, broadcast) ((id) | ((broadcast) ? 0 : I3C_CCC_DIRECT))
|
||||
|
||||
/* Commands valid in both broadcast and unicast modes */
|
||||
#define I3C_CCC_ENEC(broadcast) I3C_CCC_ID(0x0, broadcast)
|
||||
#define I3C_CCC_DISEC(broadcast) I3C_CCC_ID(0x1, broadcast)
|
||||
#define I3C_CCC_ENTAS(as, broadcast) I3C_CCC_ID(0x2 + (as), broadcast)
|
||||
#define I3C_CCC_RSTDAA(broadcast) I3C_CCC_ID(0x6, broadcast)
|
||||
#define I3C_CCC_SETMWL(broadcast) I3C_CCC_ID(0x9, broadcast)
|
||||
#define I3C_CCC_SETMRL(broadcast) I3C_CCC_ID(0xa, broadcast)
|
||||
#define I3C_CCC_SETXTIME(broadcast) ((broadcast) ? 0x28 : 0x98)
|
||||
#define I3C_CCC_VENDOR(id, broadcast) ((id) + ((broadcast) ? 0x61 : 0xe0))
|
||||
|
||||
/* Broadcast-only commands */
|
||||
#define I3C_CCC_ENTDAA I3C_CCC_ID(0x7, true)
|
||||
#define I3C_CCC_DEFSLVS I3C_CCC_ID(0x8, true)
|
||||
#define I3C_CCC_ENTTM I3C_CCC_ID(0xb, true)
|
||||
#define I3C_CCC_ENTHDR(x) I3C_CCC_ID(0x20 + (x), true)
|
||||
#define I3C_CCC_SETAASA I3C_CCC_ID(0x29, true)
|
||||
|
||||
/* Unicast-only commands */
|
||||
#define I3C_CCC_SETDASA I3C_CCC_ID(0x7, false)
|
||||
#define I3C_CCC_SETNEWDA I3C_CCC_ID(0x8, false)
|
||||
#define I3C_CCC_GETMWL I3C_CCC_ID(0xb, false)
|
||||
#define I3C_CCC_GETMRL I3C_CCC_ID(0xc, false)
|
||||
#define I3C_CCC_GETPID I3C_CCC_ID(0xd, false)
|
||||
#define I3C_CCC_GETBCR I3C_CCC_ID(0xe, false)
|
||||
#define I3C_CCC_GETDCR I3C_CCC_ID(0xf, false)
|
||||
#define I3C_CCC_GETSTATUS I3C_CCC_ID(0x10, false)
|
||||
#define I3C_CCC_GETACCMST I3C_CCC_ID(0x11, false)
|
||||
#define I3C_CCC_SETBRGTGT I3C_CCC_ID(0x13, false)
|
||||
#define I3C_CCC_GETMXDS I3C_CCC_ID(0x14, false)
|
||||
#define I3C_CCC_GETHDRCAP I3C_CCC_ID(0x15, false)
|
||||
#define I3C_CCC_GETXTIME I3C_CCC_ID(0x19, false)
|
||||
|
||||
/* List of some Defining byte values */
|
||||
#define I3C_CCC_DEF_BYTE_SYNC_TICK 0x7F
|
||||
#define I3C_CCC_DEF_BYTE_DELAY_TIME 0xBF
|
||||
#define I3C_CCC_DEF_BYTE_ASYNC_MODE0 0xDF
|
||||
#define I3C_CCC_DEF_BYTE_ASYNC_MODE1 0xEF
|
||||
#define I3C_CCC_DEF_BYTE_ASYNC_MODE2 0xF7
|
||||
#define I3C_CCC_DEF_BYTE_ASYNC_MODE3 0xFB
|
||||
#define I3C_CCC_DEF_BYTE_ASYNC_TRIG 0xFD
|
||||
#define I3C_CCC_DEF_BYTE_TPH 0x3F
|
||||
#define I3C_CCC_DEF_BYTE_TU 0x9F
|
||||
#define I3C_CCC_DEF_BYTE_ODR 0x8F
|
||||
|
||||
/**
|
||||
\brief I3C Command
|
||||
*/
|
||||
typedef struct _ARM_I3C_CMD {
|
||||
uint8_t rw;
|
||||
uint8_t cmd_id;
|
||||
uint8_t def_byte;
|
||||
uint16_t len;
|
||||
uint8_t *data;
|
||||
uint8_t addr;
|
||||
} ARM_I3C_CMD;
|
||||
|
||||
/**
|
||||
\brief I3C Status
|
||||
*/
|
||||
typedef struct _ARM_I3C_STATUS {
|
||||
uint32_t busy :1; ///< Busy flag
|
||||
uint32_t mode :1; ///< Mode: 0=Slave, 1=Master
|
||||
uint32_t ibi_slv_addr :8; ///< Address of last IBI slave
|
||||
uint32_t last_error_code :4; ///< Last occurred error
|
||||
uint32_t defslv_cnt :8; ///< Slave count from last DEFSLVS (Applicable for Sec masters only)
|
||||
uint32_t reserved :10;
|
||||
} ARM_I3C_STATUS;
|
||||
|
||||
/**
|
||||
\brief I3C device characteristics
|
||||
*/
|
||||
typedef struct _ARM_I3C_DEV_CHAR {
|
||||
uint8_t static_addr; ///< Static address
|
||||
uint8_t bcr; ///< Bus characteristics
|
||||
uint8_t dcr; ///< Device characteristics
|
||||
uint8_t dynamic_addr; ///< Dynamic address
|
||||
} ARM_I3C_DEV_CHAR;
|
||||
|
||||
/**
|
||||
\brief I3C Device Provisional ID info
|
||||
\ The data is as per the MIPI SPEC
|
||||
*/
|
||||
typedef struct _ARM_I3C_SLV_PID {
|
||||
uint32_t dcr :12; ///< Slave DCR
|
||||
uint32_t inst_id :4; ///< Slave Instance ID
|
||||
uint32_t part_id :16; ///< Slave Part ID
|
||||
uint32_t pid_sel :1; ///< Slave PID selection; 0:Vendor fixed, 1: Random
|
||||
uint32_t mipi_mfg_id :15; ///< Slave MIPI Manufacturer ID
|
||||
uint32_t reserved :16;
|
||||
} ARM_I3C_SLV_PID;
|
||||
|
||||
/**
|
||||
\brief I3C Device Primary information
|
||||
*/
|
||||
typedef struct _ARM_I3C_DEV_PRIME_INFO {
|
||||
ARM_I3C_DEV_CHAR dev_char; ///< Device characteristics
|
||||
ARM_I3C_SLV_PID pid; ///< Device PID
|
||||
} ARM_I3C_DEV_PRIME_INFO;
|
||||
|
||||
/**
|
||||
\brief I3C Device information
|
||||
\ The data is as per the MIPI SPEC
|
||||
*/
|
||||
typedef struct _ARM_I3C_DEVICE_INFO {
|
||||
ARM_I3C_DEV_PRIME_INFO prime_info; ///< Device Primary info
|
||||
uint16_t max_read_len; ///< Maximum Read length
|
||||
uint16_t max_write_len; ///< Maximum Write length
|
||||
uint32_t max_read_turnaround; ///< Maximum Read turnaround time
|
||||
uint8_t max_read_speed; ///< Maximum Read speed
|
||||
uint8_t max_write_speed; ///< Maximum write speed
|
||||
uint16_t reserved;
|
||||
} ARM_I3C_DEVICE_INFO;
|
||||
|
||||
/**
|
||||
\brief I3C Device type
|
||||
*/
|
||||
typedef enum _ARM_I3C_DEVICE_TYPE {
|
||||
ARM_I3C_DEVICE_TYPE_I3C, ///< i3c device
|
||||
ARM_I3C_DEVICE_TYPE_I2C ///< legacy i2c device
|
||||
} ARM_I3C_DEVICE_TYPE;
|
||||
|
||||
// Function documentation
|
||||
/**
|
||||
\fn ARM_DRIVER_VERSION GetVersion (void)
|
||||
\brief Get i3c driver version.
|
||||
\return \ref ARM_DRIVER_VERSION
|
||||
|
||||
\fn ARM_I3C_CAPABILITIES GetCapabilities (void)
|
||||
\brief Get i3c driver capabilities.
|
||||
\return \ref ARM_I3C_CAPABILITIES
|
||||
|
||||
\fn ARM_I3C_STATUS GetStatus (void)
|
||||
\brief Get i3c driver status.
|
||||
\return \ref ARM_I3C_STATUS
|
||||
|
||||
\fn ARM_I3C_DEVICE_INFO GetDeviceInfo (void)
|
||||
\brief Get i3c device information.
|
||||
\return \ref ARM_I3C_DEVICE_INFO
|
||||
|
||||
\fn int32_t Initialize (ARM_I3C_SignalEvent_t cb_event)
|
||||
\brief Initialize I3C Interface.
|
||||
\param[in] cb_event Pointer to \ref ARM_I3C_SignalEvent
|
||||
\return \ref execution_status
|
||||
|
||||
\fn int32_t Uninitialize (void)
|
||||
\brief De-initialize I3C Interface.
|
||||
\return \ref execution_status
|
||||
|
||||
\fn int32_t PowerControl (ARM_POWER_STATE state)
|
||||
\brief Control I3C Interface Power.
|
||||
\param[in] state Power state
|
||||
\return \ref execution_status
|
||||
|
||||
\fn int32_t MasterTransmit (uint8_t addr, const uint8_t *data, uint16_t len)
|
||||
\brief Start transmitting data as I3C Master.
|
||||
\param[in] addr Assigned Slave Address;
|
||||
Dynamic Address for i3c, Static Address for i2c slave device
|
||||
\param[in] data Pointer to buffer with data to transmit to I3C Slave
|
||||
\param[in] len Number of data bytes to transmit
|
||||
\return \ref execution_status
|
||||
|
||||
\fn int32_t MasterReceive (uint8_t addr, uint8_t *data, uint16_t len)
|
||||
\brief Start receiving data as I3C Master.
|
||||
\param[in] addr Assigned Slave Address;
|
||||
Dynamic Address for i3c, Static Address for i2c slave device
|
||||
\param[out] data Pointer to buffer for data to receive from I3C Slave
|
||||
\param[in] len Number of data bytes to receive
|
||||
\return \ref execution_status
|
||||
|
||||
\fn int32_t SlaveTransmit(struct i3c_dev *dev, const uint8_t *data, uint16_t len)
|
||||
\brief Start transmitting data as I3C Slave.
|
||||
\param[in] data Pointer to buffer with data to transmit to I3C master
|
||||
\param[in] len Number of data bytes to transmit
|
||||
\return \ref execution_status
|
||||
|
||||
\fn int32_t SlaveReceive(struct i3c_dev *dev, uint8_t *data, uint32_t len)
|
||||
\brief Start receiving data as I3C Master.
|
||||
\param[out] data Pointer to buffer for data to receive from I3C master
|
||||
\param[in] len Number of data bytes to receive
|
||||
\return \ref execution_status
|
||||
|
||||
\fn int32_t Control (uint32_t control, uint32_t arg)
|
||||
\brief Control I3C mastaer and slave Interface.
|
||||
\param[in] control Operation
|
||||
\param[in] arg Argument of operation (optional)
|
||||
\return \ref execution_status
|
||||
|
||||
\fn int32_t MasterSendCommand (ARM_I3C_CMD *cmd)
|
||||
\brief Send a I3C Command
|
||||
\param[in] cmd The I3C_CMD to be sent
|
||||
\return \ref execution status
|
||||
|
||||
\fn int32_t MasterAssignDA (ARM_I3C_CMD *addr_cmd)
|
||||
\brief Assign dynamic address to the i3c slave using SETDASA and ENTDAA
|
||||
Note: Only required for i3c slave devices;
|
||||
i2c slave device uses static address for communication \ref I3Cx_AttachSlvDev.
|
||||
\param[in] addr_cmd Command for addressing
|
||||
\return \ref execution status
|
||||
|
||||
\fn int32_t AttachSlvDev (const ARM_I3C_DEVICE_TYPE dev_type,
|
||||
const uint8_t addr)
|
||||
\brief Attach i3c/i2c device to the i3c bus.
|
||||
\param[in] dev_type Device type - i3c/i2c
|
||||
\param[in] addr dynamic addr of i3c device/static addr of i2c device
|
||||
\return \ref execution_status
|
||||
|
||||
\fn int32_t Detachdev (uint8_t addr)
|
||||
\brief Detach already attached i2c/i3c device from the i3c bus.
|
||||
\param[in] addr static address of already attached i2c device
|
||||
OR
|
||||
dynamic address of already attached i3c device
|
||||
\return \ref execution_status
|
||||
|
||||
\fn int32_t GetSlaveList (uint8_t *addr_list, uint8_t *count)
|
||||
\brief Gets list of slaves already attached
|
||||
\param[in] addr_list Address list of i3c slavesus
|
||||
\param[in] count Count of i3c slaves
|
||||
\return \ref execution_status
|
||||
|
||||
\fn int32_t GetSlaveDynAddr (const uint8_t static_addr, uint8_t *dynamic_addr)
|
||||
\brief Detach already attached i2c/i3c device from the i3c bus.
|
||||
\param[in] static_addr static address of already attached i3c device
|
||||
\param[in] dynamic_addr dynamic address of already attached i3c device
|
||||
\return \ref execution_status
|
||||
|
||||
\fn int32_t GetSlvsInfo (void* data, const uint8_t value)
|
||||
\brief Gets the received Slaves information
|
||||
\param[in] data ARM_I3C_DEV_CHAR/ARM_I3C_DEV_PRIME_INFO information store
|
||||
\param[in] value Either Slaves count or Slave address
|
||||
\return \ref execution_status
|
||||
*/
|
||||
|
||||
typedef void (*ARM_I3C_SignalEvent_t) (uint32_t event); ///< Pointer to \ref I3C_SignalEvent : Signal I3C Event.
|
||||
|
||||
/**
|
||||
\brief I3C Driver Capabilities.
|
||||
*/
|
||||
typedef struct _ARM_I3C_CAPABILITIES {
|
||||
uint32_t legacy_i2c_dev : 1; ///< legacy i2c device support
|
||||
uint32_t adaptive_mode : 1; ///< Slave I2C/I3C Adaptive mode support during boot up phase
|
||||
uint32_t ibi : 1; ///< In-Band Interrupts support
|
||||
uint32_t ibi_payload : 1; ///< In-Band Interrupt with Payload support
|
||||
uint32_t sec_master : 1; ///< Secondary Master Configuration support
|
||||
uint32_t hdr_ddr0 : 1; ///< HDR DDR0 mode support
|
||||
uint32_t hdr_tsp : 1; ///< HDR Ternary Symbol Pure-Bus mode support
|
||||
uint32_t hdr_tsl : 1; ///< HDR Ternary Symbol Legacy-Inclusive-Bus mode support
|
||||
uint32_t reserved : 24; ///< Reserved (must be zero)
|
||||
} ARM_I3C_CAPABILITIES;
|
||||
|
||||
/**
|
||||
\brief Access structure of the I3C Driver.
|
||||
*/
|
||||
typedef struct _ARM_DRIVER_I3C {
|
||||
ARM_DRIVER_VERSION (*GetVersion) (void); ///< Pointer to \ref GetVersion : Get I3C driver version.
|
||||
ARM_I3C_CAPABILITIES (*GetCapabilities) (void); ///< Pointer to \ref GetCapabilities : Get I3C driver capabilities.
|
||||
ARM_I3C_STATUS (*GetStatus) (void); ///< Pointer to \ref GetStatus : Get I3C driver status.
|
||||
ARM_I3C_DEVICE_INFO (*GetDeviceInfo) (void); ///< Pointer to \ref GetDeviceInfo : Get I3C device information.
|
||||
int32_t (*Initialize) (ARM_I3C_SignalEvent_t cb_event); ///< Pointer to \ref Initialize : Initialize I3C Interface.
|
||||
int32_t (*Uninitialize) (void); ///< Pointer to \ref Uninitialize : De-initialize I3C Interface.
|
||||
int32_t (*PowerControl) (ARM_POWER_STATE state); ///< Pointer to \ref PowerControl : Control I3C Interface Power.
|
||||
int32_t (*MasterTransmit) (uint8_t addr, const uint8_t *data, uint16_t len); ///< Pointer to \ref MasterTransmit : Start transmitting data as I3C Master.
|
||||
int32_t (*MasterReceive) (uint8_t addr, uint8_t *data, uint16_t len); ///< Pointer to \ref MasterReceive : Start receiving data as I3C Master.
|
||||
int32_t (*SlaveTransmit) (const uint8_t *data, uint16_t len); ///< Pointer to \ref MasterTransmit : Start transmitting data as I3C Slave.
|
||||
int32_t (*SlaveReceive) (uint8_t *data, uint16_t len); ///< Pointer to \ref SlaveReceive : Start receiving data as I3C Slave.
|
||||
int32_t (*Control) (uint32_t control, uint32_t arg); ///< Pointer to \ref Control : Control I3C Master and slave Interface.
|
||||
int32_t (*MasterSendCommand) (ARM_I3C_CMD *cmd); ///< Pointer to \ref MasterSendCommand : Send I3C CCC
|
||||
int32_t (*MasterAssignDA) (ARM_I3C_CMD *addr_cmd); ///< Pointer to \ref MasterAssignDA : Assign I3C Dynamic Address
|
||||
int32_t (*AttachSlvDev) (ARM_I3C_DEVICE_TYPE dev_type, const uint8_t addr); ///< Pointer to \ref AttachSlvDev : Attach i3c/i2c slave device to the i3c bus.
|
||||
int32_t (*Detachdev) (uint8_t addr); ///< Pointer to \ref Detachdev : Detach already attached i2c/i3c device from the i3c bus.
|
||||
int32_t (*GetSlaveList) (uint8_t *addr_list, uint8_t *count); ///< Pointer to \ref GetSlaveList : Fetch list of slaves attached to the bus.
|
||||
int32_t (*GetSlaveDynAddr) (const uint8_t static_addr, uint8_t *dynamic_addr); ///< Pointer to \ref GetSlaveDynAddr : Fetch dynamic address of slave given with static address.
|
||||
int32_t (*GetSlvsInfo) (void* data, const uint8_t value); ///< Pointer to \ref GetSlvsInfo : Fetches slave's characteristics.
|
||||
} const ARM_DRIVER_I3C;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* DRIVER_I3C_H_ */
|
||||
88
src/hal/alif/Alif_CMSIS/Include/Driver_LPTIMER.h
Normal file
88
src/hal/alif/Alif_CMSIS/Include/Driver_LPTIMER.h
Normal file
@ -0,0 +1,88 @@
|
||||
/* Copyright (C) 2022 Alif Semiconductor - All Rights Reserved.
|
||||
* Use, distribution and modification of this code is permitted under the
|
||||
* terms stated in the Alif Semiconductor Software License Agreement
|
||||
*
|
||||
* You should have received a copy of the Alif Semiconductor Software
|
||||
* License Agreement with this file. If not, please write to:
|
||||
* contact@alifsemi.com, or visit: https://alifsemi.com/license
|
||||
*
|
||||
*/
|
||||
|
||||
/**************************************************************************//**
|
||||
* @file Driver_LPTIMER.h
|
||||
* @author Girish BN
|
||||
* @email girish.bn@alifsemi.com
|
||||
* @version V1.0.0
|
||||
* @date 21-Aug-2020
|
||||
* @brief CMSIS-Driver for LPTIMER.
|
||||
* @bug None.
|
||||
* @Note None
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef __DRIVER_LPTIMER_H__
|
||||
#define __DRIVER_LPTIMER_H__
|
||||
|
||||
#include "Driver_Common.h"
|
||||
|
||||
typedef void (*ARM_LPTIMER_SignalEvent_t) (uint8_t event); /**< Initialization LPTIMER call back function declaration >*/
|
||||
|
||||
/****** LPTIMER Events *****/
|
||||
#define ARM_LPTIMER_EVENT_UNDERFLOW (1) /**< LPTIMER Under flow event>*/
|
||||
|
||||
/****** LPTIMER Control Codes *****/
|
||||
#define ARM_LPTIMER_SET_COUNT1 (1) /**< Set Count; arg = pointer of count var>*/
|
||||
#define ARM_LPTIMER_SET_COUNT2 (2) /**< Set Count; arg = pointer of count var>*/
|
||||
#define ARM_LPTIMER_GET_COUNT (3) /**< get Count; arg = pointer of count var>*/
|
||||
|
||||
/**
|
||||
\fn int32_t ARM_LPTIMER_Initialize (uint8_t channel, ARM_LPTIMER_CBEvent CB_event)
|
||||
\brief Initialize LPTIMER interface and register signal(call back) functions.
|
||||
\param[in] channel :LPTIMER channel number (ie. 0,1,2,3.... should be less than RTE_LPTIMER_MAX_CHANNEL)
|
||||
\param[in] CB_event: call back function.
|
||||
\param[out] int32_t : execution_status.
|
||||
|
||||
\fn int32_t ARM_LPTIMER_PowerControl (uint8_t channel, ARM_POWER_STATE state);
|
||||
\brief Control LPTIMER channel interface power.
|
||||
\param[in] channel :LPTIMER channel number (ie. 0,1,2,3.... should be less than RTE_LPTIMER_MAX_CHANNEL)
|
||||
\param[in] state : Power state
|
||||
- \ref ARM_POWER_OFF : power off: no operation possible
|
||||
- \ref ARM_POWER_LOW : low power mode: retain state, detect and signal wake-up events
|
||||
- \ref ARM_POWER_FULL : power on: full operation at maximum performance
|
||||
\param[out] int32_t : execution_status.
|
||||
|
||||
\fn int32_t ARM_LPTIMER_Control (uint8_t channel, uint32_t control, uint32_t arg)
|
||||
\brief Control LPTIMER interface.
|
||||
\param[in] channel :LPTIMER channel number (ie. 0,1,2,3.... should be less than RTE_LPTIMER_MAX_CHANNEL)
|
||||
\param[in] control_code : Operation
|
||||
-ARM_LPTIMER_CONTROL_CODE_SET_COUNT1 LPTIMER channel setting the count1 for operation
|
||||
-ARM_LPTIMER_CONTROL_CODE_SET_COUNT2 LPTIMER Channel setting the count2 for operation
|
||||
-ARM_LPTIMER_CONTROL_CODE_GET_COUNT LPTIMER Channel get the count
|
||||
\param[in] arg : Argument of operation.
|
||||
\param[out] int32_t : execution_status
|
||||
|
||||
\fn int32_t ARM_LPTIMER_Start (uint8_t channel);
|
||||
\brief Start the UTMER Channel counting.
|
||||
\param[in] channel :LPTIMER channel number (ie. 0,1,2,3.... should be less than RTE_LPTIMER_MAX_CHANNEL)
|
||||
\param[out] int32_t : execution_status.
|
||||
|
||||
\fn int32_t ARM_LPTIMER_Stop (uint8_t channel);
|
||||
\brief Stop the LPTMER Channel running count.
|
||||
\param[in] channel :LPTIMER channel number (ie. 0,1,2,3.... should be less than RTE_LPTIMER_MAX_CHANNEL)
|
||||
\param[out] int32_t : execution_status.
|
||||
|
||||
\fn int32_t ARM_LPTIMER_Uninitialize (uint8_t channel);
|
||||
\brief Un-initialize the named channel configuration
|
||||
\param[in] channel :LPTIMER channel number (ie. 0,1,2,3.... should be less than RTE_LPTIMER_MAX_CHANNEL)
|
||||
\param[out] int32_t : execution_status.
|
||||
*/
|
||||
|
||||
typedef struct _ARM_DRIVER_LPTIMER{
|
||||
int32_t (*Initialize) (uint8_t channel, ARM_LPTIMER_SignalEvent_t cb_event); /**< Pointer to \ref ARM_LPTIMER_Initialize : Initialize the LPTIMER Interface>*/
|
||||
int32_t (*PowerControl) (uint8_t channel, ARM_POWER_STATE state); /**< Pointer to \ref ARM_LPTIMER_PowerControl : Control LPIMER interface power>*/
|
||||
int32_t (*Control) (uint8_t channel, uint32_t control_code, void *arg); /**< Pointer to \ref ARM_LPTIMER_Control : Control LPTIMER interface.>*/
|
||||
int32_t (*Start) (uint8_t channel); /**< Pointer to \ref ARM_LPTIMER_Start : global starts the LPTIMER channel>*/
|
||||
int32_t (*Stop) (uint8_t channel); /**< Pointer to \ref ARM_LPTIMER_Stop : global stops the LPTIMER channel>*/
|
||||
int32_t (*Uninitialize) (uint8_t channel); /**< Pointer to \ref ARM_LPTIMER_Uninitialize : Uninitialized the LPTIMER Interface>*/
|
||||
} ARM_DRIVER_LPTIMER;
|
||||
|
||||
#endif /*< __DRIVER_LPTIMER_H__>*/
|
||||
115
src/hal/alif/Alif_CMSIS/Include/Driver_MIPI_CSI2.h
Normal file
115
src/hal/alif/Alif_CMSIS/Include/Driver_MIPI_CSI2.h
Normal file
@ -0,0 +1,115 @@
|
||||
/* Copyright (C) 2022 Alif Semiconductor - All Rights Reserved.
|
||||
* Use, distribution and modification of this code is permitted under the
|
||||
* terms stated in the Alif Semiconductor Software License Agreement
|
||||
*
|
||||
* You should have received a copy of the Alif Semiconductor Software
|
||||
* License Agreement with this file. If not, please write to:
|
||||
* contact@alifsemi.com, or visit: https://alifsemi.com/license
|
||||
*
|
||||
*/
|
||||
/**************************************************************************//**
|
||||
* @file Driver_MIPI_CSI2.h
|
||||
* @author Prasanna Ravi
|
||||
* @email prasanna.ravi@alifsemi.com
|
||||
* @version V1.0.0
|
||||
* @date 24-March-2022
|
||||
* @brief Driver Specific Header file for MIPI CSI2 Driver.
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef DRIVER_MIPI_CSI2_H_
|
||||
#define DRIVER_MIPI_CSI2_H_
|
||||
|
||||
#include "Driver_Common.h"
|
||||
|
||||
#define ARM_MIPI_CSI2_API_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(1,0) /* API version */
|
||||
|
||||
/**
|
||||
\brief MIPI CSI2 event types
|
||||
*/
|
||||
#define CSI2_EVENT_PHY_FATAL (1U << 0) ///< PHY Packet discarded event
|
||||
#define CSI2_EVENT_PKT_FATAL (1U << 1) ///< Packet fatal
|
||||
#define CSI2_EVENT_PHY (1U << 2) ///< PHY events
|
||||
#define CSI2_EVENT_LINE (1U << 3) ///< Line events
|
||||
#define CSI2_EVENT_IPI_FATAL (1U << 4) ///< Image pixel interface events
|
||||
#define CSI2_EVENT_BNDRY_FRAME_FATAL (1U << 5) ///< Boundary frame events
|
||||
#define CSI2_EVENT_SEQ_FRAME_FATAL (1U << 6) ///< Frame sequance events
|
||||
#define CSI2_EVENT_CRC_FRAME_FATAL (1U << 7) ///< CRC event
|
||||
#define CSI2_EVENT_PLD_CRC_FATAL (1U << 8) ///< Payload CRC event
|
||||
#define CSI2_EVENT_DATA_ID (1u << 9) ///< Pixel Data ID event
|
||||
#define CSI2_EVENT_ECC_CORRECT (1U << 10) ///< ECC event
|
||||
// Function documentation
|
||||
/*
|
||||
\fn ARM_DRIVER_VERSION MIPI_CSI2_GetVersion (void)
|
||||
\brief Get MIPI CSI2 driver version.
|
||||
\return \ref ARM_DRIVER_VERSION
|
||||
|
||||
\fn ARM_MIPI_CSI2_CAPABILITIES MIPI_CSI2_GetCapabilities (void)
|
||||
\brief Get MIPI CSI2 driver capabilities.
|
||||
\return \ref ARM_MIPI_DPHY_CAPABILITIES
|
||||
|
||||
\fn int32_t MIPI_CSI2_Initialize (ARM_MIPI_CSI2_SignalEvent_t cb_event)
|
||||
\brief Initialize MIPI CSI2 Interface.
|
||||
\param[in] cb_event Pointer to ARM_MIPI_CSI2_SignalEvent_t
|
||||
\return \ref execution_status
|
||||
|
||||
\fn int32_t MIPI_CSI2_Uninitialize (void)
|
||||
\brief uninitialize MIPI CSI2 Interface.
|
||||
\return \ref execution_status
|
||||
|
||||
\fn int32_t MIPI_CSI2_PowerControl (ARM_POWER_STATE state)
|
||||
\brief Control CSI2 Interface Power.
|
||||
\param[in] state Power state
|
||||
\return \ref execution_status
|
||||
|
||||
\fn int32_t MIPI_CSI2_ConfigureHost (uint32_t int_event)
|
||||
\brief Configure CSI2 Host Interface.
|
||||
\param[in] int_event interrupt event to be enabled.
|
||||
\return \ref execution_status
|
||||
|
||||
\fn int32_t MIPI_CSI2_ConfigureIPI (void)
|
||||
\brief Configure CSI2 IPI Interface.
|
||||
\return \ref execution_status
|
||||
|
||||
\fn int32_t MIPI_CSI2_StartPHY (void)
|
||||
\brief Configure CSI2 PHY Interface.
|
||||
\return \ref execution_status
|
||||
|
||||
\fn int32_t MIPI_CSI2_StartIPI(void)
|
||||
\brief Enable CSI2 IPI Interface.
|
||||
\return \ref execution_status
|
||||
|
||||
\fn int32_t MIPI_CSI2_StopIPI(void)
|
||||
\brief Disable CSI2 IPI Interface.
|
||||
\return \ref execution_status
|
||||
|
||||
\fn void ARM_MIPI_CSI2_Event_Callback (uint32_t int_event)
|
||||
\brief Signal MIPI CSI2 Events.
|
||||
\param[in] int_event \ref MIPI CSI2 event types.
|
||||
\return none.
|
||||
*/
|
||||
|
||||
/** \brief MIPI CSI2 signal event */
|
||||
typedef void (*ARM_MIPI_CSI2_SignalEvent_t) (uint32_t int_event); ///< Pointer to \ref ARM_MIPI_CSI2_SignalEvent : Signal MIPI CSI2 Event.
|
||||
|
||||
/** \brief MIPI CSI2 driver capabilities */
|
||||
typedef struct {
|
||||
uint32_t reentrant_operation :1; ///< Support for reentrant calls
|
||||
uint32_t ipi_interface :1; ///< Support Image Pixel Interface
|
||||
uint32_t idi_interface :1; ///< Support Image Data Interface
|
||||
uint32_t reserved :29; ///< Reserved (must be zero)
|
||||
}ARM_MIPI_CSI2_CAPABILITIES;
|
||||
|
||||
/** \brief Access structure of the MIPI CSI2 Driver */
|
||||
typedef struct {
|
||||
ARM_DRIVER_VERSION (*GetVersion) (void); ///< Pointer to \ref MIPI_CSI2_GetVersion : Get driver version.
|
||||
ARM_MIPI_CSI2_CAPABILITIES (*GetCapabilities) (void); ///< Pointer to \ref MIPI_CSI2_GetCapabilities : Get MIPI CSI2 driver capabilities.
|
||||
int32_t (*Initialize) (ARM_MIPI_CSI2_SignalEvent_t cb_event); ///< Pointer to \ref MIPI_CSI2_Initialize : Initialize MIPI CSI2 Interface.
|
||||
int32_t (*Uninitialize) (void); ///< Pointer to \ref MIPI_CSI2_Uninitialize : Uninitialize MIPI CSI2 Interface.
|
||||
int32_t (*PowerControl) (ARM_POWER_STATE state); ///< Pointer to \ref MIPI_CSI2_PowerControl : Control CSI2 Interface Power.
|
||||
int32_t (*ConfigureHost) (uint32_t int_event); ///< Pointer to \ref MIPI_CSI2_ConfigureHost : Configure CSI2 Host Interface.
|
||||
int32_t (*ConfigureIPI) (void); ///< Pointer to \ref MIPI_CSI2_StartPHY : Configure CSI2 PHY Interface.
|
||||
int32_t (*StartIPI) (void); ///< Pointer to \ref MIPI_CSI2_StartIPI : Enable CSI2 IPI Interface.Get driver version.
|
||||
int32_t (*StopIPI) (void); ///< Pointer to \ref MIPI_CSI2_StartIPI : Disable CSI2 IPI Interface.
|
||||
}ARM_DRIVER_MIPI_CSI2;
|
||||
|
||||
#endif /* DRIVER_MIPI_CSI2_H_ */
|
||||
121
src/hal/alif/Alif_CMSIS/Include/Driver_MIPI_DSI.h
Normal file
121
src/hal/alif/Alif_CMSIS/Include/Driver_MIPI_DSI.h
Normal file
@ -0,0 +1,121 @@
|
||||
/* Copyright (C) 2022 Alif Semiconductor - All Rights Reserved.
|
||||
* Use, distribution and modification of this code is permitted under the
|
||||
* terms stated in the Alif Semiconductor Software License Agreement
|
||||
*
|
||||
* You should have received a copy of the Alif Semiconductor Software
|
||||
* License Agreement with this file. If not, please write to:
|
||||
* contact@alifsemi.com, or visit: https://alifsemi.com/license
|
||||
*
|
||||
*/
|
||||
|
||||
/**************************************************************************//**
|
||||
* @file Driver_MIPI_DSI.h
|
||||
* @author Prasanna Ravi
|
||||
* @email prasanna.ravi@alifsemi.com
|
||||
* @version V1.0.0
|
||||
* @date 24-March-2022
|
||||
* @brief Driver Specific Header file for MIPI DSI Driver.
|
||||
******************************************************************************/
|
||||
#ifndef DRIVER_MIPI_DSI_H_
|
||||
#define DRIVER_MIPI_DSI_H_
|
||||
|
||||
#include "Driver_Common.h"
|
||||
|
||||
#define ARM_MIPI_DSI_API_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(1,0) /* API version */
|
||||
|
||||
/**
|
||||
\brief MIPI DSI event types
|
||||
*/
|
||||
#define DSI_PHY_ERROR_EVENT (1U << 0) ///< PHY error event
|
||||
#define DSI_ACK_ERROR_EVENT (1U << 1) ///< Acknowledge error report event
|
||||
#define DSI_PKT_ERROR_EVENT (1U << 2) ///< Packet error event
|
||||
#define DSI_DPI_ERROR_EVENT (1U << 3) ///< DPI error event
|
||||
|
||||
// Function documentation
|
||||
/**
|
||||
\fn ARM_DRIVER_VERSION ARM_MIPI_DSI_GetVersion (void)
|
||||
\brief Get driver version.
|
||||
\return \ref ARM_DRIVER_VERSION.
|
||||
|
||||
\fn ARM_MIPI_DSI_CAPABILITIES MIPI_DSI_GetCapabilities (void)
|
||||
\brief Get MIPI DSI driver capabilities.
|
||||
\return \ref ARM_MIPI_DPHY_CAPABILITIES.
|
||||
|
||||
\fn int32_t ARM_MIPI_DSI_Initialize (uint32_t frequency)
|
||||
\brief Initialize MIPI DSI Interface.
|
||||
\param[in] cb_event Pointer to ARM_MIPI_DSI_SignalEvent_t.
|
||||
\param[in] frequency to configure DPHY PLL.
|
||||
\return \ref execution_status.
|
||||
|
||||
\fn int32_t ARM_MIPI_DSI_Uninitialize (void)
|
||||
\brief uninitialize MIPI DSI Interface.
|
||||
\return \ref execution_status.
|
||||
|
||||
\fn int32_t ARM_MIPI_DSI_PowerControl (ARM_POWER_STATE state)
|
||||
\brief Control MIPI DSI Interface Power.
|
||||
\param[in] state Power state.
|
||||
\return \ref execution_status.
|
||||
|
||||
\fn int32_t ARM_MIPI_DSI_Control (ARM_MIPI_DSI_CONTROL control)
|
||||
\brief Control DSI Interface.
|
||||
\param[in] control DSI host and DPI Configuration.
|
||||
\param[in] arg Argument of operation (optional)
|
||||
\return \ref execution_status
|
||||
|
||||
\fn int32_t ARM_MIPI_DSI_StartCommandMode (void)
|
||||
\brief Configure DSI to start Command mode.
|
||||
\return \ref execution_status.
|
||||
|
||||
\fn int32_t ARM_MIPI_DSI_StartVideoMode (void)
|
||||
\brief Configure DSI to start Video mode.
|
||||
\return \ref execution_status.
|
||||
|
||||
\fn int32_t ARM_MIPI_DSI_Stop (void)
|
||||
\brief Shutdown DSI.
|
||||
\return \ref execution_status
|
||||
|
||||
\fn void ARM_MIPI_DSI_SignalEvent (uint32_t int_event)
|
||||
\brief Signal MIPI DSI Events.
|
||||
\param[in] int_event \ref MIPI DSI event types.
|
||||
\return none.
|
||||
*/
|
||||
|
||||
/**
|
||||
\brief DSI Configuration control
|
||||
*/
|
||||
typedef enum _ARM_MIPI_DSI_CONTROL {
|
||||
DSI_CONFIGURE_HOST,
|
||||
DSI_CONFIGURE_DPI,
|
||||
} ARM_MIPI_DSI_CONTROL;
|
||||
|
||||
/**
|
||||
\brief MIPI DSI signal event.
|
||||
*/
|
||||
typedef void (*ARM_MIPI_DSI_SignalEvent_t) (uint32_t int_event); ///< Pointer to \ref ARM_MIPI_DSI_SignalEvent : Signal MIPI DSI Event.
|
||||
|
||||
/**
|
||||
\brief MIPI DSI driver capabilities.
|
||||
*/
|
||||
typedef struct {
|
||||
uint32_t reentrant_operation :1; ///< Support for reentrant calls
|
||||
uint32_t dpi_interface :1; ///< Support video mode Interface
|
||||
uint32_t dbi_interface :1; ///< Support command mode Interface
|
||||
uint32_t reserved :29; ///< Reserved (must be zero)
|
||||
}ARM_MIPI_DSI_CAPABILITIES;
|
||||
|
||||
/**
|
||||
\brief Access structure of the MIPI DSI Driver.
|
||||
*/
|
||||
typedef struct {
|
||||
ARM_DRIVER_VERSION (*GetVersion) (void); ///< Pointer to \ref ARM_MIPI_DSI_GetVersion : Get driver version.
|
||||
ARM_MIPI_DSI_CAPABILITIES (*GetCapabilities) (void); ///< Pointer to \ref ARM_MIPI_DSI_GetCapabilities : Get MIPI DSI driver capabilities.
|
||||
int32_t (*Initialize) (ARM_MIPI_DSI_SignalEvent_t cb_event); ///< Pointer to \ref ARM_MIPI_DSI_Initialize : Initialize MIPI DSI Interface.
|
||||
int32_t (*Uninitialize) (void); ///< Pointer to \ref ARM_MIPI_DSI_Uninitialize : Uninitialize MIPI DSI Interface.
|
||||
int32_t (*PowerControl) (ARM_POWER_STATE state); ///< Pointer to \ref ARM_MIPI_DSI_PowerControl : Control MIPI DSI Interface Power.
|
||||
int32_t (*Control) (ARM_MIPI_DSI_CONTROL control, uint32_t arg); ///< Pointer to \ref ARM_MIPI_DSI_Control: Control DSI Interface.
|
||||
int32_t (*StartCommandMode)(void); ///< Pointer to \ref ARM_MIPI_DSI_StartCommandMode : Configure DSI to start Command mode.
|
||||
int32_t (*StartVideoMode) (void); ///< Pointer to \ref ARM_MIPI_DSI_StartVideoMode : Configure DSI to start Video mode.
|
||||
int32_t (*Stop) (void); ///< Pointer to \ref ARM_MIPI_DSI_Stop: Shutdown DSI.
|
||||
}ARM_DRIVER_MIPI_DSI;
|
||||
|
||||
#endif /* DRIVER_MIPI_DSI_H_ */
|
||||
117
src/hal/alif/Alif_CMSIS/Include/Driver_MRAM.h
Normal file
117
src/hal/alif/Alif_CMSIS/Include/Driver_MRAM.h
Normal file
@ -0,0 +1,117 @@
|
||||
/* Copyright (C) 2023 Alif Semiconductor - All Rights Reserved.
|
||||
* Use, distribution and modification of this code is permitted under the
|
||||
* terms stated in the Alif Semiconductor Software License Agreement
|
||||
*
|
||||
* You should have received a copy of the Alif Semiconductor Software
|
||||
* License Agreement with this file. If not, please write to:
|
||||
* contact@alifsemi.com, or visit: https://alifsemi.com/license
|
||||
*/
|
||||
|
||||
/**************************************************************************//**
|
||||
* @file Driver_MRAM.h
|
||||
* @Author Tanay Rami
|
||||
* @email <tanay@alifsemi.com>
|
||||
* @version V1.0.0
|
||||
* @date 01-June-2023
|
||||
* @brief CMSIS-Driver for MRAM (On-chip NVM (Non-Volatile Memory)).
|
||||
* Derived from ARM CMSIS "Driver_Flash.h".
|
||||
* @bug None.
|
||||
* @Note None.
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef DRIVER_MRAM_H_
|
||||
#define DRIVER_MRAM_H_
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
#include "Driver_Common.h"
|
||||
|
||||
#define ARM_MRAM_API_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(1,0) /* API version */
|
||||
|
||||
// Function documentation
|
||||
/**
|
||||
\fn ARM_DRIVER_VERSION ARM_MRAM_GetVersion (void)
|
||||
\brief Get driver version.
|
||||
\return \ref ARM_DRIVER_VERSION
|
||||
*/
|
||||
/**
|
||||
\fn ARM_MRAM_CAPABILITIES ARM_MRAM_GetCapabilities (void)
|
||||
\brief Get driver capabilities.
|
||||
\return \ref ARM_MRAM_CAPABILITIES
|
||||
*/
|
||||
/**
|
||||
\fn int32_t ARM_MRAM_Initialize (void)
|
||||
\brief Initialize the MRAM Interface.
|
||||
\return \ref execution_status
|
||||
*/
|
||||
/**
|
||||
\fn int32_t ARM_MRAM_Uninitialize (void)
|
||||
\brief De-initialize the MRAM Interface.
|
||||
\return \ref execution_status
|
||||
*/
|
||||
/**
|
||||
\fn int32_t ARM_MRAM_PowerControl (ARM_POWER_STATE state)
|
||||
\brief Control the MRAM interface power.
|
||||
\param[in] state Power state
|
||||
\return \ref execution_status
|
||||
*/
|
||||
/**
|
||||
\fn int32_t ARM_MRAM_ReadData (uint32_t addr, void *data, uint32_t cnt)
|
||||
\brief Read data from MRAM.
|
||||
\param[in] addr Data address.
|
||||
\param[out] data Pointer to a buffer storing the data read from MRAM.
|
||||
\param[in] cnt Number of data items to read.
|
||||
\return number of data items read or \ref execution_status
|
||||
*/
|
||||
/**
|
||||
\fn int32_t ARM_MRAM_ProgramData (uint32_t addr, const void *data, uint32_t cnt)
|
||||
\brief Program data to MRAM.
|
||||
\param[in] addr Data address.
|
||||
\param[in] data Pointer to a buffer containing the data to be programmed to MRAM.
|
||||
\param[in] cnt Number of data items to program.
|
||||
\return number of data items programmed or \ref execution_status
|
||||
*/
|
||||
/**
|
||||
\fn int32_t ARM_MRAM_EraseSector (uint32_t addr)
|
||||
\brief Erase MRAM Sector.
|
||||
\param[in] addr Sector address
|
||||
\return \ref execution_status
|
||||
*/
|
||||
/**
|
||||
\fn int32_t ARM_MRAM_EraseChip (void)
|
||||
\brief Erase complete MRAM.
|
||||
Optional function for faster full chip erase.
|
||||
\return \ref execution_status
|
||||
*/
|
||||
|
||||
/**
|
||||
\brief MRAM Driver Capabilities.
|
||||
*/
|
||||
typedef struct _ARM_MRAM_CAPABILITIES {
|
||||
uint32_t data_width : 1; ///< Data width: 0=128-bit
|
||||
uint32_t reserved : 31; ///< Reserved (must be zero)
|
||||
} ARM_MRAM_CAPABILITIES;
|
||||
|
||||
/**
|
||||
\brief Access structure of the MRAM Driver
|
||||
*/
|
||||
typedef struct _ARM_DRIVER_MRAM {
|
||||
ARM_DRIVER_VERSION (*GetVersion) (void); ///< Pointer to \ref ARM_MRAM_GetVersion : Get driver version.
|
||||
ARM_MRAM_CAPABILITIES (*GetCapabilities)(void); ///< Pointer to \ref ARM_MRAM_GetCapabilities : Get driver capabilities.
|
||||
int32_t (*Initialize) (void); ///< Pointer to \ref ARM_MRAM_Initialize : Initialize MRAM Interface.
|
||||
int32_t (*Uninitialize) (void); ///< Pointer to \ref ARM_MRAM_Uninitialize : De-initialize MRAM Interface.
|
||||
int32_t (*PowerControl) (ARM_POWER_STATE state); ///< Pointer to \ref ARM_MRAM_PowerControl : Control MRAM Interface Power.
|
||||
int32_t (*ReadData) (uint32_t addr, void *data, uint32_t cnt); ///< Pointer to \ref ARM_MRAM_ReadData : Read data from MRAM.
|
||||
int32_t (*ProgramData) (uint32_t addr, const void *data, uint32_t cnt); ///< Pointer to \ref ARM_MRAM_ProgramData : Program data to MRAM.
|
||||
int32_t (*EraseSector) (uint32_t addr); ///< Pointer to \ref ARM_MRAM_EraseSector : Erase MRAM Sector.
|
||||
int32_t (*EraseChip) (void); ///< Pointer to \ref ARM_MRAM_EraseChip : Erase complete MRAM.
|
||||
} const ARM_DRIVER_MRAM;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* DRIVER_MRAM_H_ */
|
||||
292
src/hal/alif/Alif_CMSIS/Include/Driver_OSPI.h
Normal file
292
src/hal/alif/Alif_CMSIS/Include/Driver_OSPI.h
Normal file
@ -0,0 +1,292 @@
|
||||
/* Copyright (C) 2022 Alif Semiconductor - All Rights Reserved.
|
||||
* Use, distribution and modification of this code is permitted under the
|
||||
* terms stated in the Alif Semiconductor Software License Agreement
|
||||
*
|
||||
* You should have received a copy of the Alif Semiconductor Software
|
||||
* License Agreement with this file. If not, please write to:
|
||||
* contact@alifsemi.com, or visit: https://alifsemi.com/license
|
||||
*
|
||||
*/
|
||||
|
||||
/**************************************************************************/
|
||||
|
||||
/*
|
||||
* Copyright (c) 2013-2020 ARM Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* $Date: 31. March 2020
|
||||
* $Revision: V2.3
|
||||
*
|
||||
* Project: SPI (Serial Peripheral Interface) Driver definitions
|
||||
*/
|
||||
|
||||
/* History:
|
||||
* Version 2.3
|
||||
* Removed Simplex Mode (deprecated)
|
||||
* Removed volatile from ARM_SPI_STATUS
|
||||
* Version 2.2
|
||||
* ARM_SPI_STATUS made volatile
|
||||
* Version 2.1
|
||||
* Renamed status flag "tx_rx_busy" to "busy"
|
||||
* Version 2.0
|
||||
* New simplified driver:
|
||||
* complexity moved to upper layer (especially data handling)
|
||||
* more unified API for different communication interfaces
|
||||
* Added:
|
||||
* Slave Mode
|
||||
* Half-duplex Modes
|
||||
* Configurable number of data bits
|
||||
* Support for TI Mode and Microwire
|
||||
* Changed prefix ARM_DRV -> ARM_DRIVER
|
||||
* Version 1.10
|
||||
* Namespace prefix ARM_ added
|
||||
* Version 1.01
|
||||
* Added "send_done_event" to Capabilities
|
||||
* Version 1.00
|
||||
* Initial release
|
||||
*/
|
||||
|
||||
/**************************************************************************//**
|
||||
* @file Driver_OSPI.h
|
||||
* @author Khushboo Singh
|
||||
* @email khushboo.singh@alifsemi.com
|
||||
* @version V1.0.0
|
||||
* @date 21-Oct-2022
|
||||
* @brief OSPI Driver header file derived from CMSIS Driver_SPI.h
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef DRIVER_OSPI_H_
|
||||
#define DRIVER_OSPI_H_
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
#include "Driver_Common.h"
|
||||
|
||||
#define ARM_OSPI_API_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(1,0) /* API version */
|
||||
|
||||
#define _ARM_Driver_OSPI_(n) Driver_OSPI##n
|
||||
#define ARM_Driver_OSPI_(n) _ARM_Driver_OSPI_(n)
|
||||
|
||||
/****** OSPI Control Codes *****/
|
||||
|
||||
#define ARM_OSPI_CONTROL_POS 0
|
||||
#define ARM_OSPI_CONTROL_MSK (0xFFUL << ARM_OSPI_CONTROL_POS)
|
||||
|
||||
/*----- OSPI Control Codes: Mode -----*/
|
||||
|
||||
#define ARM_OSPI_MODE_INACTIVE (0x00UL << ARM_OSPI_CONTROL_POS) ///< OSPI Inactive
|
||||
#define ARM_OSPI_MODE_MASTER (0x01UL << ARM_OSPI_CONTROL_POS) ///< OSPI Master (Output on MOSI, Input on MISO); arg = Bus Speed in bps
|
||||
#define ARM_OSPI_MODE_SLAVE (0x02UL << ARM_OSPI_CONTROL_POS) ///< OSPI Slave (Output on MISO, Input on MOSI)
|
||||
|
||||
/*----- OSPI Control Codes: Mode Parameters: Frame Format -----*/
|
||||
|
||||
#define ARM_OSPI_FRAME_FORMAT_POS 8
|
||||
#define ARM_OSPI_FRAME_FORMAT_MSK (7UL << ARM_OSPI_FRAME_FORMAT_POS)
|
||||
#define ARM_OSPI_CPOL0_CPHA0 (0UL << ARM_OSPI_FRAME_FORMAT_POS) ///< Clock Polarity 0, Clock Phase 0 (default)
|
||||
#define ARM_OSPI_CPOL0_CPHA1 (1UL << ARM_OSPI_FRAME_FORMAT_POS) ///< Clock Polarity 0, Clock Phase 1
|
||||
#define ARM_OSPI_CPOL1_CPHA0 (2UL << ARM_OSPI_FRAME_FORMAT_POS) ///< Clock Polarity 1, Clock Phase 0
|
||||
#define ARM_OSPI_CPOL1_CPHA1 (3UL << ARM_OSPI_FRAME_FORMAT_POS) ///< Clock Polarity 1, Clock Phase 1
|
||||
#define ARM_OSPI_TI_SSI (4UL << ARM_OSPI_FRAME_FORMAT_POS) ///< Texas Instruments Frame Format
|
||||
#define ARM_OSPI_MICROWIRE (5UL << ARM_OSPI_FRAME_FORMAT_POS) ///< National Semiconductor Microwire Frame Format
|
||||
|
||||
/*----- OSPI Control Codes: Mode Parameters: Data Bits -----*/
|
||||
|
||||
#define ARM_OSPI_DATA_BITS_POS 12
|
||||
#define ARM_OSPI_DATA_BITS_MSK (0x3FUL << ARM_OSPI_DATA_BITS_POS)
|
||||
#define ARM_OSPI_DATA_BITS(n) (((n) & 0x3FUL) << ARM_OSPI_DATA_BITS_POS) ///< Number of Data bits
|
||||
|
||||
/*----- OSPI Control Codes: Mode Parameters: Bit Order -----*/
|
||||
|
||||
#define ARM_OSPI_BIT_ORDER_POS 18
|
||||
#define ARM_OSPI_BIT_ORDER_MSK (1UL << ARM_OSPI_BIT_ORDER_POS)
|
||||
#define ARM_OSPI_MSB_LSB (0UL << ARM_OSPI_BIT_ORDER_POS) ///< OSPI Bit order from MSB to LSB (default)
|
||||
#define ARM_OSPI_LSB_MSB (1UL << ARM_OSPI_BIT_ORDER_POS) ///< OSPI Bit order from LSB to MSB
|
||||
|
||||
/*----- OSPI Control Codes: Mode Parameters: Slave Select Mode -----*/
|
||||
|
||||
#define ARM_OSPI_SS_MASTER_MODE_POS 19
|
||||
#define ARM_OSPI_SS_MASTER_MODE_MSK (3UL << ARM_OSPI_SS_MASTER_MODE_POS)
|
||||
#define ARM_OSPI_SS_MASTER_UNUSED (0UL << ARM_OSPI_SS_MASTER_MODE_POS) ///< OSPI Slave Select when Master: Not used (default)
|
||||
#define ARM_OSPI_SS_MASTER_SW (1UL << ARM_OSPI_SS_MASTER_MODE_POS) ///< OSPI Slave Select when Master: Software controlled
|
||||
#define ARM_OSPI_SS_MASTER_HW_OUTPUT (2UL << ARM_OSPI_SS_MASTER_MODE_POS) ///< OSPI Slave Select when Master: Hardware controlled Output
|
||||
#define ARM_OSPI_SS_MASTER_HW_INPUT (3UL << ARM_OSPI_SS_MASTER_MODE_POS) ///< OSPI Slave Select when Master: Hardware monitored Input
|
||||
#define ARM_OSPI_SS_SLAVE_MODE_POS 21
|
||||
#define ARM_OSPI_SS_SLAVE_MODE_MSK (1UL << ARM_OSPI_SS_SLAVE_MODE_POS)
|
||||
#define ARM_OSPI_SS_SLAVE_HW (0UL << ARM_OSPI_SS_SLAVE_MODE_POS) ///< OSPI Slave Select when Slave: Hardware monitored (default)
|
||||
#define ARM_OSPI_SS_SLAVE_SW (1UL << ARM_OSPI_SS_SLAVE_MODE_POS) ///< OSPI Slave Select when Slave: Software controlled
|
||||
|
||||
/*----- OSPI Control Codes: Miscellaneous Controls -----*/
|
||||
|
||||
#define ARM_OSPI_SET_BUS_SPEED (0x10UL << ARM_OSPI_CONTROL_POS) ///< Set Bus Speed in bps; arg = value
|
||||
#define ARM_OSPI_GET_BUS_SPEED (0x11UL << ARM_OSPI_CONTROL_POS) ///< Get Bus Speed in bps
|
||||
#define ARM_OSPI_SET_DEFAULT_TX_VALUE (0x12UL << ARM_OSPI_CONTROL_POS) ///< Set default Transmit value; arg = value
|
||||
#define ARM_OSPI_CONTROL_SS (0x13UL << ARM_OSPI_CONTROL_POS) ///< Control Slave Select; arg: 0=inactive, 1=active
|
||||
#define ARM_OSPI_ABORT_TRANSFER (0x14UL << ARM_OSPI_CONTROL_POS) ///< Abort current data transfer
|
||||
#define ARM_OSPI_SET_ADDR_LENGTH_WAIT_CYCLE (0x15UL << ARM_OSPI_CONTROL_POS)
|
||||
#define ARM_OSPI_SET_FRAME_FORMAT (0x16UL << ARM_OSPI_CONTROL_POS)
|
||||
#define ARM_OSPI_SET_DDR_MODE (0x17UL << ARM_OSPI_CONTROL_POS)
|
||||
|
||||
/*----- OSPI Custom Control codes -----*/
|
||||
|
||||
#define ARM_OSPI_ADDR_LENGTH_0_BITS 0x0
|
||||
#define ARM_OSPI_ADDR_LENGTH_8_BITS 0x2
|
||||
#define ARM_OSPI_ADDR_LENGTH_24_BITS 0x6
|
||||
#define ARM_OSPI_ADDR_LENGTH_32_BITS 0x8
|
||||
|
||||
#define ARM_OSPI_DDR_DISABLE 0x0
|
||||
#define ARM_OSPI_DDR_ENABLE 0x1
|
||||
|
||||
#define ARM_OSPI_FRF_STANDRAD 0x0 /* 0x0 Standard OSPI Format */
|
||||
#define ARM_OSPI_FRF_DUAL 0x1 /* 0x1 Dual OSPI Format */
|
||||
#define ARM_OSPI_FRF_QUAD 0x2 /* 0X2 Quad OSPI Format */
|
||||
#define ARM_OSPI_FRF_OCTAL 0x3 /* 0X2 Octal OSPI Format */
|
||||
|
||||
#define ARM_OSPI_ADDR_LENGTH_POS 0x0
|
||||
#define ARM_OSPI_WAIT_CYCLE_POS 0x8
|
||||
|
||||
/*---- OSPI Slave Select Signal definitions ----*/
|
||||
|
||||
#define ARM_OSPI_SS_INACTIVE 0UL //< OSPI Slave Select Signal Inactive
|
||||
#define ARM_OSPI_SS_ACTIVE 1UL ///< OSPI Slave Select Signal Active
|
||||
|
||||
/*----- OSPI specific error codes ----*/
|
||||
|
||||
#define ARM_OSPI_ERROR_MODE (ARM_DRIVER_ERROR_SPECIFIC - 1) ///< Specified Mode not supported
|
||||
#define ARM_OSPI_ERROR_FRAME_FORMAT (ARM_DRIVER_ERROR_SPECIFIC - 2) ///< Specified Frame Format not supported
|
||||
#define ARM_OSPI_ERROR_DATA_BITS (ARM_DRIVER_ERROR_SPECIFIC - 3) ///< Specified number of Data bits not supported
|
||||
#define ARM_OSPI_ERROR_BIT_ORDER (ARM_DRIVER_ERROR_SPECIFIC - 4) ///< Specified Bit order not supported
|
||||
#define ARM_OSPI_ERROR_SS_MODE (ARM_DRIVER_ERROR_SPECIFIC - 5) ///< Specified Slave Select Mode not supported
|
||||
|
||||
/**
|
||||
\brief OSPI Status
|
||||
*/
|
||||
typedef struct _ARM_OSPI_STATUS {
|
||||
uint32_t busy : 1; ///< Transmitter/Receiver busy flag
|
||||
uint32_t data_lost : 1; ///< Data lost: Receive overflow / Transmit underflow (cleared on start of transfer operation)
|
||||
uint32_t mode_fault : 1; ///< Mode fault detected; optional (cleared on start of transfer operation)
|
||||
uint32_t reserved : 29;
|
||||
} ARM_OSPI_STATUS;
|
||||
|
||||
/****** OSPI Event *****/
|
||||
#define ARM_OSPI_EVENT_TRANSFER_COMPLETE (1UL << 0) ///< Data Transfer completed
|
||||
#define ARM_OSPI_EVENT_DATA_LOST (1UL << 1) ///< Data lost: Receive overflow / Transmit underflow
|
||||
#define ARM_OSPI_EVENT_MODE_FAULT (1UL << 2) ///< Master Mode Fault (SS deactivated when Master)
|
||||
|
||||
// Function documentation
|
||||
/**
|
||||
\fn ARM_DRIVER_VERSION ARM_OSPI_GetVersion (void)
|
||||
\brief Get driver version.
|
||||
\return \ref ARM_DRIVER_VERSION
|
||||
|
||||
\fn ARM_OSPI_CAPABILITIES ARM_OSPI_GetCapabilities (void)
|
||||
\brief Get driver capabilities.
|
||||
\return \ref ARM_OSPI_CAPABILITIES
|
||||
|
||||
\fn int32_t ARM_OSPI_Initialize (ARM_OSPI_SignalEvent_t cb_event)
|
||||
\brief Initialize OSPI Interface.
|
||||
\param[in] cb_event Pointer to \ref ARM_OSPI_SignalEvent
|
||||
\return \ref execution_status
|
||||
|
||||
\fn int32_t ARM_OSPI_Uninitialize (void)
|
||||
\brief De-initialize OSPI Interface.
|
||||
\return \ref execution_status
|
||||
|
||||
\fn int32_t ARM_OSPI_PowerControl (ARM_POWER_STATE state)
|
||||
\brief Control OSPI Interface Power.
|
||||
\param[in] state Power state
|
||||
\return \ref execution_status
|
||||
|
||||
\fn int32_t ARM_OSPI_Send (const void *data, uint32_t num)
|
||||
\brief Start sending data to OSPI transmitter.
|
||||
\param[in] data Pointer to buffer with data to send to OSPI transmitter
|
||||
\param[in] num Number of data items to send
|
||||
\return \ref execution_status
|
||||
|
||||
\fn int32_t ARM_OSPI_Receive (void *data, uint32_t num)
|
||||
\brief Start receiving data from OSPI receiver.
|
||||
\param[out] data Pointer to buffer for data to receive from OSPI receiver
|
||||
\param[in] num Number of data items to receive
|
||||
\return \ref execution_status
|
||||
|
||||
\fn int32_t ARM_OSPI_Transfer (const void *data_out,
|
||||
void *data_in,
|
||||
uint32_t num)
|
||||
\brief Start sending/receiving data to/from OSPI transmitter/receiver.
|
||||
\param[in] data_out Pointer to buffer with data to send to OSPI transmitter
|
||||
\param[out] data_in Pointer to buffer for data to receive from OSPI receiver
|
||||
\param[in] num Number of data items to transfer
|
||||
\return \ref execution_status
|
||||
|
||||
\fn uint32_t ARM_OSPI_GetDataCount (void)
|
||||
\brief Get transferred data count.
|
||||
\return number of data items transferred
|
||||
|
||||
\fn int32_t ARM_OSPI_Control (uint32_t control, uint32_t arg)
|
||||
\brief Control OSPI Interface.
|
||||
\param[in] control Operation
|
||||
\param[in] arg Argument of operation (optional)
|
||||
\return common \ref execution_status and driver specific \ref spi_execution_status
|
||||
|
||||
\fn ARM_OSPI_STATUS ARM_OSPI_GetStatus (void)
|
||||
\brief Get OSPI status.
|
||||
\return OSPI status \ref ARM_OSPI_STATUS
|
||||
|
||||
\fn void ARM_OSPI_SignalEvent (uint32_t event)
|
||||
\brief Signal OSPI Events.
|
||||
\param[in] event \ref OSPI_events notification mask
|
||||
\return none
|
||||
*/
|
||||
|
||||
typedef void (*ARM_OSPI_SignalEvent_t) (uint32_t event); ///< Pointer to \ref ARM_OSPI_SignalEvent : Signal OSPI Event.
|
||||
|
||||
/**
|
||||
\brief OSPI Driver Capabilities.
|
||||
*/
|
||||
typedef struct _ARM_OSPI_CAPABILITIES {
|
||||
uint32_t simplex : 1; ///< supports Simplex Mode (Master and Slave) @deprecated Reserved (must be zero)
|
||||
uint32_t ti_ssi : 1; ///< supports TI Synchronous Serial Interface
|
||||
uint32_t microwire : 1; ///< supports Microwire Interface
|
||||
uint32_t event_mode_fault : 1; ///< Signal Mode Fault event: \ref ARM_OSPI_EVENT_MODE_FAULT
|
||||
uint32_t reserved : 28; ///< Reserved (must be zero)
|
||||
} ARM_OSPI_CAPABILITIES;
|
||||
|
||||
|
||||
/**
|
||||
\brief Access structure of the OSPI Driver.
|
||||
*/
|
||||
typedef struct _ARM_DRIVER_OSPI {
|
||||
ARM_DRIVER_VERSION (*GetVersion) (void); ///< Pointer to \ref ARM_OSPI_GetVersion : Get driver version.
|
||||
ARM_OSPI_CAPABILITIES (*GetCapabilities) (void); ///< Pointer to \ref ARM_OSPI_GetCapabilities : Get driver capabilities.
|
||||
int32_t (*Initialize) (ARM_OSPI_SignalEvent_t cb_event); ///< Pointer to \ref ARM_OSPI_Initialize : Initialize OSPI Interface.
|
||||
int32_t (*Uninitialize) (void); ///< Pointer to \ref ARM_OSPI_Uninitialize : De-initialize OSPI Interface.
|
||||
int32_t (*PowerControl) (ARM_POWER_STATE state); ///< Pointer to \ref ARM_OSPI_PowerControl : Control OSPI Interface Power.
|
||||
int32_t (*Send) (const void *data, uint32_t num); ///< Pointer to \ref ARM_OSPI_Send : Start sending data to OSPI Interface.
|
||||
int32_t (*Receive) ( void *data, uint32_t num); ///< Pointer to \ref ARM_OSPI_Receive : Start receiving data from OSPI Interface.
|
||||
int32_t (*Transfer) (const void *data_out,
|
||||
void *data_in,
|
||||
uint32_t num); ///< Pointer to \ref ARM_OSPI_Transfer : Start sending/receiving data to/from OSPI.
|
||||
uint32_t (*GetDataCount) (void); ///< Pointer to \ref ARM_OSPI_GetDataCount : Get transferred data count.
|
||||
int32_t (*Control) (uint32_t control, uint32_t arg); ///< Pointer to \ref ARM_OSPI_Control : Control OSPI Interface.
|
||||
ARM_OSPI_STATUS (*GetStatus) (void); ///< Pointer to \ref ARM_OSPI_GetStatus : Get OSPI status.
|
||||
} const ARM_DRIVER_OSPI;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
#endif /* DRIVER_OSPI_H_ */
|
||||
149
src/hal/alif/Alif_CMSIS/Include/Driver_PDM.h
Normal file
149
src/hal/alif/Alif_CMSIS/Include/Driver_PDM.h
Normal file
@ -0,0 +1,149 @@
|
||||
/* Copyright (C) 2023 Alif Semiconductor - All Rights Reserved.
|
||||
* Use, distribution and modification of this code is permitted under the
|
||||
* terms stated in the Alif Semiconductor Software License Agreement
|
||||
*
|
||||
* You should have received a copy of the Alif Semiconductor Software
|
||||
* License Agreement with this file. If not, please write to:
|
||||
* contact@alifsemi.com, or visit: https://alifsemi.com/license
|
||||
*
|
||||
*/
|
||||
|
||||
/**************************************************************************//**
|
||||
* @file Driver_PDM.h
|
||||
* @author Nisarga A M
|
||||
* @email nisarga.am@alifsemi.com
|
||||
* @version V1.0.0
|
||||
* @date 15-Jan-2023
|
||||
* @brief CMSIS-Driver for PDM.
|
||||
* @bug None.
|
||||
* @Note None
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef DRIVER_PDM_H_
|
||||
#define DRIVER_PDM_H_
|
||||
|
||||
#include "Driver_Common.h"
|
||||
|
||||
#ifdef _cplusplus
|
||||
extern "c"
|
||||
{
|
||||
#endif
|
||||
|
||||
#define ARM_PDM_API_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(1,0) /* API version */
|
||||
|
||||
#define ARM_PDM_MODE 0x00UL
|
||||
|
||||
/* Control code for PDM */
|
||||
#define ARM_PDM_MODE_MICROPHONE_SLEEP 0x00UL
|
||||
#define ARM_PDM_MODE_AUDIOFREQ_8K_DECM_64 0x01UL
|
||||
#define ARM_PDM_MODE_AUDIOFREQ_16K_DECM_32 0x02UL
|
||||
#define ARM_PDM_MODE_AUDIOFREQ_16K_DECM_48 0x03UL
|
||||
#define ARM_PDM_MODE_AUDIOFREQ_16K_DECM_64 0x04UL
|
||||
#define ARM_PDM_MODE_AUDIOFREQ_32K_DECM_48 0x05UL
|
||||
#define ARM_PDM_MODE_AUDIOFREQ_48K_DECM_50 0x06UL
|
||||
#define ARM_PDM_MODE_AUDIOFREQ_48K_DECM_64 0x07UL
|
||||
#define ARM_PDM_MODE_AUDIOFREQ_96K_DECM_50 0x08UL
|
||||
#define ARM_PDM_MODE_AUDIOFREQ_192K_DECM_25 0x09UL
|
||||
|
||||
/* Control code for PDM. Old definitions, to be deprecated in future releases */
|
||||
#define ARM_PDM_MODE_STANDARD_VOICE_512_CLK_FRQ ARM_PDM_MODE_AUDIOFREQ_8K_DECM_64
|
||||
#define ARM_PDM_MODE_HIGH_QUALITY_512_CLK_FRQ ARM_PDM_MODE_AUDIOFREQ_16K_DECM_32
|
||||
#define ARM_PDM_MODE_HIGH_QUALITY_768_CLK_FRQ ARM_PDM_MODE_AUDIOFREQ_16K_DECM_48
|
||||
#define ARM_PDM_MODE_HIGH_QUALITY_1024_CLK_FRQ ARM_PDM_MODE_AUDIOFREQ_16K_DECM_64
|
||||
#define ARM_PDM_MODE_WIDE_BANDWIDTH_AUDIO_1536_CLK_FRQ ARM_PDM_MODE_AUDIOFREQ_32K_DECM_48
|
||||
#define ARM_PDM_MODE_FULL_BANDWIDTH_AUDIO_2400_CLK_FRQ ARM_PDM_MODE_AUDIOFREQ_48K_DECM_50
|
||||
/* Typo in macro name, should be '3072' KHz instead of '3071' */
|
||||
#define ARM_PDM_MODE_FULL_BANDWIDTH_AUDIO_3071_CLK_FRQ ARM_PDM_MODE_AUDIOFREQ_48K_DECM_64
|
||||
#define ARM_PDM_MODE_ULTRASOUND_4800_CLOCK_FRQ ARM_PDM_MODE_AUDIOFREQ_96K_DECM_50
|
||||
#define ARM_PDM_MODE_ULTRASOUND_96_SAMPLING_RATE ARM_PDM_MODE_AUDIOFREQ_192K_DECM_25
|
||||
|
||||
#define ARM_PDM_BYPASS_IIR_FILTER 0x0AUL
|
||||
#define ARM_PDM_BYPASS_FIR_FILTER 0x0BUL
|
||||
|
||||
#define ARM_PDM_PEAK_DETECTION_NODE 0x0CUL
|
||||
#define ARM_PDM_SAMPLE_ADVANCE 0x0DUL
|
||||
#define ARM_PDM_CHANNEL_PHASE 0x0EUL
|
||||
#define ARM_PDM_CHANNEL_GAIN 0x0FUL
|
||||
#define ARM_PDM_CHANNEL_PEAK_DETECT_TH 0x10UL
|
||||
#define ARM_PDM_CHANNEL_PEAK_DETECT_ITV 0x11UL
|
||||
|
||||
/* PDM event */
|
||||
#define ARM_PDM_EVENT_ERROR (1UL << 0)
|
||||
#define ARM_PDM_EVENT_CAPTURE_COMPLETE (1UL << 1)
|
||||
#define ARM_PDM_EVENT_AUDIO_DETECTION (1UL << 2)
|
||||
|
||||
#define ARM_PDM_SELECT_RESOLUTION (1UL << 3)
|
||||
|
||||
#define ARM_PDM_16BIT_RESOLUTION (1UL << 4)
|
||||
#define ARM_PDM_32BIT_RESOLUTION (1UL << 5)
|
||||
|
||||
/* PDM channel FIR length */
|
||||
#define PDM_MAX_FIR_COEFFICIENT 18
|
||||
|
||||
#define ARM_PDM_SELECT_CHANNEL 0x01UL
|
||||
|
||||
/* PDM channels */
|
||||
#define ARM_PDM_AUDIO_CHANNEL_0 (0x00)
|
||||
#define ARM_PDM_AUDIO_CHANNEL_1 (0x01)
|
||||
#define ARM_PDM_AUDIO_CHANNEL_2 (0x02)
|
||||
#define ARM_PDM_AUDIO_CHANNEL_3 (0x03)
|
||||
#define ARM_PDM_AUDIO_CHANNEL_4 (0x04)
|
||||
#define ARM_PDM_AUDIO_CHANNEL_5 (0x05)
|
||||
#define ARM_PDM_AUDIO_CHANNEL_6 (0x06)
|
||||
#define ARM_PDM_AUDIO_CHANNEL_7 (0x07)
|
||||
|
||||
/* PDM mask channels */
|
||||
#define ARM_PDM_MASK_CHANNEL_0 (1 << ARM_PDM_AUDIO_CHANNEL_0)
|
||||
#define ARM_PDM_MASK_CHANNEL_1 (1 << ARM_PDM_AUDIO_CHANNEL_1)
|
||||
#define ARM_PDM_MASK_CHANNEL_2 (1 << ARM_PDM_AUDIO_CHANNEL_2)
|
||||
#define ARM_PDM_MASK_CHANNEL_3 (1 << ARM_PDM_AUDIO_CHANNEL_3)
|
||||
#define ARM_PDM_MASK_CHANNEL_4 (1 << ARM_PDM_AUDIO_CHANNEL_4)
|
||||
#define ARM_PDM_MASK_CHANNEL_5 (1 << ARM_PDM_AUDIO_CHANNEL_5)
|
||||
#define ARM_PDM_MASK_CHANNEL_6 (1 << ARM_PDM_AUDIO_CHANNEL_6)
|
||||
#define ARM_PDM_MASK_CHANNEL_7 (1 << ARM_PDM_AUDIO_CHANNEL_7)
|
||||
|
||||
typedef void (*ARM_PDM_SignalEvent_t) (uint32_t event); /*Pointer to \ref PDM_SignalEvent : Signal PDM Event*/
|
||||
|
||||
/**
|
||||
@brief: These channel configurations are specific to each channels
|
||||
*/
|
||||
typedef struct _PDM_CH_CONFIG {
|
||||
uint8_t ch_num; /* Channel number */
|
||||
uint32_t ch_fir_coef[PDM_MAX_FIR_COEFFICIENT]; /* Channel FIR filter Coefficient */
|
||||
uint32_t ch_iir_coef; /* Channel IIR Filter Coefficient */
|
||||
}PDM_CH_CONFIG;
|
||||
|
||||
/**
|
||||
* @brief: PDM Status
|
||||
*/
|
||||
typedef struct _ARM_PDM_STATUS {
|
||||
uint32_t rx_busy : 1; /* Receiver busy flag */
|
||||
uint32_t rx_overflow : 1; /* Receive data overflow detected */
|
||||
uint32_t reserved : 30; /* Reserved (must be Zero) */
|
||||
}ARM_PDM_STATUS;
|
||||
|
||||
/**
|
||||
@brief : PDM Driver Capabilities
|
||||
*/
|
||||
typedef struct _ARM_PDM_CAPABILITIES{
|
||||
uint32_t mono_mode :1; /* supports Mono mode */
|
||||
uint32_t synchronous :1; /* supports synchronous Receive */
|
||||
uint32_t reserved :29; /* Reserved (must be Zero) */
|
||||
}ARM_PDM_CAPABILITIES;
|
||||
|
||||
/**
|
||||
@brief Access Structure of PDM Driver
|
||||
*/
|
||||
typedef struct ARM_DRIVER_PDM{
|
||||
ARM_DRIVER_VERSION (*GetVersion) (void); /* pointer is pointing to PDM_GetVersion : used to get the driver version */
|
||||
ARM_PDM_CAPABILITIES (*GetCapabilities) (void); /* pointer is pointing to PDM_Capabilities : used to get the driver capabilities */
|
||||
int32_t (*Initialize) (ARM_PDM_SignalEvent_t cb_event); /* Pointer pointing to \ref PDM_intialize */
|
||||
int32_t (*Uninitialize) (void); /* Pointer to PDM_Uninitialize : Un-initialize comparator Interface */
|
||||
int32_t (*PowerControl) (ARM_POWER_STATE state); /* Pointer to PDM_PowerControl : Control Comparator Interface Power */
|
||||
int32_t (*Control) (uint32_t control, uint32_t arg1, uint32_t arg2); /* Pointer to PDM_Control : Control Comparator Interface */
|
||||
int32_t (*Config) (PDM_CH_CONFIG *cnfg); /* Pointer to PDM Config: Channel configurations specific to each channel */
|
||||
int32_t (*Receive) (void *data, uint32_t num); /* Pointer to Receive : PDM Receive Configuration */
|
||||
ARM_PDM_STATUS (*GetStatus) (void); /* Pointer to GetStatus: Get the PDM status */
|
||||
}const ARM_DRIVER_PDM;
|
||||
|
||||
#endif /* DRIVER_PDM_H_ */
|
||||
109
src/hal/alif/Alif_CMSIS/Include/Driver_RTC.h
Normal file
109
src/hal/alif/Alif_CMSIS/Include/Driver_RTC.h
Normal file
@ -0,0 +1,109 @@
|
||||
/* Copyright (C) 2022 Alif Semiconductor - All Rights Reserved.
|
||||
* Use, distribution and modification of this code is permitted under the
|
||||
* terms stated in the Alif Semiconductor Software License Agreement
|
||||
*
|
||||
* You should have received a copy of the Alif Semiconductor Software
|
||||
* License Agreement with this file. If not, please write to:
|
||||
* contact@alifsemi.com, or visit: https://alifsemi.com/license
|
||||
*
|
||||
*/
|
||||
|
||||
/**************************************************************************//**
|
||||
* @file Driver_RTC.h
|
||||
* @author Tanay Rami
|
||||
* @email tanay@alifsemi.com
|
||||
* @version V1.0.0
|
||||
* @date 18-Feb-2021
|
||||
* @brief RTC(Real Time Clock) driver definitions.
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef DRIVER_RTC_H_
|
||||
#define DRIVER_RTC_H_
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
/* Includes --------------------------------------------------------------------------- */
|
||||
#include "Driver_Common.h"
|
||||
|
||||
#define ARM_RTC_API_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(1,0) /* API version */
|
||||
|
||||
/*----- RTC Control Codes -----*/
|
||||
#define ARM_RTC_SET_PRESCALER (0x01UL) ///< RTC Set Prescaler; arg = Prescaler Value
|
||||
#define ARM_RTC_SET_ALARM (0x02UL) ///< RTC Set Alarm; arg = Alarm Value
|
||||
|
||||
/****** RTC Event *****/
|
||||
#define ARM_RTC_EVENT_ALARM_TRIGGER (1UL << 0) ///< Alarm Triggered;
|
||||
|
||||
|
||||
// Function documentation
|
||||
/**
|
||||
\fn ARM_DRIVER_VERSION GetVersion (void)
|
||||
\brief Get RTC driver version.
|
||||
\return \ref ARM_DRIVER_VERSION
|
||||
|
||||
\fn ARM_RTC_CAPABILITIES GetCapabilities (void)
|
||||
\brief Get RTC driver capabilities
|
||||
\return \ref RTC_CAPABILITIES
|
||||
|
||||
\fn int32_t Initialize (ARM_RTC_SignalEvent_t cb_event)
|
||||
\brief Initialize RTC Interface.
|
||||
\param[in] cb_event : Pointer to RTC Event \ref ARM_RTC_SignalEvent
|
||||
\return \ref execution_status
|
||||
|
||||
\fn int32_t Uninitialize (void)
|
||||
\brief De-initialize RTC Interface.
|
||||
\return \ref execution_status
|
||||
|
||||
\fn int32_t PowerControl (ARM_POWER_STATE state)
|
||||
\brief Control RTC Interface Power.
|
||||
\param[in] state : Power state
|
||||
\return \ref execution_status
|
||||
|
||||
\fn int32_t Control (uint32_t control, uint32_t arg)
|
||||
\brief Control RTC Interface.
|
||||
\param[in] control : Operation
|
||||
\param[in] arg : Argument of operation (optional)
|
||||
\return common \ref execution_status
|
||||
|
||||
\fn int32_t ReadCounter (uint32_t *val)
|
||||
\brief Read the current counter value.
|
||||
\param[out] val : Pointer to the address where current rtc counter value
|
||||
needs to be copied to
|
||||
\return \ref execution_status
|
||||
*/
|
||||
|
||||
typedef void (*ARM_RTC_SignalEvent_t) (uint32_t event); ///< Pointer to \ref RTC_SignalEvent : Signal RTC Event.
|
||||
|
||||
/**
|
||||
\brief RTC Device Driver Capabilities.
|
||||
*/
|
||||
typedef struct _ARM_RTC_CAPABILITIES {
|
||||
uint32_t alarm : 1; ///< supports RTC Alarm Event Callback
|
||||
uint32_t reserved : 31; ///< Reserved (must be zero)
|
||||
} ARM_RTC_CAPABILITIES;
|
||||
|
||||
|
||||
/**
|
||||
\brief Access structure of the RTC Driver.
|
||||
*/
|
||||
typedef struct _ARM_DRIVER_RTC {
|
||||
ARM_DRIVER_VERSION (*GetVersion) (void); ///< Pointer to \ref RTC_GetVersion : Get driver version.
|
||||
ARM_RTC_CAPABILITIES (*GetCapabilities) (void); ///< Pointer to \ref RTC_GetCapabilities : Get driver capabilities.
|
||||
int32_t (*Initialize) (ARM_RTC_SignalEvent_t cb_event); ///< Pointer to \ref RTC_Initialize : Initialize RTC Interface.
|
||||
int32_t (*Uninitialize) (void); ///< Pointer to \ref RTC_Uninitialize : De-initialize RTC Interface.
|
||||
int32_t (*PowerControl) (ARM_POWER_STATE state); ///< Pointer to \ref RTC_PowerControl : Control RTC Interface Power.
|
||||
int32_t (*Control) (uint32_t control, uint32_t arg); ///< Pointer to \ref RTC_Control : Control RTC Interface.
|
||||
int32_t (*ReadCounter) (uint32_t *val); ///< Pointer to \ref RTC_ReadCounter : Read the RTC current counter.
|
||||
int32_t (*LoadCounter) (uint32_t loadval); ///< Pointer to \ref RTC_LoadCounter : Load new RTC counter Value.
|
||||
} const ARM_DRIVER_RTC;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* DRIVER_RTC_H_ */
|
||||
|
||||
/************************ (C) COPYRIGHT ALIF SEMICONDUCTOR *****END OF FILE****/
|
||||
315
src/hal/alif/Alif_CMSIS/Include/Driver_SAI.h
Normal file
315
src/hal/alif/Alif_CMSIS/Include/Driver_SAI.h
Normal file
@ -0,0 +1,315 @@
|
||||
/*
|
||||
* Copyright (c) 2013-2020 ARM Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* $Date: 31. March 2020
|
||||
* $Revision: V1.2
|
||||
*
|
||||
* Project: SAI (Serial Audio Interface) Driver definitions
|
||||
*/
|
||||
|
||||
/* History:
|
||||
* Version 1.2
|
||||
* Removed volatile from ARM_SAI_STATUS
|
||||
* Version 1.1
|
||||
* ARM_SAI_STATUS made volatile
|
||||
* Version 1.0
|
||||
* Initial release
|
||||
*/
|
||||
|
||||
#ifndef DRIVER_SAI_H_
|
||||
#define DRIVER_SAI_H_
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
#include "Driver_Common.h"
|
||||
|
||||
#define ARM_SAI_API_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(1,2) /* API version */
|
||||
|
||||
|
||||
#define _ARM_Driver_SAI_(n) Driver_SAI##n
|
||||
#define ARM_Driver_SAI_(n) _ARM_Driver_SAI_(n)
|
||||
|
||||
|
||||
/****** SAI Control Codes *****/
|
||||
|
||||
#define ARM_SAI_CONTROL_Msk (0xFFUL)
|
||||
#define ARM_SAI_CONFIGURE_TX (0x01UL) ///< Configure Transmitter; arg1 and arg2 provide additional configuration
|
||||
#define ARM_SAI_CONFIGURE_RX (0x02UL) ///< Configure Receiver; arg1 and arg2 provide additional configuration
|
||||
#define ARM_SAI_CONTROL_TX (0x03UL) ///< Control Transmitter; arg1.0: 0=disable (default), 1=enable; arg1.1: mute
|
||||
#define ARM_SAI_CONTROL_RX (0x04UL) ///< Control Receiver; arg1.0: 0=disable (default), 1=enable
|
||||
#define ARM_SAI_MASK_SLOTS_TX (0x05UL) ///< Mask Transmitter slots; arg1 = mask (bit: 0=active, 1=inactive); all configured slots are active by default
|
||||
#define ARM_SAI_MASK_SLOTS_RX (0x06UL) ///< Mask Receiver slots; arg1 = mask (bit: 0=active, 1=inactive); all configured slots are active by default
|
||||
#define ARM_SAI_ABORT_SEND (0x07UL) ///< Abort \ref ARM_SAI_Send
|
||||
#define ARM_SAI_ABORT_RECEIVE (0x08UL) ///< Abort \ref ARM_SAI_Receive
|
||||
|
||||
/*----- SAI Control Codes: Configuration Parameters: Mode -----*/
|
||||
#define ARM_SAI_MODE_Pos 8
|
||||
#define ARM_SAI_MODE_Msk (1UL << ARM_SAI_MODE_Pos)
|
||||
#define ARM_SAI_MODE_MASTER (1UL << ARM_SAI_MODE_Pos) ///< Master Mode
|
||||
#define ARM_SAI_MODE_SLAVE (0UL << ARM_SAI_MODE_Pos) ///< Slave Mode (default)
|
||||
|
||||
/*----- SAI Control Codes: Configuration Parameters: Synchronization -----*/
|
||||
#define ARM_SAI_SYNCHRONIZATION_Pos 9
|
||||
#define ARM_SAI_SYNCHRONIZATION_Msk (1UL << ARM_SAI_SYNCHRONIZATION_Pos)
|
||||
#define ARM_SAI_ASYNCHRONOUS (0UL << ARM_SAI_SYNCHRONIZATION_Pos) ///< Asynchronous (default)
|
||||
#define ARM_SAI_SYNCHRONOUS (1UL << ARM_SAI_SYNCHRONIZATION_Pos) ///< Synchronous
|
||||
|
||||
/*----- SAI Control Codes: Configuration Parameters: Protocol -----*/
|
||||
#define ARM_SAI_PROTOCOL_Pos 10
|
||||
#define ARM_SAI_PROTOCOL_Msk (7UL << ARM_SAI_PROTOCOL_Pos)
|
||||
#define ARM_SAI_PROTOCOL_USER (0UL << ARM_SAI_PROTOCOL_Pos) ///< User defined (default)
|
||||
#define ARM_SAI_PROTOCOL_I2S (1UL << ARM_SAI_PROTOCOL_Pos) ///< I2S
|
||||
#define ARM_SAI_PROTOCOL_MSB_JUSTIFIED (2UL << ARM_SAI_PROTOCOL_Pos) ///< MSB (left) justified
|
||||
#define ARM_SAI_PROTOCOL_LSB_JUSTIFIED (3UL << ARM_SAI_PROTOCOL_Pos) ///< LSB (right) justified
|
||||
#define ARM_SAI_PROTOCOL_PCM_SHORT (4UL << ARM_SAI_PROTOCOL_Pos) ///< PCM with short frame
|
||||
#define ARM_SAI_PROTOCOL_PCM_LONG (5UL << ARM_SAI_PROTOCOL_Pos) ///< PCM with long frame
|
||||
#define ARM_SAI_PROTOCOL_AC97 (6UL << ARM_SAI_PROTOCOL_Pos) ///< AC'97
|
||||
|
||||
/*----- SAI Control Codes: Configuration Parameters: Data Size -----*/
|
||||
#define ARM_SAI_DATA_SIZE_Pos 13
|
||||
#define ARM_SAI_DATA_SIZE_Msk (0x1FUL << ARM_SAI_DATA_SIZE_Pos)
|
||||
#define ARM_SAI_DATA_SIZE(n) ((((n)-1UL)&0x1FUL) << ARM_SAI_DATA_SIZE_Pos) ///< Data size in bits (8..32)
|
||||
|
||||
/*----- SAI Control Codes: Configuration Parameters: Bit Order -----*/
|
||||
#define ARM_SAI_BIT_ORDER_Pos 18
|
||||
#define ARM_SAI_BIT_ORDER_Msk (1UL << ARM_SAI_BIT_ORDER_Pos)
|
||||
#define ARM_SAI_MSB_FIRST (0UL << ARM_SAI_BIT_ORDER_Pos) ///< Data is transferred with MSB first (default)
|
||||
#define ARM_SAI_LSB_FIRST (1UL << ARM_SAI_BIT_ORDER_Pos) ///< Data is transferred with LSB first; User Protocol only (ignored otherwise)
|
||||
|
||||
/*----- SAI Control Codes: Configuration Parameters: Mono Mode -----*/
|
||||
#define ARM_SAI_MONO_MODE (1UL << 19) ///< Mono Mode (only for I2S, MSB/LSB justified)
|
||||
|
||||
/*----- SAI Control Codes:Configuration Parameters: Companding -----*/
|
||||
#define ARM_SAI_COMPANDING_Pos 20
|
||||
#define ARM_SAI_COMPANDING_Msk (3UL << ARM_SAI_COMPANDING_Pos)
|
||||
#define ARM_SAI_COMPANDING_NONE (0UL << ARM_SAI_COMPANDING_Pos) ///< No companding (default)
|
||||
#define ARM_SAI_COMPANDING_A_LAW (2UL << ARM_SAI_COMPANDING_Pos) ///< A-Law companding
|
||||
#define ARM_SAI_COMPANDING_U_LAW (3UL << ARM_SAI_COMPANDING_Pos) ///< u-Law companding
|
||||
|
||||
/*----- SAI Control Codes: Configuration Parameters: Clock Polarity -----*/
|
||||
#define ARM_SAI_CLOCK_POLARITY_Pos 23
|
||||
#define ARM_SAI_CLOCK_POLARITY_Msk (1UL << ARM_SAI_CLOCK_POLARITY_Pos)
|
||||
#define ARM_SAI_CLOCK_POLARITY_0 (0UL << ARM_SAI_CLOCK_POLARITY_Pos) ///< Drive on falling edge, Capture on rising edge (default)
|
||||
#define ARM_SAI_CLOCK_POLARITY_1 (1UL << ARM_SAI_CLOCK_POLARITY_Pos) ///< Drive on rising edge, Capture on falling edge
|
||||
|
||||
/*----- SAI Control Codes: Configuration Parameters: Master Clock Pin -----*/
|
||||
#define ARM_SAI_MCLK_PIN_Pos 24
|
||||
#define ARM_SAI_MCLK_PIN_Msk (3UL << ARM_SAI_MCLK_PIN_Pos)
|
||||
#define ARM_SAI_MCLK_PIN_INACTIVE (0UL << ARM_SAI_MCLK_PIN_Pos) ///< MCLK not used (default)
|
||||
#define ARM_SAI_MCLK_PIN_OUTPUT (1UL << ARM_SAI_MCLK_PIN_Pos) ///< MCLK is output (Master only)
|
||||
#define ARM_SAI_MCLK_PIN_INPUT (2UL << ARM_SAI_MCLK_PIN_Pos) ///< MCLK is input (Master only)
|
||||
|
||||
|
||||
/****** SAI Configuration (arg1) *****/
|
||||
|
||||
/*----- SAI Configuration (arg1): Frame Length -----*/
|
||||
#define ARM_SAI_FRAME_LENGTH_Pos 0
|
||||
#define ARM_SAI_FRAME_LENGTH_Msk (0x3FFUL << ARM_SAI_FRAME_LENGTH_Pos)
|
||||
#define ARM_SAI_FRAME_LENGTH(n) ((((n)-1UL)&0x3FFUL) << ARM_SAI_FRAME_LENGTH_Pos) ///< Frame length in bits (8..1024); default depends on protocol and data
|
||||
|
||||
/*----- SAI Configuration (arg1): Frame Sync Width -----*/
|
||||
#define ARM_SAI_FRAME_SYNC_WIDTH_Pos 10
|
||||
#define ARM_SAI_FRAME_SYNC_WIDTH_Msk (0xFFUL << ARM_SAI_FRAME_SYNC_WIDTH_Pos)
|
||||
#define ARM_SAI_FRAME_SYNC_WIDTH(n) ((((n)-1UL)&0xFFUL) << ARM_SAI_FRAME_SYNC_WIDTH_Pos) ///< Frame Sync width in bits (1..256); default=1; User Protocol only (ignored otherwise)
|
||||
|
||||
/*----- SAI Configuration (arg1): Frame Sync Polarity -----*/
|
||||
#define ARM_SAI_FRAME_SYNC_POLARITY_Pos 18
|
||||
#define ARM_SAI_FRAME_SYNC_POLARITY_Msk (1UL << ARM_SAI_FRAME_SYNC_POLARITY_Pos)
|
||||
#define ARM_SAI_FRAME_SYNC_POLARITY_HIGH (0UL << ARM_SAI_FRAME_SYNC_POLARITY_Pos) ///< Frame Sync is active high (default); User Protocol only (ignored otherwise)
|
||||
#define ARM_SAI_FRAME_SYNC_POLARITY_LOW (1UL << ARM_SAI_FRAME_SYNC_POLARITY_Pos) ///< Frame Sync is active low; User Protocol only (ignored otherwise)
|
||||
|
||||
/*----- SAI Configuration (arg1): Frame Sync Early -----*/
|
||||
#define ARM_SAI_FRAME_SYNC_EARLY (1UL << 19) ///< Frame Sync one bit before the first bit of the frame; User Protocol only (ignored otherwise)
|
||||
|
||||
/*----- SAI Configuration (arg1): Slot Count -----*/
|
||||
#define ARM_SAI_SLOT_COUNT_Pos 20
|
||||
#define ARM_SAI_SLOT_COUNT_Msk (0x1FUL << ARM_SAI_SLOT_COUNT_Pos)
|
||||
#define ARM_SAI_SLOT_COUNT(n) ((((n)-1UL)&0x1FUL) << ARM_SAI_SLOT_COUNT_Pos) ///< Number of slots in frame (1..32); default=1; User Protocol only (ignored otherwise)
|
||||
|
||||
/*----- SAI Configuration (arg1): Slot Size -----*/
|
||||
#define ARM_SAI_SLOT_SIZE_Pos 25
|
||||
#define ARM_SAI_SLOT_SIZE_Msk (3UL << ARM_SAI_SLOT_SIZE_Pos)
|
||||
#define ARM_SAI_SLOT_SIZE_DEFAULT (0UL << ARM_SAI_SLOT_SIZE_Pos) ///< Slot size is equal to data size (default)
|
||||
#define ARM_SAI_SLOT_SIZE_16 (1UL << ARM_SAI_SLOT_SIZE_Pos) ///< Slot size = 16 bits; User Protocol only (ignored otherwise)
|
||||
#define ARM_SAI_SLOT_SIZE_32 (3UL << ARM_SAI_SLOT_SIZE_Pos) ///< Slot size = 32 bits; User Protocol only (ignored otherwise)
|
||||
|
||||
/*----- SAI Configuration (arg1): Slot Offset -----*/
|
||||
#define ARM_SAI_SLOT_OFFSET_Pos 27
|
||||
#define ARM_SAI_SLOT_OFFSET_Msk (0x1FUL << ARM_SAI_SLOT_OFFSET_Pos)
|
||||
#define ARM_SAI_SLOT_OFFSET(n) (((n)&0x1FUL) << ARM_SAI_SLOT_OFFSET_Pos) ///< Offset of first data bit in slot (0..31); default=0; User Protocol only (ignored otherwise)
|
||||
|
||||
/****** SAI Configuration (arg2) *****/
|
||||
|
||||
/*----- SAI Control Codes: Configuration Parameters: Audio Frequency (Master only) -----*/
|
||||
#define ARM_SAI_AUDIO_FREQ_Msk (0x0FFFFFUL) ///< Audio frequency mask
|
||||
|
||||
/*----- SAI Control Codes: Configuration Parameters: Master Clock Prescaler (Master only and MCLK Pin) -----*/
|
||||
#define ARM_SAI_MCLK_PRESCALER_Pos 20
|
||||
#define ARM_SAI_MCLK_PRESCALER_Msk (0xFFFUL << ARM_SAI_MCLK_PRESCALER_Pos)
|
||||
#define ARM_SAI_MCLK_PRESCALER(n) ((((n)-1UL)&0xFFFUL) << ARM_SAI_MCLK_PRESCALER_Pos) ///< MCLK prescaler; Audio_frequency = MCLK/n; n = 1..4096 (default=1)
|
||||
|
||||
|
||||
/****** SAI specific error codes *****/
|
||||
#define ARM_SAI_ERROR_SYNCHRONIZATION (ARM_DRIVER_ERROR_SPECIFIC - 1) ///< Specified Synchronization not supported
|
||||
#define ARM_SAI_ERROR_PROTOCOL (ARM_DRIVER_ERROR_SPECIFIC - 2) ///< Specified Protocol not supported
|
||||
#define ARM_SAI_ERROR_DATA_SIZE (ARM_DRIVER_ERROR_SPECIFIC - 3) ///< Specified Data size not supported
|
||||
#define ARM_SAI_ERROR_BIT_ORDER (ARM_DRIVER_ERROR_SPECIFIC - 4) ///< Specified Bit order not supported
|
||||
#define ARM_SAI_ERROR_MONO_MODE (ARM_DRIVER_ERROR_SPECIFIC - 5) ///< Specified Mono mode not supported
|
||||
#define ARM_SAI_ERROR_COMPANDING (ARM_DRIVER_ERROR_SPECIFIC - 6) ///< Specified Companding not supported
|
||||
#define ARM_SAI_ERROR_CLOCK_POLARITY (ARM_DRIVER_ERROR_SPECIFIC - 7) ///< Specified Clock polarity not supported
|
||||
#define ARM_SAI_ERROR_AUDIO_FREQ (ARM_DRIVER_ERROR_SPECIFIC - 8) ///< Specified Audio frequency not supported
|
||||
#define ARM_SAI_ERROR_MCLK_PIN (ARM_DRIVER_ERROR_SPECIFIC - 9) ///< Specified MCLK Pin setting not supported
|
||||
#define ARM_SAI_ERROR_MCLK_PRESCALER (ARM_DRIVER_ERROR_SPECIFIC - 10) ///< Specified MCLK Prescaler not supported
|
||||
#define ARM_SAI_ERROR_FRAME_LENGTH (ARM_DRIVER_ERROR_SPECIFIC - 11) ///< Specified Frame length not supported
|
||||
#define ARM_SAI_ERROR_FRAME_LENGHT (ARM_DRIVER_ERROR_SPECIFIC - 11) ///< Specified Frame length not supported @deprecated use \ref ARM_SAI_ERROR_FRAME_LENGTH instead
|
||||
#define ARM_SAI_ERROR_FRAME_SYNC_WIDTH (ARM_DRIVER_ERROR_SPECIFIC - 12) ///< Specified Frame Sync width not supported
|
||||
#define ARM_SAI_ERROR_FRAME_SYNC_POLARITY (ARM_DRIVER_ERROR_SPECIFIC - 13) ///< Specified Frame Sync polarity not supported
|
||||
#define ARM_SAI_ERROR_FRAME_SYNC_EARLY (ARM_DRIVER_ERROR_SPECIFIC - 14) ///< Specified Frame Sync early not supported
|
||||
#define ARM_SAI_ERROR_SLOT_COUNT (ARM_DRIVER_ERROR_SPECIFIC - 15) ///< Specified Slot count not supported
|
||||
#define ARM_SAI_ERROR_SLOT_SIZE (ARM_DRIVER_ERROR_SPECIFIC - 16) ///< Specified Slot size not supported
|
||||
#define ARM_SAI_ERROR_SLOT_OFFESET (ARM_DRIVER_ERROR_SPECIFIC - 17) ///< Specified Slot offset not supported
|
||||
|
||||
|
||||
/**
|
||||
\brief SAI Status
|
||||
*/
|
||||
typedef struct _ARM_SAI_STATUS {
|
||||
uint32_t tx_busy : 1; ///< Transmitter busy flag
|
||||
uint32_t rx_busy : 1; ///< Receiver busy flag
|
||||
uint32_t tx_underflow : 1; ///< Transmit data underflow detected (cleared on start of next send operation)
|
||||
uint32_t rx_overflow : 1; ///< Receive data overflow detected (cleared on start of next receive operation)
|
||||
uint32_t frame_error : 1; ///< Sync Frame error detected (cleared on start of next send/receive operation)
|
||||
uint32_t reserved : 27;
|
||||
} ARM_SAI_STATUS;
|
||||
|
||||
|
||||
/****** SAI Event *****/
|
||||
#define ARM_SAI_EVENT_SEND_COMPLETE (1UL << 0) ///< Send completed
|
||||
#define ARM_SAI_EVENT_RECEIVE_COMPLETE (1UL << 1) ///< Receive completed
|
||||
#define ARM_SAI_EVENT_TX_UNDERFLOW (1UL << 2) ///< Transmit data not available
|
||||
#define ARM_SAI_EVENT_RX_OVERFLOW (1UL << 3) ///< Receive data overflow
|
||||
#define ARM_SAI_EVENT_FRAME_ERROR (1UL << 4) ///< Sync Frame error in Slave mode (optional)
|
||||
|
||||
|
||||
// Function documentation
|
||||
/**
|
||||
\fn ARM_DRIVER_VERSION ARM_SAI_GetVersion (void)
|
||||
\brief Get driver version.
|
||||
\return \ref ARM_DRIVER_VERSION
|
||||
|
||||
\fn ARM_SAI_CAPABILITIES ARM_SAI_GetCapabilities (void)
|
||||
\brief Get driver capabilities.
|
||||
\return \ref ARM_SAI_CAPABILITIES
|
||||
|
||||
\fn int32_t ARM_SAI_Initialize (ARM_SAI_SignalEvent_t cb_event)
|
||||
\brief Initialize SAI Interface.
|
||||
\param[in] cb_event Pointer to \ref ARM_SAI_SignalEvent
|
||||
\return \ref execution_status
|
||||
|
||||
\fn int32_t ARM_SAI_Uninitialize (void)
|
||||
\brief De-initialize SAI Interface.
|
||||
\return \ref execution_status
|
||||
|
||||
\fn int32_t ARM_SAI_PowerControl (ARM_POWER_STATE state)
|
||||
\brief Control SAI Interface Power.
|
||||
\param[in] state Power state
|
||||
\return \ref execution_status
|
||||
|
||||
\fn int32_t ARM_SAI_Send (const void *data, uint32_t num)
|
||||
\brief Start sending data to SAI transmitter.
|
||||
\param[in] data Pointer to buffer with data to send to SAI transmitter
|
||||
\param[in] num Number of data items to send
|
||||
\return \ref execution_status
|
||||
|
||||
\fn int32_t ARM_SAI_Receive (void *data, uint32_t num)
|
||||
\brief Start receiving data from SAI receiver.
|
||||
\param[out] data Pointer to buffer for data to receive from SAI receiver
|
||||
\param[in] num Number of data items to receive
|
||||
\return \ref execution_status
|
||||
|
||||
\fn uint32_t ARM_SAI_GetTxCount (void)
|
||||
\brief Get transmitted data count.
|
||||
\return number of data items transmitted
|
||||
|
||||
\fn uint32_t ARM_SAI_GetRxCount (void)
|
||||
\brief Get received data count.
|
||||
\return number of data items received
|
||||
|
||||
\fn int32_t ARM_SAI_Control (uint32_t control, uint32_t arg1, uint32_t arg2)
|
||||
\brief Control SAI Interface.
|
||||
\param[in] control Operation
|
||||
\param[in] arg1 Argument 1 of operation (optional)
|
||||
\param[in] arg2 Argument 2 of operation (optional)
|
||||
\return common \ref execution_status and driver specific \ref sai_execution_status
|
||||
|
||||
\fn ARM_SAI_STATUS ARM_SAI_GetStatus (void)
|
||||
\brief Get SAI status.
|
||||
\return SAI status \ref ARM_SAI_STATUS
|
||||
|
||||
\fn void ARM_SAI_SignalEvent (uint32_t event)
|
||||
\brief Signal SAI Events.
|
||||
\param[in] event \ref SAI_events notification mask
|
||||
\return none
|
||||
*/
|
||||
|
||||
typedef void (*ARM_SAI_SignalEvent_t) (uint32_t event); ///< Pointer to \ref ARM_SAI_SignalEvent : Signal SAI Event.
|
||||
|
||||
|
||||
/**
|
||||
\brief SAI Driver Capabilities.
|
||||
*/
|
||||
typedef struct _ARM_SAI_CAPABILITIES {
|
||||
uint32_t asynchronous : 1; ///< supports asynchronous Transmit/Receive
|
||||
uint32_t synchronous : 1; ///< supports synchronous Transmit/Receive
|
||||
uint32_t protocol_user : 1; ///< supports user defined Protocol
|
||||
uint32_t protocol_i2s : 1; ///< supports I2S Protocol
|
||||
uint32_t protocol_justified : 1; ///< supports MSB/LSB justified Protocol
|
||||
uint32_t protocol_pcm : 1; ///< supports PCM short/long frame Protocol
|
||||
uint32_t protocol_ac97 : 1; ///< supports AC'97 Protocol
|
||||
uint32_t mono_mode : 1; ///< supports Mono mode
|
||||
uint32_t companding : 1; ///< supports Companding
|
||||
uint32_t mclk_pin : 1; ///< supports MCLK (Master Clock) pin
|
||||
uint32_t event_frame_error : 1; ///< supports Frame error event: \ref ARM_SAI_EVENT_FRAME_ERROR
|
||||
uint32_t reserved : 21; ///< Reserved (must be zero)
|
||||
} ARM_SAI_CAPABILITIES;
|
||||
|
||||
|
||||
/**
|
||||
\brief Access structure of the SAI Driver.
|
||||
*/
|
||||
typedef struct _ARM_DRIVER_SAI {
|
||||
ARM_DRIVER_VERSION (*GetVersion) (void); ///< Pointer to \ref ARM_SAI_GetVersion : Get driver version.
|
||||
ARM_SAI_CAPABILITIES (*GetCapabilities) (void); ///< Pointer to \ref ARM_SAI_GetCapabilities : Get driver capabilities.
|
||||
int32_t (*Initialize) (ARM_SAI_SignalEvent_t cb_event); ///< Pointer to \ref ARM_SAI_Initialize : Initialize SAI Interface.
|
||||
int32_t (*Uninitialize) (void); ///< Pointer to \ref ARM_SAI_Uninitialize : De-initialize SAI Interface.
|
||||
int32_t (*PowerControl) (ARM_POWER_STATE state); ///< Pointer to \ref ARM_SAI_PowerControl : Control SAI Interface Power.
|
||||
int32_t (*Send) (const void *data, uint32_t num); ///< Pointer to \ref ARM_SAI_Send : Start sending data to SAI Interface.
|
||||
int32_t (*Receive) ( void *data, uint32_t num); ///< Pointer to \ref ARM_SAI_Receive : Start receiving data from SAI Interface.
|
||||
uint32_t (*GetTxCount) (void); ///< Pointer to \ref ARM_SAI_GetTxCount : Get transmitted data count.
|
||||
uint32_t (*GetRxCount) (void); ///< Pointer to \ref ARM_SAI_GetRxCount : Get received data count.
|
||||
int32_t (*Control) (uint32_t control, uint32_t arg1, uint32_t arg2); ///< Pointer to \ref ARM_SAI_Control : Control SAI Interface.
|
||||
ARM_SAI_STATUS (*GetStatus) (void); ///< Pointer to \ref ARM_SAI_GetStatus : Get SAI status.
|
||||
} const ARM_DRIVER_SAI;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* DRIVER_SAI_H_ */
|
||||
38
src/hal/alif/Alif_CMSIS/Include/Driver_SAI_EX.h
Normal file
38
src/hal/alif/Alif_CMSIS/Include/Driver_SAI_EX.h
Normal file
@ -0,0 +1,38 @@
|
||||
/* Copyright (C) 2023 Alif Semiconductor - All Rights Reserved.
|
||||
* Use, distribution and modification of this code is permitted under the
|
||||
* terms stated in the Alif Semiconductor Software License Agreement
|
||||
*
|
||||
* You should have received a copy of the Alif Semiconductor Software
|
||||
* License Agreement with this file. If not, please write to:
|
||||
* contact@alifsemi.com, or visit: https://alifsemi.com/license
|
||||
*
|
||||
*/
|
||||
|
||||
/**************************************************************************//**
|
||||
* @file Driver_SAI_EX.h
|
||||
* @author Sudhir Sreedharan
|
||||
* @email sudhir@alifsemi.com
|
||||
* @version V1.0.0
|
||||
* @date 30-Sep-2023
|
||||
* @brief Extended Header for SAI Driver
|
||||
* @bug None
|
||||
* @Note None
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef Driver_SAI_EX_H_
|
||||
#define Driver_SAI_EX_H_
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
/****** SAI Control Codes *****/
|
||||
#define ARM_SAI_USE_CUSTOM_DMA_MCODE_TX (0xA0UL) ///< Use User defined DMA microcode arg1 provides address
|
||||
#define ARM_SAI_USE_CUSTOM_DMA_MCODE_RX (0xA1UL) ///< Use User defined DMA microcode arg1 provides address
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* Driver_SAI_EX_H_ */
|
||||
254
src/hal/alif/Alif_CMSIS/Include/Driver_SPI.h
Normal file
254
src/hal/alif/Alif_CMSIS/Include/Driver_SPI.h
Normal file
@ -0,0 +1,254 @@
|
||||
/*
|
||||
* Copyright (c) 2013-2020 ARM Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* $Date: 31. March 2020
|
||||
* $Revision: V2.3
|
||||
*
|
||||
* Project: SPI (Serial Peripheral Interface) Driver definitions
|
||||
*/
|
||||
|
||||
/* History:
|
||||
* Version 2.3
|
||||
* Removed Simplex Mode (deprecated)
|
||||
* Removed volatile from ARM_SPI_STATUS
|
||||
* Version 2.2
|
||||
* ARM_SPI_STATUS made volatile
|
||||
* Version 2.1
|
||||
* Renamed status flag "tx_rx_busy" to "busy"
|
||||
* Version 2.0
|
||||
* New simplified driver:
|
||||
* complexity moved to upper layer (especially data handling)
|
||||
* more unified API for different communication interfaces
|
||||
* Added:
|
||||
* Slave Mode
|
||||
* Half-duplex Modes
|
||||
* Configurable number of data bits
|
||||
* Support for TI Mode and Microwire
|
||||
* Changed prefix ARM_DRV -> ARM_DRIVER
|
||||
* Version 1.10
|
||||
* Namespace prefix ARM_ added
|
||||
* Version 1.01
|
||||
* Added "send_done_event" to Capabilities
|
||||
* Version 1.00
|
||||
* Initial release
|
||||
*/
|
||||
|
||||
#ifndef DRIVER_SPI_H_
|
||||
#define DRIVER_SPI_H_
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
#include "Driver_Common.h"
|
||||
|
||||
#define ARM_SPI_API_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(2,3) /* API version */
|
||||
|
||||
|
||||
#define _ARM_Driver_SPI_(n) Driver_SPI##n
|
||||
#define ARM_Driver_SPI_(n) _ARM_Driver_SPI_(n)
|
||||
|
||||
|
||||
/****** SPI Control Codes *****/
|
||||
|
||||
#define ARM_SPI_CONTROL_Pos 0
|
||||
#define ARM_SPI_CONTROL_Msk (0xFFUL << ARM_SPI_CONTROL_Pos)
|
||||
|
||||
/*----- SPI Control Codes: Mode -----*/
|
||||
#define ARM_SPI_MODE_INACTIVE (0x00UL << ARM_SPI_CONTROL_Pos) ///< SPI Inactive
|
||||
#define ARM_SPI_MODE_MASTER (0x01UL << ARM_SPI_CONTROL_Pos) ///< SPI Master (Output on MOSI, Input on MISO); arg = Bus Speed in bps
|
||||
#define ARM_SPI_MODE_SLAVE (0x02UL << ARM_SPI_CONTROL_Pos) ///< SPI Slave (Output on MISO, Input on MOSI)
|
||||
#define ARM_SPI_MODE_MASTER_SIMPLEX (0x03UL << ARM_SPI_CONTROL_Pos) ///< SPI Master (Output/Input on MOSI); arg = Bus Speed in bps @deprecated Simplex Mode has been removed
|
||||
#define ARM_SPI_MODE_SLAVE_SIMPLEX (0x04UL << ARM_SPI_CONTROL_Pos) ///< SPI Slave (Output/Input on MISO) @deprecated Simplex Mode has been removed
|
||||
|
||||
/*----- SPI Control Codes: Mode Parameters: Frame Format -----*/
|
||||
#define ARM_SPI_FRAME_FORMAT_Pos 8
|
||||
#define ARM_SPI_FRAME_FORMAT_Msk (7UL << ARM_SPI_FRAME_FORMAT_Pos)
|
||||
#define ARM_SPI_CPOL0_CPHA0 (0UL << ARM_SPI_FRAME_FORMAT_Pos) ///< Clock Polarity 0, Clock Phase 0 (default)
|
||||
#define ARM_SPI_CPOL0_CPHA1 (1UL << ARM_SPI_FRAME_FORMAT_Pos) ///< Clock Polarity 0, Clock Phase 1
|
||||
#define ARM_SPI_CPOL1_CPHA0 (2UL << ARM_SPI_FRAME_FORMAT_Pos) ///< Clock Polarity 1, Clock Phase 0
|
||||
#define ARM_SPI_CPOL1_CPHA1 (3UL << ARM_SPI_FRAME_FORMAT_Pos) ///< Clock Polarity 1, Clock Phase 1
|
||||
#define ARM_SPI_TI_SSI (4UL << ARM_SPI_FRAME_FORMAT_Pos) ///< Texas Instruments Frame Format
|
||||
#define ARM_SPI_MICROWIRE (5UL << ARM_SPI_FRAME_FORMAT_Pos) ///< National Semiconductor Microwire Frame Format
|
||||
|
||||
/*----- SPI Control Codes: Mode Parameters: Data Bits -----*/
|
||||
#define ARM_SPI_DATA_BITS_Pos 12
|
||||
#define ARM_SPI_DATA_BITS_Msk (0x3FUL << ARM_SPI_DATA_BITS_Pos)
|
||||
#define ARM_SPI_DATA_BITS(n) (((n) & 0x3FUL) << ARM_SPI_DATA_BITS_Pos) ///< Number of Data bits
|
||||
|
||||
/*----- SPI Control Codes: Mode Parameters: Bit Order -----*/
|
||||
#define ARM_SPI_BIT_ORDER_Pos 18
|
||||
#define ARM_SPI_BIT_ORDER_Msk (1UL << ARM_SPI_BIT_ORDER_Pos)
|
||||
#define ARM_SPI_MSB_LSB (0UL << ARM_SPI_BIT_ORDER_Pos) ///< SPI Bit order from MSB to LSB (default)
|
||||
#define ARM_SPI_LSB_MSB (1UL << ARM_SPI_BIT_ORDER_Pos) ///< SPI Bit order from LSB to MSB
|
||||
|
||||
/*----- SPI Control Codes: Mode Parameters: Slave Select Mode -----*/
|
||||
#define ARM_SPI_SS_MASTER_MODE_Pos 19
|
||||
#define ARM_SPI_SS_MASTER_MODE_Msk (3UL << ARM_SPI_SS_MASTER_MODE_Pos)
|
||||
#define ARM_SPI_SS_MASTER_UNUSED (0UL << ARM_SPI_SS_MASTER_MODE_Pos) ///< SPI Slave Select when Master: Not used (default)
|
||||
#define ARM_SPI_SS_MASTER_SW (1UL << ARM_SPI_SS_MASTER_MODE_Pos) ///< SPI Slave Select when Master: Software controlled
|
||||
#define ARM_SPI_SS_MASTER_HW_OUTPUT (2UL << ARM_SPI_SS_MASTER_MODE_Pos) ///< SPI Slave Select when Master: Hardware controlled Output
|
||||
#define ARM_SPI_SS_MASTER_HW_INPUT (3UL << ARM_SPI_SS_MASTER_MODE_Pos) ///< SPI Slave Select when Master: Hardware monitored Input
|
||||
#define ARM_SPI_SS_SLAVE_MODE_Pos 21
|
||||
#define ARM_SPI_SS_SLAVE_MODE_Msk (1UL << ARM_SPI_SS_SLAVE_MODE_Pos)
|
||||
#define ARM_SPI_SS_SLAVE_HW (0UL << ARM_SPI_SS_SLAVE_MODE_Pos) ///< SPI Slave Select when Slave: Hardware monitored (default)
|
||||
#define ARM_SPI_SS_SLAVE_SW (1UL << ARM_SPI_SS_SLAVE_MODE_Pos) ///< SPI Slave Select when Slave: Software controlled
|
||||
|
||||
|
||||
/*----- SPI Control Codes: Miscellaneous Controls -----*/
|
||||
#define ARM_SPI_SET_BUS_SPEED (0x10UL << ARM_SPI_CONTROL_Pos) ///< Set Bus Speed in bps; arg = value
|
||||
#define ARM_SPI_GET_BUS_SPEED (0x11UL << ARM_SPI_CONTROL_Pos) ///< Get Bus Speed in bps
|
||||
#define ARM_SPI_SET_DEFAULT_TX_VALUE (0x12UL << ARM_SPI_CONTROL_Pos) ///< Set default Transmit value; arg = value
|
||||
#define ARM_SPI_CONTROL_SS (0x13UL << ARM_SPI_CONTROL_Pos) ///< Control Slave Select; arg: 0=inactive, 1=active
|
||||
#define ARM_SPI_ABORT_TRANSFER (0x14UL << ARM_SPI_CONTROL_Pos) ///< Abort current data transfer
|
||||
|
||||
|
||||
/****** SPI Slave Select Signal definitions *****/
|
||||
#define ARM_SPI_SS_INACTIVE 0UL ///< SPI Slave Select Signal Inactive
|
||||
#define ARM_SPI_SS_ACTIVE 1UL ///< SPI Slave Select Signal Active
|
||||
|
||||
|
||||
/****** SPI specific error codes *****/
|
||||
#define ARM_SPI_ERROR_MODE (ARM_DRIVER_ERROR_SPECIFIC - 1) ///< Specified Mode not supported
|
||||
#define ARM_SPI_ERROR_FRAME_FORMAT (ARM_DRIVER_ERROR_SPECIFIC - 2) ///< Specified Frame Format not supported
|
||||
#define ARM_SPI_ERROR_DATA_BITS (ARM_DRIVER_ERROR_SPECIFIC - 3) ///< Specified number of Data bits not supported
|
||||
#define ARM_SPI_ERROR_BIT_ORDER (ARM_DRIVER_ERROR_SPECIFIC - 4) ///< Specified Bit order not supported
|
||||
#define ARM_SPI_ERROR_SS_MODE (ARM_DRIVER_ERROR_SPECIFIC - 5) ///< Specified Slave Select Mode not supported
|
||||
|
||||
|
||||
/**
|
||||
\brief SPI Status
|
||||
*/
|
||||
typedef struct _ARM_SPI_STATUS {
|
||||
uint32_t busy : 1; ///< Transmitter/Receiver busy flag
|
||||
uint32_t data_lost : 1; ///< Data lost: Receive overflow / Transmit underflow (cleared on start of transfer operation)
|
||||
uint32_t mode_fault : 1; ///< Mode fault detected; optional (cleared on start of transfer operation)
|
||||
uint32_t reserved : 29;
|
||||
} ARM_SPI_STATUS;
|
||||
|
||||
|
||||
/****** SPI Event *****/
|
||||
#define ARM_SPI_EVENT_TRANSFER_COMPLETE (1UL << 0) ///< Data Transfer completed
|
||||
#define ARM_SPI_EVENT_DATA_LOST (1UL << 1) ///< Data lost: Receive overflow / Transmit underflow
|
||||
#define ARM_SPI_EVENT_MODE_FAULT (1UL << 2) ///< Master Mode Fault (SS deactivated when Master)
|
||||
|
||||
|
||||
// Function documentation
|
||||
/**
|
||||
\fn ARM_DRIVER_VERSION ARM_SPI_GetVersion (void)
|
||||
\brief Get driver version.
|
||||
\return \ref ARM_DRIVER_VERSION
|
||||
|
||||
\fn ARM_SPI_CAPABILITIES ARM_SPI_GetCapabilities (void)
|
||||
\brief Get driver capabilities.
|
||||
\return \ref ARM_SPI_CAPABILITIES
|
||||
|
||||
\fn int32_t ARM_SPI_Initialize (ARM_SPI_SignalEvent_t cb_event)
|
||||
\brief Initialize SPI Interface.
|
||||
\param[in] cb_event Pointer to \ref ARM_SPI_SignalEvent
|
||||
\return \ref execution_status
|
||||
|
||||
\fn int32_t ARM_SPI_Uninitialize (void)
|
||||
\brief De-initialize SPI Interface.
|
||||
\return \ref execution_status
|
||||
|
||||
\fn int32_t ARM_SPI_PowerControl (ARM_POWER_STATE state)
|
||||
\brief Control SPI Interface Power.
|
||||
\param[in] state Power state
|
||||
\return \ref execution_status
|
||||
|
||||
\fn int32_t ARM_SPI_Send (const void *data, uint32_t num)
|
||||
\brief Start sending data to SPI transmitter.
|
||||
\param[in] data Pointer to buffer with data to send to SPI transmitter
|
||||
\param[in] num Number of data items to send
|
||||
\return \ref execution_status
|
||||
|
||||
\fn int32_t ARM_SPI_Receive (void *data, uint32_t num)
|
||||
\brief Start receiving data from SPI receiver.
|
||||
\param[out] data Pointer to buffer for data to receive from SPI receiver
|
||||
\param[in] num Number of data items to receive
|
||||
\return \ref execution_status
|
||||
|
||||
\fn int32_t ARM_SPI_Transfer (const void *data_out,
|
||||
void *data_in,
|
||||
uint32_t num)
|
||||
\brief Start sending/receiving data to/from SPI transmitter/receiver.
|
||||
\param[in] data_out Pointer to buffer with data to send to SPI transmitter
|
||||
\param[out] data_in Pointer to buffer for data to receive from SPI receiver
|
||||
\param[in] num Number of data items to transfer
|
||||
\return \ref execution_status
|
||||
|
||||
\fn uint32_t ARM_SPI_GetDataCount (void)
|
||||
\brief Get transferred data count.
|
||||
\return number of data items transferred
|
||||
|
||||
\fn int32_t ARM_SPI_Control (uint32_t control, uint32_t arg)
|
||||
\brief Control SPI Interface.
|
||||
\param[in] control Operation
|
||||
\param[in] arg Argument of operation (optional)
|
||||
\return common \ref execution_status and driver specific \ref spi_execution_status
|
||||
|
||||
\fn ARM_SPI_STATUS ARM_SPI_GetStatus (void)
|
||||
\brief Get SPI status.
|
||||
\return SPI status \ref ARM_SPI_STATUS
|
||||
|
||||
\fn void ARM_SPI_SignalEvent (uint32_t event)
|
||||
\brief Signal SPI Events.
|
||||
\param[in] event \ref SPI_events notification mask
|
||||
\return none
|
||||
*/
|
||||
|
||||
typedef void (*ARM_SPI_SignalEvent_t) (uint32_t event); ///< Pointer to \ref ARM_SPI_SignalEvent : Signal SPI Event.
|
||||
|
||||
|
||||
/**
|
||||
\brief SPI Driver Capabilities.
|
||||
*/
|
||||
typedef struct _ARM_SPI_CAPABILITIES {
|
||||
uint32_t simplex : 1; ///< supports Simplex Mode (Master and Slave) @deprecated Reserved (must be zero)
|
||||
uint32_t ti_ssi : 1; ///< supports TI Synchronous Serial Interface
|
||||
uint32_t microwire : 1; ///< supports Microwire Interface
|
||||
uint32_t event_mode_fault : 1; ///< Signal Mode Fault event: \ref ARM_SPI_EVENT_MODE_FAULT
|
||||
uint32_t reserved : 28; ///< Reserved (must be zero)
|
||||
} ARM_SPI_CAPABILITIES;
|
||||
|
||||
|
||||
/**
|
||||
\brief Access structure of the SPI Driver.
|
||||
*/
|
||||
typedef struct _ARM_DRIVER_SPI {
|
||||
ARM_DRIVER_VERSION (*GetVersion) (void); ///< Pointer to \ref ARM_SPI_GetVersion : Get driver version.
|
||||
ARM_SPI_CAPABILITIES (*GetCapabilities) (void); ///< Pointer to \ref ARM_SPI_GetCapabilities : Get driver capabilities.
|
||||
int32_t (*Initialize) (ARM_SPI_SignalEvent_t cb_event); ///< Pointer to \ref ARM_SPI_Initialize : Initialize SPI Interface.
|
||||
int32_t (*Uninitialize) (void); ///< Pointer to \ref ARM_SPI_Uninitialize : De-initialize SPI Interface.
|
||||
int32_t (*PowerControl) (ARM_POWER_STATE state); ///< Pointer to \ref ARM_SPI_PowerControl : Control SPI Interface Power.
|
||||
int32_t (*Send) (const void *data, uint32_t num); ///< Pointer to \ref ARM_SPI_Send : Start sending data to SPI Interface.
|
||||
int32_t (*Receive) ( void *data, uint32_t num); ///< Pointer to \ref ARM_SPI_Receive : Start receiving data from SPI Interface.
|
||||
int32_t (*Transfer) (const void *data_out,
|
||||
void *data_in,
|
||||
uint32_t num); ///< Pointer to \ref ARM_SPI_Transfer : Start sending/receiving data to/from SPI.
|
||||
uint32_t (*GetDataCount) (void); ///< Pointer to \ref ARM_SPI_GetDataCount : Get transferred data count.
|
||||
int32_t (*Control) (uint32_t control, uint32_t arg); ///< Pointer to \ref ARM_SPI_Control : Control SPI Interface.
|
||||
ARM_SPI_STATUS (*GetStatus) (void); ///< Pointer to \ref ARM_SPI_GetStatus : Get SPI status.
|
||||
} const ARM_DRIVER_SPI;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* DRIVER_SPI_H_ */
|
||||
347
src/hal/alif/Alif_CMSIS/Include/Driver_USART.h
Normal file
347
src/hal/alif/Alif_CMSIS/Include/Driver_USART.h
Normal file
@ -0,0 +1,347 @@
|
||||
/*
|
||||
* Copyright (c) 2013-2020 ARM Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* $Date: 31. March 2020
|
||||
* $Revision: V2.4
|
||||
*
|
||||
* Project: USART (Universal Synchronous Asynchronous Receiver Transmitter)
|
||||
* Driver definitions
|
||||
*/
|
||||
|
||||
/* History:
|
||||
* Version 2.4
|
||||
* Removed volatile from ARM_USART_STATUS and ARM_USART_MODEM_STATUS
|
||||
* Version 2.3
|
||||
* ARM_USART_STATUS and ARM_USART_MODEM_STATUS made volatile
|
||||
* Version 2.2
|
||||
* Corrected ARM_USART_CPOL_Pos and ARM_USART_CPHA_Pos definitions
|
||||
* Version 2.1
|
||||
* Removed optional argument parameter from Signal Event
|
||||
* Version 2.0
|
||||
* New simplified driver:
|
||||
* complexity moved to upper layer (especially data handling)
|
||||
* more unified API for different communication interfaces
|
||||
* renamed driver UART -> USART (Asynchronous & Synchronous)
|
||||
* Added modes:
|
||||
* Synchronous
|
||||
* Single-wire
|
||||
* IrDA
|
||||
* Smart Card
|
||||
* Changed prefix ARM_DRV -> ARM_DRIVER
|
||||
* Version 1.10
|
||||
* Namespace prefix ARM_ added
|
||||
* Version 1.01
|
||||
* Added events:
|
||||
* ARM_UART_EVENT_TX_EMPTY, ARM_UART_EVENT_RX_TIMEOUT
|
||||
* ARM_UART_EVENT_TX_THRESHOLD, ARM_UART_EVENT_RX_THRESHOLD
|
||||
* Added functions: SetTxThreshold, SetRxThreshold
|
||||
* Added "rx_timeout_event" to capabilities
|
||||
* Version 1.00
|
||||
* Initial release
|
||||
*/
|
||||
|
||||
#ifndef DRIVER_USART_H_
|
||||
#define DRIVER_USART_H_
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
#include "Driver_Common.h"
|
||||
|
||||
#define ARM_USART_API_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(2,4) /* API version */
|
||||
|
||||
|
||||
#define _ARM_Driver_USART_(n) Driver_USART##n
|
||||
#define ARM_Driver_USART_(n) _ARM_Driver_USART_(n)
|
||||
|
||||
|
||||
/****** USART Control Codes *****/
|
||||
|
||||
#define ARM_USART_CONTROL_Pos 0
|
||||
#define ARM_USART_CONTROL_Msk (0xFFUL << ARM_USART_CONTROL_Pos)
|
||||
|
||||
/*----- USART Control Codes: Mode -----*/
|
||||
#define ARM_USART_MODE_ASYNCHRONOUS (0x01UL << ARM_USART_CONTROL_Pos) ///< UART (Asynchronous); arg = Baudrate
|
||||
#define ARM_USART_MODE_SYNCHRONOUS_MASTER (0x02UL << ARM_USART_CONTROL_Pos) ///< Synchronous Master (generates clock signal); arg = Baudrate
|
||||
#define ARM_USART_MODE_SYNCHRONOUS_SLAVE (0x03UL << ARM_USART_CONTROL_Pos) ///< Synchronous Slave (external clock signal)
|
||||
#define ARM_USART_MODE_SINGLE_WIRE (0x04UL << ARM_USART_CONTROL_Pos) ///< UART Single-wire (half-duplex); arg = Baudrate
|
||||
#define ARM_USART_MODE_IRDA (0x05UL << ARM_USART_CONTROL_Pos) ///< UART IrDA; arg = Baudrate
|
||||
#define ARM_USART_MODE_SMART_CARD (0x06UL << ARM_USART_CONTROL_Pos) ///< UART Smart Card; arg = Baudrate
|
||||
|
||||
/*----- USART Control Codes: Mode Parameters: Data Bits -----*/
|
||||
#define ARM_USART_DATA_BITS_Pos 8
|
||||
#define ARM_USART_DATA_BITS_Msk (7UL << ARM_USART_DATA_BITS_Pos)
|
||||
#define ARM_USART_DATA_BITS_5 (5UL << ARM_USART_DATA_BITS_Pos) ///< 5 Data bits
|
||||
#define ARM_USART_DATA_BITS_6 (6UL << ARM_USART_DATA_BITS_Pos) ///< 6 Data bit
|
||||
#define ARM_USART_DATA_BITS_7 (7UL << ARM_USART_DATA_BITS_Pos) ///< 7 Data bits
|
||||
#define ARM_USART_DATA_BITS_8 (0UL << ARM_USART_DATA_BITS_Pos) ///< 8 Data bits (default)
|
||||
#define ARM_USART_DATA_BITS_9 (1UL << ARM_USART_DATA_BITS_Pos) ///< 9 Data bits
|
||||
|
||||
/*----- USART Control Codes: Mode Parameters: Parity -----*/
|
||||
#define ARM_USART_PARITY_Pos 12
|
||||
#define ARM_USART_PARITY_Msk (3UL << ARM_USART_PARITY_Pos)
|
||||
#define ARM_USART_PARITY_NONE (0UL << ARM_USART_PARITY_Pos) ///< No Parity (default)
|
||||
#define ARM_USART_PARITY_EVEN (1UL << ARM_USART_PARITY_Pos) ///< Even Parity
|
||||
#define ARM_USART_PARITY_ODD (2UL << ARM_USART_PARITY_Pos) ///< Odd Parity
|
||||
|
||||
/*----- USART Control Codes: Mode Parameters: Stop Bits -----*/
|
||||
#define ARM_USART_STOP_BITS_Pos 14
|
||||
#define ARM_USART_STOP_BITS_Msk (3UL << ARM_USART_STOP_BITS_Pos)
|
||||
#define ARM_USART_STOP_BITS_1 (0UL << ARM_USART_STOP_BITS_Pos) ///< 1 Stop bit (default)
|
||||
#define ARM_USART_STOP_BITS_2 (1UL << ARM_USART_STOP_BITS_Pos) ///< 2 Stop bits
|
||||
#define ARM_USART_STOP_BITS_1_5 (2UL << ARM_USART_STOP_BITS_Pos) ///< 1.5 Stop bits
|
||||
#define ARM_USART_STOP_BITS_0_5 (3UL << ARM_USART_STOP_BITS_Pos) ///< 0.5 Stop bits
|
||||
|
||||
/*----- USART Control Codes: Mode Parameters: Flow Control -----*/
|
||||
#define ARM_USART_FLOW_CONTROL_Pos 16
|
||||
#define ARM_USART_FLOW_CONTROL_Msk (3UL << ARM_USART_FLOW_CONTROL_Pos)
|
||||
#define ARM_USART_FLOW_CONTROL_NONE (0UL << ARM_USART_FLOW_CONTROL_Pos) ///< No Flow Control (default)
|
||||
#define ARM_USART_FLOW_CONTROL_RTS (1UL << ARM_USART_FLOW_CONTROL_Pos) ///< RTS Flow Control
|
||||
#define ARM_USART_FLOW_CONTROL_CTS (2UL << ARM_USART_FLOW_CONTROL_Pos) ///< CTS Flow Control
|
||||
#define ARM_USART_FLOW_CONTROL_RTS_CTS (3UL << ARM_USART_FLOW_CONTROL_Pos) ///< RTS/CTS Flow Control
|
||||
|
||||
/*----- USART Control Codes: Mode Parameters: Clock Polarity (Synchronous mode) -----*/
|
||||
#define ARM_USART_CPOL_Pos 18
|
||||
#define ARM_USART_CPOL_Msk (1UL << ARM_USART_CPOL_Pos)
|
||||
#define ARM_USART_CPOL0 (0UL << ARM_USART_CPOL_Pos) ///< CPOL = 0 (default)
|
||||
#define ARM_USART_CPOL1 (1UL << ARM_USART_CPOL_Pos) ///< CPOL = 1
|
||||
|
||||
/*----- USART Control Codes: Mode Parameters: Clock Phase (Synchronous mode) -----*/
|
||||
#define ARM_USART_CPHA_Pos 19
|
||||
#define ARM_USART_CPHA_Msk (1UL << ARM_USART_CPHA_Pos)
|
||||
#define ARM_USART_CPHA0 (0UL << ARM_USART_CPHA_Pos) ///< CPHA = 0 (default)
|
||||
#define ARM_USART_CPHA1 (1UL << ARM_USART_CPHA_Pos) ///< CPHA = 1
|
||||
|
||||
|
||||
/*----- USART Control Codes: Miscellaneous Controls -----*/
|
||||
#define ARM_USART_SET_DEFAULT_TX_VALUE (0x10UL << ARM_USART_CONTROL_Pos) ///< Set default Transmit value (Synchronous Receive only); arg = value
|
||||
#define ARM_USART_SET_IRDA_PULSE (0x11UL << ARM_USART_CONTROL_Pos) ///< Set IrDA Pulse in ns; arg: 0=3/16 of bit period
|
||||
#define ARM_USART_SET_SMART_CARD_GUARD_TIME (0x12UL << ARM_USART_CONTROL_Pos) ///< Set Smart Card Guard Time; arg = number of bit periods
|
||||
#define ARM_USART_SET_SMART_CARD_CLOCK (0x13UL << ARM_USART_CONTROL_Pos) ///< Set Smart Card Clock in Hz; arg: 0=Clock not generated
|
||||
#define ARM_USART_CONTROL_SMART_CARD_NACK (0x14UL << ARM_USART_CONTROL_Pos) ///< Smart Card NACK generation; arg: 0=disabled, 1=enabled
|
||||
#define ARM_USART_CONTROL_TX (0x15UL << ARM_USART_CONTROL_Pos) ///< Transmitter; arg: 0=disabled, 1=enabled
|
||||
#define ARM_USART_CONTROL_RX (0x16UL << ARM_USART_CONTROL_Pos) ///< Receiver; arg: 0=disabled, 1=enabled
|
||||
#define ARM_USART_CONTROL_BREAK (0x17UL << ARM_USART_CONTROL_Pos) ///< Continuous Break transmission; arg: 0=disabled, 1=enabled
|
||||
#define ARM_USART_ABORT_SEND (0x18UL << ARM_USART_CONTROL_Pos) ///< Abort \ref ARM_USART_Send
|
||||
#define ARM_USART_ABORT_RECEIVE (0x19UL << ARM_USART_CONTROL_Pos) ///< Abort \ref ARM_USART_Receive
|
||||
#define ARM_USART_ABORT_TRANSFER (0x1AUL << ARM_USART_CONTROL_Pos) ///< Abort \ref ARM_USART_Transfer
|
||||
|
||||
|
||||
|
||||
/****** USART specific error codes *****/
|
||||
#define ARM_USART_ERROR_MODE (ARM_DRIVER_ERROR_SPECIFIC - 1) ///< Specified Mode not supported
|
||||
#define ARM_USART_ERROR_BAUDRATE (ARM_DRIVER_ERROR_SPECIFIC - 2) ///< Specified baudrate not supported
|
||||
#define ARM_USART_ERROR_DATA_BITS (ARM_DRIVER_ERROR_SPECIFIC - 3) ///< Specified number of Data bits not supported
|
||||
#define ARM_USART_ERROR_PARITY (ARM_DRIVER_ERROR_SPECIFIC - 4) ///< Specified Parity not supported
|
||||
#define ARM_USART_ERROR_STOP_BITS (ARM_DRIVER_ERROR_SPECIFIC - 5) ///< Specified number of Stop bits not supported
|
||||
#define ARM_USART_ERROR_FLOW_CONTROL (ARM_DRIVER_ERROR_SPECIFIC - 6) ///< Specified Flow Control not supported
|
||||
#define ARM_USART_ERROR_CPOL (ARM_DRIVER_ERROR_SPECIFIC - 7) ///< Specified Clock Polarity not supported
|
||||
#define ARM_USART_ERROR_CPHA (ARM_DRIVER_ERROR_SPECIFIC - 8) ///< Specified Clock Phase not supported
|
||||
|
||||
|
||||
/**
|
||||
\brief USART Status
|
||||
*/
|
||||
typedef struct _ARM_USART_STATUS {
|
||||
uint32_t tx_busy : 1; ///< Transmitter busy flag
|
||||
uint32_t rx_busy : 1; ///< Receiver busy flag
|
||||
uint32_t tx_underflow : 1; ///< Transmit data underflow detected (cleared on start of next send operation)
|
||||
uint32_t rx_overflow : 1; ///< Receive data overflow detected (cleared on start of next receive operation)
|
||||
uint32_t rx_break : 1; ///< Break detected on receive (cleared on start of next receive operation)
|
||||
uint32_t rx_framing_error : 1; ///< Framing error detected on receive (cleared on start of next receive operation)
|
||||
uint32_t rx_parity_error : 1; ///< Parity error detected on receive (cleared on start of next receive operation)
|
||||
uint32_t reserved : 25;
|
||||
} ARM_USART_STATUS;
|
||||
|
||||
/**
|
||||
\brief USART Modem Control
|
||||
*/
|
||||
typedef enum _ARM_USART_MODEM_CONTROL {
|
||||
ARM_USART_RTS_CLEAR, ///< Deactivate RTS
|
||||
ARM_USART_RTS_SET, ///< Activate RTS
|
||||
ARM_USART_DTR_CLEAR, ///< Deactivate DTR
|
||||
ARM_USART_DTR_SET ///< Activate DTR
|
||||
} ARM_USART_MODEM_CONTROL;
|
||||
|
||||
/**
|
||||
\brief USART Modem Status
|
||||
*/
|
||||
typedef struct _ARM_USART_MODEM_STATUS {
|
||||
uint32_t cts : 1; ///< CTS state: 1=Active, 0=Inactive
|
||||
uint32_t dsr : 1; ///< DSR state: 1=Active, 0=Inactive
|
||||
uint32_t dcd : 1; ///< DCD state: 1=Active, 0=Inactive
|
||||
uint32_t ri : 1; ///< RI state: 1=Active, 0=Inactive
|
||||
uint32_t reserved : 28;
|
||||
} ARM_USART_MODEM_STATUS;
|
||||
|
||||
|
||||
/****** USART Event *****/
|
||||
#define ARM_USART_EVENT_SEND_COMPLETE (1UL << 0) ///< Send completed; however USART may still transmit data
|
||||
#define ARM_USART_EVENT_RECEIVE_COMPLETE (1UL << 1) ///< Receive completed
|
||||
#define ARM_USART_EVENT_TRANSFER_COMPLETE (1UL << 2) ///< Transfer completed
|
||||
#define ARM_USART_EVENT_TX_COMPLETE (1UL << 3) ///< Transmit completed (optional)
|
||||
#define ARM_USART_EVENT_TX_UNDERFLOW (1UL << 4) ///< Transmit data not available (Synchronous Slave)
|
||||
#define ARM_USART_EVENT_RX_OVERFLOW (1UL << 5) ///< Receive data overflow
|
||||
#define ARM_USART_EVENT_RX_TIMEOUT (1UL << 6) ///< Receive character timeout (optional)
|
||||
#define ARM_USART_EVENT_RX_BREAK (1UL << 7) ///< Break detected on receive
|
||||
#define ARM_USART_EVENT_RX_FRAMING_ERROR (1UL << 8) ///< Framing error detected on receive
|
||||
#define ARM_USART_EVENT_RX_PARITY_ERROR (1UL << 9) ///< Parity error detected on receive
|
||||
#define ARM_USART_EVENT_CTS (1UL << 10) ///< CTS state changed (optional)
|
||||
#define ARM_USART_EVENT_DSR (1UL << 11) ///< DSR state changed (optional)
|
||||
#define ARM_USART_EVENT_DCD (1UL << 12) ///< DCD state changed (optional)
|
||||
#define ARM_USART_EVENT_RI (1UL << 13) ///< RI state changed (optional)
|
||||
|
||||
|
||||
// Function documentation
|
||||
/**
|
||||
\fn ARM_DRIVER_VERSION ARM_USART_GetVersion (void)
|
||||
\brief Get driver version.
|
||||
\return \ref ARM_DRIVER_VERSION
|
||||
|
||||
\fn ARM_USART_CAPABILITIES ARM_USART_GetCapabilities (void)
|
||||
\brief Get driver capabilities
|
||||
\return \ref ARM_USART_CAPABILITIES
|
||||
|
||||
\fn int32_t ARM_USART_Initialize (ARM_USART_SignalEvent_t cb_event)
|
||||
\brief Initialize USART Interface.
|
||||
\param[in] cb_event Pointer to \ref ARM_USART_SignalEvent
|
||||
\return \ref execution_status
|
||||
|
||||
\fn int32_t ARM_USART_Uninitialize (void)
|
||||
\brief De-initialize USART Interface.
|
||||
\return \ref execution_status
|
||||
|
||||
\fn int32_t ARM_USART_PowerControl (ARM_POWER_STATE state)
|
||||
\brief Control USART Interface Power.
|
||||
\param[in] state Power state
|
||||
\return \ref execution_status
|
||||
|
||||
\fn int32_t ARM_USART_Send (const void *data, uint32_t num)
|
||||
\brief Start sending data to USART transmitter.
|
||||
\param[in] data Pointer to buffer with data to send to USART transmitter
|
||||
\param[in] num Number of data items to send
|
||||
\return \ref execution_status
|
||||
|
||||
\fn int32_t ARM_USART_Receive (void *data, uint32_t num)
|
||||
\brief Start receiving data from USART receiver.
|
||||
\param[out] data Pointer to buffer for data to receive from USART receiver
|
||||
\param[in] num Number of data items to receive
|
||||
\return \ref execution_status
|
||||
|
||||
\fn int32_t ARM_USART_Transfer (const void *data_out,
|
||||
void *data_in,
|
||||
uint32_t num)
|
||||
\brief Start sending/receiving data to/from USART transmitter/receiver.
|
||||
\param[in] data_out Pointer to buffer with data to send to USART transmitter
|
||||
\param[out] data_in Pointer to buffer for data to receive from USART receiver
|
||||
\param[in] num Number of data items to transfer
|
||||
\return \ref execution_status
|
||||
|
||||
\fn uint32_t ARM_USART_GetTxCount (void)
|
||||
\brief Get transmitted data count.
|
||||
\return number of data items transmitted
|
||||
|
||||
\fn uint32_t ARM_USART_GetRxCount (void)
|
||||
\brief Get received data count.
|
||||
\return number of data items received
|
||||
|
||||
\fn int32_t ARM_USART_Control (uint32_t control, uint32_t arg)
|
||||
\brief Control USART Interface.
|
||||
\param[in] control Operation
|
||||
\param[in] arg Argument of operation (optional)
|
||||
\return common \ref execution_status and driver specific \ref usart_execution_status
|
||||
|
||||
\fn ARM_USART_STATUS ARM_USART_GetStatus (void)
|
||||
\brief Get USART status.
|
||||
\return USART status \ref ARM_USART_STATUS
|
||||
|
||||
\fn int32_t ARM_USART_SetModemControl (ARM_USART_MODEM_CONTROL control)
|
||||
\brief Set USART Modem Control line state.
|
||||
\param[in] control \ref ARM_USART_MODEM_CONTROL
|
||||
\return \ref execution_status
|
||||
|
||||
\fn ARM_USART_MODEM_STATUS ARM_USART_GetModemStatus (void)
|
||||
\brief Get USART Modem Status lines state.
|
||||
\return modem status \ref ARM_USART_MODEM_STATUS
|
||||
|
||||
\fn void ARM_USART_SignalEvent (uint32_t event)
|
||||
\brief Signal USART Events.
|
||||
\param[in] event \ref USART_events notification mask
|
||||
\return none
|
||||
*/
|
||||
|
||||
typedef void (*ARM_USART_SignalEvent_t) (uint32_t event); ///< Pointer to \ref ARM_USART_SignalEvent : Signal USART Event.
|
||||
|
||||
|
||||
/**
|
||||
\brief USART Device Driver Capabilities.
|
||||
*/
|
||||
typedef struct _ARM_USART_CAPABILITIES {
|
||||
uint32_t asynchronous : 1; ///< supports UART (Asynchronous) mode
|
||||
uint32_t synchronous_master : 1; ///< supports Synchronous Master mode
|
||||
uint32_t synchronous_slave : 1; ///< supports Synchronous Slave mode
|
||||
uint32_t single_wire : 1; ///< supports UART Single-wire mode
|
||||
uint32_t irda : 1; ///< supports UART IrDA mode
|
||||
uint32_t smart_card : 1; ///< supports UART Smart Card mode
|
||||
uint32_t smart_card_clock : 1; ///< Smart Card Clock generator available
|
||||
uint32_t flow_control_rts : 1; ///< RTS Flow Control available
|
||||
uint32_t flow_control_cts : 1; ///< CTS Flow Control available
|
||||
uint32_t event_tx_complete : 1; ///< Transmit completed event: \ref ARM_USART_EVENT_TX_COMPLETE
|
||||
uint32_t event_rx_timeout : 1; ///< Signal receive character timeout event: \ref ARM_USART_EVENT_RX_TIMEOUT
|
||||
uint32_t rts : 1; ///< RTS Line: 0=not available, 1=available
|
||||
uint32_t cts : 1; ///< CTS Line: 0=not available, 1=available
|
||||
uint32_t dtr : 1; ///< DTR Line: 0=not available, 1=available
|
||||
uint32_t dsr : 1; ///< DSR Line: 0=not available, 1=available
|
||||
uint32_t dcd : 1; ///< DCD Line: 0=not available, 1=available
|
||||
uint32_t ri : 1; ///< RI Line: 0=not available, 1=available
|
||||
uint32_t event_cts : 1; ///< Signal CTS change event: \ref ARM_USART_EVENT_CTS
|
||||
uint32_t event_dsr : 1; ///< Signal DSR change event: \ref ARM_USART_EVENT_DSR
|
||||
uint32_t event_dcd : 1; ///< Signal DCD change event: \ref ARM_USART_EVENT_DCD
|
||||
uint32_t event_ri : 1; ///< Signal RI change event: \ref ARM_USART_EVENT_RI
|
||||
uint32_t reserved : 11; ///< Reserved (must be zero)
|
||||
} ARM_USART_CAPABILITIES;
|
||||
|
||||
|
||||
/**
|
||||
\brief Access structure of the USART Driver.
|
||||
*/
|
||||
typedef struct _ARM_DRIVER_USART {
|
||||
ARM_DRIVER_VERSION (*GetVersion) (void); ///< Pointer to \ref ARM_USART_GetVersion : Get driver version.
|
||||
ARM_USART_CAPABILITIES (*GetCapabilities) (void); ///< Pointer to \ref ARM_USART_GetCapabilities : Get driver capabilities.
|
||||
int32_t (*Initialize) (ARM_USART_SignalEvent_t cb_event); ///< Pointer to \ref ARM_USART_Initialize : Initialize USART Interface.
|
||||
int32_t (*Uninitialize) (void); ///< Pointer to \ref ARM_USART_Uninitialize : De-initialize USART Interface.
|
||||
int32_t (*PowerControl) (ARM_POWER_STATE state); ///< Pointer to \ref ARM_USART_PowerControl : Control USART Interface Power.
|
||||
int32_t (*Send) (const void *data, uint32_t num); ///< Pointer to \ref ARM_USART_Send : Start sending data to USART transmitter.
|
||||
int32_t (*Receive) ( void *data, uint32_t num); ///< Pointer to \ref ARM_USART_Receive : Start receiving data from USART receiver.
|
||||
int32_t (*Transfer) (const void *data_out,
|
||||
void *data_in,
|
||||
uint32_t num); ///< Pointer to \ref ARM_USART_Transfer : Start sending/receiving data to/from USART.
|
||||
uint32_t (*GetTxCount) (void); ///< Pointer to \ref ARM_USART_GetTxCount : Get transmitted data count.
|
||||
uint32_t (*GetRxCount) (void); ///< Pointer to \ref ARM_USART_GetRxCount : Get received data count.
|
||||
int32_t (*Control) (uint32_t control, uint32_t arg); ///< Pointer to \ref ARM_USART_Control : Control USART Interface.
|
||||
ARM_USART_STATUS (*GetStatus) (void); ///< Pointer to \ref ARM_USART_GetStatus : Get USART status.
|
||||
int32_t (*SetModemControl) (ARM_USART_MODEM_CONTROL control); ///< Pointer to \ref ARM_USART_SetModemControl : Set USART Modem Control line state.
|
||||
ARM_USART_MODEM_STATUS (*GetModemStatus) (void); ///< Pointer to \ref ARM_USART_GetModemStatus : Get USART Modem Status lines state.
|
||||
} const ARM_DRIVER_USART;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* DRIVER_USART_H_ */
|
||||
275
src/hal/alif/Alif_CMSIS/Include/Driver_UTIMER.h
Normal file
275
src/hal/alif/Alif_CMSIS/Include/Driver_UTIMER.h
Normal file
@ -0,0 +1,275 @@
|
||||
/* Copyright (C) 2023 Alif Semiconductor - All Rights Reserved.
|
||||
* Use, distribution and modification of this code is permitted under the
|
||||
* terms stated in the Alif Semiconductor Software License Agreement
|
||||
*
|
||||
* You should have received a copy of the Alif Semiconductor Software
|
||||
* License Agreement with this file. If not, please write to:
|
||||
* contact@alifsemi.com, or visit: https://alifsemi.com/license
|
||||
*
|
||||
*/
|
||||
|
||||
/**************************************************************************//**
|
||||
* @file Driver_UTIMER.h
|
||||
* @author Girish BN, Manoj A Murudi
|
||||
* @email girish.bn@alifsemi.com, manoj.murudi@alifsemi.com
|
||||
* @version V1.0.0
|
||||
* @date 02-April-2023
|
||||
* @brief CMSIS-Driver for UTIMER.
|
||||
* @bug None.
|
||||
* @Note None
|
||||
******************************************************************************/
|
||||
#ifndef __DRIVER_UTIMER_H__
|
||||
#define __DRIVER_UTIMER_H__
|
||||
|
||||
#include "Driver_Common.h"
|
||||
|
||||
typedef void (*ARM_UTIMER_SignalEvent_t) (uint8_t event); /**< Initialization UTIMER call back function declaration >*/
|
||||
|
||||
/**< UTIMER Events >*/
|
||||
#define ARM_UTIMER_EVENT_CAPTURE_A 1U /**< UTIMER Capture A event >*/
|
||||
#define ARM_UTIMER_EVENT_CAPTURE_B 2U /**< UTIMER Capture B event >*/
|
||||
#define ARM_UTIMER_EVENT_COMPARE_A 3U /**< UTIMER Compare A event >*/
|
||||
#define ARM_UTIMER_EVENT_COMPARE_B 4U /**< UTIMER Compare B event >*/
|
||||
#define ARM_UTIMER_EVENT_COMPARE_A_BUF1 5U /**< UTIMER Compare A Buf1 event >*/
|
||||
#define ARM_UTIMER_EVENT_COMPARE_A_BUF2 6U /**< UTIMER Compare A Buf2 event >*/
|
||||
#define ARM_UTIMER_EVENT_COMPARE_B_BUF1 7U /**< UTIMER Compare B Buf1 event >*/
|
||||
#define ARM_UTIMER_EVENT_COMPARE_B_BUF2 8U /**< UTIMER Compare B Buf2 event >*/
|
||||
#define ARM_UTIMER_EVENT_UNDER_FLOW 9U /**< UTIMER Underflow event >*/
|
||||
#define ARM_UTIMER_EVENT_OVER_FLOW 10U /**< UTIMER Overflow event >*/
|
||||
|
||||
/**< UTIMER Channel declaration >*/
|
||||
#define ARM_UTIMER_CHANNEL0 0U /**< UTIMER Channel 0 >*/
|
||||
#define ARM_UTIMER_CHANNEL1 1U /**< UTIMER Channel 1 >*/
|
||||
#define ARM_UTIMER_CHANNEL2 2U /**< UTIMER Channel 2 >*/
|
||||
#define ARM_UTIMER_CHANNEL3 3U /**< UTIMER Channel 3 >*/
|
||||
#define ARM_UTIMER_CHANNEL4 4U /**< UTIMER Channel 4 >*/
|
||||
#define ARM_UTIMER_CHANNEL5 5U /**< UTIMER Channel 5 >*/
|
||||
#define ARM_UTIMER_CHANNEL6 6U /**< UTIMER Channel 6 >*/
|
||||
#define ARM_UTIMER_CHANNEL7 7U /**< UTIMER Channel 7 >*/
|
||||
#define ARM_UTIMER_CHANNEL8 8U /**< UTIMER Channel 8 >*/
|
||||
#define ARM_UTIMER_CHANNEL9 9U /**< UTIMER Channel 9 >*/
|
||||
#define ARM_UTIMER_CHANNEL10 10U /**< UTIMER Channel 10 >*/
|
||||
#define ARM_UTIMER_CHANNEL11 11U /**< UTIMER Channel 11 >*/
|
||||
#define ARM_UTIMER_CHANNEL12 12U /**< QEC Channel 0 >*/
|
||||
#define ARM_UTIMER_CHANNEL13 13U /**< QEC Channel 1 >*/
|
||||
#define ARM_UTIMER_CHANNEL14 14U /**< QEC Channel 2 >*/
|
||||
#define ARM_UTIMER_CHANNEL15 15U /**< QEC Channel 3 >*/
|
||||
|
||||
#define ARM_UTIMER_COUNTER_CLEAR 1U /* UTIMER counter clear enable at counter stop */
|
||||
#define ARM_UTIMER_COUNTER_NOT_CLEAR 0U /* UTIMER counter clear disabled at counter stop */
|
||||
|
||||
/**
|
||||
* enum ARM_UTIMER_MODE.
|
||||
* Driver UTIMER modes.
|
||||
*/
|
||||
typedef enum _ARM_UTIMER_MODE {
|
||||
ARM_UTIMER_MODE_BASIC, /**< UTIMER Channel mode configure to Basic mode >*/
|
||||
ARM_UTIMER_MODE_BUFFERING, /**< UTIMER Channel mode configure to Buffering mode >*/
|
||||
ARM_UTIMER_MODE_TRIGGERING, /**< UTIMER Channel mode configure to Triggering mode >*/
|
||||
ARM_UTIMER_MODE_CAPTURING, /**< UTIMER Channel mode configure to Capturing mode >*/
|
||||
ARM_UTIMER_MODE_COMPARING, /**< UTIMER Channel mode configure to Comparing mode >*/
|
||||
ARM_UTIMER_MODE_DEAD_TIME /**< UTIMER Channel mode configure to Dead Timer mode >*/
|
||||
} ARM_UTIMER_MODE;
|
||||
|
||||
/**
|
||||
* enum ARM_UTIMER_COUNTER_DIR.
|
||||
* Driver UTIMER counter direction.
|
||||
*/
|
||||
typedef enum _ARM_UTIMER_COUNTER_DIR {
|
||||
ARM_UTIMER_COUNTER_UP, /**< UTIMER Channel counter direction up >*/
|
||||
ARM_UTIMER_COUNTER_DOWN, /**< UTIMER Channel counter direction down >*/
|
||||
ARM_UTIMER_COUNTER_TRIANGLE /**< UTIMER Channel counter direction triangle >*/
|
||||
} ARM_UTIMER_COUNTER_DIR;
|
||||
|
||||
/**
|
||||
* enum ARM_UTIMER_COUNTER.
|
||||
* Driver UTIMER counters.
|
||||
*/
|
||||
typedef enum _ARM_UTIMER_COUNTER {
|
||||
ARM_UTIMER_CNTR, /**< UTIMER counter >*/
|
||||
ARM_UTIMER_CNTR_PTR, /**< UTIMER pointer counter >*/
|
||||
ARM_UTIMER_CNTR_PTR_BUF1, /**< UTIMER pointer buffer 1 counter >*/
|
||||
ARM_UTIMER_CNTR_PTR_BUF2, /**< UTIMER pointer buffer 2 counter >*/
|
||||
ARM_UTIMER_DT_UP, /**< UTIMER Dead Time UP >*/
|
||||
ARM_UTIMER_DT_UP_BUF1, /**< UTIMER Dead Time UP buffer 1 >*/
|
||||
ARM_UTIMER_DT_DOWN, /**< UTIMER Dead Time DOWN >*/
|
||||
ARM_UTIMER_DT_DOWN_BUF1, /**< UTIMER Dead Time DOWN buffer 1 >*/
|
||||
ARM_UTIMER_COMPARE_A, /**< UTIMER compare A >*/
|
||||
ARM_UTIMER_COMPARE_B, /**< UTIMER compare B >*/
|
||||
ARM_UTIMER_COMPARE_A_BUF1, /**< UTIMER compare A buffer 1 >*/
|
||||
ARM_UTIMER_COMPARE_B_BUF1, /**< UTIMER compare B buffer 1 >*/
|
||||
ARM_UTIMER_COMPARE_A_BUF2, /**< UTIMER compare A buffer 2 >*/
|
||||
ARM_UTIMER_COMPARE_B_BUF2, /**< UTIMER compare B buffer 1 >*/
|
||||
ARM_UTIMER_CAPTURE_A, /**< UTIMER capture A >*/
|
||||
ARM_UTIMER_CAPTURE_B, /**< UTIMER capture B >*/
|
||||
ARM_UTIMER_CAPTURE_A_BUF1, /**< UTIMER capture A buffer 1 >*/
|
||||
ARM_UTIMER_CAPTURE_B_BUF1, /**< UTIMER capture B buffer 1 >*/
|
||||
ARM_UTIMER_CAPTURE_A_BUF2, /**< UTIMER capture A buffer 2 >*/
|
||||
ARM_UTIMER_CAPTURE_B_BUF2 /**< UTIMER capture B buffer 2 >*/
|
||||
} ARM_UTIMER_COUNTER;
|
||||
|
||||
/**
|
||||
* enum ARM_UTIMER_TRIGGER_SRC.
|
||||
* Driver UTIMER external event sources.
|
||||
*/
|
||||
typedef enum _ARM_UTIMER_TRIGGER_SRC {
|
||||
ARM_UTIMER_SRC_0, /**< global triggers >*/
|
||||
ARM_UTIMER_SRC_1, /**< channel events >*/
|
||||
ARM_UTIMER_FAULT_TRIGGER, /**< fault triggers >*/
|
||||
ARM_UTIMER_CNTR_PAUSE_TRIGGER /**< counter pause triggers >*/
|
||||
} ARM_UTIMER_TRIGGER_SRC;
|
||||
|
||||
/**
|
||||
* enum ARM_UTIMER_TRIGGER_TARGET.
|
||||
* Driver UTIMER trigger targets.
|
||||
*/
|
||||
typedef enum _ARM_UTIMER_TRIGGER_TARGET {
|
||||
ARM_UTIMER_TRIGGER_START, /**< Trigger target UTIMER Channel counter start >*/
|
||||
ARM_UTIMER_TRIGGER_STOP, /**< Trigger target UTIMER Channel counter stop >*/
|
||||
ARM_UTIMER_TRIGGER_CLEAR, /**< Trigger target UTIMER Channel counter clear >*/
|
||||
ARM_UTIMER_TRIGGER_UPCOUNT, /**< Trigger target UTIMER Channel Up count >*/
|
||||
ARM_UTIMER_TRIGGER_DOWNCOUNT, /**< Trigger target UTIMER Channel Down count >*/
|
||||
ARM_UTIMER_TRIGGER_CAPTURE_A, /**< Trigger target UTIMER Channel to capture counter value in Drive A >*/
|
||||
ARM_UTIMER_TRIGGER_CAPTURE_B, /**< Trigger target UTIMER Channel to capture counter value in Drive B >*/
|
||||
ARM_UTIMER_TRIGGER_DMA_CLEAR_A, /**< Trigger target UTIMER Channel to clear Drive A DMA action >*/
|
||||
ARM_UTIMER_TRIGGER_DMA_CLEAR_B /**< Trigger target UTIMER Channel to clear Drive B DMA action >*/
|
||||
} ARM_UTIMER_TRIGGER_TARGET;
|
||||
|
||||
/**
|
||||
* enum ARM_UTIMER_TRIGGER.
|
||||
* Driver UTIMER trigger types.
|
||||
*/
|
||||
typedef enum _ARM_UTIMER_TRIGGER {
|
||||
ARM_UTIMER_SRC0_TRIG0_RISING, /**< UTIMER/QEC trigger 0 rising edge >*/
|
||||
ARM_UTIMER_SRC0_TRIG0_FALLING, /**< UTIMER/QEC trigger 0 falling edge >*/
|
||||
ARM_UTIMER_SRC0_TRIG1_RISING, /**< UTIMER/QEC trigger 1 rising edge >*/
|
||||
ARM_UTIMER_SRC0_TRIG1_FALLING, /**< UTIMER/QEC trigger 1 falling edge >*/
|
||||
ARM_UTIMER_SRC0_TRIG2_RISING, /**< UTIMER/QEC trigger 2 rising edge >*/
|
||||
ARM_UTIMER_SRC0_TRIG2_FALLING, /**< UTIMER/QEC trigger 2 falling edge >*/
|
||||
ARM_UTIMER_SRC0_TRIG3_RISING, /**< UTIMER/QEC trigger 3 rising edge >*/
|
||||
ARM_UTIMER_SRC0_TRIG3_FALLING, /**< UTIMER/QEC trigger 3 falling edge >*/
|
||||
ARM_UTIMER_SRC0_TRIG4_RISING, /**< UTIMER/QEC trigger 4 rising edge >*/
|
||||
ARM_UTIMER_SRC0_TRIG4_FALLING, /**< UTIMER/QEC trigger 4 falling edge >*/
|
||||
ARM_UTIMER_SRC0_TRIG5_RISING, /**< UTIMER/QEC trigger 5 rising edge >*/
|
||||
ARM_UTIMER_SRC0_TRIG5_FALLING, /**< UTIMER/QEC trigger 5 falling edge >*/
|
||||
ARM_UTIMER_SRC0_TRIG6_RISING, /**< UTIMER/QEC trigger 6 rising edge >*/
|
||||
ARM_UTIMER_SRC0_TRIG6_FALLING, /**< UTIMER/QEC trigger 6 falling edge >*/
|
||||
ARM_UTIMER_SRC0_TRIG7_RISING, /**< UTIMER/QEC trigger 7 rising edge >*/
|
||||
ARM_UTIMER_SRC0_TRIG7_FALLING, /**< UTIMER/QEC trigger 7 falling edge >*/
|
||||
ARM_UTIMER_SRC0_TRIG8_RISING, /**< UTIMER/QEC trigger 8 rising edge >*/
|
||||
ARM_UTIMER_SRC0_TRIG8_FALLING, /**< UTIMER/QEC trigger 8 falling edge >*/
|
||||
ARM_UTIMER_SRC0_TRIG9_RISING, /**< UTIMER/QEC trigger 9 rising edge >*/
|
||||
ARM_UTIMER_SRC0_TRIG9_FALLING, /**< UTIMER/QEC trigger 9 falling edge >*/
|
||||
ARM_UTIMER_SRC0_TRIG10_RISING, /**< UTIMER/QEC trigger 10 rising edge >*/
|
||||
ARM_UTIMER_SRC0_TRIG10_FALLING, /**< UTIMER/QEC trigger 10 falling edge >*/
|
||||
ARM_UTIMER_SRC0_TRIG11_RISING, /**< UTIMER/QEC trigger 11 rising edge >*/
|
||||
ARM_UTIMER_SRC0_TRIG11_FALLING, /**< UTIMER/QEC trigger 11 falling edge >*/
|
||||
ARM_UTIMER_SRC0_TRIG12_RISING, /**< UTIMER trigger 12 rising edge >*/
|
||||
ARM_UTIMER_SRC0_TRIG12_FALLING, /**< UTIMER trigger 12 falling edge >*/
|
||||
ARM_UTIMER_SRC0_TRIG13_RISING, /**< UTIMER trigger 13 rising edge >*/
|
||||
ARM_UTIMER_SRC0_TRIG13_FALLING, /**< UTIMER trigger 13 falling edge >*/
|
||||
ARM_UTIMER_SRC0_TRIG14_RISING, /**< UTIMER trigger 14 rising edge >*/
|
||||
ARM_UTIMER_SRC0_TRIG14_FALLING, /**< UTIMER trigger 14 falling edge >*/
|
||||
ARM_UTIMER_SRC0_TRIG15_RISING, /**< UTIMER trigger 15 rising edge >*/
|
||||
ARM_UTIMER_SRC0_TRIG15_FALLING, /**< UTIMER trigger 15 falling edge >*/
|
||||
ARM_UTIMER_SRC1_DRIVE_A_RISING_B_0, /**< UTIMER Channel inputs: rising edge on driver A, 0 on driver B >*/
|
||||
ARM_UTIMER_SRC1_DRIVE_A_RISING_B_1, /**< UTIMER Channel inputs: rising edge on driver A, 1 on driver B >*/
|
||||
ARM_UTIMER_SRC1_DRIVE_A_FALLING_B_0, /**< UTIMER Channel inputs: falling edge on driver A, 0 on driver B >*/
|
||||
ARM_UTIMER_SRC1_DRIVE_A_FALLING_B_1, /**< UTIMER Channel inputs: falling edge on driver A, 1 on driver B >*/
|
||||
ARM_UTIMER_SRC1_DRIVE_B_RISING_A_0, /**< UTIMER Channel inputs: rising edge on driver B, 0 on driver A >*/
|
||||
ARM_UTIMER_SRC1_DRIVE_B_RISING_A_1, /**< UTIMER Channel inputs: rising edge on driver B, 1 on driver A >*/
|
||||
ARM_UTIMER_SRC1_DRIVE_B_FALLING_A_0, /**< UTIMER Channel inputs: falling edge on driver B, 0 on driver A >*/
|
||||
ARM_UTIMER_SRC1_DRIVE_B_FALLING_A_1, /**< UTIMER Channel inputs: falling edge on driver B, 0 on driver A >*/
|
||||
ARM_UTIMER_FAULT_TRIG0_RISING, /**< Fault trigger 0 rising edge >*/
|
||||
ARM_UTIMER_FAULT_TRIG0_FALLING, /**< Fault trigger 0 falling edge >*/
|
||||
ARM_UTIMER_FAULT_TRIG1_RISING, /**< Fault trigger 1 rising edge >*/
|
||||
ARM_UTIMER_FAULT_TRIG1_FALLING, /**< Fault trigger 1 falling edge >*/
|
||||
ARM_UTIMER_FAULT_TRIG2_RISING, /**< Fault trigger 2 rising edge >*/
|
||||
ARM_UTIMER_FAULT_TRIG2_FALLING, /**< Fault trigger 2 falling edge >*/
|
||||
ARM_UTIMER_FAULT_TRIG3_RISING, /**< Fault trigger 3 rising edge >*/
|
||||
ARM_UTIMER_FAULT_TRIG3_FALLING, /**< Fault trigger 3 falling edge >*/
|
||||
ARM_UTIMER_PAUSE_SRC_0_HIGH, /**< Pause source 0 high >*/
|
||||
ARM_UTIMER_PAUSE_SRC_0_LOW, /**< Pause source 0 low >*/
|
||||
ARM_UTIMER_PAUSE_SRC_1_HIGH, /**< Pause source 1 high >*/
|
||||
ARM_UTIMER_PAUSE_SRC_1_LOW /**< Pause source 1 low >*/
|
||||
} ARM_UTIMER_TRIGGER;
|
||||
|
||||
/** \brief UTIMER trigger configuration. */
|
||||
typedef struct _ARM_UTITMER_TRIGGER_CONFIG {
|
||||
ARM_UTIMER_TRIGGER_TARGET triggerTarget; /**< UTIMER trigger target >*/
|
||||
ARM_UTIMER_TRIGGER_SRC triggerSrc; /**< UTIMER trigger source >*/
|
||||
ARM_UTIMER_TRIGGER trigger; /**< UTIMER triggers >*/
|
||||
} ARM_UTIMER_TRIGGER_CONFIG;
|
||||
|
||||
/**
|
||||
\fn int32_t ARM_UTIMER_Initialize (uint8_t channel, ARM_UTIMER_CBEvent CB_event)
|
||||
\brief Initialize UTIMER interface and register signal(call back) functions.
|
||||
\param[in] channel :Utimer have total 12 channel, configure by feeding TIMER_CHANNEL0,1,2,3....
|
||||
\param[in] CB_event: call back function.
|
||||
\param[out] int32_t : execution_status.
|
||||
|
||||
\fn int32_t ARM_UTIMER_PowerControl (uint8_t channel, ARM_POWER_STATE state)
|
||||
\brief Control UTIMER channel interface power.
|
||||
\param[in] channel : Utimer have total 16 channel, configure by feeding TIMER_CHANNEL0,1,2,3....
|
||||
\param[in] state : Power state
|
||||
- \ref ARM_POWER_OFF : power off: no operation possible
|
||||
- \ref ARM_POWER_LOW : low power mode: retain state, detect and signal wake-up events
|
||||
- \ref ARM_POWER_FULL : power on: full operation at maximum performance
|
||||
\param[out] int32_t : execution_status.
|
||||
|
||||
\fn int32_t ARM_UTIMER_ConfigCounter (uint8_t channel, ARM_UTIMER_MODE mode, ARM_UTIMER_COUNTER_DIR dir)
|
||||
\brief Configure utimer mode and type.
|
||||
\param[in] channel : Utimer have total 16 channel, configure by feeding TIMER_CHANNEL0,1,2,3....
|
||||
\param[in] mode : Utimer mode.
|
||||
param[in] dir : Utimer counter direction.
|
||||
param[out] int32_t : execution_status.
|
||||
|
||||
\fn int32_t ARM_UTIMER_SetCount (uint8_t channel, ARM_UTIMER_COUNTER counter, uint32_t arg)
|
||||
\brief Set UTIMER counter value.
|
||||
\param[in] channel : Utimer have total 16 channel, configure by feeding TIMER_CHANNEL0,1,2,3....
|
||||
\param[in] counter : counter type.
|
||||
param[in] value : counter value.
|
||||
param[out] int32_t : execution_status.
|
||||
|
||||
\fn uint32_t ARM_UTIMER_GetCount (uint8_t channel, ARM_UTIMER_COUNTER counter)
|
||||
\brief Get UTIMER counter value.
|
||||
\param[in] channel : Utimer have total 16 channel, configure by feeding TIMER_CHANNEL0,1,2,3....
|
||||
\param[in] counter : counter type.
|
||||
param[out] uint32_t : counter value.
|
||||
|
||||
\fn int32_t ARM_UTIMER_ConfigTrigger (uint8_t channel, ARM_UTIMER_TRIGGER_CONFIG *arg)
|
||||
\brief Configure the UTMER Channel for trigger operation.
|
||||
\param[in] channel : Utimer have total 16 channel, configure by feeding TIMER_CHANNEL0,1,2,3....
|
||||
\param[in] arg : Pointer to an argument of type UTIMER_TRIGGER_CONFIG.
|
||||
\param[out] int32_t : execution_status.
|
||||
|
||||
\fn int32_t ARM_UTIMER_Start (uint8_t channel)
|
||||
\brief Start the UTMER Channel counting.
|
||||
\param[in] channel : Utimer have total 16 channel, configure by feeding TIMER_CHANNEL0,1,2,3....
|
||||
\param[out] int32_t : execution_status.
|
||||
|
||||
\fn int32_t ARM_UTIMER_Stop (uint8_t channel, bool count_clear_option)
|
||||
\brief Stop the UTMER Channel running count.
|
||||
\param[in] channel : Utimer have total 16 channel, configure by feeding TIMER_CHANNEL0,1,2,3....
|
||||
\param[in] count_clear_option : Utimer set = count clear, clear = count unclear
|
||||
\param[out] int32_t : execution_status.
|
||||
|
||||
\fn int32_t ARM_UTIMER_Uninitialize (uint8_t channel)
|
||||
\brief Un-initialize the named channel configuration
|
||||
\param[in] channel : Utimer have total 16 channel, configure by feeding TIMER_CHANNEL0,1,2,3....
|
||||
\param[out] int32_t : execution_status.
|
||||
*/
|
||||
|
||||
typedef struct _ARM_DRIVER_UTIMER {
|
||||
int32_t (*Initialize) (uint8_t channel, ARM_UTIMER_SignalEvent_t cb_event); /**< Pointer to \ref ARM_UTIMER_Initialize : Initialize the UTIMER Interface>*/
|
||||
int32_t (*PowerControl) (uint8_t channel, ARM_POWER_STATE state); /**< Pointer to \ref ARM_UTIMER_PowerControl : Control UTIMER interface power>*/
|
||||
int32_t (*ConfigCounter) (uint8_t channel, ARM_UTIMER_MODE mode, ARM_UTIMER_COUNTER_DIR dir); /**< Pointer to \ref ARM_UTIMER_ConfigCounter : Control timer type and mode for UTIMER channel>*/
|
||||
int32_t (*SetCount) (uint8_t channel, ARM_UTIMER_COUNTER counter, uint32_t value); /**< Pointer to \ref ARM_UTIMER_SetCount : Set count value for UTIMER channel>*/
|
||||
uint32_t (*GetCount) (uint8_t channel, ARM_UTIMER_COUNTER counter); /**< Pointer to \ref ARM_UTIMER_GetCount : Get count value for UTIMER channel>*/
|
||||
int32_t (*ConfigTrigger) (uint8_t channel, ARM_UTIMER_TRIGGER_CONFIG *arg); /**< Pointer to \ref ARM_UTIMER_ConfigTrigger : configure the input triggers>*/
|
||||
int32_t (*Start) (uint8_t channel); /**< Pointer to \ref ARM_UTIMER_Start : Global starts the UTIMER channel>*/
|
||||
int32_t (*Stop) (uint8_t channel, bool count_clear_option); /**< Pointer to \ref ARM_UTIMER_Stop : Global stops the UTIMER channel>*/
|
||||
int32_t (*Uninitialize) (uint8_t channel); /**< Pointer to \ref ARM_UTIMER_Uninitialize : Uninitialized the UTIMER Interface>*/
|
||||
} ARM_DRIVER_UTIMER;
|
||||
|
||||
#endif /*< __DRIVER_UTIMER_H__>*/
|
||||
117
src/hal/alif/Alif_CMSIS/Include/Driver_WDT.h
Normal file
117
src/hal/alif/Alif_CMSIS/Include/Driver_WDT.h
Normal file
@ -0,0 +1,117 @@
|
||||
/* Copyright (C) 2022 Alif Semiconductor - All Rights Reserved.
|
||||
* Use, distribution and modification of this code is permitted under the
|
||||
* terms stated in the Alif Semiconductor Software License Agreement
|
||||
*
|
||||
* You should have received a copy of the Alif Semiconductor Software
|
||||
* License Agreement with this file. If not, please write to:
|
||||
* contact@alifsemi.com, or visit: https://alifsemi.com/license
|
||||
*
|
||||
*/
|
||||
|
||||
/**************************************************************************//**
|
||||
* @file Driver_WDT.h
|
||||
* @author Tanay Rami
|
||||
* @email tanay@alifsemi.com
|
||||
* @version V1.0.0
|
||||
* @date 27-April-2021
|
||||
* @brief Watchdog Timer(WDT) driver definitions.
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef DRIVER_WDT_H_
|
||||
#define DRIVER_WDT_H_
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
/* Includes --------------------------------------------------------------------------- */
|
||||
#include "Driver_Common.h"
|
||||
|
||||
#define ARM_WDT_API_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(1,0) /* API version */
|
||||
|
||||
/*----- Watchdog Control Codes -----*/
|
||||
#define ARM_WATCHDOG_LOCK (0x01UL) ///< watchdog lock; arg = dummy
|
||||
#define ARM_WATCHDOG_UNLOCK (0x02UL) ///< watchdog unlock; arg = dummy
|
||||
|
||||
|
||||
// Function documentation
|
||||
/**
|
||||
\fn ARM_DRIVER_VERSION GetVersion (void)
|
||||
\brief Get Watchdog driver version.
|
||||
\return \ref ARM_DRIVER_VERSION
|
||||
|
||||
\fn ARM_WDT_CAPABILITIES GetCapabilities (void)
|
||||
\brief Get Watchdog driver capabilities
|
||||
\return \ref WDT_CAPABILITIES
|
||||
|
||||
\fn int32_t Initialize (uint32_t timeout)
|
||||
\brief Initialize Watchdog Interface.
|
||||
\param[in] timeout : Timeout in msec, must be > 0.
|
||||
\return \ref execution_status
|
||||
|
||||
\fn int32_t Uninitialize (void)
|
||||
\brief De-initialize Watchdog Interface.
|
||||
\return \ref execution_status
|
||||
|
||||
\fn int32_t PowerControl (ARM_POWER_STATE state)
|
||||
\brief Control Watchdog Interface Power.
|
||||
\param[in] state : Power state
|
||||
\return \ref execution_status
|
||||
|
||||
\fn int32_t Start (void)
|
||||
\brief Start Watchdog Interface.
|
||||
\return \ref execution_status
|
||||
|
||||
\fn int32_t Feed (void)
|
||||
\brief Feed Watchdog Interface.
|
||||
\return \ref execution_status
|
||||
|
||||
\fn int32_t Stop (void)
|
||||
\brief Stop Watchdog Interface.
|
||||
\return \ref execution_status
|
||||
|
||||
\fn int32_t Control (uint32_t control, uint32_t arg)
|
||||
\brief Control Watchdog Interface.
|
||||
\param[in] control : Operation
|
||||
\param[in] arg : Argument of operation (optional)
|
||||
\return common \ref execution_status
|
||||
|
||||
\fn int32_t GetRemainingTime (uint32_t *val)
|
||||
\brief Get watchdog remaining time before reset.
|
||||
\param[out] val : Pointer to the address where watchdog remaining time before reset
|
||||
needs to be copied to.
|
||||
\return \ref execution_status
|
||||
*/
|
||||
|
||||
/**
|
||||
\brief Watchdog Device Driver Capabilities.
|
||||
*/
|
||||
typedef struct _ARM_WDT_CAPABILITIES {
|
||||
uint32_t lock : 1; ///< supports Watchdog Lock-Unlock
|
||||
uint32_t reserved : 31; ///< Reserved (must be zero)
|
||||
} ARM_WDT_CAPABILITIES;
|
||||
|
||||
/**
|
||||
\brief Access structure of the Watchdog Driver.
|
||||
*/
|
||||
typedef struct _ARM_DRIVER_WDT {
|
||||
ARM_DRIVER_VERSION (*GetVersion) (void); ///< Pointer to \ref WDT_GetVersion : Get driver version.
|
||||
ARM_WDT_CAPABILITIES (*GetCapabilities) (void); ///< Pointer to \ref WDT_GetCapabilities : Get driver capabilities.
|
||||
int32_t (*Initialize) (uint32_t timeout); ///< Pointer to \ref WDT_Initialize : Initialize Watchdog Interface.
|
||||
int32_t (*Uninitialize) (void); ///< Pointer to \ref WDT_Uninitialize : De-initialize Watchdog Interface.
|
||||
int32_t (*PowerControl) (ARM_POWER_STATE state); ///< Pointer to \ref WDT_PowerControl : Control Watchdog Interface Power.
|
||||
int32_t (*Start) (void); ///< Pointer to \ref WDT_Start : Start Watchdog Interface.
|
||||
int32_t (*Feed) (void); ///< Pointer to \ref WDT_Feed : Feed Watchdog Interface.
|
||||
int32_t (*Stop) (void); ///< Pointer to \ref WDT_Stop : Stop Watchdog Interface.
|
||||
int32_t (*Control) (uint32_t control, uint32_t arg); ///< Pointer to \ref WDT_Control : Control Watchdog Interface.
|
||||
int32_t (*GetRemainingTime) (uint32_t *val); ///< Pointer to \ref WDT_GetRemainingTime : Get Watchdog remaining time before reset.
|
||||
} const ARM_DRIVER_WDT;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* DRIVER_WDT_H_ */
|
||||
|
||||
/************************ (C) COPYRIGHT ALIF SEMICONDUCTOR *****END OF FILE****/
|
||||
69
src/hal/alif/Alif_CMSIS/Include/config/dma_config.h
Normal file
69
src/hal/alif/Alif_CMSIS/Include/config/dma_config.h
Normal file
@ -0,0 +1,69 @@
|
||||
/* Copyright (C) 2023 Alif Semiconductor - All Rights Reserved.
|
||||
* Use, distribution and modification of this code is permitted under the
|
||||
* terms stated in the Alif Semiconductor Software License Agreement
|
||||
*
|
||||
* You should have received a copy of the Alif Semiconductor Software
|
||||
* License Agreement with this file. If not, please write to:
|
||||
* contact@alifsemi.com, or visit: https://alifsemi.com/license
|
||||
*
|
||||
*/
|
||||
|
||||
//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
|
||||
|
||||
#ifndef DMA_CONFIG_H_
|
||||
#define DMA_CONFIG_H_
|
||||
|
||||
// <o> DMA Destination Cache Control <0-7>
|
||||
// <i> State of AWCACHE[3,1:0] when the DMAC write the destination data
|
||||
// Bit [2] 0 = AWCACHE[3] is LOW
|
||||
// 1 = AWCACHE[3] is HIGH.
|
||||
// Bit [1] 0 = AWCACHE[1] is LOW
|
||||
// 1 = AWCACHE[1] is HIGH.
|
||||
// Bit [0] 0 = AWCACHE[0] is LOW
|
||||
// 1 = AWCACHE[0] is HIGH.
|
||||
// Setting AWCACHE[3,1]=0b10 violates the AXI protocol
|
||||
// <i> Default: 0x2
|
||||
#define DMA_DEST_CACHE_CTRL 0x2
|
||||
|
||||
// <o> DMA Source Cache Control <0-7>
|
||||
// <i> State of ARCACHE[2:0] when the DMAC reads the source data
|
||||
// Bit [2] 0 = ARCACHE[2] is LOW
|
||||
// 1 = ARCACHE[2] is HIGH.
|
||||
// Bit [1] 0 = ARCACHE[1] is LOW
|
||||
// 1 = ARCACHE[1] is HIGH.
|
||||
// Bit [0] 0 = ARCACHE[0] is LOW
|
||||
// 1 = ARCACHE[0] is HIGH.
|
||||
// Setting ARCACHE[2:1]=0b10 violates the AXI protocol
|
||||
// <i> Default: 0x2
|
||||
#define DMA_SRC_CACHE_CTRL 0x2
|
||||
|
||||
// <o> DMA Source Protection Control <0-7>
|
||||
// <i> State of ARPROT[2:0] when the DMAC reads the source data
|
||||
// Bit [2] 0 = ARPROT[2] is LOW
|
||||
// 1 = ARPROT[2] is HIGH.
|
||||
// Bit [1] 0 = ARPROT[1] is LOW
|
||||
// 1 = ARPROT[1] is HIGH.
|
||||
// Bit [0] 0 = ARPROT[0] is LOW
|
||||
// 1 = ARPROT[0] is HIGH.
|
||||
// Only DMA channels in the Secure state can program ARPROT[1] LOW
|
||||
// <i> Default: 0x0
|
||||
#define DMA_SRC_PROT_CTRL 0x0
|
||||
|
||||
// <o> DMA Destination Protection Control <0-7>
|
||||
// <i> State of AWPROT[2:0] when the DMAC write the destination data
|
||||
// Bit [2] 0 = AWPROT[2] is LOW
|
||||
// 1 = AWPROT[2] is HIGH.
|
||||
// Bit [1] 0 = AWPROT[1] is LOW
|
||||
// 1 = AWPROT[1] is HIGH.
|
||||
// Bit [0] 0 = AWPROT[0] is LOW
|
||||
// 1 = AWPROT[0] is HIGH.
|
||||
// Only DMA channels in the Secure state can program AWPROT[1] LOW
|
||||
// <i> Default: 0x0
|
||||
#define DMA_DEST_PROT_CTRL 0x0
|
||||
|
||||
// <o> DMA Microcode size
|
||||
// <i> Defines Default memory size(bytes) to hold the microcode for a channel
|
||||
// <i> Default: 128
|
||||
#define DMA_MICROCODE_SIZE 128
|
||||
|
||||
#endif /* DMA_CONFIG_H_ */
|
||||
607
src/hal/alif/Alif_CMSIS/Include/dma_opcode.h
Normal file
607
src/hal/alif/Alif_CMSIS/Include/dma_opcode.h
Normal file
@ -0,0 +1,607 @@
|
||||
/* Copyright (C) 2023 Alif Semiconductor - All Rights Reserved.
|
||||
* Use, distribution and modification of this code is permitted under the
|
||||
* terms stated in the Alif Semiconductor Software License Agreement
|
||||
*
|
||||
* You should have received a copy of the Alif Semiconductor Software
|
||||
* License Agreement with this file. If not, please write to:
|
||||
* contact@alifsemi.com, or visit: https://alifsemi.com/license
|
||||
*
|
||||
*/
|
||||
/**************************************************************************//**
|
||||
* @file dma_opcode.h
|
||||
* @author Sudhir Sreedharan
|
||||
* @email sudhir@alifsemi.com
|
||||
* @version V1.0.0
|
||||
* @date 8-Aug-2023
|
||||
* @brief DMA Opcode Generation Header File
|
||||
* @bug None.
|
||||
* @Note None
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef DMA_OPCODE_H_
|
||||
#define DMA_OPCODE_H_
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include <stdbool.h>
|
||||
#include <stdint.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
#define DMA_MAX_BACKWARD_JUMP 256 /*!< Max Loop backward jump offset */
|
||||
#define DMA_MAX_LP_CNT 256 /*!< Max Loop count */
|
||||
|
||||
/* 8 bit-opcode with variable data payload of 0, 8, 16 or 32bits */
|
||||
#define DMA_OP_1BYTE_LEN 1
|
||||
#define DMA_OP_2BYTE_LEN 2
|
||||
#define DMA_OP_3BYTE_LEN 3
|
||||
#define DMA_OP_6BYTE_LEN 6
|
||||
|
||||
#define OP_DMAADDH(ar) (0x54 | (ar << 1)) /*!< Adds an immediate 16bit value to SARn or DARn */
|
||||
#define OP_DMAADNH(ar) (0x5C | (ar << 1)) /*!< Adds an immediate 16bit negative value to SARn or DARn */
|
||||
#define OP_DMAEND 0x00 /*!< End signal as the DMAC sequence is complete */
|
||||
#define OP_DMAFLUSHP 0x35 /*!< Flush the peripheral contents and sends message to resend its level status */
|
||||
#define OP_DMAGO(ns) (0xA0 | (ns << 1)) /*!< Execute thread in secure/non-secure mode */
|
||||
#define OP_DMAKILL 0x01 /*!< Terminate Execution of a thread */
|
||||
#define OP_DMALD 0x04 /*!< Performs DMA Load operation */
|
||||
#define OP_DMALDS 0x05 /*!< Performs DMA Single Load operation */
|
||||
#define OP_DMALDB 0x07 /*!< Performs DMA Burst Load operation */
|
||||
#define OP_DMALDP(bs) (0x25 | (bs << 1)) /*!< Performs DMA Load & Notify Peripheral Single/Burst operation */
|
||||
#define OP_DMALP(lc) (0x20 | (lc << 1)) /*!< Loop instruct DMAC to load 8bit val to LC0/LC1 reg */
|
||||
#define OP_DMALPEND(nf, lc) (0x28 | (nf << 4) | (lc << 2)) /*!< Loop End, nf=0, lc=1 if DMALPFE started loop */
|
||||
#define OP_DMALPENDS(lc) (0x39 | (lc << 2)) /*!< Loop End Single */
|
||||
#define OP_DMALPENDB(lc) (0x3B | (lc << 2)) /*!< Loop End Burst */
|
||||
#define OP_DMAMOV 0xBC /*!< Move 32bit immediate into SAR/DAR/CCR */
|
||||
#define OP_DMANOP 0x18 /*!< For code alignment */
|
||||
#define OP_DMARMB 0x12 /*!< Read Memory barrier, write-after-read sequence */
|
||||
#define OP_DMASEV 0x34 /*!< Send event */
|
||||
#define OP_DMAST 0x08 /*!< Performs DMA Store operation */
|
||||
#define OP_DMASTS 0x09 /*!< Performs DMA Single Store operation */
|
||||
#define OP_DMASTB 0x0B /*!< Performs DMA Burst Store operation */
|
||||
#define OP_DMASTP(bs) (0x29 | (bs << 1)) /*!< Performs DMA Store & Notify Peripheral Single/Burst operation */
|
||||
#define OP_DMASTZ 0x0C /*!< Store Zeros */
|
||||
#define OP_DMAWFE 0x36 /*!< Wait for event */
|
||||
#define OP_DMAWFP_P(p) (0x30 | (p << 0)) /*!< Wait for peripheral with peripheral bit set */
|
||||
#define OP_DMAWFP(bs) (0x30 | (bs << 1)) /*!< Wait for peripheral in single/burst mode */
|
||||
#define OP_DMAWMB 0x13 /*!< Write memory barrier */
|
||||
|
||||
/* SWAP SIZE */
|
||||
typedef enum _DMA_SWAP {
|
||||
DMA_SWAP_NONE, /*!< No swap, 8-bit data */
|
||||
DMA_SWAP_16BIT, /*!< Swap bytes within 16-bit data */
|
||||
DMA_SWAP_32BIT, /*!< Swap bytes within 32-bit data */
|
||||
DMA_SWAP_64BIT, /*!< Swap bytes within 64-bit data */
|
||||
DMA_SWAP_128BIT, /*!< Swap bytes within 128-bit data */
|
||||
} DMA_SWAP;
|
||||
|
||||
|
||||
/* Loop counters */
|
||||
typedef enum _DMA_LC {
|
||||
DMA_LC_0,
|
||||
DMA_LC_1,
|
||||
} DMA_LC;
|
||||
|
||||
/* Burst Type */
|
||||
typedef enum _DMA_BURST {
|
||||
DMA_BURST_FIXED = 0, /*!< Fixed Address burst */
|
||||
DMA_BURST_INCREMENTING, /*!< Incrementing Address burst */
|
||||
} DMA_BURST;
|
||||
|
||||
/* Transfer type */
|
||||
typedef enum _DMA_XFER {
|
||||
DMA_XFER_SINGLE = 0,
|
||||
DMA_XFER_BURST = 1,
|
||||
DMA_XFER_PERIPHERAL = 2,
|
||||
DMA_XFER_FORCE = 2,
|
||||
} DMA_XFER;
|
||||
|
||||
/* DMA Secure State */
|
||||
typedef enum _DMA_SECURE_STATE {
|
||||
DMA_STATE_SECURE = 0, /*!< Secure State */
|
||||
DMA_STATE_NON_SECURE, /*!< Non-Secure State */
|
||||
} DMA_SECURE_STATE;
|
||||
|
||||
/* DMA registers */
|
||||
typedef enum _DMA_REG {
|
||||
DMA_REG_SAR,
|
||||
DMA_REG_CCR,
|
||||
DMA_REG_DAR
|
||||
} DMA_REG;
|
||||
|
||||
/* DMA channel control information */
|
||||
typedef union _dma_ccr_t {
|
||||
uint32_t value;
|
||||
struct {
|
||||
uint32_t src_inc : 1; /*!< Source Fixed/Increment type burst */
|
||||
uint32_t src_burst_size : 3; /*!< No of bytes DMAC reads from source in a beat */
|
||||
uint32_t src_burst_len : 4; /*!< No of data transfers in a burst when DMAC read from source */
|
||||
uint32_t src_prot_ctrl : 3; /*!< Protection control when DMAC reads from source */
|
||||
uint32_t src_cache_ctrl : 3; /*!< Cache control when DMAC reads from source */
|
||||
uint32_t dst_inc : 1; /*!< Destination Fixed/Increment type burst */
|
||||
uint32_t dst_burst_size : 3; /*!< No of bytes DMAC writes to destination in a beat */
|
||||
uint32_t dst_burst_len : 4; /*!< No of data transfers in a burst when DMAC writes to destination */
|
||||
uint32_t dst_prot_ctrl : 3; /*!< Protection control when DMAC writes to destination */
|
||||
uint32_t dst_cache_ctrl : 3; /*!< Cache control when DMAC writes to destination */
|
||||
uint32_t endian_swap_size : 3; /*!< swap size data */
|
||||
} value_b;
|
||||
} dma_ccr_t;
|
||||
|
||||
/* DMA Loop control information */
|
||||
typedef struct _dma_loop_t {
|
||||
DMA_XFER xfer_type; /*!< Transfer Type : Single/Burst/Peripheral */
|
||||
DMA_LC lc; /*!< Loop Register : LC0/LC1 */
|
||||
uint8_t jump; /*!< Backward Jump offset */
|
||||
bool nf; /*!< Loop forever flag t */
|
||||
} dma_loop_t;
|
||||
|
||||
/* DMA Opcode buffer information */
|
||||
typedef struct _dma_opcode_buf {
|
||||
uint8_t *buf; /*!< Start address of the opcode buffer */
|
||||
uint32_t off; /*!< Current Offset from start address */
|
||||
uint32_t buf_size; /*!< Total buffer size */
|
||||
} dma_opcode_buf;
|
||||
|
||||
/**
|
||||
\fn bool dma_construct_add(DMA_REG reg,
|
||||
uint16_t off,
|
||||
dma_opcode_buf *op_buf)
|
||||
\brief Build the opcode for DMAADDH
|
||||
\param[in] reg Source or Destination Address Register
|
||||
\param[in] off 16bit-immediate offset which needs to be added
|
||||
\param[in] op_buf opcode buf info
|
||||
\return bool true if the opcode fits in the allocated space
|
||||
*/
|
||||
|
||||
static inline bool dma_construct_add(DMA_REG reg,
|
||||
uint16_t off,
|
||||
dma_opcode_buf *op_buf)
|
||||
{
|
||||
if ((op_buf->off + DMA_OP_3BYTE_LEN) > op_buf->buf_size)
|
||||
return false;
|
||||
|
||||
if (reg == DMA_REG_SAR)
|
||||
op_buf->buf[(op_buf->off)++] = OP_DMAADDH(0);
|
||||
else if (reg == DMA_REG_DAR)
|
||||
op_buf->buf[(op_buf->off)++] = OP_DMAADDH(1);
|
||||
else
|
||||
return false;
|
||||
|
||||
op_buf->buf[(op_buf->off)++] = (uint8_t)off;
|
||||
op_buf->buf[(op_buf->off)++] = (uint8_t)(off >> 8);
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
/**
|
||||
\fn bool dma_construct_addneg(DMA_REG reg,
|
||||
int16_t off,
|
||||
dma_opcode_buf *op_buf)
|
||||
\brief Build the opcode for DMAADNH
|
||||
\param[in] reg Source or Destination Address Register
|
||||
\param[in] off 16bit-immediate value which needs to be subtracted
|
||||
\param[in] op_buf opcode buf info
|
||||
\return bool true if the opcode fits in the allocated space
|
||||
*/
|
||||
static inline bool dma_construct_addneg(DMA_REG reg,
|
||||
int16_t off,
|
||||
dma_opcode_buf *op_buf)
|
||||
{
|
||||
if ((op_buf->off + DMA_OP_3BYTE_LEN) > op_buf->buf_size)
|
||||
return false;
|
||||
|
||||
if (reg == DMA_REG_SAR)
|
||||
op_buf->buf[(op_buf->off)++] = OP_DMAADNH(0);
|
||||
else if (reg == DMA_REG_DAR)
|
||||
op_buf->buf[(op_buf->off)++] = OP_DMAADNH(1);
|
||||
else
|
||||
return false;
|
||||
|
||||
off = off - 1;
|
||||
off = ~off;
|
||||
op_buf->buf[(op_buf->off)++] = (uint8_t)off;
|
||||
op_buf->buf[(op_buf->off)++] = (uint8_t)(off >> 8);
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
/**
|
||||
\fn bool dma_construct_end(dma_opcode_buf *op_buf)
|
||||
\brief Build the opcode for DMAEND
|
||||
\param[in] op_buf opcode buf info
|
||||
\return bool true if the opcode fits in the allocated space
|
||||
*/
|
||||
static inline bool dma_construct_end(dma_opcode_buf *op_buf)
|
||||
{
|
||||
if ((op_buf->off + DMA_OP_1BYTE_LEN) > op_buf->buf_size)
|
||||
return false;
|
||||
|
||||
op_buf->buf[(op_buf->off)++] = OP_DMAEND;
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
/**
|
||||
\fn bool dma_construct_flushperiph(uint8_t periph,
|
||||
dma_opcode_buf *op_buf)
|
||||
\brief Build the opcode for DMAFLUSHP
|
||||
\param[in] periph peripheral number
|
||||
\param[in] op_buf opcode buf info
|
||||
\return bool true if the opcode fits in the allocated space
|
||||
*/
|
||||
static inline bool dma_construct_flushperiph(uint8_t periph,
|
||||
dma_opcode_buf *op_buf)
|
||||
{
|
||||
if ((op_buf->off + DMA_OP_2BYTE_LEN) > op_buf->buf_size)
|
||||
return false;
|
||||
|
||||
op_buf->buf[(op_buf->off)++] = OP_DMAFLUSHP;
|
||||
periph = periph & 0x1F;
|
||||
op_buf->buf[(op_buf->off)++] = (uint8_t)(periph << 3);
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
/**
|
||||
\fn bool dma_construct_go(DMA_SECURE_STATE ns,
|
||||
uint8_t channel_num,
|
||||
uint32_t imm,
|
||||
dma_opcode_buf *op_buf)
|
||||
\brief Build the opcode for DMAGO
|
||||
\param[in] ns Defines the secure/Non-Secure State
|
||||
\param[in] channel_num Defines the channel number
|
||||
\param[in] imm 32bit address where the microcode resides
|
||||
\param[in] op_buf opcode buf info
|
||||
\return void
|
||||
*/
|
||||
static inline bool dma_construct_go(DMA_SECURE_STATE ns,
|
||||
uint8_t channel_num,
|
||||
uint32_t imm,
|
||||
dma_opcode_buf *op_buf)
|
||||
{
|
||||
if ((op_buf->off + DMA_OP_6BYTE_LEN) > op_buf->buf_size)
|
||||
return false;
|
||||
|
||||
op_buf->buf[(op_buf->off)++] = (uint8_t)OP_DMAGO(ns);
|
||||
op_buf->buf[(op_buf->off)++] = channel_num & 0x7;
|
||||
op_buf->buf[(op_buf->off)++] = (uint8_t)imm;
|
||||
op_buf->buf[(op_buf->off)++] = (uint8_t)(imm >> 8);
|
||||
op_buf->buf[(op_buf->off)++] = (uint8_t)(imm >> 16);
|
||||
op_buf->buf[(op_buf->off)++] = (uint8_t)(imm >> 24);
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
/**
|
||||
\fn void dma_construct_kill(dma_opcode_buf *op_buf)
|
||||
\brief Build the opcode for DMAKILL
|
||||
\param[in] op_buf opcode buf info
|
||||
\return void
|
||||
*/
|
||||
static inline void dma_construct_kill(dma_opcode_buf *op_buf)
|
||||
{
|
||||
*op_buf->buf = OP_DMAKILL;
|
||||
}
|
||||
|
||||
/**
|
||||
\fn bool dma_construct_load(DMA_XFER xfer_type, dma_opcode_buf *op_buf
|
||||
\brief Build the opcode for DMALD
|
||||
\param[in] xfer_type Burst/Single/Force Load operation
|
||||
\param[in] op_buf opcode buf info
|
||||
\return bool true if the opcode fits in the allocated space
|
||||
*/
|
||||
static inline bool dma_construct_load(DMA_XFER xfer_type, dma_opcode_buf *op_buf)
|
||||
{
|
||||
if ((op_buf->off + DMA_OP_1BYTE_LEN) > op_buf->buf_size)
|
||||
return false;
|
||||
|
||||
if (xfer_type == DMA_XFER_FORCE)
|
||||
op_buf->buf[(op_buf->off)++] = OP_DMALD;
|
||||
else if (xfer_type == DMA_XFER_BURST)
|
||||
op_buf->buf[(op_buf->off)++] = OP_DMALDB;
|
||||
else
|
||||
op_buf->buf[(op_buf->off)++] = OP_DMALDS;
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
/**
|
||||
\fn bool dma_construct_loadperiph(DMA_XFER xfer_type,
|
||||
uint8_t periph,
|
||||
dma_opcode_buf *op_buf)
|
||||
\brief Build the opcode for DMALDP
|
||||
\param[in] xfer_type Burst or Single Load operation
|
||||
\param[in] periph Peripheral number
|
||||
\param[in] op_buf opcode buf info
|
||||
\return bool true if the opcode fits in the allocated space
|
||||
*/
|
||||
static inline bool dma_construct_loadperiph(DMA_XFER xfer_type,
|
||||
uint8_t periph,
|
||||
dma_opcode_buf *op_buf)
|
||||
{
|
||||
if ((op_buf->off + DMA_OP_2BYTE_LEN) > op_buf->buf_size)
|
||||
return false;
|
||||
|
||||
if (xfer_type > DMA_XFER_BURST)
|
||||
return false;
|
||||
|
||||
op_buf->buf[(op_buf->off)++] = (uint8_t)OP_DMALDP(xfer_type);
|
||||
periph = periph & 0x1F;
|
||||
op_buf->buf[(op_buf->off)++] = (uint8_t)(periph << 3);
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
/**
|
||||
\fn bool dma_construct_loop(DMA_LC lc,
|
||||
uint8_t iter,
|
||||
dma_opcode_buf *op_buf)
|
||||
\brief Build the opcode for DMALP
|
||||
\param[in] lc Loop Counter register number
|
||||
\param[in] iter 8bit loop value
|
||||
\param[in] op_buf opcode buf info
|
||||
\return bool true if the opcode fits in the allocated space
|
||||
*/
|
||||
static inline bool dma_construct_loop(DMA_LC lc,
|
||||
uint8_t iter,
|
||||
dma_opcode_buf *op_buf)
|
||||
{
|
||||
if ((op_buf->off + DMA_OP_2BYTE_LEN) > op_buf->buf_size)
|
||||
return false;
|
||||
|
||||
op_buf->buf[(op_buf->off)++] = (uint8_t)OP_DMALP(lc);
|
||||
op_buf->buf[(op_buf->off)++] = iter - 1;
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
/**
|
||||
\fn bool dma_construct_loopend(dma_loop_t lp_args,
|
||||
dma_opcode_buf *op_buf)
|
||||
\brief Build the opcode for DMALPEND
|
||||
\param[in] lp_args loop arguments single/burst/force, lc, nf, jump
|
||||
\param[in] op_buf opcode buf info
|
||||
\return bool true if the opcode fits in the allocated space
|
||||
*/
|
||||
static inline bool dma_construct_loopend(dma_loop_t *lp_args,
|
||||
dma_opcode_buf *op_buf)
|
||||
{
|
||||
if ((op_buf->off + DMA_OP_2BYTE_LEN) > op_buf->buf_size)
|
||||
return false;
|
||||
|
||||
if (lp_args->nf == 0)
|
||||
op_buf->buf[(op_buf->off)++] = OP_DMALPEND(0, 1);
|
||||
else if (lp_args->xfer_type == DMA_XFER_FORCE)
|
||||
op_buf->buf[(op_buf->off)++] = (uint8_t)OP_DMALPEND(1, lp_args->lc);
|
||||
else if (lp_args->xfer_type == DMA_XFER_BURST)
|
||||
op_buf->buf[(op_buf->off)++] = (uint8_t)OP_DMALPENDB(lp_args->lc);
|
||||
else
|
||||
op_buf->buf[(op_buf->off)++] = (uint8_t)OP_DMALPENDS(lp_args->lc);
|
||||
|
||||
op_buf->buf[(op_buf->off)++] = lp_args->jump;
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
/**
|
||||
\fn bool dma_construct_move(uint32_t imm,
|
||||
DMA_REG reg,
|
||||
dma_opcode_buf *op_buf)
|
||||
\brief Build the opcode for DMAMOV
|
||||
\param[in] imm 32bit immediate address
|
||||
\param[in] reg SAR/CCR/DAR register
|
||||
\param[in] op_buf opcode buf info
|
||||
\return bool true if the opcode fits in the allocated space
|
||||
*/
|
||||
static inline bool dma_construct_move(uint32_t imm,
|
||||
DMA_REG reg,
|
||||
dma_opcode_buf *op_buf)
|
||||
{
|
||||
if ((op_buf->off + DMA_OP_6BYTE_LEN) > op_buf->buf_size)
|
||||
return false;
|
||||
|
||||
op_buf->buf[(op_buf->off)++] = OP_DMAMOV;
|
||||
op_buf->buf[(op_buf->off)++] = reg & 0x7;
|
||||
op_buf->buf[(op_buf->off)++] = (uint8_t)imm;
|
||||
op_buf->buf[(op_buf->off)++] = (uint8_t)(imm >> 8);
|
||||
op_buf->buf[(op_buf->off)++] = (uint8_t)(imm >> 16);
|
||||
op_buf->buf[(op_buf->off)++] = (uint8_t)(imm >> 24);
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
/**
|
||||
\fn bool dma_construct_nop(dma_opcode_buf *op_buf)
|
||||
\brief Build the opcode for DMANOP
|
||||
\param[in] op_buf opcode buf info
|
||||
\return bool true if the opcode fits in the allocated space
|
||||
*/
|
||||
static inline bool dma_construct_nop(dma_opcode_buf *op_buf)
|
||||
{
|
||||
if ((op_buf->off + DMA_OP_1BYTE_LEN) > op_buf->buf_size)
|
||||
return false;
|
||||
|
||||
op_buf->buf[(op_buf->off)++] = OP_DMANOP;
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
/**
|
||||
\fn bool dma_construct_rmb(dma_opcode_buf *op_buf)
|
||||
\brief Build the opcode for DMARMB
|
||||
\param[in] op_buf opcode buf info
|
||||
\return bool true if the opcode fits in the allocated space
|
||||
*/
|
||||
static inline bool dma_construct_rmb(dma_opcode_buf *op_buf)
|
||||
{
|
||||
if ((op_buf->off + DMA_OP_1BYTE_LEN) > op_buf->buf_size)
|
||||
return false;
|
||||
|
||||
op_buf->buf[(op_buf->off)++] = OP_DMARMB;
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
/**
|
||||
\fn bool dma_construct_send_event(uint8_t event_num,
|
||||
dma_opcode_buf *op_buf)
|
||||
\brief Build the opcode for DMASEV
|
||||
\param[in] event_num Event number
|
||||
\param[in] op_buf opcode buf info
|
||||
\return bool true if the opcode fits in the allocated space
|
||||
*/
|
||||
static inline bool dma_construct_send_event(uint8_t event_num,
|
||||
dma_opcode_buf *op_buf)
|
||||
{
|
||||
if ((op_buf->off + DMA_OP_2BYTE_LEN) > op_buf->buf_size)
|
||||
return false;
|
||||
|
||||
op_buf->buf[(op_buf->off)++] = OP_DMASEV;
|
||||
event_num = event_num & 0x1F;
|
||||
op_buf->buf[(op_buf->off)++] = (uint8_t)(event_num << 3);
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
/**
|
||||
\fn bool dma_construct_store(DMA_XFER xfer_type,
|
||||
dma_opcode_buf *op_buf)
|
||||
\brief Build the opcode for DMAST
|
||||
\param[in] xfer_type Burst/Single/Force Load operation
|
||||
\param[in] op_buf opcode buf info
|
||||
\return bool true if the opcode fits in the allocated space
|
||||
*/
|
||||
static inline bool dma_construct_store(DMA_XFER xfer_type,
|
||||
dma_opcode_buf *op_buf)
|
||||
{
|
||||
if ((op_buf->off + DMA_OP_1BYTE_LEN) > op_buf->buf_size)
|
||||
return false;
|
||||
|
||||
if (xfer_type == DMA_XFER_FORCE)
|
||||
op_buf->buf[(op_buf->off)++] = OP_DMAST;
|
||||
else if (xfer_type == DMA_XFER_BURST)
|
||||
op_buf->buf[(op_buf->off)++] = OP_DMASTB;
|
||||
else
|
||||
op_buf->buf[(op_buf->off)++] = OP_DMASTS;
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
/**
|
||||
\fn bool dma_construct_storeperiph(DMA_XFER xfer_type,
|
||||
uint8_t periph,
|
||||
dma_opcode_buf *op_buf)
|
||||
\brief Build the opcode for DMASTP
|
||||
\param[in] xfer_type Burst or Single Store operation
|
||||
\param[in] periph Peripheral number
|
||||
\param[in] op_buf opcode buf info
|
||||
\return bool true if the opcode fits in the allocated space
|
||||
*/
|
||||
static inline bool dma_construct_storeperiph(DMA_XFER xfer_type,
|
||||
uint8_t periph,
|
||||
dma_opcode_buf *op_buf)
|
||||
{
|
||||
if ((op_buf->off + DMA_OP_2BYTE_LEN) > op_buf->buf_size)
|
||||
return false;
|
||||
|
||||
if (xfer_type > DMA_XFER_BURST)
|
||||
return false;
|
||||
|
||||
op_buf->buf[(op_buf->off)++] = (uint8_t)OP_DMASTP(xfer_type);
|
||||
periph = periph & 0x1F;
|
||||
op_buf->buf[(op_buf->off)++] = (uint8_t)(periph << 3);
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
/**
|
||||
\fn bool dma_construct_store_zeros(dma_opcode_buf *op_buf)
|
||||
\brief Build the opcode for DMASTZ
|
||||
\param[in] op_buf opcode buf info
|
||||
\return bool true if the opcode fits in the allocated space
|
||||
*/
|
||||
static inline bool dma_construct_store_zeros(dma_opcode_buf *op_buf)
|
||||
{
|
||||
if ((op_buf->off + DMA_OP_1BYTE_LEN) > op_buf->buf_size)
|
||||
return false;
|
||||
|
||||
op_buf->buf[(op_buf->off)++] = OP_DMASTZ;
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
/**
|
||||
\fn bool dma_construct_wfe(bool invalidate,
|
||||
uint8_t event_num,
|
||||
dma_opcode_buf *op_buf)
|
||||
\brief Build the opcode for DMAWFE
|
||||
\param[in] invalidate Set for invalidating the Cache
|
||||
\param[in] event_num Event number
|
||||
\param[in] op_buf opcode buf info
|
||||
\return bool true if the opcode fits in the allocated space
|
||||
*/
|
||||
static inline bool dma_construct_wfe(bool invalidate,
|
||||
uint8_t event_num,
|
||||
dma_opcode_buf *op_buf)
|
||||
{
|
||||
if ((op_buf->off + DMA_OP_2BYTE_LEN) > op_buf->buf_size)
|
||||
return false;
|
||||
|
||||
op_buf->buf[(op_buf->off)++] = OP_DMAWFE;
|
||||
event_num = event_num & 0x1F;
|
||||
op_buf->buf[(op_buf->off)++] = (uint8_t)((event_num << 3) | (invalidate << 1));
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
/**
|
||||
\fn bool dma_construct_wfp(DMA_XFER xfer_type,
|
||||
uint8_t periph_num,
|
||||
dma_opcode_buf *op_buf)
|
||||
\brief Build the opcode for DMAWFP
|
||||
\param[in] xfer_type Single/Burst/Peripheral
|
||||
\param[in] periph_num Peripheral number
|
||||
\param[in] op_buf opcode buf info
|
||||
\return bool true if the opcode fits in the allocated space
|
||||
*/
|
||||
static inline bool dma_construct_wfp(DMA_XFER xfer_type,
|
||||
uint8_t periph_num,
|
||||
dma_opcode_buf *op_buf)
|
||||
{
|
||||
if ((op_buf->off + DMA_OP_2BYTE_LEN) > op_buf->buf_size)
|
||||
return false;
|
||||
|
||||
if (xfer_type == DMA_XFER_PERIPHERAL)
|
||||
op_buf->buf[(op_buf->off)++] = OP_DMAWFP_P(1);
|
||||
else
|
||||
op_buf->buf[(op_buf->off)++] = (uint8_t)OP_DMAWFP(xfer_type);
|
||||
|
||||
periph_num = periph_num & 0x1F;
|
||||
op_buf->buf[(op_buf->off)++] = (uint8_t)(periph_num << 3);
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
/**
|
||||
\fn bool dma_construct_wmb(dma_opcode_buf *op_buf)
|
||||
\brief Build the opcode for DMAWMB
|
||||
\param[in] op_buf opcode buf info
|
||||
\return bool true if the opcode fits in the allocated space
|
||||
*/
|
||||
static inline bool dma_construct_wmb(dma_opcode_buf *op_buf)
|
||||
{
|
||||
if ((op_buf->off + DMA_OP_1BYTE_LEN) > op_buf->buf_size)
|
||||
return false;
|
||||
|
||||
op_buf->buf[(op_buf->off)++] = OP_DMAWMB;
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* DMA_OPCODE_H_ */
|
||||
149
src/hal/alif/Alif_CMSIS/Include/evtrtr.h
Normal file
149
src/hal/alif/Alif_CMSIS/Include/evtrtr.h
Normal file
@ -0,0 +1,149 @@
|
||||
/* Copyright (C) 2023 Alif Semiconductor - All Rights Reserved.
|
||||
* Use, distribution and modification of this code is permitted under the
|
||||
* terms stated in the Alif Semiconductor Software License Agreement
|
||||
*
|
||||
* You should have received a copy of the Alif Semiconductor Software
|
||||
* License Agreement with this file. If not, please write to:
|
||||
* contact@alifsemi.com, or visit: https://alifsemi.com/license
|
||||
*
|
||||
*/
|
||||
|
||||
/**************************************************************************//**
|
||||
* @file evtrtr.h
|
||||
* @author Sudhir Sreedharan
|
||||
* @email sudhir@alifsemi.com
|
||||
* @version V1.0.0
|
||||
* @date 5-May-2023
|
||||
* @brief System Control Device information for Event Router
|
||||
* @bug None.
|
||||
* @Note None
|
||||
******************************************************************************/
|
||||
#ifndef EVTRTR_H
|
||||
|
||||
#define EVTRTR_H
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include <stdint.h>
|
||||
#include <stdbool.h>
|
||||
#include "peripheral_types.h"
|
||||
#include "RTE_Components.h"
|
||||
#include CMSIS_device_header
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
/**
|
||||
* enum DMA_ACK_COMPLETION
|
||||
* Defines the completion of REQ-ACK with DMA
|
||||
*/
|
||||
typedef enum _DMA_ACK_COMPLETION
|
||||
{
|
||||
DMA_ACK_COMPLETION_PERIPHERAL, /**< Peripheral completes with DMA */
|
||||
DMA_ACK_COMPLETION_EVTRTR, /**< Event Router completes with DMA */
|
||||
} DMA_ACK_COMPLETION;
|
||||
|
||||
#define EVTRTR_DMA_CHANNEL_MAX_Msk 0x1F /* Channel range 0-31 */
|
||||
|
||||
/**
|
||||
\brief Event Router Configuration
|
||||
*/
|
||||
typedef struct _EVTRTR_CONFIG {
|
||||
|
||||
/*!< Instance number */
|
||||
const uint8_t instance;
|
||||
|
||||
/*!< Group number */
|
||||
const uint8_t group;
|
||||
|
||||
/*!< Channel number */
|
||||
const uint8_t channel;
|
||||
|
||||
/*!< Enable handshake */
|
||||
const bool enable_handshake;
|
||||
} EVTRTR_CONFIG;
|
||||
|
||||
|
||||
static inline void evtrtr0_enable_dma_channel(uint8_t channel,
|
||||
uint8_t group,
|
||||
DMA_ACK_COMPLETION ack_type)
|
||||
{
|
||||
volatile uint32_t *dma_ctrl_addr = &EVTRTR0->DMA_CTRL0 +
|
||||
(channel & EVTRTR_DMA_CHANNEL_MAX_Msk);
|
||||
|
||||
*dma_ctrl_addr = DMA_CTRL_ENA | (DMA_CTRL_SEL_Msk & group)
|
||||
| (ack_type << DMA_CTRL_ACK_TYPE_Pos);
|
||||
}
|
||||
|
||||
static inline void evtrtr0_disable_dma_channel(uint8_t channel)
|
||||
{
|
||||
volatile uint32_t *dma_ctrl_addr = &EVTRTR0->DMA_CTRL0 +
|
||||
(channel & EVTRTR_DMA_CHANNEL_MAX_Msk);
|
||||
|
||||
*dma_ctrl_addr = 0;
|
||||
}
|
||||
|
||||
static inline void evtrtr0_enable_dma_req(void)
|
||||
{
|
||||
EVTRTR0->DMA_REQ_CTRL |= (DMA_REQ_CTRL_CB | DMA_REQ_CTRL_CLB
|
||||
| DMA_REQ_CTRL_CS | DMA_REQ_CTRL_CLS);
|
||||
}
|
||||
|
||||
static inline void evtrtr0_disable_dma_req(void)
|
||||
{
|
||||
EVTRTR0->DMA_REQ_CTRL = 0;
|
||||
}
|
||||
|
||||
static inline void evtrtr0_enable_dma_handshake(uint8_t channel, uint8_t group)
|
||||
{
|
||||
volatile uint32_t *dma_ack_type_addr = &EVTRTR0->DMA_ACK_TYPE0 +
|
||||
(DMA_CTRL_SEL_Msk & group);
|
||||
|
||||
__disable_irq();
|
||||
*dma_ack_type_addr |= (1 << (channel & EVTRTR_DMA_CHANNEL_MAX_Msk));
|
||||
__enable_irq();
|
||||
}
|
||||
|
||||
static inline void evtrtr0_disable_dma_handshake(uint8_t channel, uint8_t group)
|
||||
{
|
||||
volatile uint32_t *dma_ack_type_addr = &EVTRTR0->DMA_ACK_TYPE0 +
|
||||
(DMA_CTRL_SEL_Msk & group);
|
||||
|
||||
__disable_irq();
|
||||
*dma_ack_type_addr &= ~(1 << (channel & EVTRTR_DMA_CHANNEL_MAX_Msk));
|
||||
__enable_irq();
|
||||
}
|
||||
|
||||
static inline void evtrtrlocal_enable_dma_channel(uint8_t channel,
|
||||
DMA_ACK_COMPLETION ack_type)
|
||||
{
|
||||
volatile uint32_t *dma_ctrl_addr = &EVTRTRLOCAL->DMA_CTRL0 +
|
||||
(channel & EVTRTR_DMA_CHANNEL_MAX_Msk);
|
||||
|
||||
*dma_ctrl_addr = DMA_CTRL_ENA | (ack_type << DMA_CTRL_ACK_TYPE_Pos);
|
||||
}
|
||||
|
||||
static inline void evtrtrlocal_disable_dma_channel(uint8_t channel)
|
||||
{
|
||||
volatile uint32_t *dma_ctrl_addr = &EVTRTRLOCAL->DMA_CTRL0 +
|
||||
(channel & EVTRTR_DMA_CHANNEL_MAX_Msk);
|
||||
|
||||
*dma_ctrl_addr = 0;
|
||||
}
|
||||
|
||||
static inline void evtrtrlocal_enable_dma_req(void)
|
||||
{
|
||||
EVTRTRLOCAL->DMA_REQ_CTRL |= (DMA_REQ_CTRL_CB | DMA_REQ_CTRL_CLB
|
||||
| DMA_REQ_CTRL_CS | DMA_REQ_CTRL_CLS);
|
||||
}
|
||||
|
||||
static inline void evtrtrlocal_disable_dma_req(void)
|
||||
{
|
||||
EVTRTRLOCAL->DMA_REQ_CTRL = 0;
|
||||
}
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
#endif /* EVTRTR_H */
|
||||
84
src/hal/alif/Alif_CMSIS/Source/CANFD_Private.h
Normal file
84
src/hal/alif/Alif_CMSIS/Source/CANFD_Private.h
Normal file
@ -0,0 +1,84 @@
|
||||
/* Copyright (C) 2023 Alif Semiconductor - All Rights Reserved.
|
||||
* Use, distribution and modification of this code is permitted under the
|
||||
* terms stated in the Alif Semiconductor Software License Agreement
|
||||
*
|
||||
* You should have received a copy of the Alif Semiconductor Software
|
||||
* License Agreement with this file. If not, please write to:
|
||||
* contact@alifsemi.com, or visit: https://alifsemi.com/license
|
||||
*
|
||||
*/
|
||||
|
||||
/******************************************************************************
|
||||
* @file CANFD_Private.h
|
||||
* @author Shreehari H K
|
||||
* @email shreehari.hk@alifsemi.com
|
||||
* @version V1.0.0
|
||||
* @date 05-July-2023
|
||||
* @brief Private container of canfd
|
||||
* @bug None.
|
||||
* @Note None
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef CANFD_PRIVATE_H_
|
||||
#define CANFD_PRIVATE_H_
|
||||
|
||||
#include "canfd.h"
|
||||
#include "sys_ctrl_canfd.h"
|
||||
#include "RTE_Components.h"
|
||||
#include CMSIS_device_header
|
||||
#include "Driver_CAN_EX.h"
|
||||
|
||||
#define CANFD_MAX_OBJ_SUPPORTED 2U
|
||||
|
||||
/*CANFD operational Modes */
|
||||
typedef enum _CANFD_OP_MODE
|
||||
{
|
||||
CANFD_OP_MODE_NONE = 0x0, /* No mode */
|
||||
CANFD_OP_MODE_INIT = 0x1, /* Initialization mode */
|
||||
CANFD_OP_MODE_NORMAL = 0x2, /* Normal operation mode */
|
||||
CANFD_OP_MODE_MONITOR = 0x3, /* Bus monitoring mode */
|
||||
CANFD_OP_MODE_LOOPBACK_INTERNAL = 0x4, /* Loopback internal mode */
|
||||
CANFD_OP_MODE_LOOPBACK_EXTERNAL = 0x5 /* Loopback external mode */
|
||||
}CANFD_OP_MODE;
|
||||
|
||||
/* canfd oject status*/
|
||||
typedef struct _CANFD_OBJ_STATUS
|
||||
{
|
||||
uint8_t obj_id; /* Object ID */
|
||||
ARM_CAN_OBJ_CONFIG state; /* Object state */
|
||||
}CANFD_OBJ_STATUS;
|
||||
|
||||
/* CANFD Driver state*/
|
||||
typedef struct _CANFD_DRIVER_STATE
|
||||
{
|
||||
uint32_t initialized :1; /* Driver Initialized */
|
||||
uint32_t standby :1; /* Driver in Standby */
|
||||
uint32_t powered :1; /* Driver Powered up */
|
||||
uint32_t filter_configured :1; /* Driver Acceptance filter Configured */
|
||||
uint32_t rx_busy :1; /* Busy in reception */
|
||||
uint32_t use_prim_buf :1; /* Primary buf is in use */
|
||||
uint32_t prim_buf_busy :1; /* Primary buf is busy */
|
||||
uint32_t reserved :25; /* Reserved */
|
||||
}CANFD_DRIVER_STATE;
|
||||
|
||||
/* Resource structure for CANFD */
|
||||
typedef struct _CANFD_RESOURCES
|
||||
{
|
||||
CANFD_Type *regs; /* Base address of the current instance of CANFD */
|
||||
CANFD_CNT_Type *cnt_regs; /* Base address of the CANFD Timer counter */
|
||||
ARM_CAN_SignalUnitEvent_t cb_unit_event; /* Call back function */
|
||||
ARM_CAN_SignalObjectEvent_t cb_obj_event; /* Call back function for object event */
|
||||
canfd_transfer_t data_transfer; /* Data transfer information */
|
||||
CANFD_OP_MODE op_mode; /* canfd operational mode */
|
||||
CANFD_DRIVER_STATE state; /* CANFD Driver State */
|
||||
#if RTE_CANFD_BLOCKING_MODE_ENABLE
|
||||
bool blocking_mode; /* CANFD blocking mode transfer enable */
|
||||
#endif
|
||||
uint8_t irq_priority; /* Interrupt priority */
|
||||
IRQn_Type irq_num; /* Instance IRQ number */
|
||||
ARM_CAN_STATUS status; /* CANFD instance status */
|
||||
bool fd_mode; /* CANFD Clock Control */
|
||||
CANFD_OBJ_STATUS objs[CANFD_MAX_OBJ_SUPPORTED]; /* Number of objects supported */
|
||||
}CANFD_RESOURCES;
|
||||
|
||||
#endif /* CANFD_PRIVATE_H_ */
|
||||
782
src/hal/alif/Alif_CMSIS/Source/Camera_Sensor_i2c.c
Normal file
782
src/hal/alif/Alif_CMSIS/Source/Camera_Sensor_i2c.c
Normal file
@ -0,0 +1,782 @@
|
||||
/* Copyright (C) 2022 Alif Semiconductor - All Rights Reserved.
|
||||
* Use, distribution and modification of this code is permitted under the
|
||||
* terms stated in the Alif Semiconductor Software License Agreement
|
||||
*
|
||||
* You should have received a copy of the Alif Semiconductor Software
|
||||
* License Agreement with this file. If not, please write to:
|
||||
* contact@alifsemi.com, or visit: https://alifsemi.com/license
|
||||
*
|
||||
*/
|
||||
|
||||
/**************************************************************************//**
|
||||
* @file Camera_Sensor_i2c.c
|
||||
* @author Tanay Rami
|
||||
* @email tanay@alifsemi.com
|
||||
* @version V1.0.0
|
||||
* @date 11-July-2023
|
||||
* @brief i2c driver for Camera Sensor Slave Device Communication.
|
||||
* @bug None.
|
||||
* @Note None.
|
||||
******************************************************************************/
|
||||
|
||||
/* System Includes */
|
||||
#include "RTE_Components.h"
|
||||
#include CMSIS_device_header
|
||||
|
||||
/* Project Includes */
|
||||
#include "Camera_Sensor_i2c.h"
|
||||
|
||||
/* Wrapper function for Delay
|
||||
* Delay for millisecond:
|
||||
* Provide busy loop delay
|
||||
*/
|
||||
#define DELAY_mSEC(msec) sys_busy_loop_us(msec * 1000)
|
||||
|
||||
/* i2c callback status macros */
|
||||
#define CB_XferDone 1
|
||||
#define CB_XferErr 2
|
||||
|
||||
/* I2C trasmission status macros */
|
||||
#define RESTART (0x01)
|
||||
#define STOP (0x00)
|
||||
|
||||
/* i2c callback transfer completion flag :
|
||||
* used to verify status of previous
|
||||
* transferred i3c transmit/receive API calls.
|
||||
*
|
||||
* value can be CB_XferDone or CB_XferErr.
|
||||
*/
|
||||
static volatile uint8_t CB_XferCompletionFlag = 0;
|
||||
|
||||
|
||||
/**
|
||||
\fn void camera_sensor_i2c_callback(uint32_t event)
|
||||
\brief i2c callback for Camera Sensor slave device.
|
||||
- this is internal callback to verify status of
|
||||
previous transferred transmit/receive API calls.
|
||||
- mark callback_transfer_completion_flag as
|
||||
transfer done or error as per event status.
|
||||
\param[in] event: I2C Event
|
||||
\return \ref execution_status
|
||||
*/
|
||||
static void camera_sensor_i2c_callback(uint32_t event)
|
||||
{
|
||||
/* Save received events */
|
||||
/* Optionally, user can define specific actions for an event */
|
||||
|
||||
if (event & (ARM_I2C_EVENT_TRANSFER_INCOMPLETE | ARM_I2C_EVENT_ADDRESS_NACK | ARM_I2C_EVENT_BUS_ERROR))
|
||||
{
|
||||
/* Transfer Error. */
|
||||
CB_XferCompletionFlag = CB_XferErr;
|
||||
}
|
||||
|
||||
if (event & ARM_I2C_EVENT_TRANSFER_DONE)
|
||||
{
|
||||
/* Transfer Done. */
|
||||
CB_XferCompletionFlag = CB_XferDone;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
\fn int32_t camera_sensor_i2c_init(CAMERA_SENSOR_SLAVE_I2C_CONFIG *i2c)
|
||||
\brief initialize i2c driver.
|
||||
this function will
|
||||
- select i2c instance for communication as per user input parameter.
|
||||
- initialize i2c driver with internal i2c callback.
|
||||
- power up i2c peripheral.
|
||||
- set i2c bus speed as per user input parameter.
|
||||
- attach input Camera Sensor slave device i2c address.
|
||||
- call i2c driver error if any driver API call fails.
|
||||
\param[in] i2c : Pointer to Camera Sensor slave device i2c configurations structure
|
||||
\ref CAMERA_SENSOR_SLAVE_I2C_CONFIG
|
||||
\return \ref execution_status
|
||||
*/
|
||||
int32_t camera_sensor_i2c_init(CAMERA_SENSOR_SLAVE_I2C_CONFIG *i2c)
|
||||
{
|
||||
ARM_DRIVER_I2C *drv_i2c = i2c->drv_i2c;
|
||||
int32_t ret = 0;
|
||||
|
||||
/* Initialize i3c driver */
|
||||
ret = drv_i2c->Initialize(camera_sensor_i2c_callback);
|
||||
if(ret != ARM_DRIVER_OK)
|
||||
{
|
||||
return ret;
|
||||
}
|
||||
|
||||
/* Power up i3c peripheral */
|
||||
ret = drv_i2c->PowerControl(ARM_POWER_FULL);
|
||||
if(ret != ARM_DRIVER_OK)
|
||||
{
|
||||
goto error_uninitialize;
|
||||
}
|
||||
|
||||
/* Set i2c speed mode as per user input */
|
||||
switch(i2c->bus_speed)
|
||||
{
|
||||
/* Camera Sensor slave i2c Speed Mode : Fast Mode Plus 100 KBPS */
|
||||
case ARM_I2C_BUS_SPEED_STANDARD:
|
||||
{
|
||||
ret = drv_i2c->Control(ARM_I2C_BUS_SPEED, ARM_I2C_BUS_SPEED_STANDARD);
|
||||
break;
|
||||
}
|
||||
|
||||
/* Camera Sensor slave i2c Speed Mode : Fast Mode 400 KBPS */
|
||||
case ARM_I2C_BUS_SPEED_FAST:
|
||||
{
|
||||
ret = drv_i2c->Control(ARM_I2C_BUS_SPEED, ARM_I2C_BUS_SPEED_FAST);
|
||||
break;
|
||||
}
|
||||
|
||||
/* Camera Sensor slave i2c Speed Mode : Standard Mode 1 MBPS */
|
||||
case ARM_I2C_BUS_SPEED_FAST_PLUS:
|
||||
{
|
||||
ret = drv_i2c->Control(ARM_I2C_BUS_SPEED, ARM_I2C_BUS_SPEED_FAST_PLUS);
|
||||
break;
|
||||
}
|
||||
|
||||
/* Camera Sensor slave i2c Speed Mode : Standard Mode 3.4 MBPS */
|
||||
case ARM_I2C_BUS_SPEED_HIGH:
|
||||
{
|
||||
ret = drv_i2c->Control(ARM_I2C_BUS_SPEED, ARM_I2C_BUS_SPEED_HIGH);
|
||||
break;
|
||||
}
|
||||
|
||||
default:
|
||||
{
|
||||
return ARM_DRIVER_ERROR_PARAMETER;
|
||||
}
|
||||
}
|
||||
|
||||
if(ret != ARM_DRIVER_OK)
|
||||
{
|
||||
goto error_poweroff;
|
||||
}
|
||||
|
||||
return ARM_DRIVER_OK;
|
||||
|
||||
error_poweroff:
|
||||
/* Power off I2C peripheral */
|
||||
ret = drv_i2c->PowerControl(ARM_POWER_OFF);
|
||||
if(ret != ARM_DRIVER_OK)
|
||||
{
|
||||
return ret;
|
||||
}
|
||||
|
||||
error_uninitialize:
|
||||
/* Un-initialize I2C driver */
|
||||
ret = drv_i2c->Uninitialize();
|
||||
if(ret != ARM_DRIVER_OK)
|
||||
{
|
||||
return ret;
|
||||
}
|
||||
|
||||
return ARM_DRIVER_ERROR;
|
||||
}
|
||||
|
||||
/**
|
||||
\fn int32_t camera_sensor_i2c_write(CAMERA_SENSOR_SLAVE_I2C_CONFIG *i2c,
|
||||
uint32_t reg_addr,
|
||||
uint32_t reg_value,
|
||||
CAMERA_SENSOR_I2C_REG_SIZE reg_size)
|
||||
\brief write value to Camera Sensor slave device register using i2c.
|
||||
this function will
|
||||
- fill data as per Camera Sensor slave device supported
|
||||
register address type: 8-bit/16-bit.
|
||||
- as Camera Sensor slave device supports Big endian mode:
|
||||
- convert data from Little Endian to Big Endian
|
||||
(only required if Camera Sensor slave device supports
|
||||
- 16-bit register addressing or
|
||||
- register size is >8-bit.)
|
||||
- transmit data to already attached Camera Sensor slave i2c device.
|
||||
\param[in] i2c : Pointer to Camera Sensor slave device i2c configurations structure
|
||||
\ref CAMERA_SENSOR_SLAVE_I2C_CONFIG
|
||||
\param[in] reg_addr : register address of Camera Sensor slave device
|
||||
\param[in] reg_value : register value
|
||||
\param[in] reg_size : register size \ref CAMERA_SENSOR_I2C_REG_SIZE
|
||||
\return \ref execution_status
|
||||
*/
|
||||
int32_t camera_sensor_i2c_write(CAMERA_SENSOR_SLAVE_I2C_CONFIG *i2c,
|
||||
uint32_t reg_addr,
|
||||
uint32_t reg_value,
|
||||
CAMERA_SENSOR_I2C_REG_SIZE reg_size)
|
||||
{
|
||||
uint8_t addr_low = reg_addr & 0xFF;
|
||||
uint8_t addr_high = (reg_addr >> 8) & 0xFF;
|
||||
uint8_t addr_len = 0;
|
||||
|
||||
ARM_DRIVER_I2C *drv_i2c = i2c->drv_i2c;
|
||||
|
||||
/* Max size of tx data = Max slave reg_addr_type(16-bit/2 byte) +
|
||||
* Max reg_size(32-bit/4 byte)
|
||||
*/
|
||||
uint8_t tx_data[6] = {0};
|
||||
uint8_t data_len = 0;
|
||||
|
||||
uint8_t i = 0;
|
||||
uint32_t temp = 0;
|
||||
uint32_t timeout = 0;
|
||||
int32_t ret = 0;
|
||||
CAMERA_SENSOR_I2C_REG_ADDR_TYPE reg_addr_type = i2c->cam_sensor_slave_reg_addr_type;
|
||||
|
||||
/* supports only 8-bit/16-bit Camera Sensor slave register address type. */
|
||||
if( (reg_addr_type != CAMERA_SENSOR_I2C_REG_ADDR_TYPE_8BIT) && \
|
||||
(reg_addr_type != CAMERA_SENSOR_I2C_REG_ADDR_TYPE_16BIT) )
|
||||
{
|
||||
return ARM_DRIVER_ERROR_PARAMETER;
|
||||
}
|
||||
|
||||
/* supports max 32-bit Camera Sensor slave register size. */
|
||||
if(reg_size > CAMERA_SENSOR_I2C_REG_SIZE_32BIT)
|
||||
{
|
||||
return ARM_DRIVER_ERROR_PARAMETER;
|
||||
}
|
||||
|
||||
/* To write to any Camera Sensor slave register address:
|
||||
*
|
||||
* 1.) As Camera Sensor slave device supports Big endian mode,
|
||||
* first convert input data from Little endian to Big endian.
|
||||
* (only required if Camera Sensor slave device supports
|
||||
* - 16-bit register addressing or
|
||||
* - register size is >8-bit.)
|
||||
*
|
||||
* 2.) Then Transmit data to i2c TX FIFO as shown below:
|
||||
* register address + register value
|
||||
* (base on type 8/16 bit) (base on register size 8/16/32 bit)
|
||||
*/
|
||||
|
||||
/*
|
||||
* @Note: Convert data from Little Endian to Big Endian
|
||||
* (only required if Camera Sensor slave device supports
|
||||
* - 16-bit register addressing or
|
||||
* - register size is >8-bit.)
|
||||
*
|
||||
* How much data(register address + actual data) user has to Transmit/Receive ?
|
||||
* it depends on Slave's register address location bytes.
|
||||
* Generally, Camera Slave supports 16-bit(2 Byte) register address and (8/16/32 bit) data
|
||||
* Others Accelerometer/EEPROM supports 8-bit(1 Byte) register address and (8/16/32 bit) data
|
||||
*
|
||||
* First LSB[7-0] will be added to TX FIFO and first transmitted on the i2c bus;
|
||||
* remaining bytes will be added in LSB -> MSB order.
|
||||
*
|
||||
* For Slave who supports 16-bit(2 Byte) register address and data:
|
||||
* Register Address[15:8] : Needs to be Transmit First to the i2c
|
||||
* Register Address[07:0] : Needs to be Transmit Second to the i2c
|
||||
*
|
||||
* That means,
|
||||
*
|
||||
* While transmitting to i2c TX FIFO,
|
||||
* MSB of TX data needs to be added first to the i2c TX FIFO.
|
||||
*
|
||||
* While receiving from i2c RX FIFO,
|
||||
* First MSB will be received from i3c RX FIFO.
|
||||
*
|
||||
* START I2C FIFO END
|
||||
* MSB LSB
|
||||
* 24-31 bit | 16-23 bit | 8-15 bit | 0-7 bit
|
||||
*
|
||||
* So, USER has to modify(we have already done it below for you!)
|
||||
* Transmit/Receive data (Little Endian <-> Big Endian and vice versa)
|
||||
* before sending/after receiving to/from i2c TX/RX FIFO.
|
||||
*/
|
||||
|
||||
/* if Camera Sensor slave supports 8-bit register address type. */
|
||||
if(reg_addr_type == CAMERA_SENSOR_I2C_REG_ADDR_TYPE_8BIT)
|
||||
{
|
||||
/* @Note: 8-bit Register Address Type is not yet tested
|
||||
* with any 8-bit supported Camera Sensor slave device.
|
||||
*/
|
||||
tx_data[0] = addr_low;
|
||||
addr_len = 1;
|
||||
}
|
||||
|
||||
/* if Camera Sensor slave supports 16-bit register address type. */
|
||||
if(reg_addr_type == CAMERA_SENSOR_I2C_REG_ADDR_TYPE_16BIT)
|
||||
{
|
||||
tx_data[0] = addr_high;
|
||||
tx_data[1] = addr_low;
|
||||
addr_len = 2;
|
||||
}
|
||||
|
||||
/* total data length is register address type + register size */
|
||||
data_len = (addr_len + reg_size);
|
||||
|
||||
/* For Transmit, Convert input data from Little Endian to Big Endian. */
|
||||
i = reg_size;
|
||||
temp = reg_value;
|
||||
|
||||
while(i--)
|
||||
{
|
||||
tx_data[addr_len + i] = (temp & 0xff);
|
||||
temp >>= 8;
|
||||
}
|
||||
|
||||
/* clear i2c callback completion flag. */
|
||||
CB_XferCompletionFlag = 0;
|
||||
|
||||
/* Transmit data to i2C TX FIFO. */
|
||||
ret = drv_i2c->MasterTransmit(i2c->cam_sensor_slave_addr, tx_data, data_len, STOP);
|
||||
if(ret != ARM_DRIVER_OK)
|
||||
{
|
||||
return ARM_DRIVER_ERROR;
|
||||
}
|
||||
|
||||
/* timeout in millisecond. */
|
||||
timeout = 100;
|
||||
|
||||
/* wait for i2c callback within timeout. */
|
||||
while(timeout--)
|
||||
{
|
||||
/* received callback? */
|
||||
if(CB_XferCompletionFlag)
|
||||
{
|
||||
break;
|
||||
}
|
||||
|
||||
/* sleep or wait for millisecond depending on RTOS availability. */
|
||||
DELAY_mSEC(1);
|
||||
}
|
||||
|
||||
/* i3c module failed to respond? power off and de-init i2c driver and return error. */
|
||||
if(!CB_XferCompletionFlag)
|
||||
{
|
||||
return ARM_DRIVER_ERROR;
|
||||
}
|
||||
|
||||
/* return error, if received transfer error. */
|
||||
if(CB_XferCompletionFlag == CB_XferErr)
|
||||
{
|
||||
return ARM_DRIVER_ERROR;
|
||||
}
|
||||
|
||||
/* received transfer success. */
|
||||
return ARM_DRIVER_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
\fn int32_t camera_sensor_i2c_write_burst(CAMERA_SENSOR_SLAVE_I2C_CONFIG *i2c,
|
||||
uint32_t reg_addr,
|
||||
void *reg_values,
|
||||
CAMERA_SENSOR_I2C_REG_SIZE reg_size,
|
||||
uint32_t burst_len)
|
||||
\brief write values to Camera Sensor slave device register using i2c.
|
||||
this function will
|
||||
- fill data as per Camera Sensor slave device supported
|
||||
register address type: 8-bit/16-bit.
|
||||
- as Camera Sensor slave device supports Big endian mode:
|
||||
- convert data from Little Endian to Big Endian
|
||||
(only required if Camera Sensor slave device supports
|
||||
- 16-bit register addressing or
|
||||
- register size is >8-bit.)
|
||||
- transmit data to already attached Camera Sensor slave i2c device.
|
||||
\param[in] i2c : Pointer to Camera Sensor slave device i2c configurations structure
|
||||
\ref CAMERA_SENSOR_SLAVE_I2C_CONFIG
|
||||
\param[in] reg_addr : register address of Camera Sensor slave device
|
||||
\param[in] reg_values : register values
|
||||
\param[in] reg_size : register size \ref CAMERA_SENSOR_I2C_REG_SIZE
|
||||
\param[in] burst_len : Burst length
|
||||
\return \ref execution_status
|
||||
*/
|
||||
int32_t camera_sensor_i2c_write_burst(CAMERA_SENSOR_SLAVE_I2C_CONFIG *i2c,
|
||||
uint32_t reg_addr,
|
||||
void *reg_values,
|
||||
CAMERA_SENSOR_I2C_REG_SIZE reg_size,
|
||||
uint32_t burst_len)
|
||||
{
|
||||
uint8_t addr_low = reg_addr & 0xFF;
|
||||
uint8_t addr_high = (reg_addr >> 8) & 0xFF;
|
||||
|
||||
ARM_DRIVER_I2C *drv_i2c = i2c->drv_i2c;
|
||||
|
||||
uint8_t i = 0;
|
||||
uint32_t timeout = 0;
|
||||
int32_t ret = 0;
|
||||
CAMERA_SENSOR_I2C_REG_ADDR_TYPE reg_addr_len = i2c->cam_sensor_slave_reg_addr_type;
|
||||
|
||||
/* supports only 8-bit/16-bit Camera Sensor slave register address type. */
|
||||
if( (reg_addr_len != CAMERA_SENSOR_I2C_REG_ADDR_TYPE_8BIT) && \
|
||||
(reg_addr_len != CAMERA_SENSOR_I2C_REG_ADDR_TYPE_16BIT) )
|
||||
{
|
||||
return ARM_DRIVER_ERROR_PARAMETER;
|
||||
}
|
||||
|
||||
/* total data length is register address len + (register size * burst length) */
|
||||
uint8_t data_len = ((reg_size * burst_len) + reg_addr_len);
|
||||
|
||||
if(data_len > CAMERA_SENSOR_MAX_BURST_SIZE)
|
||||
{
|
||||
return ARM_DRIVER_ERROR_PARAMETER;
|
||||
}
|
||||
|
||||
uint8_t tx_data[CAMERA_SENSOR_MAX_BURST_SIZE];
|
||||
|
||||
/* To write to any Camera Sensor slave register address:
|
||||
*
|
||||
* 1.) As Camera Sensor slave device supports Big endian mode,
|
||||
* first convert input data from Little endian to Big endian.
|
||||
* (only required if Camera Sensor slave device supports
|
||||
* - 16-bit register addressing or
|
||||
* - register size is >8-bit.)
|
||||
*
|
||||
* 2.) Then Transmit data to i2c TX FIFO as shown below:
|
||||
* register address + register value
|
||||
* (base on type 8/16 bit) (base on register size 8/16/32 bit)
|
||||
*/
|
||||
|
||||
/*
|
||||
* @Note: Convert data from Little Endian to Big Endian
|
||||
* (only required if Camera Sensor slave device supports
|
||||
* - 16-bit register addressing or
|
||||
* - register size is >8-bit.)
|
||||
*
|
||||
* How much data(register address + actual data) user has to Transmit/Receive ?
|
||||
* it depends on Slave's register address location bytes.
|
||||
* Generally, Camera Slave supports 16-bit(2 Byte) register address and (8/16/32 bit) data
|
||||
* Others Accelerometer/EEPROM supports 8-bit(1 Byte) register address and (8/16/32 bit) data
|
||||
*
|
||||
* First LSB[7-0] will be added to TX FIFO and first transmitted on the i2c bus;
|
||||
* remaining bytes will be added in LSB -> MSB order.
|
||||
*
|
||||
* For Slave who supports 16-bit(2 Byte) register address and data:
|
||||
* Register Address[15:8] : Needs to be Transmit First to the i2c
|
||||
* Register Address[07:0] : Needs to be Transmit Second to the i2c
|
||||
*
|
||||
* That means,
|
||||
*
|
||||
* While transmitting to i2c TX FIFO,
|
||||
* MSB of TX data needs to be added first to the i2c TX FIFO.
|
||||
*
|
||||
* While receiving from i2c RX FIFO,
|
||||
* First MSB will be received from i3c RX FIFO.
|
||||
*
|
||||
* START I2C FIFO END
|
||||
* MSB LSB
|
||||
* 24-31 bit | 16-23 bit | 8-15 bit | 0-7 bit
|
||||
*
|
||||
* So, USER has to modify(we have already done it below for you!)
|
||||
* Transmit/Receive data (Little Endian <-> Big Endian and vice versa)
|
||||
* before sending/after receiving to/from i2c TX/RX FIFO.
|
||||
*/
|
||||
|
||||
/* if Camera Sensor slave supports 8-bit register address type. */
|
||||
if(reg_addr_len == CAMERA_SENSOR_I2C_REG_ADDR_TYPE_8BIT)
|
||||
{
|
||||
/* @Note: 8-bit Register Address Type is not yet tested
|
||||
* with any 8-bit supported Camera Sensor slave device.
|
||||
*/
|
||||
tx_data[0] = addr_low;
|
||||
}
|
||||
|
||||
/* if Camera Sensor slave supports 16-bit register address type. */
|
||||
if(reg_addr_len == CAMERA_SENSOR_I2C_REG_ADDR_TYPE_16BIT)
|
||||
{
|
||||
tx_data[0] = addr_high;
|
||||
tx_data[1] = addr_low;
|
||||
}
|
||||
|
||||
/* For Transmit, Convert input data from Little Endian to Big Endian. */
|
||||
i = reg_addr_len;
|
||||
for(uint32_t reg_idx = 0; reg_idx < burst_len; reg_idx++)
|
||||
{
|
||||
if(reg_size == CAMERA_SENSOR_I2C_REG_SIZE_8BIT)
|
||||
{
|
||||
tx_data[i++] = (*((uint8_t *)reg_values + reg_idx));
|
||||
}
|
||||
else if(reg_size == CAMERA_SENSOR_I2C_REG_SIZE_16BIT)
|
||||
{
|
||||
tx_data[i++] = ((*((uint16_t *)reg_values + reg_idx) >> 8) & 0xff);
|
||||
tx_data[i++] = (*((uint16_t *)reg_values + reg_idx) & 0xff);
|
||||
}
|
||||
else if(reg_size == CAMERA_SENSOR_I2C_REG_SIZE_32BIT)
|
||||
{
|
||||
tx_data[i++] = ((*((uint32_t *)reg_values + reg_idx) >> 24) & 0xff);
|
||||
tx_data[i++] = ((*((uint32_t *)reg_values + reg_idx) >> 16) & 0xff);
|
||||
tx_data[i++] = ((*((uint32_t *)reg_values + reg_idx) >> 8) & 0xff);
|
||||
tx_data[i++] = (*((uint32_t *)reg_values + reg_idx) & 0xff);
|
||||
}
|
||||
}
|
||||
|
||||
/* clear i2c callback completion flag. */
|
||||
CB_XferCompletionFlag = 0;
|
||||
|
||||
/* Transmit data to i2C TX FIFO. */
|
||||
ret = drv_i2c->MasterTransmit(i2c->cam_sensor_slave_addr, tx_data, data_len, STOP);
|
||||
if(ret != ARM_DRIVER_OK)
|
||||
{
|
||||
return ARM_DRIVER_ERROR;
|
||||
}
|
||||
|
||||
/* timeout in millisecond. */
|
||||
timeout = 100;
|
||||
|
||||
/* wait for i2c callback within timeout. */
|
||||
while(timeout--)
|
||||
{
|
||||
/* received callback? */
|
||||
if(CB_XferCompletionFlag)
|
||||
{
|
||||
break;
|
||||
}
|
||||
|
||||
/* sleep or wait for millisecond depending on RTOS availability. */
|
||||
DELAY_mSEC(1);
|
||||
}
|
||||
|
||||
/* i3c module failed to respond? power off and de-init i2c driver and return error. */
|
||||
if(!CB_XferCompletionFlag)
|
||||
{
|
||||
return ARM_DRIVER_ERROR;
|
||||
}
|
||||
|
||||
/* return error, if received transfer error. */
|
||||
if(CB_XferCompletionFlag == CB_XferErr)
|
||||
{
|
||||
return ARM_DRIVER_ERROR;
|
||||
}
|
||||
|
||||
/* received transfer success. */
|
||||
return ARM_DRIVER_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
\fn int32_t camera_sensor_i2c_read(CAMERA_SENSOR_SLAVE_I2C_CONFIG *i2c,
|
||||
uint32_t reg_addr,
|
||||
uint32_t *reg_value,
|
||||
CAMERA_SENSOR_I2C_REG_SIZE reg_size)
|
||||
\brief read value from Camera Sensor slave device register using i2c.
|
||||
this function will
|
||||
- to read from register,
|
||||
- first transmit register address location,
|
||||
- then receive register value from that location.
|
||||
- fill data as per Camera Sensor slave device supported
|
||||
register address type 8-bit/16-bit.
|
||||
- transmit data to already attached Camera Sensor slave i2c device.
|
||||
- receive data from attached Camera Sensor slave i2c device depending on
|
||||
register size.
|
||||
- As Camera Sensor slave device supports Big endian mode:
|
||||
- convert received data from Big Endian to Little Endian
|
||||
(only required if Camera Sensor slave supports
|
||||
- 16-bit register addressing
|
||||
- reg_size is >8-bit.)
|
||||
\param[in] i2c : Pointer to Camera Sensor slave device i2c configurations structure
|
||||
\ref CAMERA_SENSOR_SLAVE_I2C_CONFIG
|
||||
\param[in] reg_addr : register address of Camera Sensor slave device
|
||||
\param[in] reg_value : pointer to register value
|
||||
\param[in] reg_size : register size \ref CAMERA_SENSOR_I2C_REG_SIZE
|
||||
\return \ref execution_status
|
||||
*/
|
||||
int32_t camera_sensor_i2c_read(CAMERA_SENSOR_SLAVE_I2C_CONFIG *i2c,
|
||||
uint32_t reg_addr,
|
||||
uint32_t *reg_value,
|
||||
CAMERA_SENSOR_I2C_REG_SIZE reg_size)
|
||||
{
|
||||
uint8_t addr_low = reg_addr & 0xFF;
|
||||
uint8_t addr_high = (reg_addr >> 8) & 0xFF;
|
||||
uint8_t addr_len = 0;
|
||||
|
||||
ARM_DRIVER_I2C *drv_i2c = i2c->drv_i2c;
|
||||
|
||||
/* Max size of tx data = Max reg_addr type(16-bit/2 byte) */
|
||||
uint8_t tx_data[2] = {00};
|
||||
|
||||
/* Max size of rx data = Max reg_size(32-bit/4 byte) */
|
||||
uint8_t rx_data[4] = {00};
|
||||
uint8_t data_len = 0;
|
||||
|
||||
uint8_t i = 0;
|
||||
uint32_t temp = 0;
|
||||
uint32_t timeout = 0;
|
||||
int32_t ret = 0;
|
||||
|
||||
CAMERA_SENSOR_I2C_REG_ADDR_TYPE reg_addr_type = i2c->cam_sensor_slave_reg_addr_type;
|
||||
|
||||
/* supports only 8-bit/16-bit Camera Sensor slave register address type. */
|
||||
if( (reg_addr_type != CAMERA_SENSOR_I2C_REG_ADDR_TYPE_8BIT) && \
|
||||
(reg_addr_type != CAMERA_SENSOR_I2C_REG_ADDR_TYPE_16BIT) )
|
||||
{
|
||||
return ARM_DRIVER_ERROR_PARAMETER;
|
||||
}
|
||||
|
||||
/* supports max 32-bit Camera Sensor slave register size. */
|
||||
if(reg_size > CAMERA_SENSOR_I2C_REG_SIZE_32BIT)
|
||||
{
|
||||
return ARM_DRIVER_ERROR_PARAMETER;
|
||||
}
|
||||
|
||||
/* To Read from any Camera Sensor slave register address:
|
||||
*
|
||||
* 1.) As Camera Sensor slave device supports Big endian mode,
|
||||
* first convert input data from Little endian to Big endian.
|
||||
* (only required if Camera Sensor slave device supports
|
||||
* - 16-bit register addressing or
|
||||
* - register size is >8-bit.)
|
||||
*
|
||||
* 2.) Then Transmit data(register address location) to i2c TX FIFO
|
||||
* as shown below:
|
||||
* register address
|
||||
* (base on type 8/16 bit)
|
||||
*
|
||||
* 3.) Receive data from register location using i2c RX FIFO
|
||||
* as shown below:
|
||||
* read register value
|
||||
* (base on register size 8/16/32 bit)
|
||||
*
|
||||
* 4.) Convert Receive data back from Big Endian to Little Endian
|
||||
* (only required if Camera Sensor slave device supports
|
||||
* - 16-bit register addressing or
|
||||
* - register size is >8-bit.)
|
||||
*/
|
||||
|
||||
/*
|
||||
* @Note: Convert data from Big Endian to Little Endian.
|
||||
* (only required if Camera Sensor slave device supports
|
||||
* - 16-bit register addressing or
|
||||
* - register size is >8-bit.)
|
||||
*
|
||||
* How much data(register address + actual data) user has to Transmit/Receive ?
|
||||
* it depends on Slave's register address location bytes.
|
||||
* Generally, Camera Slave supports 16-bit(2 Byte) register address and (8/16/32 bit) data
|
||||
* Others Accelerometer/EEPROM supports 8-bit(1 Byte) register address and (8/16/32 bit) data
|
||||
*
|
||||
* First LSB[7-0] will be added to TX FIFO and first transmitted on the i2c bus;
|
||||
* remaining bytes will be added in LSB -> MSB order.
|
||||
*
|
||||
* For Slave who supports 16-bit(2 Byte) register address and data:
|
||||
* Register Address[15:8] : Needs to be Transmit First to the i2c
|
||||
* Register Address[07:0] : Needs to be Transmit Second to the i2c
|
||||
*
|
||||
* That means,
|
||||
*
|
||||
* While transmitting to i2c TX FIFO,
|
||||
* MSB of TX data needs to be added first to the i2c TX FIFO.
|
||||
*
|
||||
* While receiving from i2c RX FIFO,
|
||||
* First MSB will be received from i2c RX FIFO.
|
||||
*
|
||||
* START I2C FIFO END
|
||||
* MSB LSB
|
||||
* 24-31 bit | 16-23 bit | 8-15 bit | 0-7 bit
|
||||
*
|
||||
* So, USER has to modify(we have already done it below for you!)
|
||||
* Transmit/Receive data (Little Endian <-> Big Endian and vice versa)
|
||||
* before sending/after receiving to/from i2c TX/RX FIFO.
|
||||
*/
|
||||
|
||||
/* if Camera Sensor slave supports 8-bit register address type. */
|
||||
if(reg_addr_type == CAMERA_SENSOR_I2C_REG_ADDR_TYPE_8BIT)
|
||||
{
|
||||
/* @Note: 8-bit Register Address Type is not yet tested
|
||||
* with any 8-bit supported Camera Sensor slave device.
|
||||
*/
|
||||
tx_data[0] = addr_low;
|
||||
addr_len = 1;
|
||||
}
|
||||
|
||||
/* if Camera Sensor slave supports 16-bit register address type. */
|
||||
if(reg_addr_type == CAMERA_SENSOR_I2C_REG_ADDR_TYPE_16BIT)
|
||||
{
|
||||
tx_data[0] = addr_high;
|
||||
tx_data[1] = addr_low;
|
||||
addr_len = 2;
|
||||
}
|
||||
|
||||
/* transmit register location, data length is only register address type. */
|
||||
data_len = addr_len;
|
||||
|
||||
/* clear i2c callback completion flag. */
|
||||
CB_XferCompletionFlag = 0;
|
||||
|
||||
/* Transmit data to I2C TX FIFO. */
|
||||
ret = drv_i2c->MasterTransmit(i2c->cam_sensor_slave_addr, tx_data, data_len, STOP);
|
||||
if(ret != ARM_DRIVER_OK)
|
||||
{
|
||||
return ARM_DRIVER_ERROR;
|
||||
}
|
||||
|
||||
/* timeout in millisecond. */
|
||||
timeout = 100;
|
||||
|
||||
/* wait for i2c callback within timeout. */
|
||||
while(timeout--)
|
||||
{
|
||||
/* received callback? */
|
||||
if(CB_XferCompletionFlag)
|
||||
{
|
||||
break;
|
||||
}
|
||||
|
||||
/* sleep or wait for millisecond depending on RTOS availability. */
|
||||
DELAY_mSEC(1);
|
||||
}
|
||||
|
||||
/* i3c module failed to respond? power off and de-init i2c driver and return error. */
|
||||
if(!CB_XferCompletionFlag)
|
||||
{
|
||||
return ARM_DRIVER_ERROR;
|
||||
}
|
||||
|
||||
/* return error, if received transfer error. */
|
||||
if(CB_XferCompletionFlag == CB_XferErr)
|
||||
{
|
||||
return ARM_DRIVER_ERROR;
|
||||
}
|
||||
|
||||
/* received transfer success.
|
||||
* now, read from register address location.
|
||||
* data length will be register address size. */
|
||||
data_len = reg_size;
|
||||
|
||||
/* clear i2c callback completion flag. */
|
||||
CB_XferCompletionFlag = 0;
|
||||
|
||||
/* Receive data from I2C RX FIFO. */
|
||||
ret = drv_i2c->MasterReceive(i2c->cam_sensor_slave_addr, rx_data, data_len, 0x00);
|
||||
if(ret != ARM_DRIVER_OK)
|
||||
{
|
||||
return ARM_DRIVER_ERROR;
|
||||
}
|
||||
|
||||
/* timeout in millisecond. */
|
||||
timeout = 100;
|
||||
|
||||
/* wait for i2c callback within timeout. */
|
||||
while(timeout--)
|
||||
{
|
||||
/* received callback? */
|
||||
if(CB_XferCompletionFlag)
|
||||
{
|
||||
break;
|
||||
}
|
||||
|
||||
/* sleep or wait for millisecond depending on RTOS availability. */
|
||||
DELAY_mSEC(1);
|
||||
}
|
||||
|
||||
/* i3c module failed to respond? power off and de-init i2c driver and return error. */
|
||||
if(!CB_XferCompletionFlag)
|
||||
{
|
||||
return ARM_DRIVER_ERROR;
|
||||
}
|
||||
|
||||
/* return error, if received transfer error. */
|
||||
if(CB_XferCompletionFlag == CB_XferErr)
|
||||
{
|
||||
return ARM_DRIVER_ERROR;
|
||||
}
|
||||
|
||||
/* received transfer success.
|
||||
* now for Receive, Convert received data back from Big Endian to Little Endian. */
|
||||
i = 0;
|
||||
temp = 0;
|
||||
for(i=0; i<reg_size; i++)
|
||||
{
|
||||
temp <<= 8;
|
||||
temp |= rx_data[i];
|
||||
}
|
||||
|
||||
/* update register value */
|
||||
*reg_value = temp;
|
||||
|
||||
return ARM_DRIVER_OK;
|
||||
}
|
||||
|
||||
/************************ (C) COPYRIGHT ALIF SEMICONDUCTOR *****END OF FILE****/
|
||||
94
src/hal/alif/Alif_CMSIS/Source/Camera_Sensor_i2c.h
Normal file
94
src/hal/alif/Alif_CMSIS/Source/Camera_Sensor_i2c.h
Normal file
@ -0,0 +1,94 @@
|
||||
/* Copyright (C) 2023 Alif Semiconductor - All Rights Reserved.
|
||||
* Use, distribution and modification of this code is permitted under the
|
||||
* terms stated in the Alif Semiconductor Software License Agreement
|
||||
*
|
||||
* You should have received a copy of the Alif Semiconductor Software
|
||||
* License Agreement with this file. If not, please write to:
|
||||
* contact@alifsemi.com, or visit: https://alifsemi.com/license
|
||||
*
|
||||
*/
|
||||
|
||||
/**************************************************************************//**
|
||||
* @file Camera_Sensor_i2c.h
|
||||
* @author Tanay Rami
|
||||
* @email tanay@alifsemi.com
|
||||
* @version V1.0.0
|
||||
* @date 11-July-2023
|
||||
* @brief i2c definitions for Camera Sensor Slave Device
|
||||
* Communication.
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef CAMERA_SENSOR_I2C_H_
|
||||
#define CAMERA_SENSOR_I2C_H_
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
#include <stdint.h>
|
||||
#include "Driver_I2C.h"
|
||||
|
||||
/* To ensure proper operation, please allocate sufficient stack
|
||||
* space for the camera_sensor_i2c_write_burst API in your application
|
||||
* configuration. This includes the 50-byte buffer along with the
|
||||
* driver's own stack requirements.*/
|
||||
#define CAMERA_SENSOR_MAX_BURST_SIZE 50
|
||||
|
||||
/**
|
||||
\brief Camera Sensor i2c Register Address Type
|
||||
*/
|
||||
typedef enum _CAMERA_SENSOR_I2C_REG_ADDR_TYPE {
|
||||
CAMERA_SENSOR_I2C_REG_ADDR_TYPE_8BIT = 1, /* Camera Sensor i2c Register Address type : 8-bit */
|
||||
CAMERA_SENSOR_I2C_REG_ADDR_TYPE_16BIT = 2, /* Camera Sensor i2c Register Address type : 16-bit */
|
||||
} CAMERA_SENSOR_I2C_REG_ADDR_TYPE;
|
||||
|
||||
/**
|
||||
\brief Camera Sensor i2c Register Size
|
||||
*/
|
||||
typedef enum _CAMERA_SENSOR_I2C_REG_SIZE {
|
||||
CAMERA_SENSOR_I2C_REG_SIZE_8BIT = 1, /* Camera Sensor i2c Register Size : 8-bit */
|
||||
CAMERA_SENSOR_I2C_REG_SIZE_16BIT = 2, /* Camera Sensor i2c Register Size : 16-bit */
|
||||
CAMERA_SENSOR_I2C_REG_SIZE_32BIT = 4, /* Camera Sensor i2c Register Size : 32-bit */
|
||||
} CAMERA_SENSOR_I2C_REG_SIZE;
|
||||
|
||||
/**
|
||||
\brief Camera Sensor Slave i2c Configuration
|
||||
*/
|
||||
typedef struct CAMERA_SENSOR_SLAVE_I2C_CONFIG {
|
||||
ARM_DRIVER_I2C *drv_i2c; /* Camera Sensor i2C driver instance */
|
||||
uint16_t bus_speed; /* Camera Sensor slave i2c Bus Speed */
|
||||
uint8_t cam_sensor_slave_addr; /* Camera Sensor slave i2c Address */
|
||||
CAMERA_SENSOR_I2C_REG_ADDR_TYPE cam_sensor_slave_reg_addr_type; /* Camera Sensor slave i2c Register Address type */
|
||||
} CAMERA_SENSOR_SLAVE_I2C_CONFIG;
|
||||
|
||||
|
||||
/* initialize i2c driver. */
|
||||
int32_t camera_sensor_i2c_init(CAMERA_SENSOR_SLAVE_I2C_CONFIG *i2c);
|
||||
|
||||
/* write value to Camera Sensor slave register using i2c. */
|
||||
int32_t camera_sensor_i2c_write(CAMERA_SENSOR_SLAVE_I2C_CONFIG *i2c,
|
||||
uint32_t reg_addr,
|
||||
uint32_t reg_value,
|
||||
CAMERA_SENSOR_I2C_REG_SIZE reg_size);
|
||||
|
||||
/* write burst of values to Camera Sensor slave register using i2c. */
|
||||
int32_t camera_sensor_i2c_write_burst(CAMERA_SENSOR_SLAVE_I2C_CONFIG *i2c,
|
||||
uint32_t reg_addr,
|
||||
void *reg_values,
|
||||
CAMERA_SENSOR_I2C_REG_SIZE reg_size,
|
||||
uint32_t burst_len);
|
||||
|
||||
/* read value from Camera Sensor slave register using i2c. */
|
||||
int32_t camera_sensor_i2c_read(CAMERA_SENSOR_SLAVE_I2C_CONFIG *i2c,
|
||||
uint32_t reg_addr,
|
||||
uint32_t *reg_value,
|
||||
CAMERA_SENSOR_I2C_REG_SIZE reg_size);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* CAMERA_SENSOR_I2C_H_ */
|
||||
|
||||
/************************ (C) COPYRIGHT ALIF SEMICONDUCTOR *****END OF FILE****/
|
||||
343
src/hal/alif/Alif_CMSIS/Source/DPHY_CSI2.c
Normal file
343
src/hal/alif/Alif_CMSIS/Source/DPHY_CSI2.c
Normal file
@ -0,0 +1,343 @@
|
||||
/* Copyright (C) 2024 Alif Semiconductor - All Rights Reserved.
|
||||
* Use, distribution and modification of this code is permitted under the
|
||||
* terms stated in the Alif Semiconductor Software License Agreement
|
||||
*
|
||||
* You should have received a copy of the Alif Semiconductor Software
|
||||
* License Agreement with this file. If not, please write to:
|
||||
* contact@alifsemi.com, or visit: https://alifsemi.com/license
|
||||
*
|
||||
*/
|
||||
|
||||
/******************************************************************************
|
||||
* @file DPHY_CSI.c
|
||||
* @author Prasanna Ravi and Chandra Bhushan Singh
|
||||
* @email prasanna.ravi@alifsemi.com and chandrabhushan.singh@alifsemi.com
|
||||
* @version V1.0.0
|
||||
* @date 14-May-2024
|
||||
* @brief Driver for MIPI DPHY CSI2.
|
||||
* @bug None.
|
||||
* @Note None.
|
||||
******************************************************************************/
|
||||
#include <stdint.h>
|
||||
#include "Driver_Common.h"
|
||||
#include "RTE_Components.h"
|
||||
#include CMSIS_device_header
|
||||
#include "RTE_Device.h"
|
||||
#include "DPHY_Test_and_Control_Interface.h"
|
||||
#include "DPHY_Private.h"
|
||||
#include "dphy.h"
|
||||
#include "sys_ctrl_dphy.h"
|
||||
#include "DPHY_CSI2.h"
|
||||
#include "csi.h"
|
||||
#include "sys_ctrl_csi.h"
|
||||
|
||||
/*DPHY initialize status global variables*/
|
||||
static volatile uint32_t csi2_init_status = 0;
|
||||
|
||||
/*hsfreqrange and osc_freq_target range*/
|
||||
extern const DPHY_FREQ_RANGE frequency_range[];
|
||||
|
||||
/**
|
||||
\fn static void MIPI_CSI2_DPHY_Shutdown (uint8_t state)
|
||||
\brief PHY shutdown line control callback function.
|
||||
\param[in] state ENABLE/DISABLE the line.
|
||||
*/
|
||||
static void MIPI_CSI2_DPHY_Shutdown (uint8_t state)
|
||||
{
|
||||
if(state == ENABLE)
|
||||
{
|
||||
csi_enable_dphy_shutdown_line((CSI_Type *)CSI_BASE);
|
||||
}
|
||||
else
|
||||
{
|
||||
csi_disable_dphy_shutdown_line((CSI_Type *)CSI_BASE);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
\fn static void MIPI_CSI2_DPHY_Testclr (uint8_t state)
|
||||
\brief PHY testclr line control callback function.
|
||||
\param[in] state ENABLE/DISABLE the line.
|
||||
*/
|
||||
static void MIPI_CSI2_DPHY_Testclr (uint8_t state)
|
||||
{
|
||||
if(state == ENABLE)
|
||||
{
|
||||
csi_enable_dphy_testclr_line((CSI_Type *)CSI_BASE);
|
||||
}
|
||||
else
|
||||
{
|
||||
csi_disable_dphy_testclr_line((CSI_Type *)CSI_BASE);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
\fn static void MIPI_CSI2_DPHY_Rst (uint8_t state)
|
||||
\brief PHY reset line control callback function.
|
||||
\param[in] state ENABLE/DISABLE the line.
|
||||
*/
|
||||
static void MIPI_CSI2_DPHY_Rst (uint8_t state)
|
||||
{
|
||||
if(state == ENABLE)
|
||||
{
|
||||
csi_enable_dphy_reset_line((CSI_Type *)CSI_BASE);
|
||||
}
|
||||
else
|
||||
{
|
||||
csi_disable_dphy_reset_line((CSI_Type *)CSI_BASE);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
\fn static uint8_t MIPI_CSI2_DPHY_Stopstate (void)
|
||||
\brief status of stopstate from PHY
|
||||
\return ret status of stopstate.
|
||||
*/
|
||||
static DPHY_STOPSTATE MIPI_CSI2_DPHY_Stopstate (void)
|
||||
{
|
||||
uint8_t ret = 0;
|
||||
|
||||
if(csi_get_lane_stopstate_status((CSI_Type *)CSI_BASE, CSI_LANE_CLOCK) == CSI_LANE_STOPSTATE_ON)
|
||||
{
|
||||
ret |= DPHY_STOPSTATE_CLOCK;
|
||||
}
|
||||
|
||||
if(csi_get_lane_stopstate_status((CSI_Type *)CSI_BASE, CSI_LANE_0) == CSI_LANE_STOPSTATE_ON)
|
||||
{
|
||||
ret |= DPHY_STOPSTATE_LANE0;
|
||||
}
|
||||
|
||||
if(csi_get_lane_stopstate_status((CSI_Type *)CSI_BASE, CSI_LANE_1) == CSI_LANE_STOPSTATE_ON)
|
||||
{
|
||||
ret |= DPHY_STOPSTATE_LANE1;
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/**
|
||||
\fn uint8_t DPHY_CSI2_Read_Mask (uint16_t address,
|
||||
uint8_t pos,
|
||||
uint8_t width)
|
||||
\brief Read Mask CSI2 DPHY registers.
|
||||
\param[in] address is register index.
|
||||
\param[in] pos is start bit position.
|
||||
\param[in] width is number bits to read.
|
||||
\return return received data from DPHY register.
|
||||
*/
|
||||
uint8_t DPHY_CSI2_Read_Mask (uint16_t address,
|
||||
uint8_t pos,
|
||||
uint8_t width)
|
||||
{
|
||||
return (MIPI_DPHY_Read(address, DPHY_MODE_CFG_CSI2) >> pos) & ((1 << width) - 1);
|
||||
}
|
||||
|
||||
/**
|
||||
\fn void DPHY_CSI2_Write_Mask (uint16_t address,
|
||||
uint8_t data,
|
||||
uint8_t pos,
|
||||
uint8_t width)
|
||||
\brief write Mask CSI2 DPHY registers.
|
||||
\param[in] address is register index
|
||||
\param[in] data is value to be write to the DPHY register.
|
||||
\param[in] pos is start bit position.
|
||||
\param[in] width is number bits to write.
|
||||
*/
|
||||
void DPHY_CSI2_Write_Mask (uint16_t address,
|
||||
uint8_t data,
|
||||
uint8_t pos,
|
||||
uint8_t width)
|
||||
{
|
||||
uint8_t reg_data = 0;
|
||||
uint8_t mask = (1U << width) - 1;
|
||||
|
||||
reg_data = MIPI_DPHY_Read(address, DPHY_MODE_CFG_CSI2);
|
||||
reg_data &= ~(mask << pos);
|
||||
reg_data |= (data & mask) << pos;
|
||||
MIPI_DPHY_Write(address, reg_data, DPHY_MODE_CFG_CSI2);
|
||||
}
|
||||
|
||||
/**
|
||||
\fn void DPHY_PowerEnable (void)
|
||||
\brief Enable DPHY Interface Power.
|
||||
*/
|
||||
static void DPHY_PowerEnable (void)
|
||||
{
|
||||
enable_csi_periph_clk();
|
||||
|
||||
enable_rxdphy_configure_clock();
|
||||
|
||||
}
|
||||
|
||||
/**
|
||||
\fn void DPHY_PowerDisable (void)
|
||||
\brief Disable DPHY Interface Power.
|
||||
*/
|
||||
static void DPHY_PowerDisable (void)
|
||||
{
|
||||
|
||||
disable_csi_periph_clk();
|
||||
|
||||
disable_rxdphy_configure_clock();
|
||||
|
||||
}
|
||||
|
||||
/**
|
||||
\fn int32_t DPHY_SlaveSetup (uint32_t clock_frequency, uint8_t n_lanes)
|
||||
\brief MIPI DPHY Rx startup sequence.
|
||||
\param[in] clock_frequency DPHY clock frequency.
|
||||
\param[in] n_lanes number of lanes.
|
||||
\return \ref execution_status
|
||||
*/
|
||||
static int32_t DPHY_SlaveSetup (uint32_t clock_frequency, uint8_t n_lanes)
|
||||
{
|
||||
uint32_t bitrate_mbps = (clock_frequency * 2)/1000000;
|
||||
uint8_t hsfreqrange = 0;
|
||||
uint8_t cfgclkfreqrange = 0;
|
||||
uint32_t osc_freq_target = 0;
|
||||
uint8_t range = 0;
|
||||
uint8_t stopstate_check =0;
|
||||
uint32_t lp_count = 0;
|
||||
|
||||
csi_set_n_active_lanes((CSI_Type *)CSI_BASE, (n_lanes - 1));
|
||||
|
||||
if(bitrate_mbps < 80 || bitrate_mbps > 2500)
|
||||
{
|
||||
return ARM_DRIVER_ERROR;
|
||||
}
|
||||
|
||||
for(range = 0; (bitrate_mbps > frequency_range[range].bitrate_in_mbps);
|
||||
++range);
|
||||
|
||||
hsfreqrange = frequency_range[range].hsfreqrange;
|
||||
osc_freq_target = frequency_range[range].osc_freq_target;
|
||||
|
||||
MIPI_CSI2_DPHY_Rst(DISABLE);
|
||||
|
||||
MIPI_CSI2_DPHY_Shutdown(DISABLE);
|
||||
|
||||
set_rx_dphy_txrx(DPHY_MODE_SLAVE);
|
||||
|
||||
set_rx_dphy_testport_select(DPHY_TESTPORT_SELECT_RX);
|
||||
MIPI_CSI2_DPHY_Testclr(ENABLE);
|
||||
set_rx_dphy_testport_select(DPHY_TESTPORT_SELECT_TX);
|
||||
MIPI_CSI2_DPHY_Testclr(ENABLE);
|
||||
|
||||
sys_busy_loop_us(1);
|
||||
|
||||
set_rx_dphy_testport_select(DPHY_TESTPORT_SELECT_RX);
|
||||
MIPI_CSI2_DPHY_Testclr(DISABLE);
|
||||
set_rx_dphy_testport_select(DPHY_TESTPORT_SELECT_TX);
|
||||
MIPI_CSI2_DPHY_Testclr(DISABLE);
|
||||
|
||||
set_rx_dphy_hsfreqrange(hsfreqrange);
|
||||
|
||||
DPHY_CSI2_Write_Mask(dphy4txtester_DIG_RDWR_TX_PLL_13, 0x3, 0, 2);
|
||||
|
||||
DPHY_CSI2_Write_Mask(dphy4txtester_DIG_RDWR_TX_CB_1, 0x2, 0, 2);
|
||||
|
||||
DPHY_CSI2_Write_Mask(dphy4txtester_DIG_RDWR_TX_CB_0, 0x2, 5, 2);
|
||||
|
||||
DPHY_CSI2_Write_Mask(dphy4txtester_DIG_RDWR_TX_PLL_9, 0x1, 3, 1);
|
||||
|
||||
set_rx_dphy_testport_select(DPHY_TESTPORT_SELECT_RX);
|
||||
|
||||
DPHY_CSI2_Write_Mask(dphy4rxtester_DIG_RDWR_RX_CLKLANE_LANE_6, 0x1, 7, 1);
|
||||
|
||||
if((bitrate_mbps) == 80)
|
||||
{
|
||||
DPHY_CSI2_Write_Mask(dphy4rxtester_DIG_RD_RX_SYS_1, 0x85, 0, 8);
|
||||
}
|
||||
|
||||
DPHY_CSI2_Write_Mask(dphy4rxtester_DIG_RDWR_RX_RX_STARTUP_OVR_2, (uint8_t)osc_freq_target, 0, 8);
|
||||
|
||||
DPHY_CSI2_Write_Mask(dphy4rxtester_DIG_RDWR_RX_RX_STARTUP_OVR_3, (uint8_t)(osc_freq_target >> 8), 0, 4);
|
||||
|
||||
DPHY_CSI2_Write_Mask(dphy4rxtester_DIG_RDWR_RX_RX_STARTUP_OVR_4, 0x1, 0, 1);
|
||||
|
||||
cfgclkfreqrange = (DPHY_FCFG_CLOCK_MHZ - 17) * 4;
|
||||
|
||||
set_rx_dphy_cfgclkfreqrange(cfgclkfreqrange);
|
||||
|
||||
set_rx_dphy_basedir((1U << n_lanes) - 1);
|
||||
|
||||
set_rx_dphy_forcerxmode((1U << n_lanes) - 1);
|
||||
|
||||
sys_busy_loop_us(1);
|
||||
|
||||
MIPI_CSI2_DPHY_Shutdown(ENABLE);
|
||||
|
||||
sys_busy_loop_us(1);
|
||||
|
||||
MIPI_CSI2_DPHY_Rst(ENABLE);
|
||||
|
||||
stopstate_check |= DPHY_STOPSTATE_CLOCK | (n_lanes == 1 ? (DPHY_STOPSTATE_LANE0) :
|
||||
(DPHY_STOPSTATE_LANE0) | (DPHY_STOPSTATE_LANE1) );
|
||||
|
||||
while(MIPI_CSI2_DPHY_Stopstate() != stopstate_check)
|
||||
{
|
||||
if(lp_count++ < 1000000)
|
||||
{
|
||||
sys_busy_loop_us(1);
|
||||
}
|
||||
else
|
||||
{
|
||||
return ARM_DRIVER_ERROR;
|
||||
}
|
||||
}
|
||||
|
||||
unset_rx_dphy_forcerxmode((1U << n_lanes) - 1);
|
||||
|
||||
return ARM_DRIVER_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
\fn int32_t CSI2_DPHY_Initialize (uint32_t frequency, uint8_t n_lanes)
|
||||
\brief Initialize MIPI CSI2 DPHY Interface.
|
||||
\param[in] frequency to configure DPHY PLL.
|
||||
\param[in] n_lanes number of lanes.
|
||||
\return \ref execution_status
|
||||
*/
|
||||
int32_t CSI2_DPHY_Initialize (uint32_t frequency, uint8_t n_lanes)
|
||||
{
|
||||
int32_t ret = ARM_DRIVER_OK;
|
||||
|
||||
if(csi2_init_status == DPHY_INIT_STATUS_INITIALIZED)
|
||||
{
|
||||
return ARM_DRIVER_OK;
|
||||
|
||||
}
|
||||
|
||||
DPHY_PowerEnable();
|
||||
|
||||
ret = DPHY_SlaveSetup(frequency, n_lanes);
|
||||
if(ret != ARM_DRIVER_OK)
|
||||
{
|
||||
return ret;
|
||||
}
|
||||
|
||||
csi2_init_status = DPHY_INIT_STATUS_INITIALIZED;
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/**
|
||||
\fn int32_t CSI2_DPHY_Uninitialize (void)
|
||||
\brief Uninitialize MIPI CSI2 DPHY Interface.
|
||||
\return \ref execution_status
|
||||
*/
|
||||
int32_t CSI2_DPHY_Uninitialize (void)
|
||||
{
|
||||
if(csi2_init_status == DPHY_INIT_STATUS_UNINITIALIZED)
|
||||
{
|
||||
return ARM_DRIVER_OK;
|
||||
}
|
||||
|
||||
MIPI_CSI2_DPHY_Rst(DISABLE);
|
||||
MIPI_CSI2_DPHY_Shutdown(DISABLE);
|
||||
DPHY_PowerDisable();
|
||||
|
||||
csi2_init_status = DPHY_INIT_STATUS_UNINITIALIZED;
|
||||
|
||||
return ARM_DRIVER_OK;
|
||||
}
|
||||
41
src/hal/alif/Alif_CMSIS/Source/DPHY_CSI2.h
Normal file
41
src/hal/alif/Alif_CMSIS/Source/DPHY_CSI2.h
Normal file
@ -0,0 +1,41 @@
|
||||
/* Copyright (C) 2024 Alif Semiconductor - All Rights Reserved.
|
||||
* Use, distribution and modification of this code is permitted under the
|
||||
* terms stated in the Alif Semiconductor Software License Agreement
|
||||
*
|
||||
* You should have received a copy of the Alif Semiconductor Software
|
||||
* License Agreement with this file. If not, please write to:
|
||||
* contact@alifsemi.com, or visit: https://alifsemi.com/license
|
||||
*
|
||||
*/
|
||||
|
||||
/******************************************************************************
|
||||
* @file DPHY_DSI.h
|
||||
* @author Prasanna Ravi
|
||||
* @email prasanna.ravi@alifsemi.com
|
||||
* @version V1.0.0
|
||||
* @date 14-May-2024
|
||||
* @brief Driver Specific Header file for DPHY CSI2 Driver.
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef DPHY_CSI2_H_
|
||||
#define DPHY_CSI2_H_
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
/**
|
||||
\fn int32_t CSI2_DPHY_Initialize (uint32_t frequency, uint8_t n_lanes)
|
||||
\brief Initialize MIPI CSI2 DPHY Interface.
|
||||
\param[in] frequency to configure DPHY PLL.
|
||||
\param[in] n_lanes number of lanes.
|
||||
\return \ref execution_status
|
||||
*/
|
||||
int32_t CSI2_DPHY_Initialize (uint32_t frequency, uint8_t n_lanes);
|
||||
|
||||
/**
|
||||
\fn int32_t CSI2_DPHY_Uninitialize (void)
|
||||
\brief Uninitialize MIPI CSI2 DPHY Interface.
|
||||
\return \ref execution_status
|
||||
*/
|
||||
int32_t CSI2_DPHY_Uninitialize (void);
|
||||
|
||||
#endif /* DPHY_CSI2_H_ */
|
||||
197
src/hal/alif/Alif_CMSIS/Source/DPHY_Common.c
Normal file
197
src/hal/alif/Alif_CMSIS/Source/DPHY_Common.c
Normal file
@ -0,0 +1,197 @@
|
||||
/* Copyright (C) 2024 Alif Semiconductor - All Rights Reserved.
|
||||
* Use, distribution and modification of this code is permitted under the
|
||||
* terms stated in the Alif Semiconductor Software License Agreement
|
||||
*
|
||||
* You should have received a copy of the Alif Semiconductor Software
|
||||
* License Agreement with this file. If not, please write to:
|
||||
* contact@alifsemi.com, or visit: https://alifsemi.com/license
|
||||
*
|
||||
*/
|
||||
|
||||
/******************************************************************************
|
||||
* @file DPHY_Common.c
|
||||
* @author Prasanna Ravi and Chandra Bhushan Singh
|
||||
* @email prasanna.ravi@alifsemi.com and chandrabhushan.singh@alifsemi.com
|
||||
* @version V1.0.0
|
||||
* @date 14-May-2024
|
||||
* @brief Driver for MIPI DPHY test and control interface and common data.
|
||||
* @bug None.
|
||||
* @Note None.
|
||||
******************************************************************************/
|
||||
#include <stdint.h>
|
||||
#include <stddef.h>
|
||||
#include "DPHY_Test_and_Control_Interface.h"
|
||||
#include "DPHY_Private.h"
|
||||
#include "dphy.h"
|
||||
#include "RTE_Components.h"
|
||||
#include CMSIS_device_header
|
||||
|
||||
/*hsfreqrange and osc_freq_target range*/
|
||||
const DPHY_FREQ_RANGE frequency_range[] =
|
||||
{
|
||||
{ 80, 0x00, 0x1E9 }, { 90, 0x10, 0x1E9 }, { 100, 0x20, 0x1E9 },
|
||||
{ 110, 0x30, 0x1E9 }, { 120, 0x01, 0x1E9 }, { 130, 0x11, 0x1E9 },
|
||||
{ 140, 0x21, 0x1E9 }, { 150, 0x31, 0x1E9 }, { 160, 0x02, 0x1E9 },
|
||||
{ 170, 0x12, 0x1E9 }, { 180, 0x22, 0x1E9 }, { 190, 0x32, 0x1E9 },
|
||||
{ 205, 0x03, 0x1E9 }, { 220, 0x13, 0x1E9 }, { 235, 0x23, 0x1E9 },
|
||||
{ 250, 0x33, 0x1E9 }, { 275, 0x04, 0x1E9 }, { 300, 0x14, 0x1E9 },
|
||||
{ 325, 0x25, 0x1E9 }, { 350, 0x35, 0x1E9 }, { 400, 0x05, 0x1E9 },
|
||||
{ 450, 0x16, 0x1E9 }, { 500, 0x26, 0x1E9 }, { 550, 0x37, 0x1E9 },
|
||||
{ 600, 0x07, 0x1E9 }, { 650, 0x18, 0x1E9 }, { 700, 0x28, 0x1E9 },
|
||||
{ 750, 0x39, 0x1E9 }, { 800, 0x09, 0x1E9 }, { 850, 0x19, 0x1E9 },
|
||||
{ 900, 0x29, 0x1E9 }, { 950, 0x3A, 0x1E9 }, { 1000, 0x0A, 0x1E9 },
|
||||
{ 1050, 0x1A, 0x1E9 }, { 1100, 0x2A, 0x1E9 }, { 1150, 0x3B, 0x1E9 },
|
||||
{ 1200, 0x0B, 0x1E9 }, { 1250, 0x1B, 0x1E9 }, { 1300, 0x2B, 0x1E9 },
|
||||
{ 1350, 0x3C, 0x1E9 }, { 1400, 0x0C, 0x1E9 }, { 1450, 0x1C, 0x1E9 },
|
||||
{ 1500, 0x2C, 0x1E9 }, { 1550, 0x3D, 0x12F }, { 1600, 0x0D, 0x139 },
|
||||
{ 1650, 0x1D, 0x143 }, { 1700, 0x2E, 0x14D }, { 1750, 0x3E, 0x156 },
|
||||
{ 1800, 0x0E, 0x160 }, { 1850, 0x1E, 0x16A }, { 1900, 0x2F, 0x174 },
|
||||
{ 1950, 0x3F, 0x17D }, { 2000, 0x0F, 0x187 }, { 2050, 0x40, 0x191 },
|
||||
{ 2100, 0x41, 0x19B }, { 2150, 0x42, 0x19B }, { 2200, 0x43, 0x19B },
|
||||
{ 2250, 0x44, 0x19B }, { 2300, 0x45, 0x19B }, { 2350, 0x46, 0x19B },
|
||||
{ 2400, 0x47, 0x19B }, { 2450, 0x48, 0x19B }, { 2500, 0x49, 0x19B }
|
||||
};
|
||||
|
||||
/**
|
||||
\fn static uint8_t MIPI_DPHY_Read (uint16_t address, DPHY_Mode mode)
|
||||
\brief Test and control interface protocol to read DPHY registers.
|
||||
\param[in] address index on DPHY register.
|
||||
\param[in] mode is to select the DPHY mode(CSI2/DSI).
|
||||
\return ret register value.
|
||||
*/
|
||||
uint8_t MIPI_DPHY_Read (uint16_t address, DPHY_MODE_CFG mode)
|
||||
{
|
||||
uint8_t ret = 0;
|
||||
uint32_t read_reg = 0;
|
||||
volatile uint32_t *test_ctrl0 = NULL;
|
||||
volatile uint32_t *test_ctrl1 = NULL;
|
||||
|
||||
if(mode == DPHY_MODE_CFG_DSI)
|
||||
{
|
||||
test_ctrl0 = (uint32_t *)PHY_DSI_TEST_CTRL0_BASE;
|
||||
test_ctrl1 = (uint32_t *)PHY_DSI_TEST_CTRL1_BASE;
|
||||
}
|
||||
else
|
||||
{
|
||||
test_ctrl0 = (uint32_t *)PHY_CSI_TEST_CTRL0_BASE;
|
||||
test_ctrl1 = (uint32_t *)PHY_CSI_TEST_CTRL1_BASE;
|
||||
}
|
||||
|
||||
/*Ensure that t(r)x_testclk and t(r)x_testen is set to low*/
|
||||
CLEAR_BIT(*test_ctrl0, PHY_TESTCLK_Msk);
|
||||
CLEAR_BIT(*test_ctrl1, PHY_TESTEN_Msk);
|
||||
/*Set t(r)x_testen to high. */
|
||||
SET_BIT(*test_ctrl1, PHY_TESTEN_Msk);
|
||||
/*Set t(r)x_testen to high. */
|
||||
SET_BIT(*test_ctrl0, PHY_TESTCLK_Msk);
|
||||
/*Place 0x00 in t(r)x_testdin.*/
|
||||
read_reg = READ_REG(*test_ctrl1);
|
||||
read_reg &= ~(PHY_TESTDIN_Msk);
|
||||
WRITE_REG(*test_ctrl1, read_reg);
|
||||
/*Set t(r)x_testclk to low (with the falling edge on t(r)x_testclk,
|
||||
the t(r)x_testdin signal content is latched internally).*/
|
||||
CLEAR_BIT(*test_ctrl0, PHY_TESTCLK_Msk);
|
||||
/*Set t(r)x_testen to low*/
|
||||
CLEAR_BIT(*test_ctrl1, PHY_TESTEN_Msk);
|
||||
/*Place the 8-bit word corresponding to the testcode MSBs in t(r)x_testdin.*/
|
||||
read_reg = READ_REG(*test_ctrl1);
|
||||
read_reg &= ~(PHY_TESTDIN_Msk);
|
||||
read_reg |= _VAL2FLD(PHY_TESTDIN, (address >> 8));
|
||||
WRITE_REG(*test_ctrl1, read_reg);
|
||||
/*Set t(r)x_testclk to high.*/
|
||||
SET_BIT(*test_ctrl0, PHY_TESTCLK_Msk);
|
||||
/*Set t(r)x_testclk to low*/
|
||||
CLEAR_BIT(*test_ctrl0, PHY_TESTCLK_Msk);
|
||||
/*Set t(r)x_testen to high*/
|
||||
SET_BIT(*test_ctrl1, PHY_TESTEN_Msk);
|
||||
/*Set t(r)x_testclk to high.*/
|
||||
SET_BIT(*test_ctrl0, PHY_TESTCLK_Msk);
|
||||
/*Place the 8-bit word test data in t(r)x_testdin.*/
|
||||
read_reg = READ_REG(*test_ctrl1);
|
||||
read_reg &= ~(PHY_TESTDIN_Msk);
|
||||
read_reg |= _VAL2FLD(PHY_TESTDIN, address);
|
||||
WRITE_REG(*test_ctrl1, read_reg);
|
||||
/*Set t(r)x_testclk to low (with the falling edge on t(r)x_testclk,
|
||||
the t(r)x_testdin signal content is latched internally).*/
|
||||
CLEAR_BIT(*test_ctrl0, PHY_TESTCLK_Msk);
|
||||
read_reg = READ_REG(*test_ctrl1);
|
||||
read_reg &= (PHY_TESTDOUT_Msk);
|
||||
ret = _FLD2VAL(PHY_TESTDOUT, read_reg);
|
||||
/*Set t(r)x_testen to low.*/
|
||||
CLEAR_BIT(*test_ctrl1, PHY_TESTEN_Msk);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/**
|
||||
\fn static void MIPI_CSI2_DPHY_Write (uint16_t address, uint8_t data)
|
||||
\brief Test and control interface protocol to Write DPHY registers.
|
||||
\param[in] address index on DPHY register.
|
||||
\param[in] data register value.
|
||||
\param[in] mode is to select the DPHY mode(CSI2/DSI).
|
||||
*/
|
||||
void MIPI_DPHY_Write (uint16_t address, uint8_t data, DPHY_MODE_CFG mode)
|
||||
{
|
||||
uint32_t read_reg = 0;
|
||||
volatile uint32_t *test_ctrl0 = NULL;
|
||||
volatile uint32_t *test_ctrl1 = NULL;
|
||||
|
||||
if(mode == DPHY_MODE_CFG_DSI)
|
||||
{
|
||||
test_ctrl0 = (uint32_t *)PHY_DSI_TEST_CTRL0_BASE;
|
||||
test_ctrl1 = (uint32_t *)PHY_DSI_TEST_CTRL1_BASE;
|
||||
}
|
||||
else
|
||||
{
|
||||
test_ctrl0 = (uint32_t *)PHY_CSI_TEST_CTRL0_BASE;
|
||||
test_ctrl1 = (uint32_t *)PHY_CSI_TEST_CTRL1_BASE;
|
||||
}
|
||||
|
||||
/*Ensure that t(r)x_testclk and t(r)x_testen is set to low*/
|
||||
CLEAR_BIT(*test_ctrl0, PHY_TESTCLK_Msk);
|
||||
CLEAR_BIT(*test_ctrl1, PHY_TESTEN_Msk);
|
||||
/*Set t(r)x_testen to high. */
|
||||
SET_BIT(*test_ctrl1, PHY_TESTEN_Msk);
|
||||
/*Set t(r)x_testen to high. */
|
||||
SET_BIT(*test_ctrl0, PHY_TESTCLK_Msk);
|
||||
/*Place 0x00 in t(r)x_testdin.*/
|
||||
read_reg = READ_REG(*test_ctrl1);
|
||||
read_reg &= ~(PHY_TESTDIN_Msk);
|
||||
WRITE_REG(*test_ctrl1, read_reg);
|
||||
/*Set t(r)x_testclk to low (with the falling edge on t(r)x_testclk,
|
||||
the t(r)x_testdin signal content is latched internally).*/
|
||||
CLEAR_BIT(*test_ctrl0, PHY_TESTCLK_Msk);
|
||||
/*Set t(r)x_testen to low*/
|
||||
CLEAR_BIT(*test_ctrl1, PHY_TESTEN_Msk);
|
||||
/*Place the 8-bit word corresponding to the testcode MSBs in t(r)x_testdin.*/
|
||||
read_reg = READ_REG(*test_ctrl1);
|
||||
read_reg &= ~(PHY_TESTDIN_Msk);
|
||||
read_reg |= _VAL2FLD(PHY_TESTDIN, (address >> 8));
|
||||
WRITE_REG(*test_ctrl1, read_reg);
|
||||
/*Set t(r)x_testclk to high.*/
|
||||
SET_BIT(*test_ctrl0, PHY_TESTCLK_Msk);
|
||||
/*Set t(r)x_testclk to low*/
|
||||
CLEAR_BIT(*test_ctrl0, PHY_TESTCLK_Msk);
|
||||
/*Set t(r)x_testen to high*/
|
||||
SET_BIT(*test_ctrl1, PHY_TESTEN_Msk);
|
||||
/*Set t(r)x_testclk to high.*/
|
||||
SET_BIT(*test_ctrl0, PHY_TESTCLK_Msk);
|
||||
/*Place the 8-bit word test data in t(r)x_testdin.*/
|
||||
read_reg = READ_REG(*test_ctrl1);
|
||||
read_reg &= ~(PHY_TESTDIN_Msk);
|
||||
read_reg |= _VAL2FLD(PHY_TESTDIN, address);
|
||||
WRITE_REG(*test_ctrl1, read_reg);
|
||||
/*Set t(r)x_testclk to low (with the falling edge on t(r)x_testclk,
|
||||
the t(r)x_testdin signal content is latched internally).*/
|
||||
CLEAR_BIT(*test_ctrl0, PHY_TESTCLK_Msk);
|
||||
/*Set t(r)x_testen to low.*/
|
||||
CLEAR_BIT(*test_ctrl1, PHY_TESTEN_Msk);
|
||||
/*Place the 8-bit word corresponding to the page offset in t(r)x_testdin.*/
|
||||
read_reg = READ_REG(*test_ctrl1);
|
||||
read_reg &= ~(PHY_TESTDIN_Msk);
|
||||
read_reg |= _VAL2FLD(PHY_TESTDIN, data);
|
||||
WRITE_REG(*test_ctrl1, read_reg);
|
||||
/*Set t(r)x_testclk to high (test data is programmed internally).*/
|
||||
SET_BIT(*test_ctrl0, PHY_TESTCLK_Msk);
|
||||
CLEAR_BIT(*test_ctrl0, PHY_TESTCLK_Msk);
|
||||
}
|
||||
488
src/hal/alif/Alif_CMSIS/Source/DPHY_DSI.c
Normal file
488
src/hal/alif/Alif_CMSIS/Source/DPHY_DSI.c
Normal file
@ -0,0 +1,488 @@
|
||||
/* Copyright (C) 2024 Alif Semiconductor - All Rights Reserved.
|
||||
* Use, distribution and modification of this code is permitted under the
|
||||
* terms stated in the Alif Semiconductor Software License Agreement
|
||||
*
|
||||
* You should have received a copy of the Alif Semiconductor Software
|
||||
* License Agreement with this file. If not, please write to:
|
||||
* contact@alifsemi.com, or visit: https://alifsemi.com/license
|
||||
*
|
||||
*/
|
||||
|
||||
/******************************************************************************
|
||||
* @file DPHY_DSI.c
|
||||
* @author Prasanna Ravi and Chandra Bhushan Singh
|
||||
* @email prasanna.ravi@alifsemi.com and chandrabhushan.singh@alifsemi.com
|
||||
* @version V1.0.0
|
||||
* @date 14-May-2024
|
||||
* @brief Driver for MIPI DPHY DSI.
|
||||
* @bug None.
|
||||
* @Note None.
|
||||
******************************************************************************/
|
||||
#include <stdint.h>
|
||||
#include "Driver_Common.h"
|
||||
#include "RTE_Components.h"
|
||||
#include CMSIS_device_header
|
||||
#include "RTE_Device.h"
|
||||
#include "DPHY_Test_and_Control_Interface.h"
|
||||
#include "DPHY_Private.h"
|
||||
#include "dphy.h"
|
||||
#include "sys_ctrl_dphy.h"
|
||||
#include "dsi.h"
|
||||
#include "sys_ctrl_dsi.h"
|
||||
#include "DPHY_DSI.h"
|
||||
|
||||
/*DPHY initialize status global variables*/
|
||||
static volatile uint32_t dsi_init_status = 0;
|
||||
|
||||
/*hsfreqrange and osc_freq_target range*/
|
||||
extern const DPHY_FREQ_RANGE frequency_range[];
|
||||
|
||||
/*vco_cntrl range*/
|
||||
static const DPHY_PLL_VCO_CTRL vco_ctrl_range[] =
|
||||
{
|
||||
{ 1170, 0x03 }, { 975, 0x07 }, { 853.125, 0x08 }, { 706.875, 0x08 },
|
||||
{ 585, 0x0B }, { 487.5, 0x0F }, { 426.56, 0x10 }, { 353.4, 0x10 },
|
||||
{ 292.5, 0x13 }, { 243.75, 0x17 }, { 213.3, 0x18 }, { 176.72, 0x18 },
|
||||
{ 146.25, 0x1B }, { 121.88, 0x1F }, { 106.64, 0x20 }, { 88.36, 0x20 },
|
||||
{ 73.13, 0x23}, { 60.93, 0x27 }, { 53.32, 0x28 }, { 44.18, 0x28 },
|
||||
{ 40, 0x2B}
|
||||
};
|
||||
|
||||
/*Output division factor range*/
|
||||
static const DPHY_PLL_OUTPUT_DIVISION_FACTOR pll_p_factor[] =
|
||||
{
|
||||
{ 1000, 2 }, { 500, 4 }, { 250, 8 }, { 125, 16 }, { 62.5, 32 }, { 40, 64 }
|
||||
};
|
||||
|
||||
/**
|
||||
\fn static void MIPI_DSI_DPHY_Shutdown (uint8_t state)
|
||||
\brief PHY shutdown line control callback function.
|
||||
\param[in] state ENABLE/DISABLE the line.
|
||||
*/
|
||||
static void MIPI_DSI_DPHY_Shutdown (uint8_t state)
|
||||
{
|
||||
if(state == ENABLE)
|
||||
{
|
||||
dsi_phy_shutdown_enable((DSI_Type *)DSI_BASE);
|
||||
}
|
||||
else
|
||||
{
|
||||
dsi_phy_shutdown_disable((DSI_Type *)DSI_BASE);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
\fn static void MIPI_DSI_DPHY_Rst (uint8_t state)
|
||||
\brief PHY reset line control callback function.
|
||||
\param[in] state ENABLE/DISABLE the line.
|
||||
*/
|
||||
static void MIPI_DSI_DPHY_Rst (uint8_t state)
|
||||
{
|
||||
if(state == ENABLE)
|
||||
{
|
||||
dsi_phy_reset_enable((DSI_Type *)DSI_BASE);
|
||||
}
|
||||
else
|
||||
{
|
||||
dsi_phy_reset_disable((DSI_Type *)DSI_BASE);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
\fn static void MIPI_DSI_DPHY_Enableclk (uint8_t state)
|
||||
\brief PHY enable clock line control callback function.
|
||||
\param[in] state ENABLE/DISABLE the line.
|
||||
*/
|
||||
static void MIPI_DSI_DPHY_Enableclk (uint8_t state)
|
||||
{
|
||||
if(state == ENABLE)
|
||||
{
|
||||
dsi_phy_enable_clock((DSI_Type *)DSI_BASE);
|
||||
}
|
||||
else
|
||||
{
|
||||
dsi_phy_disable_clock((DSI_Type *)DSI_BASE);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
\fn static void MIPI_DSI_DPHY_Testclr (uint8_t state)
|
||||
\brief PHY testclr line control callback function.
|
||||
\param[in] state ENABLE/DISABLE the line.
|
||||
*/
|
||||
static void MIPI_DSI_DPHY_Testclr (uint8_t state)
|
||||
{
|
||||
if(state == ENABLE)
|
||||
{
|
||||
dsi_phy_testclr_enable((DSI_Type *)DSI_BASE);
|
||||
}
|
||||
else
|
||||
{
|
||||
dsi_phy_testclr_disable((DSI_Type *)DSI_BASE);
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
/**
|
||||
\fn static DSI_PLL_STATUS MIPI_DSI_DPHY_PLL_Lock (void)
|
||||
\brief PHY testclr line control callback function.
|
||||
\return return status of the PLL lock.
|
||||
*/
|
||||
static DSI_PLL_STATUS MIPI_DSI_DPHY_PLL_Lock (void)
|
||||
{
|
||||
return dsi_get_phy_lock_status((DSI_Type *)DSI_BASE);
|
||||
}
|
||||
|
||||
/**
|
||||
\fn static uint8_t MIPI_DSI_DPHY_Stopstate (void)
|
||||
\brief status of stopstate from PHY
|
||||
\return return status of stopstate.
|
||||
*/
|
||||
static DPHY_STOPSTATE MIPI_DSI_DPHY_Stopstate (void)
|
||||
{
|
||||
uint8_t ret = 0;
|
||||
|
||||
if(dsi_get_lane_stopstate_status((DSI_Type *)DSI_BASE, DSI_LANE_CLOCK) == DSI_LANE_STOPSTATE_ON)
|
||||
{
|
||||
ret |= DPHY_STOPSTATE_CLOCK;
|
||||
}
|
||||
|
||||
if(dsi_get_lane_stopstate_status((DSI_Type *)DSI_BASE, DSI_LANE_0) == DSI_LANE_STOPSTATE_ON)
|
||||
{
|
||||
ret |= DPHY_STOPSTATE_LANE0;
|
||||
}
|
||||
|
||||
if(dsi_get_lane_stopstate_status((DSI_Type *)DSI_BASE, DSI_LANE_1) == DSI_LANE_STOPSTATE_ON)
|
||||
{
|
||||
ret |= DPHY_STOPSTATE_LANE1;
|
||||
}
|
||||
|
||||
return ret;
|
||||
|
||||
}
|
||||
|
||||
/**
|
||||
\fn uint8_t DPHY_DSI_Read_Mask (uint16_t address,
|
||||
uint8_t pos,
|
||||
uint8_t width)
|
||||
\brief Read Mask DSI DPHY registers.
|
||||
\param[in] address is register index.
|
||||
\param[in] pos is start bit position.
|
||||
\param[in] width is number bits to read.
|
||||
\return return received data from DPHY register.
|
||||
*/
|
||||
uint8_t DPHY_DSI_Read_Mask (uint16_t address,
|
||||
uint8_t pos,
|
||||
uint8_t width)
|
||||
{
|
||||
return (MIPI_DPHY_Read(address, DPHY_MODE_CFG_DSI) >> pos) & ((1 << width) - 1);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\fn void DPHY_DSI_Write_Mask (uint16_t address,
|
||||
uint8_t data,
|
||||
uint8_t pos,
|
||||
uint8_t width)
|
||||
\brief write Mask DSI DPHY registers.
|
||||
\param[in] address is register index
|
||||
\param[in] data is value to be write to the DPHY register.
|
||||
\param[in] pos is start bit position.
|
||||
\param[in] width is number bits to write.
|
||||
*/
|
||||
void DPHY_DSI_Write_Mask (uint16_t address,
|
||||
uint8_t data,
|
||||
uint8_t pos,
|
||||
uint8_t width)
|
||||
{
|
||||
uint8_t reg_data = 0;
|
||||
uint8_t mask = (1U << width) - 1;
|
||||
|
||||
reg_data = MIPI_DPHY_Read(address, DPHY_MODE_CFG_DSI);
|
||||
reg_data &= ~(mask << pos);
|
||||
reg_data |= (data & mask) << pos;
|
||||
MIPI_DPHY_Write(address,reg_data, DPHY_MODE_CFG_DSI);
|
||||
}
|
||||
|
||||
/**
|
||||
\fn void DPHY_PowerEnable (void)
|
||||
\brief Enable DPHY Interface Power.
|
||||
*/
|
||||
static void DPHY_PowerEnable (void)
|
||||
{
|
||||
enable_dphy_pll_reference_clock();
|
||||
|
||||
enable_txdphy_configure_clock();
|
||||
|
||||
enable_dsi_periph_clk();
|
||||
}
|
||||
|
||||
/**
|
||||
\fn void DPHY_PowerDisable (void)
|
||||
\brief Disable DPHY Interface Power.
|
||||
*/
|
||||
static void DPHY_PowerDisable (void)
|
||||
{
|
||||
|
||||
disable_dsi_periph_clk();
|
||||
|
||||
disable_txdphy_configure_clock();
|
||||
|
||||
disable_dphy_pll_reference_clock();
|
||||
}
|
||||
|
||||
/**
|
||||
\fn int32_t DPHY_ConfigurePLL(uint32_t clock_frequency)
|
||||
\brief configuring MIPI TX DPHY PLL.
|
||||
\param[in] clock_frequency DPHY clock frequency.
|
||||
\return \ref execution_status
|
||||
*/
|
||||
static int32_t DPHY_ConfigurePLL(uint32_t clock_frequency)
|
||||
{
|
||||
float frequency_in_mhz = clock_frequency/1000000.0f;
|
||||
uint32_t pll_m = 0;
|
||||
uint8_t pll_p = 0;
|
||||
uint8_t vco_ctrl = 0;
|
||||
uint8_t range = 0;
|
||||
pll_config_t pll_config;
|
||||
|
||||
uint8_t pll_n = RTE_MIPI_DSI_PLL_INPUT_DIV_FACTOR_N;
|
||||
|
||||
if(((DPHY_FCLKIN_MHZ/pll_n) > 24) || ((DPHY_FCLKIN_MHZ/pll_n) < 8))
|
||||
{
|
||||
return ARM_DRIVER_ERROR_PARAMETER;
|
||||
}
|
||||
|
||||
for( range = 0; (range < ARRAY_SIZE(vco_ctrl_range) - 1) &&
|
||||
((frequency_in_mhz) < vco_ctrl_range[range].frequency_mhz);
|
||||
++range);
|
||||
|
||||
vco_ctrl = vco_ctrl_range[range].vco_ctrl;
|
||||
|
||||
for( range = 0; (range < ARRAY_SIZE(pll_p_factor) - 1) &&
|
||||
((frequency_in_mhz) <= pll_p_factor[range].frequency_mhz);
|
||||
++range);
|
||||
|
||||
pll_p = pll_p_factor[range].p;
|
||||
|
||||
pll_m = (uint32_t)((frequency_in_mhz * pll_n * pll_p * 2) / DPHY_FCLKIN_MHZ);
|
||||
|
||||
set_dphy_pll_clksel(DPHY_PLL_CLKSEL_CLOCK_GENERAT);
|
||||
|
||||
enable_dphy_pll_shadow_clear();
|
||||
|
||||
sys_busy_loop_us(1);
|
||||
|
||||
disable_dphy_pll_shadow_clear();
|
||||
|
||||
pll_config.pll_gmp_ctrl = DPHY_GMP_CNTRL;
|
||||
pll_config.pll_m = pll_m;
|
||||
pll_config.pll_n = (pll_n - 1);
|
||||
pll_config.pll_cpbias_ctrl = DPHY_CPBIAS_CNTRL;
|
||||
pll_config.pll_int_ctrl = DPHY_INT_CNTRL;
|
||||
pll_config.pll_prop_ctrl = DPHY_PROP_CNTRL;
|
||||
pll_config.pll_vco_ctrl = vco_ctrl;
|
||||
|
||||
set_dphy_pll_configuration(&pll_config);
|
||||
|
||||
sys_busy_loop_us(1);
|
||||
|
||||
enable_dphy_updatepll();
|
||||
|
||||
sys_busy_loop_us(1);
|
||||
|
||||
disable_dphy_updatepll();
|
||||
|
||||
DPHY_DSI_Write_Mask(dphy4txtester_DIG_RDWR_TX_PLL_17, 0x1, 7, 1);
|
||||
|
||||
DPHY_DSI_Write_Mask(dphy4txtester_DIG_RDWR_TX_PLL_17, 0x1, 6, 1);
|
||||
|
||||
return ARM_DRIVER_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
\fn int32_t DPHY_MasterSetup (uint32_t clock_frequency, uint8_t n_lanes)
|
||||
\brief MIPI DPHY Tx startup sequence.
|
||||
\param[in] clock_frequency DPHY clock frequency.
|
||||
\param[in] n_lanes number of lanes.
|
||||
\return \ref execution_status
|
||||
*/
|
||||
static int32_t DPHY_MasterSetup (uint32_t clock_frequency, uint8_t n_lanes)
|
||||
{
|
||||
uint32_t bitrate_mbps = (clock_frequency * 2)/1000000;
|
||||
uint8_t hsfreqrange = 0;
|
||||
uint8_t cfgclkfreqrange = 0;
|
||||
uint8_t range = 0;
|
||||
uint8_t stopstate_check = 0;
|
||||
uint32_t lp_count = 0;
|
||||
|
||||
if(bitrate_mbps < 80 || bitrate_mbps > 2500)
|
||||
{
|
||||
return ARM_DRIVER_ERROR;
|
||||
}
|
||||
|
||||
for(range = 0; (bitrate_mbps > frequency_range[range].bitrate_in_mbps);
|
||||
++range);
|
||||
|
||||
hsfreqrange = frequency_range[range].hsfreqrange;
|
||||
|
||||
dsi_set_active_lanes((DSI_Type *)DSI_BASE, n_lanes - 1);
|
||||
|
||||
MIPI_DSI_DPHY_Rst(DISABLE);
|
||||
|
||||
MIPI_DSI_DPHY_Shutdown(DISABLE);
|
||||
|
||||
set_tx_dphy_txrx(DPHY_MODE_MASTER);
|
||||
|
||||
set_tx_dphy_testport_select(DPHY_TESTPORT_SELECT_RX);
|
||||
MIPI_DSI_DPHY_Testclr(ENABLE);
|
||||
set_tx_dphy_testport_select(DPHY_TESTPORT_SELECT_TX);
|
||||
MIPI_DSI_DPHY_Testclr(ENABLE);
|
||||
|
||||
sys_busy_loop_us(1);
|
||||
|
||||
set_tx_dphy_testport_select(DPHY_TESTPORT_SELECT_RX);
|
||||
MIPI_DSI_DPHY_Testclr(DISABLE);
|
||||
set_tx_dphy_testport_select(DPHY_TESTPORT_SELECT_TX);
|
||||
MIPI_DSI_DPHY_Testclr(DISABLE);
|
||||
|
||||
set_tx_dphy_hsfreqrange(hsfreqrange);
|
||||
|
||||
DPHY_DSI_Write_Mask(dphy4txtester_DIG_RDWR_TX_PLL_13, 0x3, 0, 2);
|
||||
|
||||
DPHY_DSI_Write_Mask(dphy4txtester_DIG_RDWR_TX_CB_1, 0x2, 0, 2);
|
||||
|
||||
DPHY_DSI_Write_Mask(dphy4txtester_DIG_RDWR_TX_CB_0, 0x2, 5, 2);
|
||||
|
||||
if(bitrate_mbps < 450)
|
||||
DPHY_DSI_Write_Mask(dphy4txtester_DIG_RDWR_TX_CB_2, 0x1, 4, 1);
|
||||
|
||||
DPHY_DSI_Write_Mask(dphy4txtester_DIG_RDWR_TX_CLK_TERMLOWCAP, 0x2, 0, 2);
|
||||
|
||||
if(bitrate_mbps <= 1000)
|
||||
{
|
||||
DPHY_DSI_Write_Mask(dphy4txtester_DIG_RDWR_TX_SLEW_5,
|
||||
(uint8_t)DPHY_LESS_THEN_1GBPS_SR_OSC_FREQ_TARGET,
|
||||
0, 8);
|
||||
DPHY_DSI_Write_Mask(dphy4txtester_DIG_RDWR_TX_SLEW_6,
|
||||
(uint8_t)(DPHY_LESS_THEN_1GBPS_SR_OSC_FREQ_TARGET >> 8),
|
||||
0, 4);
|
||||
DPHY_DSI_Write_Mask(dphy4txtester_DIG_RDWR_TX_SLEW_7, 0x1, 4, 1);
|
||||
DPHY_DSI_Write_Mask(dphy4txtester_DIG_RDWR_TX_SLEW_7, 0x1, 0, 1);
|
||||
}
|
||||
else if ((bitrate_mbps > 1000) && (bitrate_mbps <= 1500))
|
||||
{
|
||||
DPHY_DSI_Write_Mask(dphy4txtester_DIG_RDWR_TX_SLEW_5,
|
||||
(uint8_t)DPHY_MORE_THEN_1GBPS_SR_OSC_FREQ_TARGET,
|
||||
0, 8);
|
||||
DPHY_DSI_Write_Mask(dphy4txtester_DIG_RDWR_TX_SLEW_6,
|
||||
(uint8_t)(DPHY_MORE_THEN_1GBPS_SR_OSC_FREQ_TARGET >> 8),
|
||||
0, 4);
|
||||
}
|
||||
|
||||
cfgclkfreqrange = (DPHY_FCFG_CLOCK_MHZ - 17) * 4;
|
||||
|
||||
set_tx_dphy_cfgclkfreqrange(cfgclkfreqrange);
|
||||
|
||||
if(DPHY_ConfigurePLL(clock_frequency) != ARM_DRIVER_OK)
|
||||
{
|
||||
return ARM_DRIVER_ERROR_PARAMETER;
|
||||
}
|
||||
|
||||
unset_tx_dphy_basedir((1U << n_lanes) - 1);
|
||||
|
||||
unset_tx_dphy_forcerxmode((1U << n_lanes) - 1);
|
||||
|
||||
sys_busy_loop_us(1);
|
||||
|
||||
MIPI_DSI_DPHY_Enableclk(ENABLE);
|
||||
|
||||
sys_busy_loop_us(1);
|
||||
|
||||
MIPI_DSI_DPHY_Shutdown(ENABLE);
|
||||
|
||||
sys_busy_loop_us(1);
|
||||
|
||||
MIPI_DSI_DPHY_Rst(ENABLE);
|
||||
|
||||
while(MIPI_DSI_DPHY_PLL_Lock() != (DSI_PLL_STATUS) DPHY_PLL_STATUS_PLL_LOCK)
|
||||
{
|
||||
if(lp_count++ < 1000000)
|
||||
{
|
||||
sys_busy_loop_us(1);
|
||||
}
|
||||
else
|
||||
{
|
||||
return ARM_DRIVER_ERROR;
|
||||
}
|
||||
}
|
||||
|
||||
stopstate_check = DPHY_STOPSTATE_CLOCK | (n_lanes == 1 ? (DPHY_STOPSTATE_LANE0) :
|
||||
(DPHY_STOPSTATE_LANE0) | (DPHY_STOPSTATE_LANE1) );
|
||||
|
||||
lp_count = 0;
|
||||
while(MIPI_DSI_DPHY_Stopstate() != stopstate_check)
|
||||
{
|
||||
if(lp_count++ < 1000000)
|
||||
{
|
||||
sys_busy_loop_us(1);
|
||||
}
|
||||
else
|
||||
{
|
||||
return ARM_DRIVER_ERROR;
|
||||
}
|
||||
}
|
||||
|
||||
return ARM_DRIVER_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
\fn int32_t DSI_DPHY_Initialize (uint32_t frequency, uint8_t n_lanes)
|
||||
\brief Initialize MIPI DSI DPHY Interface.
|
||||
\param[in] frequency to configure DPHY PLL.
|
||||
\param[in] n_lanes number of lanes.
|
||||
\return \ref execution_status
|
||||
*/
|
||||
int32_t DSI_DPHY_Initialize (uint32_t frequency, uint8_t n_lanes)
|
||||
{
|
||||
int32_t ret = ARM_DRIVER_OK;
|
||||
|
||||
if(dsi_init_status == DPHY_INIT_STATUS_INITIALIZED)
|
||||
{
|
||||
return ARM_DRIVER_OK;
|
||||
}
|
||||
|
||||
DPHY_PowerEnable();
|
||||
|
||||
ret = DPHY_MasterSetup(frequency, n_lanes);
|
||||
if(ret != ARM_DRIVER_OK)
|
||||
{
|
||||
return ret;
|
||||
}
|
||||
|
||||
dsi_init_status = DPHY_INIT_STATUS_INITIALIZED;
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/**
|
||||
\fn int32_t DSI_DPHY_Uninitialize (void)
|
||||
\brief Uninitialize MIPI DSI DPHY Interface.
|
||||
\return \ref execution_status
|
||||
*/
|
||||
int32_t DSI_DPHY_Uninitialize (void)
|
||||
{
|
||||
if(dsi_init_status == DPHY_INIT_STATUS_UNINITIALIZED)
|
||||
{
|
||||
return ARM_DRIVER_OK;
|
||||
}
|
||||
|
||||
MIPI_DSI_DPHY_Rst(DISABLE);
|
||||
MIPI_DSI_DPHY_Shutdown(DISABLE);
|
||||
MIPI_DSI_DPHY_Enableclk(DISABLE);
|
||||
DPHY_PowerDisable();
|
||||
|
||||
dsi_init_status = DPHY_INIT_STATUS_UNINITIALIZED;
|
||||
|
||||
return ARM_DRIVER_OK;
|
||||
}
|
||||
41
src/hal/alif/Alif_CMSIS/Source/DPHY_DSI.h
Normal file
41
src/hal/alif/Alif_CMSIS/Source/DPHY_DSI.h
Normal file
@ -0,0 +1,41 @@
|
||||
/* Copyright (C) 2024 Alif Semiconductor - All Rights Reserved.
|
||||
* Use, distribution and modification of this code is permitted under the
|
||||
* terms stated in the Alif Semiconductor Software License Agreement
|
||||
*
|
||||
* You should have received a copy of the Alif Semiconductor Software
|
||||
* License Agreement with this file. If not, please write to:
|
||||
* contact@alifsemi.com, or visit: https://alifsemi.com/license
|
||||
*
|
||||
*/
|
||||
|
||||
/******************************************************************************
|
||||
* @file DPHY_DSI.h
|
||||
* @author Prasanna Ravi
|
||||
* @email prasanna.ravi@alifsemi.com
|
||||
* @version V1.0.0
|
||||
* @date 14-May-2024
|
||||
* @brief Driver Specific Header file for DPHY DSI Driver.
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef DPHY_DSI_H_
|
||||
#define DPHY_DSI_H_
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
/**
|
||||
\fn int32_t DSI_DPHY_Initialize (uint32_t frequency, uint8_t n_lanes)
|
||||
\brief Initialize MIPI DSI DPHY Interface.
|
||||
\param[in] frequency to configure DPHY PLL.
|
||||
\param[in] n_lanes number of lanes.
|
||||
\return \ref execution_status
|
||||
*/
|
||||
int32_t DSI_DPHY_Initialize (uint32_t frequency, uint8_t n_lanes);
|
||||
|
||||
/**
|
||||
\fn int32_t DSI_DPHY_Uninitialize (void)
|
||||
\brief Uninitialize MIPI DSI DPHY Interface.
|
||||
\return \ref execution_status
|
||||
*/
|
||||
int32_t DSI_DPHY_Uninitialize (void);
|
||||
|
||||
#endif /* DPHY_DSI_H_ */
|
||||
38
src/hal/alif/Alif_CMSIS/Source/DPHY_Loopback_test.h
Normal file
38
src/hal/alif/Alif_CMSIS/Source/DPHY_Loopback_test.h
Normal file
@ -0,0 +1,38 @@
|
||||
/* Copyright (C) 2023 Alif Semiconductor - All Rights Reserved.
|
||||
* Use, distribution and modification of this code is permitted under the
|
||||
* terms stated in the Alif Semiconductor Software License Agreement
|
||||
*
|
||||
* You should have received a copy of the Alif Semiconductor Software
|
||||
* License Agreement with this file. If not, please write to:
|
||||
* contact@alifsemi.com, or visit: https://alifsemi.com/license
|
||||
*
|
||||
*/
|
||||
|
||||
/**************************************************************************//**
|
||||
* @file DPHY_Loopback_test.h
|
||||
* @author Prasanna Ravi
|
||||
* @email prasanna.ravi@alifsemi.com
|
||||
* @version V1.0.0
|
||||
* @date 10-Feb-2023
|
||||
* @brief DPHY loopback test specific Header File.
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef DPHY_LOOPBACK_TEST_H_
|
||||
#define DPHY_LOOPBACK_TEST_H_
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
/* Return status for PHY2PHY loopback test*/
|
||||
#define TPASS 0
|
||||
#define TFAIL -1
|
||||
|
||||
/**
|
||||
\fn int32_t DPHY_External_Loopback_Test (uint32_t frequency, uint32_t loopback_test_run_time_us)
|
||||
\brief External Loopback test.
|
||||
\param[in] frequency to configure DPHY PLL.
|
||||
\param[in] time in microseconds for which loopback test should run.
|
||||
\return return test status TPASS or TFAIL.
|
||||
*/
|
||||
int32_t DPHY_External_Loopback_Test (uint32_t frequency, uint32_t loopback_test_run_time_us);
|
||||
|
||||
#endif /* DPHY_LOOPBACK_TEST_H_ */
|
||||
95
src/hal/alif/Alif_CMSIS/Source/DPHY_Private.h
Normal file
95
src/hal/alif/Alif_CMSIS/Source/DPHY_Private.h
Normal file
@ -0,0 +1,95 @@
|
||||
/* Copyright (C) 2022 Alif Semiconductor - All Rights Reserved.
|
||||
* Use, distribution and modification of this code is permitted under the
|
||||
* terms stated in the Alif Semiconductor Software License Agreement
|
||||
*
|
||||
* You should have received a copy of the Alif Semiconductor Software
|
||||
* License Agreement with this file. If not, please write to:
|
||||
* contact@alifsemi.com, or visit: https://alifsemi.com/license
|
||||
*
|
||||
*/
|
||||
|
||||
/**************************************************************************//**
|
||||
* @file DPHY_Private.h
|
||||
* @author Prasanna Ravi
|
||||
* @email prasanna.ravi@alifsemi.com
|
||||
* @version V1.0.0
|
||||
* @date 24-Feb-2022
|
||||
* @brief Driver Specific Header file for DPHY Driver.
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef DPHY_PRIVATE_H_
|
||||
#define DPHY_PRIVATE_H_
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
/*Helper macro*/
|
||||
#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
|
||||
|
||||
/**
|
||||
* enum DPHY_STOPSTATE
|
||||
* DPHY physical lanes stop state status
|
||||
*/
|
||||
typedef enum _DPHY_STOPSTATE {
|
||||
DPHY_STOPSTATE_LANE0 = (1U << 0), /**< DPHY lane 0 stopstate status */
|
||||
DPHY_STOPSTATE_LANE1 = (1U << 1), /**< DPHY lane 1 stopstate status */
|
||||
DPHY_STOPSTATE_CLOCK = (1U << 2), /**< DPHY lane clock stopstate status */
|
||||
} DPHY_STOPSTATE;
|
||||
|
||||
/**
|
||||
* enum DPHY_PLL_STATUS
|
||||
* DPHY PLL lock status
|
||||
*/
|
||||
typedef enum _DPHY_PLL_STATUS {
|
||||
DPHY_PLL_STATUS_NO_PLL_LOCK, /**< DPHY status locked */
|
||||
DPHY_PLL_STATUS_PLL_LOCK, /**< DPHY status not locked */
|
||||
} DPHY_PLL_STATUS;
|
||||
|
||||
/**
|
||||
* enum DPHY_INIT_STATUS
|
||||
* DPHY initialization status
|
||||
*/
|
||||
typedef enum _DPHY_INIT_STATUS {
|
||||
DPHY_INIT_STATUS_UNINITIALIZED, /**< DPHY driver uinitialized */
|
||||
DPHY_INIT_STATUS_INITIALIZED, /**< DPHY driver initialized */
|
||||
}DPHY_INIT_STATUS;
|
||||
|
||||
/**
|
||||
* enum DPHY_MODE_CFG
|
||||
* DPHY mode(CIS2/DSI)
|
||||
*/
|
||||
typedef enum _DPHY_MODE_CFG {
|
||||
DPHY_MODE_CFG_DSI, /**< DPHY mode DSI */
|
||||
DPHY_MODE_CFG_CSI2, /**< DPHY mode CSI2 */
|
||||
}DPHY_MODE_CFG;
|
||||
|
||||
/** \brief hsfreqrange and osc_freq_target range */
|
||||
typedef struct _DPHY_FREQ_RANGE {
|
||||
uint16_t bitrate_in_mbps; /**< DPHY data rate in mbps */
|
||||
uint8_t hsfreqrange; /**< DPHY HS frequency range */
|
||||
uint16_t osc_freq_target; /**< DPHY oscillator frequency target */
|
||||
}DPHY_FREQ_RANGE;
|
||||
|
||||
/** \brief PLL vco_cntrl range */
|
||||
typedef struct _DPHY_PLL_VCO_CTRL {
|
||||
float frequency_mhz; /**< DPHY frequency in MHZ */
|
||||
int8_t vco_ctrl; /**< DPHY VCO control */
|
||||
}DPHY_PLL_VCO_CTRL;
|
||||
|
||||
/**
|
||||
\brief PLL Output division factor range
|
||||
*/
|
||||
typedef struct _DPHY_PLL_OUTPUT_DIVISION_FACTOR {
|
||||
float frequency_mhz; /**< DPHY frequency in MHZ */
|
||||
int8_t p; /**< DPHY output division factor*/
|
||||
}DPHY_PLL_OUTPUT_DIVISION_FACTOR;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* DPHY_PRIVATE_H_ */
|
||||
@ -0,0 +1,46 @@
|
||||
/* Copyright (C) 2024 Alif Semiconductor - All Rights Reserved.
|
||||
* Use, distribution and modification of this code is permitted under the
|
||||
* terms stated in the Alif Semiconductor Software License Agreement
|
||||
*
|
||||
* You should have received a copy of the Alif Semiconductor Software
|
||||
* License Agreement with this file. If not, please write to:
|
||||
* contact@alifsemi.com, or visit: https://alifsemi.com/license
|
||||
*
|
||||
*/
|
||||
|
||||
/******************************************************************************
|
||||
* @file DPHY_Test_and_Control_Interface.h
|
||||
* @author Prasanna Ravi and Chandra Bhushan Singh
|
||||
* @email prasanna.ravi@alifsemi.com and chandrabhushan.singh@alifsemi.com
|
||||
* @version V1.0.0
|
||||
* @date 14-May-2024
|
||||
* @brief Driver for MIPI DPHY test and control interface.
|
||||
* @bug None.
|
||||
* @Note None.
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef DPHY_TEST_AND_CONTROL_INTERFACE_H_
|
||||
#define DPHY_TEST_AND_CONTROL_INTERFACE_H_
|
||||
|
||||
#include <stdint.h>
|
||||
#include "DPHY_Private.h"
|
||||
|
||||
/**
|
||||
\fn static uint8_t MIPI_DPHY_Read (uint16_t address, DPHY_Mode mode)
|
||||
\brief Test and control interface protocol to read DPHY registers.
|
||||
\param[in] address index on DPHY register.
|
||||
\param[in] mode is to select the DPHY mode(CSI2/DSI).
|
||||
\return ret register value.
|
||||
*/
|
||||
uint8_t MIPI_DPHY_Read (uint16_t address, DPHY_MODE_CFG mode);
|
||||
|
||||
/**
|
||||
\fn static void MIPI_CSI2_DPHY_Write (uint16_t address, uint8_t data)
|
||||
\brief Test and control interface protocol to Write DPHY registers.
|
||||
\param[in] address index on DPHY register.
|
||||
\param[in] data register value.
|
||||
\param[in] mode is to select the DPHY mode(CSI2/DSI).
|
||||
*/
|
||||
void MIPI_DPHY_Write (uint16_t address, uint8_t data, DPHY_MODE_CFG mode);
|
||||
|
||||
#endif /* DPHY_TEST_AND_CONTROL_INTERFACE_H_ */
|
||||
46
src/hal/alif/Alif_CMSIS/Source/DSI_DCS.h
Normal file
46
src/hal/alif/Alif_CMSIS/Source/DSI_DCS.h
Normal file
@ -0,0 +1,46 @@
|
||||
/* Copyright (C) 2022 Alif Semiconductor - All Rights Reserved.
|
||||
* Use, distribution and modification of this code is permitted under the
|
||||
* terms stated in the Alif Semiconductor Software License Agreement
|
||||
*
|
||||
* You should have received a copy of the Alif Semiconductor Software
|
||||
* License Agreement with this file. If not, please write to:
|
||||
* contact@alifsemi.com, or visit: https://alifsemi.com/license
|
||||
*
|
||||
*/
|
||||
|
||||
/**************************************************************************//**
|
||||
* @file DSI_DCS.h
|
||||
* @author Prasanna Ravi
|
||||
* @email prasanna.ravi@alifsemi.com
|
||||
* @version V1.0.0
|
||||
* @date 01-July-2022
|
||||
* @brief DCS Specific Header file for MIPI DSI Driver.
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef MIPI_DSI_DCS_H_
|
||||
#define MIPI_DSI_DCS_H_
|
||||
|
||||
/**
|
||||
\fn void DSI_DCS_Short_Write (uint8_t cmd, uint8_t data)
|
||||
\brief Perform MIPI DSI DCS Short write.
|
||||
\param[in] cmd is DCS command info.
|
||||
\param[in] data to send.
|
||||
*/
|
||||
void DSI_DCS_Short_Write (uint8_t cmd, uint8_t data);
|
||||
|
||||
/**
|
||||
\fn void DSI_DCS_CMD_Short_Write (uint8_t cmd)
|
||||
\brief Perform MIPI DSI DCS Short write only command.
|
||||
\param[in] cmd is DCS command info.
|
||||
*/
|
||||
void DSI_DCS_CMD_Short_Write (uint8_t cmd);
|
||||
|
||||
/**
|
||||
\fn void DSI_DCS_Long_Write (uint8_t cmd, uint32_t data)
|
||||
\brief Perform MIPI DSI DCS Short write.
|
||||
\param[in] data pointer to data buffer.
|
||||
\param[in] len data buffer length.
|
||||
*/
|
||||
void DSI_DCS_Long_Write (uint8_t* data, uint32_t len);
|
||||
|
||||
#endif /* MIPI_DSI_DCS_H_ */
|
||||
1606
src/hal/alif/Alif_CMSIS/Source/Driver_ADC.c
Normal file
1606
src/hal/alif/Alif_CMSIS/Source/Driver_ADC.c
Normal file
File diff suppressed because it is too large
Load Diff
59
src/hal/alif/Alif_CMSIS/Source/Driver_ADC_Private.h
Normal file
59
src/hal/alif/Alif_CMSIS/Source/Driver_ADC_Private.h
Normal file
@ -0,0 +1,59 @@
|
||||
/* Copyright (C) 2023 Alif Semiconductor - All Rights Reserved.
|
||||
* Use, distribution and modification of this code is permitted under the
|
||||
* terms stated in the Alif Semiconductor Software License Agreement
|
||||
*
|
||||
* You should have received a copy of the Alif Semiconductor Software
|
||||
* License Agreement with this file. If not, please write to:
|
||||
* contact@alifsemi.com, or visit: https://alifsemi.com/license
|
||||
*/
|
||||
|
||||
#ifndef DRIVER_ADC_PRIVATE_H_
|
||||
#define DRIVER_ADC_PRIVATE_H_
|
||||
|
||||
/*---System include ----*/
|
||||
#include "RTE_Device.h"
|
||||
#include "RTE_Components.h"
|
||||
#include CMSIS_device_header
|
||||
|
||||
#include "Driver_ADC.h"
|
||||
#include "adc.h"
|
||||
#include "sys_ctrl_adc.h"
|
||||
|
||||
typedef enum {
|
||||
ADC_FLAG_DRV_INIT_DONE = (1U << 0), /* ADC Driver is Initialized */
|
||||
ADC_FLAG_DRV_POWER_DONE = (1U << 1), /* ADC Driver is Powered */
|
||||
} ADC_FLAG_Type;
|
||||
|
||||
/* Access structure for the saving the ADC Setting and status*/
|
||||
typedef struct _ADC_RESOURCES
|
||||
{
|
||||
ARM_ADC_SignalEvent_t cb_event; /* ADC APPLICATION CALLBACK EVENT */
|
||||
ADC_Type *regs; /* ADC register base address */
|
||||
conv_info_t conv; /* ADC conversion information */
|
||||
ADC_INSTANCE drv_instance; /* ADC Driver instances */
|
||||
IRQn_Type intr_done0_irq_num; /* ADC avg sample ready interrupt number */
|
||||
IRQn_Type intr_done1_irq_num; /* ADC all sample taken interrupt number */
|
||||
IRQn_Type intr_cmpa_irq_num; /* ADC comparator A interrupt number */
|
||||
IRQn_Type intr_cmpb_irq_num; /* ADC comparator B interrupt number */
|
||||
uint8_t ext_trig_val; /* ADC external trigger enable value */
|
||||
uint8_t busy; /* ADC conversion busy flag */
|
||||
uint32_t intr_done0_irq_priority; /* ADC done0 Irq Priority */
|
||||
uint32_t intr_done1_irq_priority; /* ADC done1 Irq Priority */
|
||||
uint32_t intr_cmpa_irq_priority; /* ADC cmpa Irq Priority */
|
||||
uint32_t intr_cmpb_irq_priority; /* ADC cmpb Irq Priority */
|
||||
uint32_t state; /* ADC state */
|
||||
uint32_t clock_div; /* ADC clock divisor */
|
||||
uint32_t avg_sample_num; /* ADC average sample number */
|
||||
uint32_t sample_width; /* ADC sample width */
|
||||
uint32_t shift_n_bit; /* ADC number of bits to shift */
|
||||
uint32_t shift_left_or_right; /* ADC shift bit left or right */
|
||||
bool differential_enable; /* ADC12 differential enable */
|
||||
bool comparator_enable; /* ADC12 comparator enable */
|
||||
uint8_t comparator_bias; /* ADC12 comparator bias */
|
||||
uint32_t pga_enable; /* ADC Programmable gain amplifier(PGA) enable */
|
||||
uint32_t pga_value; /* ADC Programmable gain amplifier(PGA) */
|
||||
uint32_t bias; /* ADC24 bias control value */
|
||||
uint32_t output_rate; /* ADC24 output rate */
|
||||
}ADC_RESOURCES;
|
||||
|
||||
#endif /* DRIVER_ADC_PRIVATE_H_ */
|
||||
1605
src/hal/alif/Alif_CMSIS/Source/Driver_CAN.c
Normal file
1605
src/hal/alif/Alif_CMSIS/Source/Driver_CAN.c
Normal file
File diff suppressed because it is too large
Load Diff
792
src/hal/alif/Alif_CMSIS/Source/Driver_CDC200.c
Normal file
792
src/hal/alif/Alif_CMSIS/Source/Driver_CDC200.c
Normal file
@ -0,0 +1,792 @@
|
||||
/* Copyright (C) 2023 Alif Semiconductor - All Rights Reserved.
|
||||
* Use, distribution and modification of this code is permitted under the
|
||||
* terms stated in the Alif Semiconductor Software License Agreement
|
||||
*
|
||||
* You should have received a copy of the Alif Semiconductor Software
|
||||
* License Agreement with this file. If not, please write to:
|
||||
* contact@alifsemi.com, or visit: https://alifsemi.com/license
|
||||
*
|
||||
*/
|
||||
|
||||
/**************************************************************************//**
|
||||
* @file Driver_CDC200.c
|
||||
* @author Girish BN and Prasanna Ravi
|
||||
* @email girish.bn@alifsemi.com and prasanna.ravi@alifsemi.com
|
||||
* @version V1.0.0
|
||||
* @date 28-Sep-2023
|
||||
* @brief Display controller CDC200 driver source file.
|
||||
* @bug None.
|
||||
* @Note None.
|
||||
******************************************************************************/
|
||||
|
||||
#include "Driver_CDC200.h"
|
||||
#include "Driver_CDC_Private.h"
|
||||
#include "sys_ctrl_cdc.h"
|
||||
#include "system_utils.h"
|
||||
#include "RTE_Device.h"
|
||||
#include "display.h"
|
||||
|
||||
#define ARM_CDC200_DRV_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(1, 0) /*driver version*/
|
||||
|
||||
#if !(RTE_CDC200)
|
||||
#error "CDC200 is not enabled in the RTE_Device.h"
|
||||
#endif
|
||||
|
||||
#if (!defined(RTE_Drivers_CDC200))
|
||||
#error "CDC200 not configured in RTE_Components.h!"
|
||||
#endif
|
||||
|
||||
#if (RTE_MIPI_DSI)
|
||||
|
||||
#include "Driver_MIPI_DSI.h"
|
||||
|
||||
/*MIPI DSI driver instance*/
|
||||
extern ARM_DRIVER_MIPI_DSI Driver_MIPI_DSI;
|
||||
|
||||
/*MIPI DSI driver callback*/
|
||||
void MIPI_DSI_Event_Callback (uint32_t int_event);
|
||||
|
||||
#endif
|
||||
|
||||
/*Driver Version*/
|
||||
static const ARM_DRIVER_VERSION DriverVersion =
|
||||
{
|
||||
ARM_CDC200_API_VERSION,
|
||||
ARM_CDC200_DRV_VERSION
|
||||
};
|
||||
|
||||
/* Driver Capabilities */
|
||||
static const ARM_CDC200_CAPABILITIES DriverCapabilities =
|
||||
{
|
||||
0, /* Not supports reentrant_operation */
|
||||
1, /* DPI interface supported */
|
||||
0 /* reserved (must be zero) */
|
||||
};
|
||||
|
||||
/**
|
||||
\fn ARM_DRIVER_VERSION CDC200_GetVersion (void)
|
||||
\brief Get CDC200 driver version.
|
||||
\return \ref ARM_DRIVER_VERSION.
|
||||
*/
|
||||
static ARM_DRIVER_VERSION CDC200_GetVersion (void)
|
||||
{
|
||||
return DriverVersion;
|
||||
}
|
||||
|
||||
/**
|
||||
\fn ARM_CDC200_CAPABILITIES CDC200_GetCapabilities (void)
|
||||
\brief Get CDC200 driver capabilities.
|
||||
\return \ref ARM_CDC200_CAPABILITIES.
|
||||
*/
|
||||
static ARM_CDC200_CAPABILITIES CDC200_GetCapabilities (void)
|
||||
{
|
||||
return DriverCapabilities;
|
||||
}
|
||||
|
||||
/**
|
||||
\fn static int32_t CDC200_Init (ARM_CDC200_SignalEvent_t cb_event,
|
||||
DISPLAY_PANEL_DEVICE *display_panel,
|
||||
CDC_RESOURCES *cdc)
|
||||
\brief Initialize CDC200 Interface.
|
||||
\param[in] cb_event Pointer to ARM_CDC200_SignalEvent_t.
|
||||
\param[in] display_panel Pointer to display panel resources.
|
||||
\param[in] cdc Pointer to CDC resources.
|
||||
\return \ref execution_status.
|
||||
*/
|
||||
static int32_t CDC200_Init (ARM_CDC200_SignalEvent_t cb_event,
|
||||
DISPLAY_PANEL_DEVICE *display_panel,
|
||||
CDC_RESOURCES *cdc)
|
||||
{
|
||||
int32_t ret = ARM_DRIVER_OK;
|
||||
|
||||
if (cdc->state.initialized == 1)
|
||||
{
|
||||
return ARM_DRIVER_OK;
|
||||
}
|
||||
|
||||
if(display_panel == NULL)
|
||||
{
|
||||
return ARM_DRIVER_ERROR_PARAMETER;
|
||||
}
|
||||
|
||||
if (!cb_event)
|
||||
{
|
||||
return ARM_DRIVER_ERROR_PARAMETER;
|
||||
}
|
||||
|
||||
cdc->cb_event = cb_event;
|
||||
|
||||
/*Error checking on timing parameters*/
|
||||
if(((display_panel->hsync_time + display_panel->hbp_time +
|
||||
display_panel->hactive_time + display_panel->hfp_time - 1) > 0xFFFFU))
|
||||
{
|
||||
return ARM_DRIVER_ERROR_PARAMETER;
|
||||
}
|
||||
|
||||
if(((display_panel->vsync_line + display_panel->vbp_line +
|
||||
display_panel->vactive_line + display_panel->vfp_line - 1) > 0xFFFFU))
|
||||
{
|
||||
return ARM_DRIVER_ERROR_PARAMETER;
|
||||
}
|
||||
|
||||
#if (RTE_MIPI_DSI)
|
||||
/*Initializing MIPI DSI, if the LCD Panel is MIPI DSI LCD Panel*/
|
||||
ret = Driver_MIPI_DSI.Initialize (MIPI_DSI_Event_Callback);
|
||||
if (ret != ARM_DRIVER_OK)
|
||||
{
|
||||
return ret;
|
||||
}
|
||||
#endif
|
||||
|
||||
cdc->state.initialized = 1;
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/**
|
||||
\fn static int32_t CDC200_Uninit (CDC_RESOURCES *cdc)
|
||||
\brief uninitialize CDC200 Interface.
|
||||
\param[in] cdc Pointer to CDC resources.
|
||||
\return \ref execution_status.
|
||||
*/
|
||||
static int32_t CDC200_Uninit (CDC_RESOURCES *cdc)
|
||||
{
|
||||
int32_t ret = ARM_DRIVER_OK;
|
||||
cdc->cb_event = NULL;
|
||||
|
||||
if (cdc->state.initialized == 0)
|
||||
{
|
||||
return ARM_DRIVER_OK;
|
||||
}
|
||||
|
||||
if (cdc->state.powered == 1)
|
||||
{
|
||||
return ARM_DRIVER_ERROR;
|
||||
}
|
||||
|
||||
#if (RTE_MIPI_DSI)
|
||||
/*Uninitializing MIPI DSI, if the LCD Panel is MIPI DSI LCD Panel*/
|
||||
ret = Driver_MIPI_DSI.Uninitialize ();
|
||||
if (ret != ARM_DRIVER_OK)
|
||||
{
|
||||
return ret;
|
||||
}
|
||||
#endif
|
||||
|
||||
cdc->state.initialized = 0;
|
||||
return ret;
|
||||
}
|
||||
|
||||
/**
|
||||
\fn static int32_t CDC200_PowerCtrl (ARM_POWER_STATE state,
|
||||
DISPLAY_PANEL_DEVICE *display_panel,
|
||||
CDC_RESOURCES *cdc)
|
||||
\brief Control CDC200 Interface Power.
|
||||
\param[in] state Power state.
|
||||
\param[in] display_panel Pointer to display panel resources.
|
||||
\param[in] cdc Pointer to CDC resources.
|
||||
\return \ref execution_status.
|
||||
*/
|
||||
static int32_t CDC200_PowerCtrl (ARM_POWER_STATE state,
|
||||
DISPLAY_PANEL_DEVICE *display_panel,
|
||||
CDC_RESOURCES *cdc)
|
||||
{
|
||||
int32_t ret = ARM_DRIVER_OK;
|
||||
uint32_t htotal, vtotal;
|
||||
int pixclk_div;
|
||||
|
||||
if (cdc->state.initialized == 0)
|
||||
{
|
||||
return ARM_DRIVER_ERROR;
|
||||
}
|
||||
|
||||
switch (state)
|
||||
{
|
||||
case ARM_POWER_OFF:
|
||||
|
||||
{
|
||||
if (cdc->state.powered == 0)
|
||||
{
|
||||
return ARM_DRIVER_OK;
|
||||
}
|
||||
|
||||
#if (RTE_MIPI_DSI)
|
||||
/*Disable MIPI DSI*/
|
||||
ret = Driver_MIPI_DSI.PowerControl (ARM_POWER_OFF);
|
||||
if (ret != ARM_DRIVER_OK)
|
||||
{
|
||||
return ret;
|
||||
}
|
||||
#endif
|
||||
/*Disabling Line IRQ*/
|
||||
NVIC_DisableIRQ (CDC_SCANLINE0_IRQ_IRQn);
|
||||
NVIC_ClearPendingIRQ (CDC_SCANLINE0_IRQ_IRQn);
|
||||
|
||||
/* Disabling pixel clock */
|
||||
disable_cdc_pixel_clk ();
|
||||
|
||||
/* Disabling Source clock */
|
||||
disable_dpi_periph_clk ();
|
||||
|
||||
cdc->state.powered = 0;
|
||||
break;
|
||||
}
|
||||
|
||||
case ARM_POWER_FULL:
|
||||
{
|
||||
if (cdc->state.powered == 1)
|
||||
{
|
||||
return ARM_DRIVER_OK;
|
||||
}
|
||||
|
||||
#if (RTE_MIPI_DSI)
|
||||
/*Enable MIPI DSI*/
|
||||
ret = Driver_MIPI_DSI.PowerControl (ARM_POWER_FULL);
|
||||
if (ret != ARM_DRIVER_OK)
|
||||
{
|
||||
return ret;
|
||||
}
|
||||
#endif
|
||||
|
||||
/* LCD Manufacturer provides the Frame timing values
|
||||
* HTOTAL = WIDTH + HSYNC + HFP + HBP
|
||||
* VTOTAL = HEIGHT + VSYNC + VFP + VBP
|
||||
* Calculate the pixel clock for DPI controller
|
||||
* PIXCLK = FPS x HTOTAL x VTOTAL
|
||||
* Calculate the pixel clock divider
|
||||
* PIXCLK_DIV = CDC200_PIXCLK_SOURCE / PIXCLK
|
||||
*/
|
||||
htotal = (display_panel->hsync_time
|
||||
+ display_panel->hbp_time
|
||||
+ display_panel->hfp_time
|
||||
+ display_panel->hactive_time);
|
||||
|
||||
vtotal = (display_panel->vsync_line
|
||||
+ display_panel->vbp_line
|
||||
+ display_panel->vfp_line
|
||||
+ display_panel->vactive_line);
|
||||
|
||||
pixclk_div = (int)((float)GetSystemAXIClock() / (htotal * vtotal * RTE_CDC200_DPI_FPS) + 0.5f);
|
||||
|
||||
/*Checking clk divider is less than 2 because 0 and 1 are illegal value*/
|
||||
if (pixclk_div < 2 || pixclk_div > 511)
|
||||
{
|
||||
return ARM_DRIVER_ERROR_PARAMETER;
|
||||
}
|
||||
|
||||
/* Enabling Source clock */
|
||||
enable_dpi_periph_clk ();
|
||||
|
||||
/* Configuring pixel clock */
|
||||
set_cdc_pixel_clk (RTE_CDC200_CLK_SEL, pixclk_div);
|
||||
|
||||
/*Enabling Line IRQ*/
|
||||
NVIC_ClearPendingIRQ (CDC_SCANLINE0_IRQ_IRQn);
|
||||
NVIC_SetPriority (CDC_SCANLINE0_IRQ_IRQn, cdc->irq_priority);
|
||||
NVIC_EnableIRQ (CDC_SCANLINE0_IRQ_IRQn);
|
||||
|
||||
cdc->state.powered = 1;
|
||||
break;
|
||||
}
|
||||
|
||||
case ARM_POWER_LOW:
|
||||
default:
|
||||
{
|
||||
return ARM_DRIVER_ERROR_UNSUPPORTED;
|
||||
}
|
||||
}
|
||||
|
||||
return ARM_DRIVER_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
\fn static int32_t CDC200_control (uint32_t control, uint32_t arg,
|
||||
DISPLAY_PANEL_DEVICE *display_panel,
|
||||
CDC_RESOURCES *cdc)
|
||||
\brief Control the display controller.
|
||||
\param[in] control CDC200 contol code operation.
|
||||
- \ref CDC200_CONFIGURE_DISPLAY : Configure Display
|
||||
- \ref CDC200_FRAMEBUF_UPDATE : Update layer Frame buffer
|
||||
- \ref CDC200_FRAMEBUF_UPDATE_VSYNC : Update layer Frame buffer on vertical blanking
|
||||
- \ref CDC200_SCANLINE0_EVENT : Enable/Disable Scanline0 event
|
||||
- \ref CDC200_CONFIGURE_LAYER : Configure Layer
|
||||
- \ref CDC200_LAYER_ON : Turn On the Layer
|
||||
- \ref CDC200_LAYER_OFF : Turn Off the Layer
|
||||
- \ref CDC200_CONFIGURE_LAYER_WINDOW : Configure Layer window
|
||||
- \ref CDC200_CONFIGURE_BG_COLOR : Configure Background color
|
||||
- \ref CDC200_CONFIGURE_LAYER_BLENDING : Configure Layer blending
|
||||
\param[in] arg Argument of operation.
|
||||
- CDC200_CONFIGURE_DISPLAY : Frame buffer address
|
||||
- CDC200_FRAMEBUF_UPDATE : Frame buffer address
|
||||
- CDC200_FRAMEBUF_UPDATE_VSYNC : Frame buffer address
|
||||
- CDC200_SCANLINE0_EVENT : ENABLE/DISABLE
|
||||
- CDC200_CONFIGURE_LAYER : Pointer to layer info \ref ARM_CDC200_LAYER_INFO
|
||||
- CDC200_LAYER_ON : layer index /ref ARM_CDC200_LAYER_INDEX
|
||||
- CDC200_LAYER_OFF : layer index /ref ARM_CDC200_LAYER_INDEX
|
||||
- CDC200_CONFIGURE_LAYER_WINDOW : Pointer to layer info \ref ARM_CDC200_LAYER_INFO
|
||||
- CDC200_CONFIGURE_BG_COLOR : Background color setting
|
||||
- /ref ARM_CDC200_BGC_BLUE(x)
|
||||
- /ref ARM_CDC200_BGC_GREEN(x)
|
||||
- /ref ARM_CDC200_BGC_RED(x)
|
||||
- CDC200_CONFIGURE_LAYER_BLENDING : Pointer to layer info \ref ARM_CDC200_LAYER_INFO
|
||||
\param[in] display_panel Pointer to display panel resources.
|
||||
\param[in] cdc Pointer to CDC resources.
|
||||
\return \ref execution_status.
|
||||
*/
|
||||
static int32_t CDC200_control (uint32_t control, uint32_t arg,
|
||||
DISPLAY_PANEL_DEVICE *display_panel,
|
||||
CDC_RESOURCES *cdc)
|
||||
{
|
||||
uint32_t ret = ARM_DRIVER_OK;
|
||||
|
||||
if (cdc->state.powered == 0)
|
||||
{
|
||||
return ARM_DRIVER_ERROR;
|
||||
}
|
||||
|
||||
switch (control)
|
||||
{
|
||||
case CDC200_CONFIGURE_DISPLAY:
|
||||
{
|
||||
cdc_cfg_info_t cdc_info;
|
||||
cdc_layer_info_t layer_info;
|
||||
|
||||
/*Setup display controller*/
|
||||
cdc_info.timing_info.hactive = display_panel->hactive_time;
|
||||
cdc_info.timing_info.hfp = display_panel->hfp_time;
|
||||
cdc_info.timing_info.hbp = display_panel->hbp_time;
|
||||
cdc_info.timing_info.hsync = display_panel->hsync_time;
|
||||
cdc_info.timing_info.vactive = display_panel->vactive_line;
|
||||
cdc_info.timing_info.vfp = display_panel->vfp_line;
|
||||
cdc_info.timing_info.vbp = display_panel->vbp_line;
|
||||
cdc_info.timing_info.vsync = display_panel->vsync_line;
|
||||
|
||||
cdc_info.bgc.red = cdc->bgc->red;
|
||||
cdc_info.bgc.green = cdc->bgc->green;
|
||||
cdc_info.bgc.blue = cdc->bgc->blue;
|
||||
|
||||
cdc_info.line_irq_pos = (display_panel->vsync_line +
|
||||
display_panel->vbp_line +
|
||||
display_panel->vactive_line);
|
||||
|
||||
cdc_info.sh_rld = CDC_SHADOW_RELOAD_IMR;
|
||||
|
||||
layer_info.fb_addr = LocalToGlobal((void*)arg);
|
||||
layer_info.line_length_in_pixels = display_panel->hactive_time;
|
||||
layer_info.const_alpha = cdc->const_alpha;
|
||||
layer_info.blend_factor = cdc->blend_factor;
|
||||
layer_info.num_lines = display_panel->vactive_line;
|
||||
layer_info.pix_format = cdc->pixel_format;
|
||||
|
||||
layer_info.win_info.h_start_pos = (display_panel->hsync_time +
|
||||
display_panel->hbp_time);
|
||||
layer_info.win_info.h_stop_pos = ((display_panel->hsync_time +
|
||||
display_panel->hbp_time +
|
||||
display_panel->hactive_time) - 1);
|
||||
layer_info.win_info.v_start_pos = (display_panel->vsync_line +
|
||||
display_panel->vbp_line);
|
||||
layer_info.win_info.v_stop_pos = ((display_panel->vsync_line +
|
||||
display_panel->vbp_line +
|
||||
display_panel->vactive_line) - 1);
|
||||
|
||||
layer_info.sh_rld = CDC_SHADOW_RELOAD_IMR;
|
||||
|
||||
cdc_set_hsync_polarity(cdc->regs, display_panel->cdc_info->hsync_polarity);
|
||||
cdc_set_vsync_polarity(cdc->regs, display_panel->cdc_info->vsync_polarity);
|
||||
cdc_set_pclkout_polarity(cdc->regs, display_panel->cdc_info->pclk_polarity);
|
||||
cdc_set_blank_polarity(cdc->regs, display_panel->cdc_info->blank_polarity);
|
||||
|
||||
cdc_set_cfg (cdc->regs, &cdc_info);
|
||||
cdc_set_layer_cfg (cdc->regs, CDC_LAYER_1, &layer_info);
|
||||
|
||||
cdc_layer_on (cdc->regs, CDC_LAYER_1, CDC_SHADOW_RELOAD_IMR);
|
||||
|
||||
#if (RTE_MIPI_DSI)
|
||||
/*MIPI DSI Configure Host*/
|
||||
ret = Driver_MIPI_DSI.Control (DSI_CONFIGURE_HOST, 0);
|
||||
if (ret != ARM_DRIVER_OK)
|
||||
{
|
||||
return ret;
|
||||
}
|
||||
|
||||
/*Start Command mode and Configure LCD Panel*/
|
||||
ret = Driver_MIPI_DSI.StartCommandMode ();
|
||||
if (ret != ARM_DRIVER_OK)
|
||||
{
|
||||
return ret;
|
||||
}
|
||||
|
||||
/*MIPI DSI Configure DPI*/
|
||||
ret = Driver_MIPI_DSI.Control (DSI_CONFIGURE_DPI, 0);
|
||||
if (ret != ARM_DRIVER_OK)
|
||||
{
|
||||
return ret;
|
||||
}
|
||||
#endif
|
||||
|
||||
cdc->state.configured = 1;
|
||||
break;
|
||||
}
|
||||
|
||||
case CDC200_FRAMEBUF_UPDATE:
|
||||
{
|
||||
|
||||
/*Update the buffer start address for new buffer content*/
|
||||
cdc_set_layer_fb_addr (cdc->regs, CDC_LAYER_1, CDC_SHADOW_RELOAD_IMR, LocalToGlobal((void*)arg));
|
||||
break;
|
||||
}
|
||||
|
||||
case CDC200_FRAMEBUF_UPDATE_VSYNC:
|
||||
{
|
||||
|
||||
/* Update the buffer start address for new buffer content */
|
||||
cdc_set_layer_fb_addr (cdc->regs, CDC_LAYER_1, CDC_SHADOW_RELOAD_VBR, LocalToGlobal((void*)arg));
|
||||
break;
|
||||
}
|
||||
|
||||
case CDC200_SCANLINE0_EVENT:
|
||||
{
|
||||
/*Enable/Disable Scanline0 IRQ*/
|
||||
if(arg == ENABLE)
|
||||
{
|
||||
cdc_irq_enable (cdc->regs, CDC_IRQ_LINE);
|
||||
}
|
||||
else if (arg == DISABLE)
|
||||
{
|
||||
cdc_irq_disable (cdc->regs, CDC_IRQ_LINE);
|
||||
}
|
||||
else
|
||||
{
|
||||
return ARM_DRIVER_ERROR_PARAMETER;
|
||||
}
|
||||
break;
|
||||
}
|
||||
|
||||
case CDC200_CONFIGURE_LAYER:
|
||||
{
|
||||
ARM_CDC200_LAYER_INFO *cdc200_layer_info = (ARM_CDC200_LAYER_INFO *)arg;
|
||||
cdc_layer_info_t layer_info;
|
||||
|
||||
/* Configure Layer */
|
||||
layer_info.win_info.v_start_pos = cdc200_layer_info->win_info.v_start_pos;
|
||||
layer_info.win_info.v_stop_pos = cdc200_layer_info->win_info.v_stop_pos;
|
||||
layer_info.win_info.h_start_pos = cdc200_layer_info->win_info.h_start_pos;
|
||||
layer_info.win_info.h_stop_pos = cdc200_layer_info->win_info.h_stop_pos;
|
||||
|
||||
layer_info.pix_format = (CDC_PIXEL_FORMAT)cdc200_layer_info->pix_format;
|
||||
layer_info.const_alpha = cdc200_layer_info->const_alpha;
|
||||
layer_info.blend_factor = (CDC_BLEND_FACTOR)cdc200_layer_info->blend_factor;
|
||||
layer_info.fb_addr = LocalToGlobal((void*)cdc200_layer_info->fb_addr);
|
||||
layer_info.line_length_in_pixels = cdc200_layer_info->line_length_in_pixels;
|
||||
layer_info.num_lines = cdc200_layer_info->num_lines;
|
||||
|
||||
layer_info.sh_rld = CDC_SHADOW_RELOAD_IMR;
|
||||
|
||||
cdc_set_layer_cfg (cdc->regs, (CDC_LAYER)cdc200_layer_info->layer_idx, &layer_info);
|
||||
break;
|
||||
}
|
||||
|
||||
case CDC200_LAYER_ON:
|
||||
{
|
||||
if((arg != ARM_CDC200_LAYER_1) && (arg != ARM_CDC200_LAYER_2))
|
||||
{
|
||||
return ARM_DRIVER_ERROR_PARAMETER;
|
||||
}
|
||||
/* Turn On layer */
|
||||
cdc_layer_on (cdc->regs, arg, CDC_SHADOW_RELOAD_IMR);
|
||||
break;
|
||||
}
|
||||
|
||||
case CDC200_LAYER_OFF:
|
||||
{
|
||||
if((arg != ARM_CDC200_LAYER_1) && (arg != ARM_CDC200_LAYER_2))
|
||||
{
|
||||
return ARM_DRIVER_ERROR_PARAMETER;
|
||||
}
|
||||
/* Turn Off layer */
|
||||
cdc_layer_off (cdc->regs, arg, CDC_SHADOW_RELOAD_IMR);
|
||||
break;
|
||||
}
|
||||
|
||||
case CDC200_CONFIGURE_LAYER_WINDOW:
|
||||
{
|
||||
ARM_CDC200_LAYER_INFO *cdc200_layer_info = (ARM_CDC200_LAYER_INFO *)arg;
|
||||
cdc_window_info_t win_info;
|
||||
|
||||
/* Configure Layer window*/
|
||||
win_info.v_start_pos = cdc200_layer_info->win_info.v_start_pos;
|
||||
win_info.v_stop_pos = cdc200_layer_info->win_info.v_stop_pos;
|
||||
win_info.h_start_pos = cdc200_layer_info->win_info.h_start_pos;
|
||||
win_info.h_stop_pos = cdc200_layer_info->win_info.h_stop_pos;
|
||||
|
||||
cdc_set_layer_fb_window (cdc->regs, (CDC_LAYER)cdc200_layer_info->layer_idx,
|
||||
CDC_SHADOW_RELOAD_IMR, &win_info);
|
||||
break;
|
||||
}
|
||||
|
||||
case CDC200_CONFIGURE_BG_COLOR:
|
||||
{
|
||||
cdc_backgnd_color_info_t bgc_info;
|
||||
|
||||
/* Configure Background color*/
|
||||
bgc_info.red = _FLD2VAL(ARM_CDC200_BGC_RED, arg);
|
||||
bgc_info.green = _FLD2VAL(ARM_CDC200_BGC_GREEN, arg);
|
||||
bgc_info.blue = _FLD2VAL(ARM_CDC200_BGC_BLUE, arg);
|
||||
|
||||
cdc_set_backgnd_color(cdc->regs, CDC_SHADOW_RELOAD_IMR, &bgc_info);
|
||||
break;
|
||||
}
|
||||
|
||||
case CDC200_CONFIGURE_LAYER_BLENDING:
|
||||
{
|
||||
ARM_CDC200_LAYER_INFO *cdc200_layer_info = (ARM_CDC200_LAYER_INFO *)arg;
|
||||
|
||||
/* Configure Layer Blending*/
|
||||
cdc_set_layer_blending (cdc->regs, (CDC_LAYER)cdc200_layer_info->layer_idx,
|
||||
CDC_SHADOW_RELOAD_IMR, cdc200_layer_info->const_alpha,
|
||||
(CDC_BLEND_FACTOR)cdc200_layer_info->blend_factor);
|
||||
break;
|
||||
}
|
||||
|
||||
default:
|
||||
{
|
||||
return ARM_DRIVER_ERROR_UNSUPPORTED;
|
||||
}
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/**
|
||||
\fn static int32_t CDC200_GetVerticalPos (DISPLAY_PANEL_DEVICE *display_panel,
|
||||
CDC_RESOURCES *cdc)
|
||||
\brief Get current vertical position count.
|
||||
\param[in] display_panel Pointer to display panel resources.
|
||||
\param[in] cdc Pointer to CDC resources.
|
||||
\return return current vertical position.
|
||||
*/
|
||||
static int32_t CDC200_GetVerticalPos (DISPLAY_PANEL_DEVICE *display_panel,
|
||||
CDC_RESOURCES *cdc)
|
||||
{
|
||||
return ((int) cdc_get_y_position_status (cdc->regs)
|
||||
-display_panel->vsync_line - display_panel->vbp_line);
|
||||
}
|
||||
|
||||
/**
|
||||
\fn static int32_t CDC200_Start (CDC_RESOURCES *cdc)
|
||||
\brief Start the display controller.
|
||||
\param[in] cdc Pointer to CDC resources.
|
||||
\return \ref execution_status.
|
||||
*/
|
||||
static int32_t CDC200_Start (CDC_RESOURCES *cdc)
|
||||
{
|
||||
uint32_t ret = ARM_DRIVER_OK;
|
||||
|
||||
if (cdc->state.configured == 0)
|
||||
{
|
||||
return ARM_DRIVER_ERROR;
|
||||
}
|
||||
|
||||
#if (RTE_MIPI_DSI)
|
||||
/*Start MIPI DSI and LCD Panel*/
|
||||
ret = Driver_MIPI_DSI.StartVideoMode ();
|
||||
if (ret != ARM_DRIVER_OK)
|
||||
{
|
||||
return ret;
|
||||
}
|
||||
#endif
|
||||
|
||||
/*Enable Display Controller CDC200*/
|
||||
cdc_global_enable (cdc->regs);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/**
|
||||
\fn static int32_t CDC200_Stop (CDC_RESOURCES *cdc)
|
||||
\brief Stop the display controller.
|
||||
\param[in] cdc Pointer to CDC resources.
|
||||
\return \ref execution_status.
|
||||
*/
|
||||
static int32_t CDC200_Stop (CDC_RESOURCES *cdc)
|
||||
{
|
||||
uint32_t ret = ARM_DRIVER_OK;
|
||||
|
||||
if (cdc->state.powered == 0)
|
||||
{
|
||||
return ARM_DRIVER_ERROR;
|
||||
}
|
||||
|
||||
/*Disable Display Controller CDC200*/
|
||||
cdc_global_disable (cdc->regs);
|
||||
|
||||
#if (RTE_MIPI_DSI)
|
||||
/*Stop MIPI DSI and LCD Panel*/
|
||||
ret = Driver_MIPI_DSI.Stop ();
|
||||
if (ret != ARM_DRIVER_OK)
|
||||
{
|
||||
return ret;
|
||||
}
|
||||
#endif
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/**
|
||||
\fn static void CDC200_ISR (CDC_RESOURCES *cdc)
|
||||
\brief CDC200 interrupt service routine
|
||||
\param[in] cdc Pointer to CDC resources
|
||||
*/
|
||||
static void CDC200_ISR (CDC_RESOURCES *cdc)
|
||||
{
|
||||
uint32_t irq_st = cdc_get_irq_status (cdc->regs);
|
||||
|
||||
if (!(cdc->cb_event))
|
||||
{
|
||||
return;
|
||||
}
|
||||
|
||||
if (irq_st & CDC_IRQ_LINE)
|
||||
{
|
||||
cdc->cb_event (ARM_CDC_SCANLINE0_EVENT);
|
||||
cdc_irq_clear (cdc->regs, CDC_IRQ_LINE);
|
||||
}
|
||||
}
|
||||
|
||||
#if (RTE_CDC200)
|
||||
|
||||
/* DSI LCD Panel access structure */
|
||||
static DISPLAY_PANEL_DEVICE *display_panel;
|
||||
|
||||
cdc_backgnd_color_info_t BGC_INFO =
|
||||
{
|
||||
.red = RTE_CDC200_BGC_RED,
|
||||
.green = RTE_CDC200_BGC_GREEN,
|
||||
.blue = RTE_CDC200_BGC_BLUE
|
||||
};
|
||||
|
||||
CDC_RESOURCES CDC_RES =
|
||||
{
|
||||
.regs = (CDC_Type*) CDC_BASE,
|
||||
.cb_event = NULL,
|
||||
.bgc = &BGC_INFO,
|
||||
.pixel_format = RTE_CDC200_PIXEL_FORMAT,
|
||||
.const_alpha = RTE_CDC200_CONSTANT_ALPHA,
|
||||
.blend_factor = RTE_CDC200_BLEND_FACTOR,
|
||||
.irq_priority = RTE_CDC200_IRQ_PRI,
|
||||
.state = {0},
|
||||
};
|
||||
|
||||
#if (RTE_MIPI_DSI)
|
||||
/**
|
||||
\fn void MIPI_DSI_Event_Callback (uint32_t int_event)
|
||||
\brief Signal MIPI DSI Events.
|
||||
\param[in] int_event \ref MIPI DSI event types.
|
||||
\return none.
|
||||
*/
|
||||
void MIPI_DSI_Event_Callback (uint32_t int_event)
|
||||
{
|
||||
ARG_UNUSED(int_event);
|
||||
CDC_RES.cb_event (ARM_CDC_DSI_ERROR_EVENT);
|
||||
}
|
||||
#endif
|
||||
|
||||
/**
|
||||
\fn int32_t CDC200_Initialize (ARM_CDC200_SignalEvent_t cb_event)
|
||||
\brief Initialize CDC200 Interface.
|
||||
\param[in] cb_event Pointer to ARM_CDC200_SignalEvent_t.
|
||||
\return \ref execution_status.
|
||||
*/
|
||||
static int32_t CDC200_Initialize (ARM_CDC200_SignalEvent_t cb_event)
|
||||
{
|
||||
display_panel = Get_Display_Panel();
|
||||
return CDC200_Init (cb_event, display_panel, &CDC_RES);
|
||||
}
|
||||
|
||||
/**
|
||||
\fn int32_t CDC200_Uninitialize (void)
|
||||
\brief Uninitialize CDC200 Interface.
|
||||
\return \ref execution_status.
|
||||
*/
|
||||
static int32_t CDC200_Uninitialize (void)
|
||||
{
|
||||
return CDC200_Uninit (&CDC_RES);
|
||||
}
|
||||
|
||||
/**
|
||||
\fn int32_t CDC200_PowerControl (ARM_POWER_STATE state)
|
||||
\brief Control CDC200 Interface Power.
|
||||
\param[in] state Power state.
|
||||
\return \ref execution_status.
|
||||
*/
|
||||
static int32_t CDC200_PowerControl (ARM_POWER_STATE state)
|
||||
{
|
||||
return CDC200_PowerCtrl (state, display_panel, &CDC_RES);
|
||||
}
|
||||
|
||||
/**
|
||||
\fn int32_t CDC200_Control (uint32_t control, uint32_t arg)
|
||||
\brief Control the display controller.
|
||||
\param[in] control CDC200 Configuration.
|
||||
\param[in] arg Argument of operation (optional).
|
||||
\return \ref execution_status.
|
||||
*/
|
||||
static int32_t CDC200_Control (uint32_t control, uint32_t arg)
|
||||
{
|
||||
return CDC200_control (control, arg, display_panel, &CDC_RES);
|
||||
}
|
||||
|
||||
/**
|
||||
\fn int32_t CDC200_GetVerticalPosition (void)
|
||||
\brief Get current vertical position count.
|
||||
\return return current vertical Position.
|
||||
*/
|
||||
static int32_t CDC200_GetVerticalPosition (void)
|
||||
{
|
||||
return CDC200_GetVerticalPos (display_panel, &CDC_RES);
|
||||
}
|
||||
|
||||
/**
|
||||
\fn int32_t CDC200_StartDisplay (void)
|
||||
\brief Start the display controller.
|
||||
\return \ref execution_status.
|
||||
*/
|
||||
static int32_t CDC200_StartDisplay (void)
|
||||
{
|
||||
return CDC200_Start (&CDC_RES);
|
||||
}
|
||||
|
||||
/**
|
||||
\fn int32_t CDC200_StopDisplay (void)
|
||||
\brief Stop the display controller.
|
||||
\return \ref execution_status.
|
||||
*/
|
||||
static int32_t CDC200_StopDisplay (void)
|
||||
{
|
||||
return CDC200_Stop (&CDC_RES);
|
||||
}
|
||||
|
||||
/**
|
||||
\fn void CDC200_SCANLINE0_IRQHandler (void)
|
||||
\brief CDC200 SCANLINE0 IRQ Handler.
|
||||
*/
|
||||
void CDC_SCANLINE0_IRQHandler(void)
|
||||
{
|
||||
CDC200_ISR (&CDC_RES);
|
||||
}
|
||||
|
||||
extern ARM_DRIVER_CDC200 Driver_CDC200;
|
||||
|
||||
ARM_DRIVER_CDC200 Driver_CDC200 =
|
||||
{
|
||||
CDC200_GetVersion,
|
||||
CDC200_GetCapabilities,
|
||||
CDC200_Initialize,
|
||||
CDC200_Uninitialize,
|
||||
CDC200_PowerControl,
|
||||
CDC200_Control,
|
||||
CDC200_GetVerticalPosition,
|
||||
CDC200_StartDisplay,
|
||||
CDC200_StopDisplay
|
||||
};
|
||||
#endif
|
||||
59
src/hal/alif/Alif_CMSIS/Source/Driver_CDC_Private.h
Normal file
59
src/hal/alif/Alif_CMSIS/Source/Driver_CDC_Private.h
Normal file
@ -0,0 +1,59 @@
|
||||
/* Copyright (C) 2023 Alif Semiconductor - All Rights Reserved.
|
||||
* Use, distribution and modification of this code is permitted under the
|
||||
* terms stated in the Alif Semiconductor Software License Agreement
|
||||
*
|
||||
* You should have received a copy of the Alif Semiconductor Software
|
||||
* License Agreement with this file. If not, please write to:
|
||||
* contact@alifsemi.com, or visit: https://alifsemi.com/license
|
||||
*
|
||||
*/
|
||||
|
||||
/**************************************************************************//**
|
||||
* @file Driver_CDC_Private.h
|
||||
* @author Prasanna Ravi
|
||||
* @email prasanna.ravi@alifsemi.com
|
||||
* @version V1.0.0
|
||||
* @date 28-Sep-2023
|
||||
* @brief CDC driver Specific Header file.
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef DRIVER_CDC_PRIVATE_H_
|
||||
#define DRIVER_CDC_PRIVATE_H_
|
||||
|
||||
#include "RTE_Components.h"
|
||||
#include CMSIS_device_header
|
||||
|
||||
#include "Driver_CDC200.h"
|
||||
|
||||
#include "cdc.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
/** \brief CDC Driver states. */
|
||||
typedef volatile struct _CDC_DRIVER_STATE {
|
||||
uint32_t initialized : 1; /**< Driver Initialized */
|
||||
uint32_t powered : 1; /**< Driver powered */
|
||||
uint32_t configured : 1; /**< Driver configured */
|
||||
uint32_t reserved : 29; /**< Reserved */
|
||||
} CDC_DRIVER_STATE;
|
||||
|
||||
/** \brief Resources for a CDC instance */
|
||||
typedef struct _CDC_RESOURCES {
|
||||
CDC_Type *regs; /**< Pointer to regs */
|
||||
ARM_CDC200_SignalEvent_t cb_event; /**< Pointer to call back function */
|
||||
cdc_backgnd_color_info_t *bgc; /**< Pointer to CDC background color */
|
||||
CDC_PIXEL_FORMAT pixel_format; /**< CDC pixel format */
|
||||
uint8_t const_alpha; /**< Layer constant alpha */
|
||||
CDC_BLEND_FACTOR blend_factor; /**< Layer blending factor */
|
||||
uint32_t irq_priority; /**< Interrupt priority */
|
||||
CDC_DRIVER_STATE state; /**< CDC driver status */
|
||||
} CDC_RESOURCES;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* DRIVER_CDC_PRIVATE_H_ */
|
||||
920
src/hal/alif/Alif_CMSIS/Source/Driver_CMP.c
Normal file
920
src/hal/alif/Alif_CMSIS/Source/Driver_CMP.c
Normal file
@ -0,0 +1,920 @@
|
||||
/* Copyright (C) 2023 Alif Semiconductor - All Rights Reserved.
|
||||
* Use, distribution and modification of this code is permitted under the
|
||||
* terms stated in the Alif Semiconductor Software License Agreement
|
||||
*
|
||||
* You should have received a copy of the Alif Semiconductor Software
|
||||
* License Agreement with this file. If not, please write to:
|
||||
* contact@alifsemi.com, or visit: https://alifsemi.com/license
|
||||
*
|
||||
*/
|
||||
|
||||
/* Project Includes */
|
||||
#include "cmp.h"
|
||||
#include "Driver_CMP.h"
|
||||
#include "Driver_CMP_Private.h"
|
||||
#include "analog_config.h"
|
||||
#include "sys_ctrl_cmp.h"
|
||||
|
||||
#if !(RTE_HSCMP0 || RTE_HSCMP1 || RTE_HSCMP2 || RTE_HSCMP3 || RTE_LPCMP)
|
||||
#error "Comparator is not configured in RTE_device.h!"
|
||||
#endif
|
||||
|
||||
#if(defined(RTE_Drivers_CMP0) && !RTE_HSCMP0)
|
||||
#error "HSCMP0 not configured in RTE_Device.h!"
|
||||
#endif
|
||||
|
||||
#if(defined(RTE_Drivers_CMP1) && !RTE_HSCMP1)
|
||||
#error "CMP1 not configured in RTE_Device.h!"
|
||||
#endif
|
||||
|
||||
#if(defined(RTE_Drivers_CMP2) && !RTE_HSCMP2)
|
||||
#error "HSCMP2 not configured in RTE_Device.h!"
|
||||
#endif
|
||||
|
||||
#if(defined(RTE_Drivers_CMP3) && !RTE_HSCMP3)
|
||||
#error "HSCMP3 not configured in RTE_Device.h!"
|
||||
#endif
|
||||
|
||||
#if(defined(RTE_Drivers_LPCMP) && !RTE_LPCMP)
|
||||
#error "LPCMP not configured in RTE_Device.h!"
|
||||
#endif
|
||||
|
||||
#define ARM_CMP_DRV_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(1, 0) /* Driver version */
|
||||
|
||||
/*Driver version*/
|
||||
static const ARM_DRIVER_VERSION DriverVersion = {
|
||||
ARM_CMP_API_VERSION,
|
||||
ARM_CMP_DRV_VERSION
|
||||
};
|
||||
|
||||
/*Driver Capabilities */
|
||||
static const ARM_COMPARATOR_CAPABILITIES DriverCapabilities = {
|
||||
1,/* Ability to invert the input signal */
|
||||
1,/* Used to define when to look at the comparator input */
|
||||
1,/* Supports Filter function */
|
||||
1,/* Supports Prescaler function */
|
||||
0 /* Reserved ( must be ZERO) */
|
||||
};
|
||||
|
||||
/**
|
||||
@fn ARM_DRIVER_VERSION CMP_GetVersion(void)
|
||||
@brief get CMP version
|
||||
@param none
|
||||
@return driver version
|
||||
*/
|
||||
static ARM_DRIVER_VERSION CMP_GetVersion(void)
|
||||
{
|
||||
return DriverVersion;
|
||||
}
|
||||
|
||||
/**
|
||||
@fn ARM_COMPARATOR_CAPABILITIES CMP_GetCapabilities(void)
|
||||
@brief get Comparator Capabilities
|
||||
@param none
|
||||
@return driver Capabilities
|
||||
*/
|
||||
static ARM_COMPARATOR_CAPABILITIES CMP_GetCapabilities(void)
|
||||
{
|
||||
return DriverCapabilities;
|
||||
}
|
||||
|
||||
/**
|
||||
@fn void AnalogConfig(uint8_t instance)
|
||||
@brief Analog configuration register includes Vbat and comparator
|
||||
@param[in] instance : Comparator instances
|
||||
@return none
|
||||
*/
|
||||
static void AnalogConfig(uint8_t instance)
|
||||
{
|
||||
if(instance != CMP_INSTANCE_LP)
|
||||
{
|
||||
/* Analog configuration comparator register2 */
|
||||
analog_config_cmp_reg2();
|
||||
}
|
||||
|
||||
/* Analog configuration Vbat register2 */
|
||||
analog_config_vbat_reg2();
|
||||
}
|
||||
|
||||
/**
|
||||
* @fn CMP_Initialize(ARM_Comparator_SignalEvent_t cb_event, CMP_RESOURCES *CMP )
|
||||
* @brief Initialize the Analog Comparator
|
||||
* @param[in] cb_event : Pointer to /ref ARM_Comparator_SignalEvent_t cb_event
|
||||
* @param[in] CMP : Pointer to Comparator resources
|
||||
* @return ARM_DRIVER_OK : if driver initialized successfully
|
||||
*/
|
||||
static int32_t CMP_Initialize(ARM_Comparator_SignalEvent_t cb_event, CMP_RESOURCES *CMP )
|
||||
{
|
||||
int32_t ret = ARM_DRIVER_OK;
|
||||
|
||||
if(!cb_event)
|
||||
return ARM_DRIVER_ERROR_PARAMETER;
|
||||
|
||||
/* User call back Event */
|
||||
CMP->cb_event = cb_event;
|
||||
|
||||
/* Set state to initialize */
|
||||
CMP->state.initialized = 1;
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/**
|
||||
@fn int32_t CMP_Uninitialize(CMP_RESOURCES *CMP)
|
||||
@brief Un-Initialize the Analog Comparator
|
||||
@param[in] CMP : Pointer to Comparator resources
|
||||
@return ARM_DRIVER_OK : if Comparator successfully uninitialized or already not initialized
|
||||
*/
|
||||
static int32_t CMP_Uninitialize(CMP_RESOURCES *CMP)
|
||||
{
|
||||
int32_t ret = ARM_DRIVER_OK;
|
||||
|
||||
if(!CMP)
|
||||
return ARM_DRIVER_ERROR_PARAMETER;
|
||||
|
||||
/* Check initialized has done or not */
|
||||
if(CMP->state.initialized == 0)
|
||||
return ARM_DRIVER_OK;
|
||||
|
||||
/* set call back to NULL */
|
||||
CMP->cb_event = NULL;
|
||||
|
||||
/* Reset the state */
|
||||
CMP->state.initialized = 0;
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/**
|
||||
* @fn CMP_PowerControl(ARM_POWER_STATE state,CMP_RESOURCES *CMP )
|
||||
* @brief power the driver and enable NVIC
|
||||
Initialize the following in ARM_POWER_FULL:
|
||||
- Access vbat and CMP register configuration
|
||||
- Select the positive and negative terminal of CMP
|
||||
- Mask the interrupt
|
||||
Un-Initialize the following in ARM_POWER_OFF:
|
||||
-clear the CMP configuration
|
||||
-set call back to NULL
|
||||
-Disable the interrupt mask
|
||||
-Reset the state
|
||||
* @param[in] state : power state
|
||||
* @param[in] CMP : pointer to /ref CMP_RESOURCES
|
||||
* @return ARM_DRIVER_OK : if power done successful
|
||||
ARM_DRIVER_ERROR : if initialize is not done
|
||||
*/
|
||||
static int32_t CMP_PowerControl(ARM_POWER_STATE state,CMP_RESOURCES *CMP )
|
||||
{
|
||||
int32_t ret = ARM_DRIVER_OK;
|
||||
|
||||
switch (state)
|
||||
{
|
||||
case ARM_POWER_FULL:
|
||||
if(CMP->state.initialized == 0)
|
||||
return ARM_DRIVER_ERROR;
|
||||
|
||||
if(CMP->state.powered == 1)
|
||||
return ARM_DRIVER_OK;
|
||||
|
||||
/* Clear Any Pending IRQ */
|
||||
NVIC_ClearPendingIRQ(CMP->irq_num);
|
||||
|
||||
/* Set the priority */
|
||||
NVIC_SetPriority(CMP->irq_num, CMP->irq_priority);
|
||||
|
||||
/* Enable the NIVC */
|
||||
NVIC_EnableIRQ(CMP->irq_num);
|
||||
|
||||
enable_cmp_clk(CMP->drv_instance);
|
||||
|
||||
/* Initialization for Analog configuration register */
|
||||
AnalogConfig(CMP->drv_instance);
|
||||
|
||||
/* Initialize the CMP configurations */
|
||||
cmp_set_config(CMP->drv_instance, CMP->config);
|
||||
|
||||
if(CMP->drv_instance != CMP_INSTANCE_LP)
|
||||
{
|
||||
/* To disable the interrupt */
|
||||
cmp_disable_interrupt(CMP->regs);
|
||||
}
|
||||
|
||||
/* Set the power state enabled */
|
||||
CMP->state.powered = 1;
|
||||
|
||||
break;
|
||||
|
||||
case ARM_POWER_OFF:
|
||||
|
||||
/* Disable CMP NVIC */
|
||||
NVIC_DisableIRQ(CMP->irq_num);
|
||||
|
||||
/* Clear Any Pending IRQ */
|
||||
NVIC_ClearPendingIRQ(CMP->irq_num);
|
||||
|
||||
disable_cmp(CMP->drv_instance);
|
||||
|
||||
if(CMP->drv_instance == CMP_INSTANCE_LP)
|
||||
{
|
||||
lpcmp_clear_config();
|
||||
}
|
||||
else
|
||||
{
|
||||
/* clear the CMP configuration */
|
||||
cmp_clear_config(CMP->regs);
|
||||
|
||||
/* To the enable the interrupt */
|
||||
cmp_disable_interrupt(CMP->regs);
|
||||
}
|
||||
|
||||
disable_cmp_clk(CMP->drv_instance);
|
||||
|
||||
/* Reset the power status of CMP */
|
||||
CMP->state.powered = 0;
|
||||
|
||||
break;
|
||||
|
||||
case ARM_POWER_LOW:
|
||||
default:
|
||||
return ARM_DRIVER_ERROR_UNSUPPORTED;
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief CMP_Control(CMP_RESOURCES *CMP, uint32_t control, uint32_t arg)
|
||||
* @brief CMSIS-Driver comparator control.
|
||||
Control comparator Interface.
|
||||
* @param[in] CMP : Pointer to comparator resources
|
||||
* @param[in] control : Operation \ref Driver_Comparator.h : comparator control codes
|
||||
* @param[in] arg : Argument of operation (optional)
|
||||
* @return ARM_DRIVER_ERROR_PARAMETER : if comparator device is invalid
|
||||
ARM_DRIVER_OK : if comparator successfully uninitialized or already not initialized
|
||||
*/
|
||||
static int32_t CMP_Control(CMP_RESOURCES *CMP, uint32_t control, uint32_t arg)
|
||||
{
|
||||
int32_t ret = ARM_DRIVER_OK;
|
||||
|
||||
if(CMP->state.initialized == 0)
|
||||
return ARM_DRIVER_ERROR;
|
||||
|
||||
if(CMP->state.powered == 0)
|
||||
return ARM_DRIVER_ERROR;
|
||||
|
||||
switch(control)
|
||||
{
|
||||
case ARM_CMP_POLARITY_CONTROL:
|
||||
|
||||
if(arg > CMP_POLARITY_MAX_VALUE)
|
||||
return ARM_DRIVER_ERROR_PARAMETER;
|
||||
|
||||
/* If active, invert the value of CMP_OUT (comparison result) */
|
||||
cmp_set_polarity_ctrl(CMP->regs, arg);
|
||||
|
||||
break;
|
||||
|
||||
case ARM_CMP_FILTER_CONTROL:
|
||||
|
||||
if(arg < CMP_FILTER_MIN_VALUE || arg > CMP_FILTER_MAX_VALUE)
|
||||
return ARM_DRIVER_ERROR_PARAMETER;
|
||||
|
||||
/* To enable the filter function and adding filter values to the filter control register */
|
||||
cmp_set_filter_ctrl(CMP->regs, arg);
|
||||
|
||||
break;
|
||||
|
||||
case ARM_CMP_PRESCALER_CONTROL:
|
||||
|
||||
if(arg > CMP_PRESCALER_MAX_VALUE)
|
||||
return ARM_DRIVER_ERROR_PARAMETER;
|
||||
|
||||
/* Comparator input will be sampled at the given clocks */
|
||||
cmp_set_prescaler_ctrl(CMP->regs, arg);
|
||||
|
||||
break;
|
||||
|
||||
case ARM_CMP_WINDOW_CONTROL_ENABLE:
|
||||
|
||||
if(arg > CMP_WINDOW_MAX_VALUE)
|
||||
return ARM_DRIVER_ERROR_PARAMETER;
|
||||
|
||||
/* Set comparator window control */
|
||||
cmp_set_window_ctrl(CMP->regs, arg);
|
||||
|
||||
break;
|
||||
|
||||
case ARM_CMP_WINDOW_CONTROL_DISABLE:
|
||||
|
||||
if(arg > CMP_WINDOW_MAX_VALUE)
|
||||
return ARM_DRIVER_ERROR_PARAMETER;
|
||||
|
||||
/* Clear comparator window control */
|
||||
cmp_clear_window_ctrl(CMP->regs, arg);
|
||||
|
||||
break;
|
||||
|
||||
default:
|
||||
ret = ARM_DRIVER_ERROR_UNSUPPORTED;
|
||||
}
|
||||
return ret;
|
||||
}
|
||||
|
||||
/**
|
||||
* @fn CMP_Start(CMP_RESOURCES *CMP)
|
||||
* @brief CMSIS-Driver Comparator Start
|
||||
* Clear the IRQ before re-starting
|
||||
* Enable the Comparator.
|
||||
* @param[in] CMP : Pointer to Comparator resources
|
||||
* @return ARM_DRIVER_OK : if the function are return successful
|
||||
* ARM_DRIVER_ERROR : if initialize is not done
|
||||
*/
|
||||
static int32_t CMP_Start(CMP_RESOURCES *CMP)
|
||||
{
|
||||
int32_t ret = ARM_DRIVER_OK;
|
||||
|
||||
if(CMP->state.initialized == 0)
|
||||
return ARM_DRIVER_ERROR;
|
||||
|
||||
if(CMP->state.powered == 0)
|
||||
return ARM_DRIVER_ERROR;
|
||||
|
||||
/* Enable the Comparator module */
|
||||
enable_cmp(CMP->drv_instance);
|
||||
|
||||
if(CMP->drv_instance != CMP_INSTANCE_LP)
|
||||
{
|
||||
/* enable the interrupt(unmask the interrupt 0x0)*/
|
||||
cmp_enable_interrupt(CMP->regs);
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/**
|
||||
* @fn CMP_Stop(CMP_RESOURCES *CMP)
|
||||
* @brief CMSIS-Driver Comparator Stop
|
||||
* Disable the Comparator.
|
||||
* @param[in] CMP : Pointer to Comparator resources
|
||||
* @return ARM_DRIVER_OK : if the function are return successful
|
||||
* ARM_DRIVER_ERROR : if initialize is not done
|
||||
*/
|
||||
static int32_t CMP_Stop(CMP_RESOURCES *CMP)
|
||||
{
|
||||
int32_t ret = ARM_DRIVER_OK;
|
||||
if(CMP->state.initialized == 0)
|
||||
return ARM_DRIVER_ERROR;
|
||||
|
||||
if(CMP->state.powered == 0)
|
||||
return ARM_DRIVER_ERROR;
|
||||
|
||||
/* Disable the Comparator module */
|
||||
disable_cmp(CMP->drv_instance);
|
||||
|
||||
if(CMP->drv_instance != CMP_INSTANCE_LP)
|
||||
{
|
||||
/* Disable the interrupt */
|
||||
cmp_disable_interrupt(CMP->regs);
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/**
|
||||
\fn void CMP_IRQ_handler(CMP_RESOURCES *CMP)
|
||||
\brief CMP Interrupt service routine.
|
||||
\param[in] CMP : Pointer to Comparator resources
|
||||
*/
|
||||
static void CMP_IRQ_handler(CMP_RESOURCES *CMP)
|
||||
{
|
||||
if(CMP->drv_instance != CMP_INSTANCE_LP)
|
||||
{
|
||||
cmp_irq_handler(CMP->regs);
|
||||
}
|
||||
|
||||
/* Clear Any Pending IRQ */
|
||||
NVIC_ClearPendingIRQ(CMP->irq_num);
|
||||
|
||||
/* call user callback */
|
||||
CMP->cb_event(ARM_CMP_FILTER_EVENT_OCCURRED);
|
||||
}
|
||||
|
||||
/* HSCMP0 driver instance */
|
||||
#if(RTE_HSCMP0)
|
||||
|
||||
/* Comparator Configurations */
|
||||
static CMP_RESOURCES HSCMP0 = {
|
||||
.cb_event = NULL,
|
||||
.regs = (CMP_Type *)CMP0_BASE,
|
||||
.drv_instance = CMP_INSTANCE_0,
|
||||
.state = {0},
|
||||
.irq_num = (IRQn_Type)CMP0_IRQ_IRQn,
|
||||
.config = (RTE_CMP0_SEL_POSITIVE << 0 ) |
|
||||
(RTE_CMP0_SEL_NEGATIVE << 2) |
|
||||
(RTE_CMP0_SEL_HYSTERISIS << 4 ),
|
||||
.irq_priority = RTE_CMP0_IRQ_PRIORITY
|
||||
};
|
||||
|
||||
/**
|
||||
* @fn CMP0_Initialize(ARM_Comparator_SignalEvent_t cb_event)
|
||||
* @brief Initialize the Analog Comparator
|
||||
* @param[in] cb_event : Pointer to /ref ARM_Comparator_SignalEvent_t cb_event
|
||||
* @return \ref execution_status
|
||||
*/
|
||||
static int32_t CMP0_Initialize(ARM_Comparator_SignalEvent_t cb_event)
|
||||
{
|
||||
return CMP_Initialize(cb_event, &HSCMP0);
|
||||
}
|
||||
|
||||
/**
|
||||
* @fn int32_t CMP0_Uninitialize(void)
|
||||
* @brief Un-Initialize the Analog Comparator
|
||||
* @return \ref execution_status
|
||||
*/
|
||||
static int32_t CMP0_Uninitialize(void)
|
||||
{
|
||||
return CMP_Uninitialize(&HSCMP0);
|
||||
}
|
||||
|
||||
/**
|
||||
* @fn int32_t CMP0_PowerControl(ARM_POWER_STATE state)
|
||||
* @brief Control CMP Interface Power.
|
||||
* @param[in] state Power state
|
||||
* @return \ref execution_status
|
||||
*/
|
||||
static int32_t CMP0_PowerControl(ARM_POWER_STATE state)
|
||||
{
|
||||
return CMP_PowerControl(state, &HSCMP0);
|
||||
}
|
||||
|
||||
/**
|
||||
* @fn int32_t CMP0_Control(uint32_t control, uint32_t arg)
|
||||
* @brief Control CMP Interface.
|
||||
* @param[in] control operation
|
||||
* @param[in] arg : Argument of operation (optional)
|
||||
* @return \ref execution_status
|
||||
*/
|
||||
static int32_t CMP0_Control(uint32_t control, uint32_t arg)
|
||||
{
|
||||
return CMP_Control(&HSCMP0, control, arg);
|
||||
}
|
||||
|
||||
/**
|
||||
* @fn int32_t CMP0_Start(void)
|
||||
* @brief Enable CMP interface
|
||||
* @return \ref execution_status
|
||||
*/
|
||||
static int32_t CMP0_Start(void)
|
||||
{
|
||||
return CMP_Start(&HSCMP0);
|
||||
}
|
||||
|
||||
/**
|
||||
* @fn int32_t CMP0_Stop(void)
|
||||
* @brief Disable CMP interface
|
||||
* @return \ref execution_status
|
||||
*/
|
||||
static int32_t CMP0_Stop(void)
|
||||
{
|
||||
return CMP_Stop(&HSCMP0);
|
||||
}
|
||||
|
||||
/**
|
||||
* @fn CMP0_IRQHandler(void)
|
||||
* @brief Run the IRQ Handler for CMP0
|
||||
*/
|
||||
void CMP0_IRQHandler(void)
|
||||
{
|
||||
CMP_IRQ_handler(&HSCMP0);
|
||||
}
|
||||
|
||||
extern ARM_DRIVER_CMP Driver_CMP0;
|
||||
ARM_DRIVER_CMP Driver_CMP0 =
|
||||
{
|
||||
CMP_GetVersion,
|
||||
CMP_GetCapabilities,
|
||||
CMP0_Initialize,
|
||||
CMP0_Uninitialize,
|
||||
CMP0_PowerControl,
|
||||
CMP0_Control,
|
||||
CMP0_Start,
|
||||
CMP0_Stop
|
||||
};
|
||||
|
||||
#endif
|
||||
|
||||
/* HSCMP1 driver instance */
|
||||
#if(RTE_HSCMP1)
|
||||
|
||||
/* Comparator Configurations */
|
||||
static CMP_RESOURCES HSCMP1 = {
|
||||
.cb_event = NULL,
|
||||
.regs = (CMP_Type *)CMP1_BASE,
|
||||
.drv_instance = CMP_INSTANCE_1,
|
||||
.state = {0},
|
||||
.irq_num = (IRQn_Type)CMP1_IRQ_IRQn,
|
||||
.config = (RTE_CMP1_SEL_POSITIVE << 7) |
|
||||
(RTE_CMP1_SEL_NEGATIVE << 9) |
|
||||
(RTE_CMP1_SEL_HYSTERISIS << 11),
|
||||
.irq_priority = RTE_CMP1_IRQ_PRIORITY
|
||||
};
|
||||
|
||||
/**
|
||||
* @fn CMP1_Initialize(ARM_Comparator_SignalEvent_t cb_event)
|
||||
* @brief Initialize the Analog Comparator
|
||||
* @param[in] cb_event : Pointer to /ref ARM_Comparator_SignalEvent_t cb_event
|
||||
* @return \ref execution_status
|
||||
*/
|
||||
static int32_t CMP1_Initialize(ARM_Comparator_SignalEvent_t cb_event)
|
||||
{
|
||||
return CMP_Initialize(cb_event, &HSCMP1);
|
||||
}
|
||||
|
||||
/**
|
||||
* @fn int32_t CMP1_Uninitialize(void)
|
||||
* @brief Un-Initialize the Analog Comparator
|
||||
* @return \ref execution_status
|
||||
*/
|
||||
static int32_t CMP1_Uninitialize(void)
|
||||
{
|
||||
return CMP_Uninitialize(&HSCMP1);
|
||||
}
|
||||
|
||||
/**
|
||||
* @fn int32_t CMP1_PowerControl(ARM_POWER_STATE state)
|
||||
* @brief Control CMP Interface Power.
|
||||
* @param[in] state Power state
|
||||
* @return \ref execution_status
|
||||
*/
|
||||
static int32_t CMP1_PowerControl(ARM_POWER_STATE state)
|
||||
{
|
||||
return CMP_PowerControl(state, &HSCMP1);
|
||||
}
|
||||
|
||||
/**
|
||||
* @fn int32_t CMP1_Control(uint32_t control, uint32_t arg)
|
||||
* @brief Control CMP Interface.
|
||||
* @param[in] control operation
|
||||
* @param[in] arg : Argument of operation (optional)
|
||||
* @return \ref execution_status
|
||||
*/
|
||||
static int32_t CMP1_Control(uint32_t control, uint32_t arg)
|
||||
{
|
||||
return CMP_Control(&HSCMP1, control, arg);
|
||||
}
|
||||
|
||||
/**
|
||||
* @fn int32_t CMP1_Start(void)
|
||||
* @brief Enable CMP interface
|
||||
* @return \ref execution_status
|
||||
*/
|
||||
static int32_t CMP1_Start(void)
|
||||
{
|
||||
return CMP_Start(&HSCMP1);
|
||||
}
|
||||
|
||||
/**
|
||||
* @fn int32_t CMP1_Stop(void)
|
||||
* @brief Disable CMP interface
|
||||
* @return \ref execution_status
|
||||
*/
|
||||
static int32_t CMP1_Stop(void)
|
||||
{
|
||||
return CMP_Stop(&HSCMP1);
|
||||
}
|
||||
|
||||
/**
|
||||
* @fn CMP1_IRQHandler(void)
|
||||
* @brief Run the IRQ Handler for CMP1
|
||||
*/
|
||||
void CMP1_IRQHandler (void)
|
||||
{
|
||||
CMP_IRQ_handler(&HSCMP1);
|
||||
}
|
||||
|
||||
extern ARM_DRIVER_CMP Driver_CMP1;
|
||||
ARM_DRIVER_CMP Driver_CMP1 =
|
||||
{
|
||||
CMP_GetVersion,
|
||||
CMP_GetCapabilities,
|
||||
CMP1_Initialize,
|
||||
CMP1_Uninitialize,
|
||||
CMP1_PowerControl,
|
||||
CMP1_Control,
|
||||
CMP1_Start,
|
||||
CMP1_Stop
|
||||
};
|
||||
|
||||
#endif
|
||||
|
||||
/* HSCMP2 driver instance */
|
||||
#if(RTE_HSCMP2)
|
||||
|
||||
/* Comparator Configurations */
|
||||
static CMP_RESOURCES HSCMP2 = {
|
||||
.cb_event = NULL,
|
||||
.regs = (CMP_Type *)CMP2_BASE,
|
||||
.drv_instance = CMP_INSTANCE_2,
|
||||
.state = {0},
|
||||
.irq_num = (IRQn_Type)CMP2_IRQ_IRQn,
|
||||
.config = (RTE_CMP2_SEL_POSITIVE << 14) |
|
||||
(RTE_CMP2_SEL_NEGATIVE << 16) |
|
||||
(RTE_CMP2_SEL_HYSTERISIS << 18),
|
||||
.irq_priority = RTE_CMP2_IRQ_PRIORITY
|
||||
};
|
||||
|
||||
/**
|
||||
* @fn int32_t CMP2_Initialize(ARM_Comparator_SignalEvent_t cb_event)
|
||||
* @brief Initialize the Analog Comparator
|
||||
* @param[in] cb_event : Pointer to /ref ARM_Comparator_SignalEvent_t cb_event
|
||||
* @return \ref execution_status
|
||||
*/
|
||||
static int32_t CMP2_Initialize(ARM_Comparator_SignalEvent_t cb_event)
|
||||
{
|
||||
return CMP_Initialize(cb_event, &HSCMP2);
|
||||
}
|
||||
|
||||
/**
|
||||
* @fn int32_t CMP2_Uninitialize(void)
|
||||
* @brief Un-Initialize the Analog Comparator
|
||||
* @return \ref execution_status
|
||||
*/
|
||||
static int32_t CMP2_Uninitialize(void)
|
||||
{
|
||||
return CMP_Uninitialize(&HSCMP2);
|
||||
}
|
||||
|
||||
/**
|
||||
* @fn int32_t CMP2_PowerControl(ARM_POWER_STATE state)
|
||||
* @brief Control CMP Interface Power.
|
||||
* @param[in] state Power state
|
||||
* @return \ref execution_status
|
||||
*/
|
||||
static int32_t CMP2_PowerControl(ARM_POWER_STATE state)
|
||||
{
|
||||
return CMP_PowerControl(state, &HSCMP2);
|
||||
}
|
||||
|
||||
/**
|
||||
* @fn int32_t CMP2_Control(uint32_t control, uint32_t arg)
|
||||
* @brief Control CMP Interface.
|
||||
* @param[in] control operation
|
||||
* @param[in] arg : Argument of operation (optional)
|
||||
* @return \ref execution_status
|
||||
*/
|
||||
static int32_t CMP2_Control(uint32_t control, uint32_t arg)
|
||||
{
|
||||
return CMP_Control(&HSCMP2, control, arg);
|
||||
}
|
||||
|
||||
/**
|
||||
* @fn int32_t CMP2_Start(void)
|
||||
* @brief Enable CMP interface
|
||||
* @return \ref execution_status
|
||||
*/
|
||||
static int32_t CMP2_Start(void)
|
||||
{
|
||||
return (CMP_Start(&HSCMP2));
|
||||
}
|
||||
|
||||
/**
|
||||
* @fn int32_t CMP2_Stop(void)
|
||||
* @brief Disable CMP interface
|
||||
* @return \ref execution_status
|
||||
*/
|
||||
static int32_t CMP2_Stop(void)
|
||||
{
|
||||
return CMP_Stop(&HSCMP2);
|
||||
}
|
||||
|
||||
/**
|
||||
* @fn CMP2_IRQHandler(void)
|
||||
* @brief Run the IRQ Handler for CMP2
|
||||
*/
|
||||
void CMP2_IRQHandler(void)
|
||||
{
|
||||
CMP_IRQ_handler(&HSCMP2);
|
||||
}
|
||||
|
||||
extern ARM_DRIVER_CMP Driver_CMP2;
|
||||
ARM_DRIVER_CMP Driver_CMP2 =
|
||||
{
|
||||
CMP_GetVersion,
|
||||
CMP_GetCapabilities,
|
||||
CMP2_Initialize,
|
||||
CMP2_Uninitialize,
|
||||
CMP2_PowerControl,
|
||||
CMP2_Control,
|
||||
CMP2_Start,
|
||||
CMP2_Stop
|
||||
};
|
||||
|
||||
#endif
|
||||
|
||||
/* HSCMP3 driver instance */
|
||||
#if(RTE_HSCMP3)
|
||||
|
||||
/* Comparator Configurations */
|
||||
static CMP_RESOURCES HSCMP3 = {
|
||||
.cb_event = NULL,
|
||||
.regs = (CMP_Type *)CMP3_BASE,
|
||||
.drv_instance = CMP_INSTANCE_3,
|
||||
.state = {0},
|
||||
.irq_num = (IRQn_Type)CMP3_IRQ_IRQn,
|
||||
.config = (RTE_CMP3_SEL_POSITIVE << 21) |
|
||||
(RTE_CMP3_SEL_NEGATIVE << 23) |
|
||||
(RTE_CMP3_SEL_HYSTERISIS << 25),
|
||||
.irq_priority = RTE_CMP3_IRQ_PRIORITY
|
||||
};
|
||||
|
||||
/**
|
||||
* @fn int32_t CMP3_Initialize(ARM_Comparator_SignalEvent_t cb_event)
|
||||
* @brief Initialize the Analog Comparator
|
||||
* @param[in] cb_event : Pointer to /ref ARM_Comparator_SignalEvent_t cb_event
|
||||
* @return \ref execution_status
|
||||
*/
|
||||
static int32_t CMP3_Initialize(ARM_Comparator_SignalEvent_t cb_event)
|
||||
{
|
||||
return CMP_Initialize(cb_event, &HSCMP3);
|
||||
}
|
||||
|
||||
/**
|
||||
* @fn int32_t CMP3_Uninitialize(void)
|
||||
* @brief Un-Initialize the Analog Comparator
|
||||
* @return \ref execution_status
|
||||
*/
|
||||
static int32_t CMP3_Uninitialize(void)
|
||||
{
|
||||
return CMP_Uninitialize(&HSCMP3);
|
||||
}
|
||||
|
||||
/**
|
||||
* @fn int32_t CMP3_PowerControl(ARM_POWER_STATE state)
|
||||
* @brief Control CMP Interface Power.
|
||||
* @param[in] state Power state
|
||||
* @return \ref execution_status
|
||||
*/
|
||||
static int32_t CMP3_PowerControl(ARM_POWER_STATE state)
|
||||
{
|
||||
return (CMP_PowerControl(state, &HSCMP3));
|
||||
}
|
||||
|
||||
/**
|
||||
* @fn int32_t CMP3_Control(uint32_t control, uint32_t arg)
|
||||
* @brief Control CMP Interface.
|
||||
* @param[in] control operation
|
||||
* @param[in] arg : Argument of operation (optional)
|
||||
* @return \ref execution_status
|
||||
*/
|
||||
static int32_t CMP3_Control(uint32_t control, uint32_t arg)
|
||||
{
|
||||
return CMP_Control(&HSCMP3, control, arg);
|
||||
}
|
||||
|
||||
/**
|
||||
* @fn int32_t CMP3_Start(void)
|
||||
* @brief Enable CMP interface
|
||||
* @return \ref execution_status
|
||||
*/
|
||||
static int32_t CMP3_Start(void)
|
||||
{
|
||||
return CMP_Start(&HSCMP3);
|
||||
}
|
||||
|
||||
/**
|
||||
* @fn int32_t CMP3_Stop(void)
|
||||
* @brief Disable CMP interface
|
||||
* @return \ref execution_status
|
||||
*/
|
||||
static int32_t CMP3_Stop(void)
|
||||
{
|
||||
return CMP_Stop(&HSCMP3);
|
||||
}
|
||||
|
||||
/**
|
||||
* @fn CMP3_IRQHandler(void)
|
||||
* @brief Run the IRQ Handler for CMP3
|
||||
*/
|
||||
void CMP3_IRQHandler(void)
|
||||
{
|
||||
CMP_IRQ_handler(&HSCMP3);
|
||||
}
|
||||
|
||||
extern ARM_DRIVER_CMP Driver_CMP3;
|
||||
ARM_DRIVER_CMP Driver_CMP3 =
|
||||
{
|
||||
CMP_GetVersion,
|
||||
CMP_GetCapabilities,
|
||||
CMP3_Initialize,
|
||||
CMP3_Uninitialize,
|
||||
CMP3_PowerControl,
|
||||
CMP3_Control,
|
||||
CMP3_Start,
|
||||
CMP3_Stop
|
||||
};
|
||||
|
||||
#endif
|
||||
|
||||
/* LPCMP driver instance */
|
||||
#if(RTE_LPCMP)
|
||||
|
||||
/* Comparator Configurations */
|
||||
static CMP_RESOURCES LPCMP = {
|
||||
.cb_event = NULL,
|
||||
.drv_instance = CMP_INSTANCE_LP,
|
||||
.state = {0},
|
||||
.irq_num = (IRQn_Type)LPCMP_IRQ_IRQn,
|
||||
.config = (RTE_LPCMP_SEL_POSITIVE << 25) |
|
||||
(RTE_LPCMP_SEL_NEGATIVE << 27) |
|
||||
(RTE_LPCMP_SEL_HYSTERISIS << 29),
|
||||
.irq_priority = RTE_LPCMP_IRQ_PRIORITY
|
||||
};
|
||||
|
||||
/**
|
||||
* @fn int32_t LPCMP_Initialize(ARM_Comparator_SignalEvent_t cb_event)
|
||||
* @brief Initialize the LPCMP
|
||||
* @param[in] cb_event : Pointer to /ref ARM_Comparator_SignalEvent_t cb_event
|
||||
* @return \ref execution_status
|
||||
*/
|
||||
static int32_t LPCMP_Initialize(ARM_Comparator_SignalEvent_t cb_event)
|
||||
{
|
||||
return CMP_Initialize(cb_event, &LPCMP);
|
||||
}
|
||||
|
||||
/**
|
||||
* @fn int32_t LPCMP_Uninitialize(void)
|
||||
* @brief Un-Initialize the LPCMP
|
||||
* @return \ref execution_status
|
||||
*/
|
||||
static int32_t LPCMP_Uninitialize(void)
|
||||
{
|
||||
return CMP_Uninitialize(&LPCMP);
|
||||
}
|
||||
|
||||
/**
|
||||
* @fn int32_t LPCMP_PowerControl(ARM_POWER_STATE state)
|
||||
* @brief Control LPCMP Interface Power.
|
||||
* @param[in] state Power state
|
||||
* @return \ref execution_status
|
||||
*/
|
||||
static int32_t LPCMP_PowerControl(ARM_POWER_STATE state)
|
||||
{
|
||||
return (CMP_PowerControl(state, &LPCMP));
|
||||
}
|
||||
|
||||
/**
|
||||
* @fn int32_t LPCMP_Control(uint32_t control, uint32_t arg)
|
||||
* @brief No control API is required for LPCMP.
|
||||
* @param[in] control operation
|
||||
* @param[in] arg : Argument of operation (optional)
|
||||
* @return ARM_DRIVER_ERROR
|
||||
*/
|
||||
static int32_t LPCMP_Control(uint32_t control, uint32_t arg)
|
||||
{
|
||||
ARG_UNUSED(control);
|
||||
ARG_UNUSED(arg);
|
||||
return ARM_DRIVER_ERROR;
|
||||
}
|
||||
|
||||
/**
|
||||
* @fn int32_t LPCMP_Start(void)
|
||||
* @brief Enable LPCMP interface
|
||||
* @return \ref execution_status
|
||||
*/
|
||||
static int32_t LPCMP_Start(void)
|
||||
{
|
||||
return CMP_Start(&LPCMP);
|
||||
}
|
||||
|
||||
/**
|
||||
* @fn int32_t LPCMP_Stop(void)
|
||||
* @brief Disable LPCMP interface
|
||||
* @return \ref execution_status
|
||||
*/
|
||||
static int32_t LPCMP_Stop(void)
|
||||
{
|
||||
return CMP_Stop(&LPCMP);
|
||||
}
|
||||
|
||||
/**
|
||||
* @fn LPCMP_IRQHandler(void)
|
||||
* @brief Run the IRQ Handler for LPCMP
|
||||
*/
|
||||
void LPCMP_IRQHandler(void)
|
||||
{
|
||||
CMP_IRQ_handler(&LPCMP);
|
||||
}
|
||||
|
||||
extern ARM_DRIVER_CMP Driver_LPCMP;
|
||||
ARM_DRIVER_CMP Driver_LPCMP =
|
||||
{
|
||||
CMP_GetVersion,
|
||||
CMP_GetCapabilities,
|
||||
LPCMP_Initialize,
|
||||
LPCMP_Uninitialize,
|
||||
LPCMP_PowerControl,
|
||||
LPCMP_Control,
|
||||
LPCMP_Start,
|
||||
LPCMP_Stop
|
||||
};
|
||||
|
||||
#endif
|
||||
56
src/hal/alif/Alif_CMSIS/Source/Driver_CMP_Private.h
Normal file
56
src/hal/alif/Alif_CMSIS/Source/Driver_CMP_Private.h
Normal file
@ -0,0 +1,56 @@
|
||||
/* Copyright (C) 2023 Alif Semiconductor - All Rights Reserved.
|
||||
* Use, distribution and modification of this code is permitted under the
|
||||
* terms stated in the Alif Semiconductor Software License Agreement
|
||||
*
|
||||
* You should have received a copy of the Alif Semiconductor Software
|
||||
* License Agreement with this file. If not, please write to:
|
||||
* contact@alifsemi.com, or visit: https://alifsemi.com/license
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef DRIVER_CMP_PRIVATE_H_
|
||||
#define DRIVER_CMP_PRIVATE_H_
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
/* System includes */
|
||||
#include "RTE_Device.h"
|
||||
#include "RTE_Components.h"
|
||||
#include CMSIS_device_header
|
||||
|
||||
#define CMP_CTRL_BASE CMP0_BASE
|
||||
|
||||
#include "sys_ctrl_cmp.h"
|
||||
|
||||
/**
|
||||
@brief : CMP Driver states
|
||||
*/
|
||||
typedef volatile struct _CMP_DRIVER_STATE {
|
||||
uint32_t initialized : 1; /* Driver Initialized */
|
||||
uint32_t powered : 1; /* Driver powered */
|
||||
uint32_t reserved : 30; /* Reserved */
|
||||
} CMP_DRIVER_STATE;
|
||||
|
||||
/**
|
||||
* struct CMP_RESOURCES: structure representing a Analog comparator device
|
||||
* @regs : Register address of the Comparator
|
||||
* @drv_instance : Driver instance
|
||||
* @state : Comparator driver state
|
||||
* @irq_num : Comparator interrupt number
|
||||
* @config : Comparator configuration information
|
||||
* @irq_priority : Comparator interrupt Priority
|
||||
*/
|
||||
typedef struct _CMP_RESOURCES{
|
||||
ARM_Comparator_SignalEvent_t cb_event; /* Comparator application event callback */
|
||||
CMP_Type *regs; /* Comparator register base address */
|
||||
CMP_INSTANCE drv_instance; /* Driver instance */
|
||||
CMP_DRIVER_STATE state; /* Comparator Driver state */
|
||||
IRQn_Type irq_num; /* Comparator interrupt number */
|
||||
uint32_t config; /* Comparator configuration information */
|
||||
uint32_t irq_priority; /* Comparator interrupt Priority */
|
||||
}CMP_RESOURCES;
|
||||
|
||||
#endif /* DRIVER_CMP_PRIVATE_H_ */
|
||||
895
src/hal/alif/Alif_CMSIS/Source/Driver_CPI.c
Normal file
895
src/hal/alif/Alif_CMSIS/Source/Driver_CPI.c
Normal file
@ -0,0 +1,895 @@
|
||||
/* Copyright (C) 2023 Alif Semiconductor - All Rights Reserved.
|
||||
* Use, distribution and modification of this code is permitted under the
|
||||
* terms stated in the Alif Semiconductor Software License Agreement
|
||||
*
|
||||
* You should have received a copy of the Alif Semiconductor Software
|
||||
* License Agreement with this file. If not, please write to:
|
||||
* contact@alifsemi.com, or visit: https://alifsemi.com/license
|
||||
*
|
||||
*/
|
||||
|
||||
/**************************************************************************//**
|
||||
* @file Driver_CPI.c
|
||||
* @author Tanay Rami and Chandra Bhushan Singh
|
||||
* @email tanay@alifsemi.com and chandrabhushan.singh@alifsemi.com
|
||||
* @version V1.0.0
|
||||
* @date 27-March-2023
|
||||
* @brief CMSIS-Driver for Camera Controller
|
||||
* @bug None.
|
||||
* @Note None.
|
||||
******************************************************************************/
|
||||
|
||||
/* System Includes */
|
||||
#include "RTE_Device.h"
|
||||
|
||||
/* Project Includes */
|
||||
#include "Camera_Sensor.h"
|
||||
|
||||
/* CPI Includes */
|
||||
#include "cpi.h"
|
||||
#include "Driver_CPI_Private.h"
|
||||
|
||||
/* CMSIS CPI driver Includes */
|
||||
#include "Driver_CPI.h"
|
||||
|
||||
#if !(RTE_CPI || RTE_LPCPI)
|
||||
#error "CAMERA is not enabled in the RTE_Device.h"
|
||||
#endif
|
||||
|
||||
#if !defined(RTE_Drivers_CPI)
|
||||
#error "CAMERA not configured in RTE_Components.h!"
|
||||
#endif
|
||||
|
||||
#if (RTE_MIPI_CSI2)
|
||||
#include "Driver_MIPI_CSI2.h"
|
||||
extern ARM_DRIVER_MIPI_CSI2 Driver_MIPI_CSI2;
|
||||
|
||||
/**
|
||||
\fn void ARM_MIPI_CSI2_Event_Callback (uint32_t int_event)
|
||||
\brief Signal MIPI CSI2 Events.
|
||||
\param[in] int_event \ref MIPI CSI2 event types.
|
||||
\return none.
|
||||
*/
|
||||
void ARM_MIPI_CSI2_Event_Callback (uint32_t int_event);
|
||||
#endif
|
||||
|
||||
#define ARM_CPI_DRV_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(1, 0) /* driver version */
|
||||
|
||||
/* Driver Version */
|
||||
static const ARM_DRIVER_VERSION DriverVersion = {
|
||||
ARM_CPI_API_VERSION,
|
||||
ARM_CPI_DRV_VERSION
|
||||
};
|
||||
|
||||
/* Driver Capabilities */
|
||||
static const ARM_CPI_CAPABILITIES DriverCapabilities = {
|
||||
1, /* Supports CPI Snapshot mode,
|
||||
In this mode CPI will capture one frame
|
||||
then it gets stop. */
|
||||
1, /* Supports CPI video mode,
|
||||
In this mode CPI will capture frame
|
||||
continuously. */
|
||||
0 /* Reserved (must be zero) */
|
||||
};
|
||||
|
||||
/**
|
||||
\fn ARM_DRIVER_VERSION CPI_GetVersion(void)
|
||||
\brief get Camera version
|
||||
\return driver version
|
||||
*/
|
||||
static ARM_DRIVER_VERSION CPI_GetVersion(void)
|
||||
{
|
||||
return DriverVersion;
|
||||
}
|
||||
|
||||
/**
|
||||
\fn ARM_CPI_CAPABILITIES CPI_GetCapabilities(void)
|
||||
\brief get CPI capabilites
|
||||
\return driver capabilites
|
||||
*/
|
||||
static ARM_CPI_CAPABILITIES CPI_GetCapabilities(void)
|
||||
{
|
||||
return DriverCapabilities;
|
||||
}
|
||||
|
||||
/**
|
||||
\fn int32_t CPIx_Initialize(CPI_RESOURCES *CPI, CAMERA_SENSOR_DEVICE *cam_sensor,
|
||||
ARM_CPI_SignalEvent_t cb_event)
|
||||
\brief Initialize Camera Sensor and CPI.
|
||||
this function will
|
||||
- set the user callback event
|
||||
- call Camera Sensor initialize
|
||||
- if MIPI CSI is enabled, call CSI initialize
|
||||
\param[in] CPI Pointer to CPI resources structure
|
||||
\param[in] cam_sensor Pointer to Camera Sensor Device resources structure
|
||||
\param[in] cb_event Pointer to Camera Event \ref ARM_CAMERA_CONTROLLER_SignalEvent_t
|
||||
\return \ref execution_status
|
||||
*/
|
||||
static int32_t CPIx_Initialize(CPI_RESOURCES *CPI, CAMERA_SENSOR_DEVICE *cam_sensor,
|
||||
ARM_CPI_SignalEvent_t cb_event)
|
||||
{
|
||||
int32_t ret = ARM_DRIVER_OK;
|
||||
|
||||
if(cam_sensor == NULL)
|
||||
{
|
||||
return ARM_DRIVER_ERROR_PARAMETER;
|
||||
}
|
||||
|
||||
if (CPI->status.initialized == 1)
|
||||
{
|
||||
/* Driver is already initialized */
|
||||
return ARM_DRIVER_OK;
|
||||
}
|
||||
|
||||
if (!cb_event)
|
||||
{
|
||||
return ARM_DRIVER_ERROR_PARAMETER;
|
||||
}
|
||||
|
||||
/* Set the user callback event. */
|
||||
CPI->cb_event = cb_event;
|
||||
|
||||
/* Call Camera Sensor specific init */
|
||||
ret = cam_sensor->ops->Init();
|
||||
if(ret != ARM_DRIVER_OK)
|
||||
{
|
||||
return ret;
|
||||
}
|
||||
|
||||
#if (RTE_MIPI_CSI2)
|
||||
/*Initializing MIPI CSI2 if the sensor is MIPI CSI2 sensor*/
|
||||
ret = Driver_MIPI_CSI2.Initialize(ARM_MIPI_CSI2_Event_Callback);
|
||||
if(ret != ARM_DRIVER_OK)
|
||||
{
|
||||
return ret;
|
||||
}
|
||||
#endif
|
||||
|
||||
if(!cam_sensor->cpi_info)
|
||||
{
|
||||
return ARM_DRIVER_ERROR_PARAMETER;
|
||||
}
|
||||
|
||||
/* CPI Frame Configuration. */
|
||||
CPI->cnfg->frame.width = cam_sensor->width;
|
||||
CPI->cnfg->frame.height = cam_sensor->height;
|
||||
|
||||
/* Set the driver flag as initialized. */
|
||||
CPI->status.initialized = 1;
|
||||
|
||||
return ARM_DRIVER_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
\fn int32_t CPIx_Uninitialize(CPI_RESOURCES *CPI, CAMERA_SENSOR_DEVICE *camera_sensor)
|
||||
\brief Un-Initialize Camera Sensor and CPI.
|
||||
- Un-initialize Camera Sensor
|
||||
- If MIPI CSI is enabled, call CSI uninitialize
|
||||
\param[in] CPI Pointer to CPI resources structure
|
||||
\param[in] cam_sensor Pointer to Camera Sensor Device resources structure
|
||||
\return \ref execution_status
|
||||
*/
|
||||
static int32_t CPIx_Uninitialize(CPI_RESOURCES *CPI, CAMERA_SENSOR_DEVICE *camera_sensor)
|
||||
{
|
||||
int32_t ret = ARM_DRIVER_OK;
|
||||
|
||||
if (CPI->status.initialized == 0)
|
||||
{
|
||||
/* Driver is uninitialized */
|
||||
return ARM_DRIVER_OK;
|
||||
}
|
||||
|
||||
if (CPI->status.powered == 1)
|
||||
{
|
||||
/* Driver is not powered off */
|
||||
return ARM_DRIVER_ERROR;
|
||||
}
|
||||
|
||||
/* Call Camera Sensor specific uninit */
|
||||
camera_sensor->ops->Uninit();
|
||||
|
||||
#if (RTE_MIPI_CSI2)
|
||||
/*Uninitializing MIPI CSI2 if the sensor is MIPI CSI2 sensor*/
|
||||
ret = Driver_MIPI_CSI2.Uninitialize();
|
||||
if(ret != ARM_DRIVER_OK)
|
||||
{
|
||||
return ret;
|
||||
}
|
||||
#endif
|
||||
/* Reset driver flags. */
|
||||
CPI->status.initialized = 0;
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/**
|
||||
\fn int32_t CPIx_PowerControl(CPI_RESOURCES *CPI, ARM_POWER_STATE state)
|
||||
\brief Camera power control.
|
||||
\param[in] CPI Pointer to CPI resources structure
|
||||
\param[in] state Power state
|
||||
\return \ref execution_status
|
||||
*/
|
||||
static int32_t CPIx_PowerControl(CPI_RESOURCES *CPI, ARM_POWER_STATE state)
|
||||
{
|
||||
int32_t ret = ARM_DRIVER_OK;
|
||||
|
||||
if (CPI->status.initialized == 0)
|
||||
{
|
||||
/* Driver is not initialized */
|
||||
return ARM_DRIVER_ERROR;
|
||||
}
|
||||
|
||||
switch (state)
|
||||
{
|
||||
case ARM_POWER_OFF:
|
||||
{
|
||||
if (CPI->status.powered == 0)
|
||||
{
|
||||
/* Driver is already powered off */
|
||||
return ARM_DRIVER_OK;
|
||||
}
|
||||
|
||||
/* Disable Camera IRQ */
|
||||
NVIC_DisableIRQ(CPI->irq_num);
|
||||
|
||||
/* Clear Any Pending Camera IRQ */
|
||||
NVIC_ClearPendingIRQ(CPI->irq_num);
|
||||
|
||||
if(CPI->drv_instance == CPI_INSTANCE_CPI0)
|
||||
{
|
||||
disable_cpi_periph_clk();
|
||||
}
|
||||
else
|
||||
{
|
||||
disable_lpcpi_periph_clk();
|
||||
}
|
||||
|
||||
#if (RTE_MIPI_CSI2)
|
||||
/*Disable MIPI CSI2*/
|
||||
ret = Driver_MIPI_CSI2.PowerControl(ARM_POWER_OFF);
|
||||
if(ret != ARM_DRIVER_OK)
|
||||
{
|
||||
return ret;
|
||||
}
|
||||
#endif
|
||||
|
||||
/* Reset the power status of Camera. */
|
||||
CPI->status.powered = 0;
|
||||
break;
|
||||
}
|
||||
|
||||
case ARM_POWER_FULL:
|
||||
{
|
||||
if (CPI->status.powered == 1)
|
||||
{
|
||||
/* Driver is already powered ON */
|
||||
return ARM_DRIVER_OK;
|
||||
}
|
||||
|
||||
if(CPI->drv_instance == CPI_INSTANCE_CPI0)
|
||||
{
|
||||
enable_cpi_periph_clk();
|
||||
}
|
||||
else
|
||||
{
|
||||
enable_lpcpi_periph_clk();
|
||||
}
|
||||
|
||||
/* Disable CPI Interrupt. */
|
||||
cpi_disable_interrupt(CPI->regs, CAM_INTR_STOP | CAM_INTR_HSYNC | CAM_INTR_VSYNC |
|
||||
CAM_INTR_INFIFO_OVERRUN | CAM_INTR_OUTFIFO_OVERRUN |
|
||||
CAM_INTR_BRESP_ERR);
|
||||
|
||||
/* Enable Camera IRQ */
|
||||
NVIC_ClearPendingIRQ(CPI->irq_num);
|
||||
NVIC_SetPriority(CPI->irq_num, CPI->irq_priority);
|
||||
NVIC_EnableIRQ(CPI->irq_num);
|
||||
|
||||
#if (RTE_MIPI_CSI2)
|
||||
/*Enable MIPI CSI2*/
|
||||
ret = Driver_MIPI_CSI2.PowerControl(ARM_POWER_FULL);
|
||||
if(ret != ARM_DRIVER_OK)
|
||||
{
|
||||
return ret;
|
||||
}
|
||||
#endif
|
||||
|
||||
/* Set the power flag enabled */
|
||||
CPI->status.powered = 1;
|
||||
break;
|
||||
}
|
||||
|
||||
case ARM_POWER_LOW:
|
||||
|
||||
default:
|
||||
{
|
||||
return ARM_DRIVER_ERROR_UNSUPPORTED;
|
||||
}
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/**
|
||||
\fn int32_t CPI_StartCapture(CPI_RESOURCES *CPI)
|
||||
\brief Start CPI
|
||||
This function will
|
||||
- check CPI capture status
|
||||
- set frame buffer start address
|
||||
- start capture in Snapshot /video mode.
|
||||
-clear control register
|
||||
-activate software reset
|
||||
-clear control register
|
||||
-enable snapshot or video mode with FIFO clock source selection
|
||||
and start capture
|
||||
\param[in] CPI Pointer to CPI resources structure
|
||||
\return \ref execution_status
|
||||
*/
|
||||
static int32_t CPI_StartCapture(CPI_RESOURCES *CPI)
|
||||
{
|
||||
/* Check CPI is busy in capturing? */
|
||||
if(cpi_get_capture_status(CPI->regs) != CPI_VIDEO_CAPTURE_STATUS_NOT_CAPTURING)
|
||||
{
|
||||
return ARM_DRIVER_ERROR_BUSY;
|
||||
}
|
||||
|
||||
/* Set Frame Buffer Start Address Register */
|
||||
cpi_set_framebuff_start_addr(CPI->regs, CPI->cnfg->framebuff_saddr);
|
||||
|
||||
/* Start Camera Capture in Snapshot mode/continuous capture mode */
|
||||
cpi_start_capture(CPI->regs, CPI->capture_mode);
|
||||
|
||||
return ARM_DRIVER_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
\fn int32_t CPI_StopCapture(CPI_RESOURCES *CPI)
|
||||
\brief Stop CPI
|
||||
This function will
|
||||
- disable CPI interrupt.
|
||||
- clear control register to stop capturing.
|
||||
\param[in] CPI Pointer to CPI resources structure
|
||||
\return \ref execution_status
|
||||
*/
|
||||
static int32_t CPI_StopCapture(CPI_RESOURCES *CPI)
|
||||
{
|
||||
/* Disable CPI Interrupt. */
|
||||
cpi_disable_interrupt(CPI->regs, CAM_INTR_STOP | CAM_INTR_HSYNC | CAM_INTR_VSYNC |
|
||||
CAM_INTR_INFIFO_OVERRUN | CAM_INTR_OUTFIFO_OVERRUN |
|
||||
CAM_INTR_BRESP_ERR);
|
||||
|
||||
/* Stop Clear CPI control */
|
||||
cpi_stop_capture(CPI->regs);
|
||||
|
||||
return ARM_DRIVER_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
\fn int32_t CPIx_Capture(CPI_RESOURCES *CPI, CAMERA_SENSOR_DEVICE *camera_sensor,
|
||||
void *framebuffer_startaddr,
|
||||
CPI_MODE_SELECT mode
|
||||
\brief Start Camera Sensor and CPI (in Snapshot mode or video mode).
|
||||
In Snapshot mode, CPI will capture one frame then it gets stop.
|
||||
In Video mode, CPI will capture video data continuously.
|
||||
This function will
|
||||
- call Camera Sensor Start
|
||||
- set frame buffer start address in CPI
|
||||
- set CPI Capture mode as Snapshot mode or video mode.
|
||||
- start capturing
|
||||
\param[in] CPI Pointer to CPI resources structure
|
||||
\param[in] cam_sensor Pointer to Camera Sensor Device resources structure
|
||||
\param[in] framebuffer_startaddr Pointer to frame buffer start address,
|
||||
where camera captured image will be stored.
|
||||
/param[in] mode 0: Capture video frames continuously
|
||||
1: Capture one frame and stop
|
||||
\return \ref execution_status
|
||||
*/
|
||||
static int32_t CPIx_Capture(CPI_RESOURCES *CPI, CAMERA_SENSOR_DEVICE *camera_sensor,
|
||||
void *framebuffer_startaddr,
|
||||
CPI_MODE_SELECT mode)
|
||||
{
|
||||
int32_t ret = ARM_DRIVER_OK;
|
||||
|
||||
if(CPI->status.sensor_configured == 0)
|
||||
{
|
||||
return ARM_DRIVER_ERROR;
|
||||
}
|
||||
|
||||
if(!framebuffer_startaddr)
|
||||
{
|
||||
return ARM_DRIVER_ERROR_PARAMETER;
|
||||
}
|
||||
|
||||
/* Check CPI is busy in capturing? */
|
||||
if(cpi_get_capture_status(CPI->regs) != CPI_VIDEO_CAPTURE_STATUS_NOT_CAPTURING)
|
||||
{
|
||||
return ARM_DRIVER_ERROR_BUSY;
|
||||
}
|
||||
|
||||
#if (RTE_MIPI_CSI2)
|
||||
ret = Driver_MIPI_CSI2.StartIPI();
|
||||
if(ret != ARM_DRIVER_OK)
|
||||
{
|
||||
return ret;
|
||||
}
|
||||
#endif
|
||||
|
||||
/* Call Camera Sensor specific Start */
|
||||
ret = camera_sensor->ops->Start();
|
||||
if(ret != ARM_DRIVER_OK)
|
||||
{
|
||||
goto Error_Stop_CSI;
|
||||
}
|
||||
|
||||
/* Update Frame Buffer Start Address */
|
||||
CPI->cnfg->framebuff_saddr = LocalToGlobal(framebuffer_startaddr);
|
||||
|
||||
/* Set capture mode */
|
||||
CPI->capture_mode = mode;
|
||||
|
||||
/* CPI start capturing */
|
||||
ret = CPI_StartCapture(CPI);
|
||||
if(ret != ARM_DRIVER_OK)
|
||||
{
|
||||
goto Error_Stop_Camera_Sensor;
|
||||
}
|
||||
|
||||
return ARM_DRIVER_OK;
|
||||
|
||||
Error_Stop_Camera_Sensor:
|
||||
/* Stop CPI */
|
||||
ret = camera_sensor->ops->Stop();
|
||||
if(ret != ARM_DRIVER_OK)
|
||||
{
|
||||
return ret;
|
||||
}
|
||||
|
||||
Error_Stop_CSI:
|
||||
#if (RTE_MIPI_CSI2)
|
||||
/*Stop MIPI CSI2 IPI interface*/
|
||||
ret = Driver_MIPI_CSI2.StopIPI();
|
||||
if(ret != ARM_DRIVER_OK)
|
||||
{
|
||||
return ret;
|
||||
}
|
||||
#endif
|
||||
|
||||
return ARM_DRIVER_ERROR;
|
||||
}
|
||||
|
||||
/**
|
||||
\fn int32_t CPIx_Stop(CPI_RESOURCES *CPI, CAMERA_SENSOR_DEVICE *cam_sensor)
|
||||
\brief Stop Camera Sensor and CPI.
|
||||
\param[in] CPI Pointer to CPI resources structure
|
||||
\param[in] cam_sensor Pointer to Camera Sensor Device resources structure
|
||||
\return \ref execution_status
|
||||
*/
|
||||
static int32_t CPIx_Stop(CPI_RESOURCES *CPI, CAMERA_SENSOR_DEVICE *camera_sensor)
|
||||
{
|
||||
int32_t ret = ARM_DRIVER_OK;
|
||||
|
||||
/* Call Camera Sensor specific Stop */
|
||||
ret = camera_sensor->ops->Stop();
|
||||
if(ret != ARM_DRIVER_OK)
|
||||
{
|
||||
return ret;
|
||||
}
|
||||
|
||||
#if (RTE_MIPI_CSI2)
|
||||
/*Stop MIPI CSI2 IPI interface*/
|
||||
ret = Driver_MIPI_CSI2.StopIPI();
|
||||
if(ret != ARM_DRIVER_OK)
|
||||
{
|
||||
return ret;
|
||||
}
|
||||
#endif
|
||||
|
||||
/* Stop CPI */
|
||||
ret = CPI_StopCapture(CPI);
|
||||
if(ret != ARM_DRIVER_OK)
|
||||
{
|
||||
return ret;
|
||||
}
|
||||
|
||||
return ARM_DRIVER_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
\fn int32_t CPIx_Control(CPI_RESOURCES *CPI,CAMERA_SENSOR_DEVICE *cam_sensor,
|
||||
uint32_t control, uint32_t arg)
|
||||
\brief Control CPI and Camera Sensor.
|
||||
\param[in] CPI Pointer to CPI resources structure
|
||||
\param[in] cam_sensor Pointer to Camera Sensor Device resources structure
|
||||
\param[in] control Operation
|
||||
\param[in] arg Argument of operation
|
||||
\return \ref execution_status
|
||||
*/
|
||||
static int32_t CPIx_Control(CPI_RESOURCES *CPI, CAMERA_SENSOR_DEVICE *camera_sensor,
|
||||
uint32_t control, uint32_t arg)
|
||||
{
|
||||
int32_t ret = ARM_DRIVER_OK;
|
||||
uint32_t cam_sensor_control = 0;
|
||||
uint32_t irqs = 0;
|
||||
|
||||
if (CPI->status.initialized == 0)
|
||||
{
|
||||
return ARM_DRIVER_ERROR;
|
||||
}
|
||||
|
||||
switch(control)
|
||||
{
|
||||
case CPI_SOFTRESET:
|
||||
{
|
||||
cpi_software_reset(CPI->regs);
|
||||
break;
|
||||
}
|
||||
|
||||
case CPI_CONFIGURE:
|
||||
{
|
||||
/* Set all CPI Configurations. */
|
||||
cpi_cfg_info_t cpi_info;
|
||||
|
||||
if(camera_sensor->interface == CAMERA_SENSOR_INTERFACE_PARALLEL)
|
||||
{
|
||||
cpi_info.sensor_info.interface = CPI_INTERFACE_PARALLEL;
|
||||
}
|
||||
else
|
||||
{
|
||||
cpi_info.sensor_info.interface = CPI_INTERFACE_MIPI_CSI;
|
||||
}
|
||||
|
||||
cpi_info.sensor_info.vsync_wait = camera_sensor->cpi_info->vsync_wait;
|
||||
cpi_info.sensor_info.vsync_mode = camera_sensor->cpi_info->vsync_mode;
|
||||
cpi_info.rw_roundup = CPI->row_roundup;
|
||||
cpi_info.sensor_info.pixelclk_pol = camera_sensor->cpi_info->pixelclk_pol;
|
||||
cpi_info.sensor_info.hsync_pol = camera_sensor->cpi_info->hsync_pol;
|
||||
cpi_info.sensor_info.vsync_pol = camera_sensor->cpi_info->vsync_pol;
|
||||
cpi_info.sensor_info.data_mode = camera_sensor->cpi_info->data_mode;
|
||||
cpi_info.sensor_info.code10on8 = camera_sensor->cpi_info->code10on8;
|
||||
cpi_info.sensor_info.data_endianness = camera_sensor->cpi_info->data_endianness;
|
||||
cpi_info.sensor_info.data_mask = camera_sensor->cpi_info->data_mask;
|
||||
|
||||
cpi_info.fifo_ctrl.wr_wmark = DEFAULT_WRITE_WMARK;
|
||||
cpi_info.fifo_ctrl.rd_wmark = CPI->cnfg->fifo->read_watermark;
|
||||
|
||||
cpi_info.frame_cfg.data = CPI->cnfg->frame.width;
|
||||
cpi_info.frame_cfg.row = (CPI->cnfg->frame.height - 1);
|
||||
|
||||
cpi_info.csi_ipi_color_mode = camera_sensor->cpi_info->csi_mode;
|
||||
|
||||
cpi_set_config(CPI->regs, &cpi_info);
|
||||
|
||||
break;
|
||||
}
|
||||
|
||||
case CPI_CAMERA_SENSOR_CONFIGURE:
|
||||
{
|
||||
/* Camera Sensor configure */
|
||||
cam_sensor_control = 1;
|
||||
break;
|
||||
}
|
||||
|
||||
case CPI_EVENTS_CONFIGURE:
|
||||
{
|
||||
/* Configure and enable CPI interrupt */
|
||||
irqs |= (arg & ARM_CPI_EVENT_CAMERA_CAPTURE_STOPPED) ? CAM_INTR_STOP : 0;
|
||||
irqs |= (arg & ARM_CPI_EVENT_CAMERA_FRAME_VSYNC_DETECTED) ? CAM_INTR_VSYNC : 0;
|
||||
irqs |= (arg & ARM_CPI_EVENT_CAMERA_FRAME_HSYNC_DETECTED) ? CAM_INTR_HSYNC : 0;
|
||||
irqs |= (arg & ARM_CPI_EVENT_ERR_CAMERA_INPUT_FIFO_OVERRUN) ? CAM_INTR_INFIFO_OVERRUN : 0;
|
||||
irqs |= (arg & ARM_CPI_EVENT_ERR_CAMERA_OUTPUT_FIFO_OVERRUN) ? CAM_INTR_OUTFIFO_OVERRUN : 0;
|
||||
irqs |= (arg & ARM_CPI_EVENT_ERR_HARDWARE) ? CAM_INTR_BRESP_ERR : 0;
|
||||
|
||||
cpi_enable_interrupt(CPI->regs, irqs);
|
||||
|
||||
break;
|
||||
}
|
||||
|
||||
case CPI_CAMERA_SENSOR_GAIN:
|
||||
case CPI_CAMERA_SENSOR_AE:
|
||||
case CPI_CAMERA_SENSOR_AE_TARGET_LUMA:
|
||||
{
|
||||
/*Camera sensor controls*/
|
||||
ret = camera_sensor->ops->Control(control, arg);
|
||||
if(ret != ARM_DRIVER_OK)
|
||||
{
|
||||
return ret;
|
||||
}
|
||||
break;
|
||||
}
|
||||
|
||||
default:
|
||||
{
|
||||
return ARM_DRIVER_ERROR_UNSUPPORTED;
|
||||
}
|
||||
}
|
||||
|
||||
/* Call Camera Sensor specific Control if required. */
|
||||
if(cam_sensor_control)
|
||||
{
|
||||
|
||||
#if (RTE_MIPI_CSI2)
|
||||
/*Configure MIPI CSI2 host and IPI interface*/
|
||||
ret = Driver_MIPI_CSI2.ConfigureHost(CSI2_EVENT_PHY_FATAL | CSI2_EVENT_PKT_FATAL | CSI2_EVENT_PHY |
|
||||
CSI2_EVENT_LINE | CSI2_EVENT_IPI_FATAL | CSI2_EVENT_BNDRY_FRAME_FATAL |
|
||||
CSI2_EVENT_SEQ_FRAME_FATAL | CSI2_EVENT_CRC_FRAME_FATAL |
|
||||
CSI2_EVENT_PLD_CRC_FATAL | CSI2_EVENT_DATA_ID | CSI2_EVENT_ECC_CORRECT);
|
||||
if(ret != ARM_DRIVER_OK)
|
||||
{
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = Driver_MIPI_CSI2.ConfigureIPI();
|
||||
if(ret != ARM_DRIVER_OK)
|
||||
{
|
||||
return ret;
|
||||
}
|
||||
#endif
|
||||
|
||||
camera_sensor->ops->Control(control, arg);
|
||||
CPI->status.sensor_configured = 1;
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/**
|
||||
\fn int32_t CPIx_IRQHandler(CPI_RESOURCES *CPI)
|
||||
\brief Camera interrupt handler.
|
||||
This function will
|
||||
- check CPI received interrupt status.
|
||||
- update events based on interrupt status.
|
||||
- call the user callback function if any event occurs.
|
||||
- clear interrupt status.
|
||||
\param[in] CPI Pointer to CPI resources structure
|
||||
\return \ref execution_status
|
||||
*/
|
||||
static void CPIx_IRQHandler(CPI_RESOURCES *CPI)
|
||||
{
|
||||
uint32_t irqs = 0u;
|
||||
uint32_t event = 0U;
|
||||
uint32_t intr_status = 0U;
|
||||
|
||||
intr_status = cpi_get_interrupt_status(CPI->regs);
|
||||
|
||||
/* received capture stop interrupt? */
|
||||
if(intr_status & CAM_INTR_STOP)
|
||||
{
|
||||
irqs |= CAM_INTR_STOP;
|
||||
event |= ARM_CPI_EVENT_CAMERA_CAPTURE_STOPPED;
|
||||
}
|
||||
|
||||
/* received hsync detected interrupt? */
|
||||
if(intr_status & CAM_INTR_HSYNC)
|
||||
{
|
||||
irqs |= CAM_INTR_HSYNC;
|
||||
event |= ARM_CPI_EVENT_CAMERA_FRAME_HSYNC_DETECTED;
|
||||
}
|
||||
|
||||
/* received vsync detected interrupt? */
|
||||
if(intr_status & CAM_INTR_VSYNC)
|
||||
{
|
||||
irqs |= CAM_INTR_VSYNC;
|
||||
event |= ARM_CPI_EVENT_CAMERA_FRAME_VSYNC_DETECTED;
|
||||
}
|
||||
|
||||
/* received fifo over-run interrupt? */
|
||||
if(intr_status & CAM_INTR_INFIFO_OVERRUN)
|
||||
{
|
||||
irqs |= CAM_INTR_INFIFO_OVERRUN;
|
||||
event |= ARM_CPI_EVENT_ERR_CAMERA_INPUT_FIFO_OVERRUN;
|
||||
}
|
||||
|
||||
/* received fifo under-run interrupt? */
|
||||
if(intr_status & CAM_INTR_OUTFIFO_OVERRUN)
|
||||
{
|
||||
irqs |= CAM_INTR_OUTFIFO_OVERRUN;
|
||||
event |= ARM_CPI_EVENT_ERR_CAMERA_OUTPUT_FIFO_OVERRUN;
|
||||
}
|
||||
|
||||
/* received bus error interrupt? */
|
||||
if(intr_status & CAM_INTR_BRESP_ERR)
|
||||
{
|
||||
irqs |= CAM_INTR_BRESP_ERR;
|
||||
event |= ARM_CPI_EVENT_ERR_HARDWARE;
|
||||
}
|
||||
|
||||
/* call the user callback if any event occurs */
|
||||
if ((event != 0U) && (CPI->cb_event != NULL) )
|
||||
{
|
||||
CPI->cb_event(event);
|
||||
}
|
||||
|
||||
/* clear interrupt by writing one(W1C) */
|
||||
cpi_irq_handler_clear_intr_status(CPI->regs, irqs);
|
||||
}
|
||||
|
||||
/* CPI Driver Instance */
|
||||
#if (RTE_CPI)
|
||||
|
||||
/* CPI sensor access structure */
|
||||
static CAMERA_SENSOR_DEVICE *cpi_sensor;
|
||||
|
||||
/* CPI FIFO Water mark Configuration. */
|
||||
static CPI_FIFO_CONFIG fifo_config =
|
||||
{
|
||||
.read_watermark = RTE_CPI_FIFO_READ_WATERMARK,
|
||||
.write_watermark = RTE_CPI_FIFO_WRITE_WATERMARK,
|
||||
};
|
||||
|
||||
/* CPI color code Configuration. */
|
||||
static CPI_CONFIG config =
|
||||
{
|
||||
.fifo = &fifo_config,
|
||||
};
|
||||
|
||||
/* CPI Device Resource */
|
||||
static CPI_RESOURCES CPI_CTRL =
|
||||
{
|
||||
.regs = (CPI_Type *) CPI_BASE,
|
||||
.irq_num = CAM_IRQ_IRQn,
|
||||
.irq_priority = RTE_CPI_IRQ_PRI,
|
||||
.drv_instance = CPI_INSTANCE_CPI0,
|
||||
.row_roundup = RTE_CPI_ROW_ROUNDUP,
|
||||
.cnfg = &config,
|
||||
};
|
||||
|
||||
#if (RTE_MIPI_CSI2)
|
||||
/**
|
||||
\fn void ARM_MIPI_CSI2_Event_Callback (uint32_t int_event)
|
||||
\brief Signal MIPI CSI2 Events.
|
||||
\param[in] int_event \ref MIPI CSI2 event types.
|
||||
\return none.
|
||||
*/
|
||||
void ARM_MIPI_CSI2_Event_Callback (uint32_t int_event)
|
||||
{
|
||||
ARG_UNUSED(int_event);
|
||||
CPI_CTRL.cb_event (ARM_CPI_EVENT_MIPI_CSI2_ERROR);
|
||||
}
|
||||
#endif
|
||||
|
||||
/* wrapper functions for CPI */
|
||||
static int32_t CPI_Initialize(ARM_CPI_SignalEvent_t cb_event)
|
||||
{
|
||||
cpi_sensor = Get_Camera_Sensor();
|
||||
return CPIx_Initialize(&CPI_CTRL, cpi_sensor, cb_event);
|
||||
}
|
||||
|
||||
static int32_t CPI_Uninitialize(void)
|
||||
{
|
||||
return CPIx_Uninitialize(&CPI_CTRL, cpi_sensor);
|
||||
}
|
||||
|
||||
static int32_t CPI_PowerControl(ARM_POWER_STATE state)
|
||||
{
|
||||
return CPIx_PowerControl(&CPI_CTRL, state);
|
||||
}
|
||||
|
||||
static int32_t CPI_CaptureFrame(void *framebuffer_startaddr)
|
||||
{
|
||||
return CPIx_Capture(&CPI_CTRL, cpi_sensor, framebuffer_startaddr, CPI_MODE_SELECT_SNAPSHOT);
|
||||
}
|
||||
|
||||
static int32_t CPI_CaptureVideo(void *framebuffer_startaddr)
|
||||
{
|
||||
return CPIx_Capture(&CPI_CTRL, cpi_sensor, framebuffer_startaddr, CPI_MODE_SELECT_VIDEO);
|
||||
}
|
||||
|
||||
static int32_t CPI_Stop(void)
|
||||
{
|
||||
return CPIx_Stop(&CPI_CTRL, cpi_sensor);
|
||||
}
|
||||
|
||||
static int32_t CPI_Control(uint32_t control, uint32_t arg)
|
||||
{
|
||||
return CPIx_Control(&CPI_CTRL, cpi_sensor, control, arg);
|
||||
}
|
||||
|
||||
void CAM_IRQHandler(void)
|
||||
{
|
||||
CPIx_IRQHandler(&CPI_CTRL);
|
||||
}
|
||||
|
||||
extern ARM_DRIVER_CPI Driver_CPI;
|
||||
ARM_DRIVER_CPI Driver_CPI =
|
||||
{
|
||||
CPI_GetVersion,
|
||||
CPI_GetCapabilities,
|
||||
CPI_Initialize,
|
||||
CPI_Uninitialize,
|
||||
CPI_PowerControl,
|
||||
CPI_CaptureFrame,
|
||||
CPI_CaptureVideo,
|
||||
CPI_Stop,
|
||||
CPI_Control,
|
||||
};
|
||||
|
||||
#endif /* End of RTE_CPI */
|
||||
|
||||
/* LPCPI Driver Instance */
|
||||
#if (RTE_LPCPI)
|
||||
|
||||
/* LPCPI sensor access structure */
|
||||
static CAMERA_SENSOR_DEVICE *lpcpi_sensor;
|
||||
|
||||
/* LPCPI FIFO Water mark Configuration. */
|
||||
static CPI_FIFO_CONFIG fifo_cnfg =
|
||||
{
|
||||
.read_watermark = RTE_LPCPI_FIFO_READ_WATERMARK,
|
||||
.write_watermark = RTE_LPCPI_FIFO_WRITE_WATERMARK,
|
||||
};
|
||||
|
||||
/* LPCPI color code Configuration. */
|
||||
static CPI_CONFIG cnfg =
|
||||
{
|
||||
.fifo = &fifo_cnfg,
|
||||
};
|
||||
|
||||
/* LPCPI Device Resource */
|
||||
static CPI_RESOURCES LPCPI_CTRL =
|
||||
{
|
||||
.regs = (CPI_Type *) LPCPI_BASE,
|
||||
.irq_num = LPCPI_IRQ_IRQn,
|
||||
.irq_priority = RTE_LPCPI_IRQ_PRI,
|
||||
.drv_instance = CPI_INSTANCE_LPCPI,
|
||||
.cnfg = &cnfg,
|
||||
};
|
||||
|
||||
/* wrapper functions for LPCPI */
|
||||
static int32_t LPCPI_Initialize(ARM_CPI_SignalEvent_t cb_event)
|
||||
{
|
||||
lpcpi_sensor = Get_LPCamera_Sensor();
|
||||
return CPIx_Initialize(&LPCPI_CTRL, lpcpi_sensor, cb_event);
|
||||
}
|
||||
|
||||
static int32_t LPCPI_Uninitialize(void)
|
||||
{
|
||||
return CPIx_Uninitialize(&LPCPI_CTRL, lpcpi_sensor);
|
||||
}
|
||||
|
||||
static int32_t LPCPI_PowerControl(ARM_POWER_STATE state)
|
||||
{
|
||||
return CPIx_PowerControl(&LPCPI_CTRL, state);
|
||||
}
|
||||
|
||||
static int32_t LPCPI_CaptureFrame(void *framebuffer_startaddr)
|
||||
{
|
||||
return CPIx_Capture(&LPCPI_CTRL, lpcpi_sensor, framebuffer_startaddr, CPI_MODE_SELECT_SNAPSHOT);
|
||||
}
|
||||
|
||||
static int32_t LPCPI_CaptureVideo(void *framebuffer_startaddr)
|
||||
{
|
||||
return CPIx_Capture(&LPCPI_CTRL, lpcpi_sensor, framebuffer_startaddr, CPI_MODE_SELECT_VIDEO);
|
||||
}
|
||||
|
||||
static int32_t LPCPI_Stop(void)
|
||||
{
|
||||
return CPIx_Stop(&LPCPI_CTRL, lpcpi_sensor);
|
||||
}
|
||||
|
||||
static int32_t LPCPI_Control(uint32_t control, uint32_t arg)
|
||||
{
|
||||
return CPIx_Control(&LPCPI_CTRL, lpcpi_sensor, control, arg);
|
||||
}
|
||||
|
||||
void LPCPI_IRQHandler(void)
|
||||
{
|
||||
CPIx_IRQHandler(&LPCPI_CTRL);
|
||||
}
|
||||
|
||||
extern ARM_DRIVER_CPI Driver_LPCPI;
|
||||
ARM_DRIVER_CPI Driver_LPCPI =
|
||||
{
|
||||
CPI_GetVersion,
|
||||
CPI_GetCapabilities,
|
||||
LPCPI_Initialize,
|
||||
LPCPI_Uninitialize,
|
||||
LPCPI_PowerControl,
|
||||
LPCPI_CaptureFrame,
|
||||
LPCPI_CaptureVideo,
|
||||
LPCPI_Stop,
|
||||
LPCPI_Control,
|
||||
};
|
||||
|
||||
#endif /* End of RTE_LPCPI */
|
||||
|
||||
/************************ (C) COPYRIGHT ALIF SEMICONDUCTOR *****END OF FILE****/
|
||||
96
src/hal/alif/Alif_CMSIS/Source/Driver_CPI_Private.h
Normal file
96
src/hal/alif/Alif_CMSIS/Source/Driver_CPI_Private.h
Normal file
@ -0,0 +1,96 @@
|
||||
/* Copyright (C) 2023 Alif Semiconductor - All Rights Reserved.
|
||||
* Use, distribution and modification of this code is permitted under the
|
||||
* terms stated in the Alif Semiconductor Software License Agreement
|
||||
*
|
||||
* You should have received a copy of the Alif Semiconductor Software
|
||||
* License Agreement with this file. If not, please write to:
|
||||
* contact@alifsemi.com, or visit: https://alifsemi.com/license
|
||||
*
|
||||
*/
|
||||
|
||||
/**************************************************************************//**
|
||||
* @file Driver_CPI_Private.h
|
||||
* @author Chandra Bhushan Singh
|
||||
* @email chandrabhushan.singh@alifsemi.com
|
||||
* @version V1.0.0
|
||||
* @date 27-March-2023
|
||||
* @brief CMSIS Driver Private Header file.
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef DRIVER_CPI_PRIVATE_H_
|
||||
|
||||
#define DRIVER_CPI_PRIVATE_H_
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
#include "RTE_Device.h"
|
||||
#include "RTE_Components.h"
|
||||
#include CMSIS_device_header
|
||||
|
||||
/* Project Includes */
|
||||
#include "Driver_CPI.h"
|
||||
|
||||
#include "cpi.h"
|
||||
|
||||
#include "sys_ctrl_cpi.h"
|
||||
|
||||
/**
|
||||
* enum CPI_INSTANCE.
|
||||
* CPI instances.
|
||||
*/
|
||||
typedef enum _CPI_INSTANCE
|
||||
{
|
||||
CPI_INSTANCE_CPI0, /**< CPI instance as CPI */
|
||||
CPI_INSTANCE_LPCPI /**< CPI instance as LPCPI */
|
||||
} CPI_INSTANCE;
|
||||
|
||||
/** \brief CPI Frame Configuration */
|
||||
typedef struct _CPI_FRAME_CONFIG {
|
||||
uint16_t width; /**< Frame Width(Column) */
|
||||
uint16_t height; /**< Frame Height(Row) */
|
||||
} CPI_FRAME_CONFIG;
|
||||
|
||||
/** \brief CPI FIFO Configuration */
|
||||
typedef struct _CPI_FIFO_CONFIG {
|
||||
uint8_t read_watermark; /**< FIFO Read Water mark 0,1: illegal */
|
||||
uint8_t write_watermark; /**< FIFO Write Water mark 0,1: illegal */
|
||||
} CPI_FIFO_CONFIG;
|
||||
|
||||
/** \brief CPI Configurations */
|
||||
typedef struct _CPI_CONFIG {
|
||||
CPI_FRAME_CONFIG frame; /**< Frame Configuration */
|
||||
uint32_t framebuff_saddr; /**< Frame Buffer Start Address Configuration */
|
||||
CPI_FIFO_CONFIG *fifo; /**< FIFO Configuration */
|
||||
}CPI_CONFIG;
|
||||
|
||||
/** \brief CPI Status */
|
||||
typedef struct CPI_DRIVER_STATE {
|
||||
uint32_t initialized : 1; /**< Driver Initialized */
|
||||
uint32_t powered : 1; /**< Driver powered */
|
||||
uint32_t sensor_configured : 1; /**< Camera sensor configured */
|
||||
uint32_t reserved : 29; /**< Reserved */
|
||||
} CPI_DRIVER_STATE;
|
||||
|
||||
/** \brief CPI Device Resource Structure */
|
||||
typedef struct _CPI_RESOURCES {
|
||||
ARM_CPI_SignalEvent_t cb_event; /**< CPI Application Event Callback */
|
||||
CPI_Type *regs; /**< CPI Register Base Address */
|
||||
CPI_INSTANCE drv_instance; /**< CPI driver instances */
|
||||
CPI_DRIVER_STATE status; /**< CPI Status */
|
||||
uint8_t irq_priority; /**< CPI Interrupt Priority */
|
||||
IRQn_Type irq_num; /**< CPI Interrupt Vector Number */
|
||||
CPI_ROW_ROUNDUP row_roundup; /**< CPI row roundup */
|
||||
CPI_MODE_SELECT capture_mode; /**< CPI capture mode */
|
||||
CPI_CONFIG *cnfg; /**< CPI Configurations */
|
||||
} CPI_RESOURCES;
|
||||
|
||||
#define DEFAULT_WRITE_WMARK 0x18
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* DRIVER_CPI_PRIVATE_H_ */
|
||||
1003
src/hal/alif/Alif_CMSIS/Source/Driver_CRC.c
Normal file
1003
src/hal/alif/Alif_CMSIS/Source/Driver_CRC.c
Normal file
File diff suppressed because it is too large
Load Diff
66
src/hal/alif/Alif_CMSIS/Source/Driver_CRC_Private.h
Normal file
66
src/hal/alif/Alif_CMSIS/Source/Driver_CRC_Private.h
Normal file
@ -0,0 +1,66 @@
|
||||
/* Copyright (C) 2023 Alif Semiconductor - All Rights Reserved.
|
||||
* Use, distribution and modification of this code is permitted under the
|
||||
* terms stated in the Alif Semiconductor Software License Agreement
|
||||
*
|
||||
* You should have received a copy of the Alif Semiconductor Software
|
||||
* License Agreement with this file. If not, please write to:
|
||||
* contact@alifsemi.com, or visit: https://alifsemi.com/license
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef DRIVER_CRC_PRIVATE_H_
|
||||
#define DRIVER_CRC_PRIVATE_H_
|
||||
|
||||
/* System includes */
|
||||
#include "RTE_Device.h"
|
||||
#include "RTE_Components.h"
|
||||
#include CMSIS_device_header
|
||||
|
||||
#if (RTE_CRC0_DMA_ENABLE || RTE_CRC1_DMA_ENABLE)
|
||||
#define CRC_DMA_ENABLE 1
|
||||
#else
|
||||
#define CRC_DMA_ENABLE 0
|
||||
#endif
|
||||
|
||||
#if CRC_DMA_ENABLE
|
||||
#include <DMA_Common.h>
|
||||
#endif
|
||||
|
||||
/* Project includes */
|
||||
#include "crc.h"
|
||||
#include "Driver_CRC.h"
|
||||
|
||||
#define CRC_8_BIT_SIZE 0 /* To select the 8 bit algorithm size */
|
||||
#define CRC_16_BIT_SIZE 1 /* To select the 16 bit algorithm size */
|
||||
#define CRC_32_BIT_SIZE 2 /* To select the 32 bit algorithm size */
|
||||
|
||||
#define CRC_DMA_MIN_TRANSFER_LEN 900
|
||||
/**
|
||||
@brief : CRC Driver states
|
||||
*/
|
||||
typedef volatile struct _CRC_DRIVER_STATE {
|
||||
uint32_t initialized : 1; /* Driver Initialized */
|
||||
uint32_t powered : 1; /* Driver powered */
|
||||
uint32_t reserved : 30; /* Reserved */
|
||||
} CRC_DRIVER_STATE;
|
||||
|
||||
/**
|
||||
@brief : Access structure for the saving the CRC Setting and status
|
||||
*/
|
||||
typedef struct _CRC_RESOURCES
|
||||
{
|
||||
ARM_CRC_SignalEvent_t cb_event; /* CRC application callback event */
|
||||
CRC_Type *regs; /* CRC register address */
|
||||
CRC_DRIVER_STATE state; /* CRC Driver state */
|
||||
uint8_t busy; /* CRC compute busy flag */
|
||||
crc_transfer_t transfer; /* CRC transfer params */
|
||||
#if CRC_DMA_ENABLE
|
||||
const bool dma_enable; /* DMA enable */
|
||||
const uint32_t dma_irq_priority; /* DMA IRQ priority number */
|
||||
ARM_DMA_SignalEvent_t dma_cb; /* CRC DMA Callback */
|
||||
DMA_PERIPHERAL_CONFIG dma_cfg; /* DMA configuration */
|
||||
volatile uint32_t dma_event; /* Result of DMA operation */
|
||||
#endif
|
||||
}CRC_RESOURCES;
|
||||
|
||||
#endif /* DRIVER_CRC_PRIVATE_H_ */
|
||||
114
src/hal/alif/Alif_CMSIS/Source/Driver_CSI_Private.h
Normal file
114
src/hal/alif/Alif_CMSIS/Source/Driver_CSI_Private.h
Normal file
@ -0,0 +1,114 @@
|
||||
/* Copyright (C) 2023 Alif Semiconductor - All Rights Reserved.
|
||||
* Use, distribution and modification of this code is permitted under the
|
||||
* terms stated in the Alif Semiconductor Software License Agreement
|
||||
*
|
||||
* You should have received a copy of the Alif Semiconductor Software
|
||||
* License Agreement with this file. If not, please write to:
|
||||
* contact@alifsemi.com, or visit: https://alifsemi.com/license
|
||||
*
|
||||
*/
|
||||
|
||||
/**************************************************************************//**
|
||||
* @file Driver_CSI_Private.h
|
||||
* @author Chandra Bhushan Singh
|
||||
* @email chandrabhushan.singh@alifsemi.com
|
||||
* @version V1.0.0
|
||||
* @date 12-April-2023
|
||||
* @brief CMSIS Driver private header file.
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef DRIVER_CSI_PRIVATE_H_
|
||||
|
||||
#define DRIVER_CSI_PRIVATE_H_
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
/* System includes */
|
||||
#include "RTE_Device.h"
|
||||
#include "RTE_Components.h"
|
||||
#include CMSIS_device_header
|
||||
|
||||
/* CSI includes */
|
||||
#include "Driver_MIPI_CSI2.h"
|
||||
#include "csi.h"
|
||||
#include "cpi.h"
|
||||
|
||||
/*Helper macro*/
|
||||
#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
|
||||
#define MAX(a, b, c) ((a) <= (b) ? ((b) <= (c) ? (c) : (b)) : ((a) <= (c) ? (c) : (a)))
|
||||
|
||||
/** \brief CSI IPI frame info */
|
||||
typedef struct _CSI_FRAME_INFO
|
||||
{
|
||||
uint32_t hsa_time; /**< CSI IPI Horizontal Synchronism Active Period */
|
||||
uint32_t hbp_time; /**< CSI IPI Horizontal Back Porch Period */
|
||||
uint32_t hsd_time; /**< CSI IPI Horizontal Sync porch delay Period */
|
||||
uint32_t hactive_time; /**< CSI IPI Line Time Count Size */
|
||||
uint32_t vsa_line; /**< CSI IPI Vertical Synchronism Active period */
|
||||
uint32_t vbp_line; /**< CSI IPI Vertical Back Porch period */
|
||||
uint32_t vfp_line; /**< CSI IPI Vertical Front Porch period */
|
||||
uint32_t vactive_line; /**< CSI IPI Vertical Active period */
|
||||
} CSI_FRAME_INFO;
|
||||
|
||||
/** \brief CSI IPI advanced features */
|
||||
typedef struct _CSI_IPI_ADV_INFO
|
||||
{
|
||||
uint8_t sync_evnt_mode; /**< CSI IPI sync event type */
|
||||
uint8_t event_sel; /**< CSI IPI line event select */
|
||||
uint8_t en_embedded; /**< CSI IPI embedded packet */
|
||||
uint8_t en_blanking; /**< CSI IPI blank packet */
|
||||
uint8_t en_null; /**< CSI IPI null packet */
|
||||
uint8_t en_line_start; /**< CSI IPI line start packet */
|
||||
uint8_t en_video; /**< CSI IPI video packet */
|
||||
uint8_t ipi_dt; /**< CSI IPI data to be overwrite */
|
||||
uint8_t ipi_dt_overwrite; /**< CSI IPI data overwrite */
|
||||
} CSI_IPI_ADV_INFO;
|
||||
|
||||
/** \brief CSI IPI info */
|
||||
typedef struct _CSI_IPI_INFO
|
||||
{
|
||||
uint32_t ipi_memflush; /**< CSI IPI memory flush */
|
||||
uint8_t ipi_mode; /**< CSI IPI mode */
|
||||
uint8_t ipi_color_com; /**< CSI IPI color component */
|
||||
CSI_FRAME_INFO *frame_info; /**< CSI frame information */
|
||||
CSI_IPI_ADV_INFO *adv_features; /**< CSI IPI advanced features */
|
||||
} CSI_IPI_INFO;
|
||||
|
||||
/** \brief CSI State */
|
||||
typedef struct _CSI_DRIVER_STATE
|
||||
{
|
||||
uint32_t initialized : 1; /**< CSI Driver Initialized */
|
||||
uint32_t powered : 1; /**< CSI Driver powered */
|
||||
uint32_t csi_configured : 1; /**< CSI configuration(host and IPI) */
|
||||
uint32_t reserved : 29; /**< Reserved */
|
||||
} CSI_DRIVER_STATE;
|
||||
|
||||
/** \brief CSI CPI related data settings */
|
||||
typedef struct _CSI_CPI_DATA_MODE_SETTINGS
|
||||
{
|
||||
CSI_DATA_TYPE data_type; /**< CSI data type */
|
||||
CSI_IPI_COLOR_COM_TYPE ipi_color_com; /**< CSI IPI Color component */
|
||||
CPI_COLOR_MODE_CONFIG cpi_color_mode; /**< CPI CSI color mode */
|
||||
CPI_DATA_MODE cpi_data_mode; /**< CPI Data mode */
|
||||
uint32_t bpp; /**< bits per pixel */
|
||||
} CSI_CPI_DATA_MODE_SETTINGS;
|
||||
|
||||
/** \brief CSI driver resources */
|
||||
typedef struct _CSI_RESOURCES
|
||||
{
|
||||
CSI_Type *regs; /**< CSI Register Base Address */
|
||||
ARM_MIPI_CSI2_SignalEvent_t cb_event; /**< CSI Application Event Callback */
|
||||
CSI_DRIVER_STATE status; /**< CSI Status */
|
||||
CSI_IPI_INFO *ipi_info; /**< CSI IPI information */
|
||||
IRQn_Type irq; /**< CSI Interrupt Vector Number */
|
||||
uint8_t irq_priority; /**< CSI Interrupt Priority */
|
||||
uint8_t pixel_data_type; /**< CSI IPI pixel data type */
|
||||
uint8_t csi_pixclk_div; /**< CSI clock divisor */
|
||||
uint8_t n_lanes; /**< CSI number of lanes select */
|
||||
uint8_t vc_id; /**< CSI virtual channel ID */
|
||||
} CSI_RESOURCES;
|
||||
|
||||
#endif /* DRIVER_CSI_PRIVATE_H_ */
|
||||
473
src/hal/alif/Alif_CMSIS/Source/Driver_DAC.c
Normal file
473
src/hal/alif/Alif_CMSIS/Source/Driver_DAC.c
Normal file
@ -0,0 +1,473 @@
|
||||
/* Copyright (C) 2022 Alif Semiconductor - All Rights Reserved.
|
||||
* Use, distribution and modification of this code is permitted under the
|
||||
* terms stated in the Alif Semiconductor Software License Agreement
|
||||
*
|
||||
* You should have received a copy of the Alif Semiconductor Software
|
||||
* License Agreement with this file. If not, please write to:
|
||||
* contact@alifsemi.com, or visit: https://alifsemi.com/license
|
||||
*
|
||||
*/
|
||||
|
||||
/**************************************************************************//**
|
||||
* @file Driver_DAC.c
|
||||
* @author Nisarga A M
|
||||
* @email nisarga.am@alifsemi.com
|
||||
* @version V1.0.0
|
||||
* @date 22-Feb-2022
|
||||
* @brief DAC(Digital to Analog Converter) driver definitions.DAC0 connected
|
||||
* to P2_2 and DAC1 connected to P2_3.
|
||||
******************************************************************************/
|
||||
|
||||
/* Project Includes */
|
||||
#include "Driver_DAC_Private.h"
|
||||
#include "analog_config.h"
|
||||
|
||||
#if !(RTE_DAC0 || RTE_DAC1)
|
||||
#error "DAC is not enabled in the RTE_device.h"
|
||||
#endif
|
||||
|
||||
#if (defined(RTE_Drivers_DAC0) && !RTE_DAC0)
|
||||
#error "DAC0 not configured in RTE_Device.h!"
|
||||
#endif
|
||||
|
||||
#if (defined(RTE_Drivers_DAC1) && !RTE_DAC1)
|
||||
#error "DAC1 not configured in RTE_Device.h!"
|
||||
#endif
|
||||
|
||||
#define ARM_DAC_DRV_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(1, 0) /* Driver version */
|
||||
|
||||
/*Driver version*/
|
||||
static const ARM_DRIVER_VERSION DriverVersion = {
|
||||
ARM_DAC_API_VERSION,
|
||||
ARM_DAC_DRV_VERSION
|
||||
};
|
||||
|
||||
/*Driver Capabilities */
|
||||
static const ARM_DAC_CAPABILITIES DriverCapabilities = {
|
||||
1,/* 12 bit DAC resolution */
|
||||
0 /* Reserved ( must be ZERO) */
|
||||
};
|
||||
|
||||
/**
|
||||
@fn void analog_config(void)
|
||||
@brief Analog configuration register includes Vbat and comparator
|
||||
@param[in] none
|
||||
@return none
|
||||
*/
|
||||
static void Analog_Config(void)
|
||||
{
|
||||
/* Analog configuration Vbat register2 */
|
||||
analog_config_vbat_reg2();
|
||||
|
||||
/* Analog configuration comparator register2 */
|
||||
analog_config_cmp_reg2();
|
||||
}
|
||||
|
||||
/**
|
||||
@fn ARM_DRIVER_VERSION DAC_GetVersion(void)
|
||||
@brief get DAC version
|
||||
@param none
|
||||
@return driver version
|
||||
*/
|
||||
static ARM_DRIVER_VERSION DAC_GetVersion(void)
|
||||
{
|
||||
return DriverVersion;
|
||||
}
|
||||
|
||||
/**
|
||||
@fn ARM_RTC_CAPABILITIES DAC_GetCapabilities(void)
|
||||
@brief get DAC Capabilites
|
||||
@param none
|
||||
@return driver Capabilites
|
||||
*/
|
||||
static ARM_DAC_CAPABILITIES DAC_GetCapabilities(void)
|
||||
{
|
||||
return DriverCapabilities;
|
||||
}
|
||||
|
||||
/**
|
||||
@fn int32_t DAC_Initialize(DAC_RESOURCES *DAC)
|
||||
@brief Initialize the DAC
|
||||
@param[in] DAC : Pointer to DAC resources
|
||||
@return ARM_DRIVER_ERROR_PARAMETER : if dac parameter is invalid
|
||||
ARM_DRIVER_OK : if dac successfully initialized
|
||||
*/
|
||||
static int32_t DAC_Initialize(DAC_RESOURCES *DAC)
|
||||
{
|
||||
int32_t ret = ARM_DRIVER_OK;
|
||||
|
||||
/* Setting the flag */
|
||||
DAC->flags.initialized = 0x1U;
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/**
|
||||
@fn int32_t DAC_Uninitialize(DAC_RESOURCES *DAC)
|
||||
@brief Un-Initialize the DAC
|
||||
@param[in] DAC : Pointer to DAC resources
|
||||
@return ARM_DRIVER_OK : if dac successfully initialized
|
||||
*/
|
||||
static int32_t DAC_Uninitialize(DAC_RESOURCES *DAC)
|
||||
{
|
||||
int32_t ret = ARM_DRIVER_OK;
|
||||
|
||||
/* Reset the flag */
|
||||
DAC->flags.initialized = 0x0U;
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/**
|
||||
@fn int32_t DAC_PowerControl(ARM_POWER_STATE state,
|
||||
DAC_RESOURCES *DAC)
|
||||
@brief CMSIS-DRIVER DAC power control
|
||||
@param[in] state : Power state
|
||||
@param[in] DAC : Pointer to DAC resources
|
||||
@return ARM_DRIVER_ERROR_PARAMETER : if initialize is not done
|
||||
ARM_DRIVER_OK : if power done successful
|
||||
*/
|
||||
static int32_t DAC_PowerControl(ARM_POWER_STATE state,
|
||||
DAC_RESOURCES *DAC)
|
||||
{
|
||||
if(DAC->flags.initialized == 0x0U)
|
||||
{
|
||||
return ARM_DRIVER_ERROR;
|
||||
}
|
||||
|
||||
switch((int32_t)state)
|
||||
{
|
||||
case ARM_POWER_OFF:
|
||||
|
||||
/* If already powered OFF returns OK*/
|
||||
if(DAC->flags.powered == 0x0U)
|
||||
{
|
||||
return ARM_DRIVER_OK;
|
||||
}
|
||||
|
||||
/* Clear the DAC configuration */
|
||||
dac_clear_config(DAC->regs);
|
||||
|
||||
disable_dac_periph_clk(DAC->instance);
|
||||
|
||||
disable_cmp_periph_clk();
|
||||
|
||||
DAC->flags.powered = 0x0U;
|
||||
break;
|
||||
|
||||
case ARM_POWER_FULL:
|
||||
|
||||
if(DAC->flags.powered == 0x1U)
|
||||
{
|
||||
return ARM_DRIVER_OK;
|
||||
}
|
||||
|
||||
enable_cmp_periph_clk();
|
||||
|
||||
enable_dac_periph_clk(DAC->instance);
|
||||
|
||||
/* Initialization for Analog configuration register */
|
||||
Analog_Config();
|
||||
|
||||
/* DAC Disable */
|
||||
dac_disable(DAC->regs);
|
||||
|
||||
/* DAC reset released */
|
||||
dac_reset_deassert(DAC->regs);
|
||||
|
||||
/* Initialize DAC configuration */
|
||||
dac_set_config(DAC->regs, DAC->input_mux_val, DAC->dac_twoscomp_in);
|
||||
|
||||
DAC->flags.powered = 0x1U;
|
||||
|
||||
break;
|
||||
|
||||
case ARM_POWER_LOW:
|
||||
default:
|
||||
return ARM_DRIVER_ERROR_UNSUPPORTED;
|
||||
}
|
||||
return ARM_DRIVER_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
@fn int32_t DAC_Control(DAC_RESOURCES *DAC, uint32_t control, uint32_t arg)
|
||||
@brief CMSIS-Driver dac control.
|
||||
Control DAC Interface.
|
||||
@param[in] DAC : Pointer to DAC resources
|
||||
@param[in] control : Operation \ref Driver_DAC.h : DAC control codes
|
||||
@param[in] arg : Argument of operation (optional)
|
||||
@return ARM_DRIVER_ERROR_PARAMETER : if dac parameter is invalid
|
||||
ARM_DRIVER_OK : if dac successfully initialized
|
||||
*/
|
||||
static int32_t DAC_Control(DAC_RESOURCES *DAC, uint32_t control, uint32_t arg)
|
||||
{
|
||||
ARG_UNUSED(arg);
|
||||
int32_t ret = ARM_DRIVER_OK;
|
||||
|
||||
if(DAC->flags.powered == 0x0U)
|
||||
{
|
||||
return ARM_DRIVER_ERROR;
|
||||
}
|
||||
|
||||
switch (control)
|
||||
{
|
||||
case ARM_DAC_RESET:
|
||||
|
||||
if (arg)
|
||||
{
|
||||
/* DAC reset asserted */
|
||||
dac_reset_assert(DAC->regs);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* DAC reset released */
|
||||
dac_reset_deassert(DAC->regs);
|
||||
}
|
||||
break;
|
||||
|
||||
case ARM_DAC_INPUT_BYPASS_MODE:
|
||||
|
||||
/* Set DAC input through bypass mode */
|
||||
dac_set_bypass_input(DAC->regs, arg);
|
||||
break;
|
||||
|
||||
case ARM_DAC_SELECT_IBIAS_OUTPUT:
|
||||
|
||||
/* Set DAC output current */
|
||||
dac_set_output_current(DAC->regs, arg);
|
||||
break;
|
||||
|
||||
case ARM_DAC_CAPACITANCE_HP_MODE:
|
||||
|
||||
/* Set capacitance for DAC signal */
|
||||
dac_set_capacitance(DAC->regs, arg);
|
||||
break;
|
||||
|
||||
default:
|
||||
ret = ARM_DRIVER_ERROR_UNSUPPORTED;
|
||||
break;
|
||||
}
|
||||
return ret;
|
||||
}
|
||||
|
||||
/**
|
||||
* @fn DAC_Start (DAC_RESOURCES *DAC)
|
||||
* @brief CMSIS-Driver DAC Start
|
||||
* Enable the DAC.
|
||||
@param[in] DAC : Pointer to DAC resources
|
||||
@return ARM_DRIVER_OK : if dac successfully uninitialized or already not initialized
|
||||
*/
|
||||
static int32_t DAC_Start (DAC_RESOURCES *DAC)
|
||||
{
|
||||
int32_t ret = ARM_DRIVER_OK;
|
||||
|
||||
if(DAC->flags.powered == 0x0U)
|
||||
{
|
||||
return ARM_DRIVER_ERROR;
|
||||
}
|
||||
|
||||
if(DAC->flags.dac_drv_start == 0x1U)
|
||||
{
|
||||
return ARM_DRIVER_OK;
|
||||
}
|
||||
|
||||
/* Enable the DAC */
|
||||
dac_enable(DAC->regs);
|
||||
|
||||
DAC->flags.dac_drv_start = 0x1U;
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/**
|
||||
*@fn DAC_Stop (DAC_RESOURCES *DAC)
|
||||
*@brief CMSIS-Driver DAC Stop
|
||||
Disable the DAC
|
||||
*@param[in] DAC : Pointer to DAC resources
|
||||
*@return ARM_DRIVER_OK : if function return successfully
|
||||
*/
|
||||
static int32_t DAC_Stop (DAC_RESOURCES *DAC)
|
||||
{
|
||||
int32_t ret = ARM_DRIVER_OK;
|
||||
|
||||
if(DAC->flags.powered == 0x0U)
|
||||
{
|
||||
return ARM_DRIVER_ERROR;
|
||||
}
|
||||
|
||||
/* Disable the DAC */
|
||||
dac_disable(DAC->regs);
|
||||
|
||||
DAC->flags.dac_drv_start = 0x0U;
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/**
|
||||
@fn DAC_SetInput(DAC_RESOURCES *DAC, uint32_t value)
|
||||
@brief CMSIS-Driver to set the DAC input.
|
||||
@param[in] Input : Operation
|
||||
@param[in] value : DAC input
|
||||
@param[in] DAC : Pointer to dac resources
|
||||
@return ARM_DRIVER_ERROR_PARAMETER : if parameter are invalid
|
||||
ARM_DRIVER_OK : if the function return successful
|
||||
*/
|
||||
static int32_t DAC_SetInput(DAC_RESOURCES *DAC, uint32_t value)
|
||||
{
|
||||
int32_t ret = ARM_DRIVER_OK;
|
||||
|
||||
if(DAC->flags.dac_drv_start == 0x0U)
|
||||
{
|
||||
/* error:Driver is not started */
|
||||
return ARM_DRIVER_ERROR;
|
||||
}
|
||||
|
||||
/* If bypass mode is not enabled then pass
|
||||
the input through the DAC_IN reg */
|
||||
if(!(dac_input_mux_enabled(DAC->regs)))
|
||||
{
|
||||
/* Set dac input */
|
||||
dac_input(DAC->regs, value);
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/* DAC0 driver instance */
|
||||
#if(RTE_DAC0)
|
||||
|
||||
/* DAC configuration */
|
||||
static DAC_RESOURCES DAC0 = {
|
||||
.regs = (DAC_Type *)DAC120_BASE,
|
||||
.flags = {0},
|
||||
.input_mux_val = (RTE_DAC0_INPUT_BYP_MUX_EN),
|
||||
.dac_twoscomp_in = (RTE_DAC0_TWOSCOMP_EN),
|
||||
.instance = DAC_INSTANCE_0
|
||||
};
|
||||
|
||||
/* Function Name: DAC0_Initialize */
|
||||
static int32_t DAC0_Initialize(void)
|
||||
{
|
||||
return (DAC_Initialize(&DAC0));
|
||||
}
|
||||
|
||||
/* Function Name: DAC0_uninitialize */
|
||||
static int32_t DAC0_Uninitialize(void)
|
||||
{
|
||||
return (DAC_Uninitialize(&DAC0));
|
||||
}
|
||||
|
||||
/* Function Name: DAC0_PowerControl */
|
||||
static int32_t DAC0_PowerControl(ARM_POWER_STATE state)
|
||||
{
|
||||
return (DAC_PowerControl(state, &DAC0));
|
||||
}
|
||||
|
||||
/* Function Name: DAC0_Control */
|
||||
static int32_t DAC0_Control(uint32_t control, uint32_t arg)
|
||||
{
|
||||
return (DAC_Control(&DAC0, control, arg));
|
||||
}
|
||||
|
||||
/* Function Name: DAC0_Start */
|
||||
static int32_t DAC0_Start(void)
|
||||
{
|
||||
return (DAC_Start(&DAC0));
|
||||
}
|
||||
|
||||
/* Function Name: DAC0_Stop */
|
||||
static int32_t DAC0_Stop(void)
|
||||
{
|
||||
return (DAC_Stop(&DAC0));
|
||||
}
|
||||
|
||||
/* Function Name: DAC0_SetInput */
|
||||
static int32_t DAC0_SetInput(uint32_t value)
|
||||
{
|
||||
return (DAC_SetInput(&DAC0, value));
|
||||
}
|
||||
|
||||
extern ARM_DRIVER_DAC Driver_DAC0;
|
||||
ARM_DRIVER_DAC Driver_DAC0 =
|
||||
{
|
||||
DAC_GetVersion,
|
||||
DAC_GetCapabilities,
|
||||
DAC0_Initialize,
|
||||
DAC0_Uninitialize,
|
||||
DAC0_PowerControl,
|
||||
DAC0_Control,
|
||||
DAC0_Start,
|
||||
DAC0_Stop,
|
||||
DAC0_SetInput
|
||||
};
|
||||
|
||||
#endif /*RTE_DAC0 */
|
||||
|
||||
/* DAC1 driver instance */
|
||||
#if(RTE_DAC1)
|
||||
|
||||
/* DAC1 configuration */
|
||||
static DAC_RESOURCES DAC1 = {
|
||||
.regs = (DAC_Type *)DAC121_BASE,
|
||||
.flags = {0},
|
||||
.input_mux_val = (RTE_DAC1_INPUT_BYP_MUX_EN),
|
||||
.dac_twoscomp_in = (RTE_DAC1_TWOSCOMP_EN),
|
||||
.instance = DAC_INSTANCE_1
|
||||
};
|
||||
/* Function Name: DAC1_Initialize */
|
||||
static int32_t DAC1_Initialize(void)
|
||||
{
|
||||
return (DAC_Initialize(&DAC1));
|
||||
}
|
||||
|
||||
/* Function Name: DAC1_uninitialize */
|
||||
static int32_t DAC1_Uninitialize(void)
|
||||
{
|
||||
return (DAC_Uninitialize(&DAC1));
|
||||
}
|
||||
|
||||
/* Function Name: DAC1_PowerControl */
|
||||
static int32_t DAC1_PowerControl(ARM_POWER_STATE state)
|
||||
{
|
||||
return (DAC_PowerControl(state, &DAC1));
|
||||
}
|
||||
|
||||
/* Function Name: DAC1_Control */
|
||||
static int32_t DAC1_Control(uint32_t control, uint32_t arg)
|
||||
{
|
||||
return (DAC_Control(&DAC1, control, arg));
|
||||
}
|
||||
|
||||
/* Function Name: DAC1_Start */
|
||||
static int32_t DAC1_Start(void)
|
||||
{
|
||||
return (DAC_Start(&DAC1));
|
||||
}
|
||||
|
||||
/* Function Name: DAC1_Stop */
|
||||
static int32_t DAC1_Stop(void)
|
||||
{
|
||||
return (DAC_Stop(&DAC1));
|
||||
}
|
||||
|
||||
/* Function Name: DAC1_SetInput */
|
||||
static int32_t DAC1_SetInput(uint32_t value)
|
||||
{
|
||||
return (DAC_SetInput(&DAC1, value));
|
||||
}
|
||||
|
||||
extern ARM_DRIVER_DAC Driver_DAC1;
|
||||
ARM_DRIVER_DAC Driver_DAC1 =
|
||||
{
|
||||
DAC_GetVersion,
|
||||
DAC_GetCapabilities,
|
||||
DAC1_Initialize,
|
||||
DAC1_Uninitialize,
|
||||
DAC1_PowerControl,
|
||||
DAC1_Control,
|
||||
DAC1_Start,
|
||||
DAC1_Stop,
|
||||
DAC1_SetInput
|
||||
};
|
||||
|
||||
#endif /* RTE_DAC1 */
|
||||
58
src/hal/alif/Alif_CMSIS/Source/Driver_DAC_Private.h
Normal file
58
src/hal/alif/Alif_CMSIS/Source/Driver_DAC_Private.h
Normal file
@ -0,0 +1,58 @@
|
||||
/* Copyright (C) 2023 Alif Semiconductor - All Rights Reserved.
|
||||
* Use, distribution and modification of this code is permitted under the
|
||||
* terms stated in the Alif Semiconductor Software License Agreement
|
||||
*
|
||||
* You should have received a copy of the Alif Semiconductor Software
|
||||
* License Agreement with this file. If not, please write to:
|
||||
* contact@alifsemi.com, or visit: https://alifsemi.com/license
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef DRIVER_DAC_PRIVATE_H_
|
||||
#define DRIVER_DAC_PRIVATE_H_
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
/* System includes */
|
||||
#include "RTE_Device.h"
|
||||
#include "RTE_Components.h"
|
||||
#include CMSIS_device_header
|
||||
|
||||
/* Project includes */
|
||||
#include "dac.h"
|
||||
#include "Driver_DAC.h"
|
||||
#include "sys_ctrl_dac.h"
|
||||
|
||||
/**
|
||||
@brief : DAC flags to check the DAC initialization, DAC power done and DAC started.
|
||||
*/
|
||||
typedef struct _DAC_DRIVER_STATE{
|
||||
uint32_t initialized :1; /* Driver Initialized */
|
||||
uint32_t powered :1; /* Driver Powered up */
|
||||
uint32_t dac_drv_start :1; /* Driver is Started */
|
||||
uint32_t reserved :29; /* Reserved */
|
||||
} DAC_DRIVER_STATE;
|
||||
|
||||
/**
|
||||
* struct DAC_RESOURCES: structure representing a DAC device
|
||||
* @regs : Register address of the DAC
|
||||
* @flags : DAC driver flags
|
||||
* @config : DAC configuration information
|
||||
*/
|
||||
typedef struct _DAC_resources
|
||||
{
|
||||
DAC_Type *regs; /* DAC register address */
|
||||
DAC_DRIVER_STATE flags; /* DAC Driver Flags */
|
||||
DAC_INSTANCE instance; /* DAC Driver instance */
|
||||
bool dac_twoscomp_in; /* Convert two's complement to unsigned binary data */
|
||||
uint8_t input_mux_val; /* DAC input data source */
|
||||
}DAC_RESOURCES;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* DRIVER_DAC_PRIVATE_H_ */
|
||||
1997
src/hal/alif/Alif_CMSIS/Source/Driver_DMA.c
Normal file
1997
src/hal/alif/Alif_CMSIS/Source/Driver_DMA.c
Normal file
File diff suppressed because it is too large
Load Diff
69
src/hal/alif/Alif_CMSIS/Source/Driver_DMA_Private.h
Normal file
69
src/hal/alif/Alif_CMSIS/Source/Driver_DMA_Private.h
Normal file
@ -0,0 +1,69 @@
|
||||
/* Copyright (C) 2022 Alif Semiconductor - All Rights Reserved.
|
||||
* Use, distribution and modification of this code is permitted under the
|
||||
* terms stated in the Alif Semiconductor Software License Agreement
|
||||
*
|
||||
* You should have received a copy of the Alif Semiconductor Software
|
||||
* License Agreement with this file. If not, please write to:
|
||||
* contact@alifsemi.com, or visit: https://alifsemi.com/license
|
||||
*
|
||||
*/
|
||||
|
||||
/**************************************************************************//**
|
||||
* @file Driver_DMA_Private.h
|
||||
* @author Sudhir Sreedharan
|
||||
* @email sudhir@alifsemi.com
|
||||
* @version V1.0.0
|
||||
* @date 04-Nov-2020
|
||||
* @brief DMA Driver Private header
|
||||
* @bug None
|
||||
* @Note None
|
||||
******************************************************************************/
|
||||
#ifndef DRIVER_DMA_PRIVATE_H
|
||||
|
||||
#define DRIVER_DMA_PRIVATE_H
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "Driver_DMA.h"
|
||||
#include "RTE_Device.h"
|
||||
#include "RTE_Components.h"
|
||||
#include CMSIS_device_header
|
||||
|
||||
#include <dma_ctrl.h>
|
||||
#include "sys_ctrl_dma.h"
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
/** \brief DMA Driver states. */
|
||||
typedef struct _DMA_DRIVER_STATE {
|
||||
uint32_t initialized : 1; /* Driver Initialized*/
|
||||
uint32_t powered : 1; /* Device powered */
|
||||
uint32_t reserved : 30;/* Reserved */
|
||||
} DMA_DRIVER_STATE;
|
||||
|
||||
typedef union _DMA_DRV_STATUS {
|
||||
uint32_t status; /*!< DMA Driver status */
|
||||
ARM_DMA_STATUS status_b; /*!< DMA Driver status bits */
|
||||
} DMA_DRV_STATUS;
|
||||
|
||||
typedef struct _DMA_RESOURCES {
|
||||
DMA_Type *regs; /*!< DMA register map */
|
||||
ARM_DMA_SignalEvent_t cb_event[DMA_MAX_EVENTS]; /*!< DMA Application Event Callback */
|
||||
dma_config_info_t cfg; /*!< DMA Controller configuration */
|
||||
DMA_SECURE_STATE ns_iface; /*!< DMA interface to be used */
|
||||
DMA_DRV_STATUS drv_status; /*!< DMA Driver Status */
|
||||
DMA_DRIVER_STATE state; /*!< DMA Driver State */
|
||||
uint8_t consumer_cnt; /*!< DMA Consumer Counter */
|
||||
const IRQn_Type irq_start; /*!< DMA irq0 start index */
|
||||
const uint32_t abort_irq_priority; /*!< DMA Abort IRQ priority */
|
||||
const DMA_INSTANCE instance; /*!< DMA controller instance */
|
||||
} DMA_RESOURCES;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* DRIVER_DMA_PRIVATE_H */
|
||||
86
src/hal/alif/Alif_CMSIS/Source/Driver_DSI_Private.h
Normal file
86
src/hal/alif/Alif_CMSIS/Source/Driver_DSI_Private.h
Normal file
@ -0,0 +1,86 @@
|
||||
/* Copyright (C) 2023 Alif Semiconductor - All Rights Reserved.
|
||||
* Use, distribution and modification of this code is permitted under the
|
||||
* terms stated in the Alif Semiconductor Software License Agreement
|
||||
*
|
||||
* You should have received a copy of the Alif Semiconductor Software
|
||||
* License Agreement with this file. If not, please write to:
|
||||
* contact@alifsemi.com, or visit: https://alifsemi.com/license
|
||||
*
|
||||
*/
|
||||
|
||||
/**************************************************************************//**
|
||||
* @file Driver_DSI_Private.h
|
||||
* @author Prasanna Ravi
|
||||
* @email prasanna.ravi@alifsemi.com
|
||||
* @version V1.0.0
|
||||
* @date 17-April-2023
|
||||
* @brief DSI driver Specific Header file.
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef DRIVER_DSI_PRIVATE_H_
|
||||
#define DRIVER_DSI_PRIVATE_H_
|
||||
|
||||
#include "RTE_Components.h"
|
||||
#include CMSIS_device_header
|
||||
|
||||
#include "Driver_MIPI_DSI.h"
|
||||
|
||||
#include "dsi.h"
|
||||
#include "cdc.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
/*Helper macro*/
|
||||
#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
|
||||
|
||||
/** \brief DSI DPHY high speed transition timings */
|
||||
typedef struct _DSI_DPHY_HS_TRANSITION_TIMINGS_RANGE {
|
||||
uint16_t bitrate_mbps; /**< DPHY data rate in mbps */
|
||||
uint16_t clklp2hs_time; /**< DPHY clock lane LP to HS transition time */
|
||||
uint16_t clkhs2lp_time; /**< DPHY clock lane HS to LP transition time */
|
||||
uint16_t lp2hs_time; /**< DPHY data lane LP to HS transition time */
|
||||
uint16_t hs2lp_time; /**< DPHY data lane HS to LP transition time */
|
||||
} DSI_DPHY_HS_TRANSITION_TIMINGS_RANGE;
|
||||
|
||||
/** \brief DSI Driver states. */
|
||||
typedef volatile struct _DSI_DRIVER_STATE {
|
||||
uint32_t initialized : 1; /**< Driver Initialized */
|
||||
uint32_t powered : 1; /**< Driver powered */
|
||||
uint32_t host_configured : 1; /**< Driver host configured */
|
||||
uint32_t dpi_configured : 1; /**< Driver DPI configured */
|
||||
uint32_t panel_initialized : 1; /**< Driver panel initialized */
|
||||
uint32_t reserved : 27; /**< Reserved */
|
||||
} DSI_DRIVER_STATE;
|
||||
|
||||
/** \brief DSI DPI Info */
|
||||
typedef struct _DSI_DPI_INFO{
|
||||
DSI_VIDEO_MODE vid_mode; /**< video mode */
|
||||
uint32_t vid_pkt_size; /**< video packet size */
|
||||
uint32_t vid_num_chunks; /**< video number of chunks */
|
||||
uint32_t vid_null_size; /**< video null packet size */
|
||||
}DSI_DPI_INFO;
|
||||
|
||||
/**
|
||||
\brief MIPI DSI driver info
|
||||
*/
|
||||
typedef struct _DSI_RESOURCES{
|
||||
DSI_Type *reg_base; /**< Pointer to regs */
|
||||
ARM_MIPI_DSI_SignalEvent_t cb_event; /**< Pointer to call back function */
|
||||
uint32_t frequency; /**< DSI PHY Frequency */
|
||||
uint32_t tx_ecs_clk_div; /**< Tx escape clock divider value */
|
||||
uint32_t horizontal_timing; /**< Total horizontal timing */
|
||||
uint32_t vertical_timing; /**< Total vertical timing */
|
||||
DSI_DPI_INFO *dpi_info; /**< Pointer to DPI info */
|
||||
IRQn_Type irq; /**< Interrupt number */
|
||||
uint32_t irq_priority; /**< Interrupt priority */
|
||||
DSI_DRIVER_STATE state; /**< DSI driver status */
|
||||
}DSI_RESOURCES;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* DRIVER_DSI_PRIVATE_H_ */
|
||||
1941
src/hal/alif/Alif_CMSIS/Source/Driver_GPIO.c
Normal file
1941
src/hal/alif/Alif_CMSIS/Source/Driver_GPIO.c
Normal file
File diff suppressed because it is too large
Load Diff
101
src/hal/alif/Alif_CMSIS/Source/Driver_GPIO_Private.h
Normal file
101
src/hal/alif/Alif_CMSIS/Source/Driver_GPIO_Private.h
Normal file
@ -0,0 +1,101 @@
|
||||
/* Copyright (C) 2023 Alif Semiconductor - All Rights Reserved.
|
||||
* Use, distribution and modification of this code is permitted under the
|
||||
* terms stated in the Alif Semiconductor Software License Agreement
|
||||
*
|
||||
* You should have received a copy of the Alif Semiconductor Software
|
||||
* License Agreement with this file. If not, please write to:
|
||||
* contact@alifsemi.com, or visit: https://alifsemi.com/license
|
||||
*
|
||||
*/
|
||||
|
||||
/**************************************************************************//**
|
||||
* @file Driver_GPIO_Private.h
|
||||
* @author Girish BN, Manoj A Murudi
|
||||
* @email girish.bn@alifsemi.com, manoj.murudi@alifsemi.com
|
||||
* @version V1.0.0
|
||||
* @date 29-March-2023
|
||||
* @brief Header file for GPIO.
|
||||
* @bug None.
|
||||
* @Note None
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef DRIVER_GPIO_PRIVATE_H_
|
||||
|
||||
#define DRIVER_GPIO_PRIVATE_H_
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
#include "RTE_Device.h"
|
||||
#include "RTE_Components.h"
|
||||
#include CMSIS_device_header
|
||||
|
||||
#include "Driver_GPIO.h"
|
||||
#include "gpio.h"
|
||||
|
||||
#define GPIO_PORT_MAX_PIN_NUMBER 0x8U /* Number of pins in each port */
|
||||
|
||||
#define ARM_GPIO_BIT_IRQ_POLARITY_Pos 0U ///< bits - 0
|
||||
#define ARM_GPIO_BIT_IRQ_POLARITY_Msk (1U << ARM_GPIO_BIT_IRQ_POLARITY_Pos)
|
||||
#define ARM_GPIO_BIT_IRQ_POLARITY(x) (((x)& ARM_GPIO_BIT_IRQ_POLARITY_Msk) >> ARM_GPIO_BIT_IRQ_POLARITY_Pos)
|
||||
|
||||
#define ARM_GPIO_BIT_IRQ_BOTH_EDGE_Pos 1U ///< bits - 1
|
||||
#define ARM_GPIO_BIT_IRQ_BOTH_EDGE_Msk (1U << ARM_GPIO_BIT_IRQ_BOTH_EDGE_Pos)
|
||||
#define ARM_GPIO_BIT_IRQ_BOTH_EDGE(x) (((x)& ARM_GPIO_BIT_IRQ_BOTH_EDGE_Msk) >> ARM_GPIO_BIT_IRQ_BOTH_EDGE_Pos)
|
||||
|
||||
#define ARM_GPIO_BIT_IRQ_SENSITIVE_Pos 2U ///< bits - 2
|
||||
#define ARM_GPIO_BIT_IRQ_SENSITIVE_Msk (1U << ARM_GPIO_BIT_IRQ_SENSITIVE_Pos)
|
||||
#define ARM_GPIO_BIT_IRQ_SENSITIVE(x) (((x)& ARM_GPIO_BIT_IRQ_SENSITIVE_Msk) >> ARM_GPIO_BIT_IRQ_SENSITIVE_Pos)
|
||||
|
||||
/**
|
||||
* enum GPIO_INSTANCE.
|
||||
* GPIO instances.
|
||||
*/
|
||||
typedef enum _GPIO_INSTANCE
|
||||
{
|
||||
GPIO0_INSTANCE,
|
||||
GPIO1_INSTANCE,
|
||||
GPIO2_INSTANCE,
|
||||
GPIO3_INSTANCE,
|
||||
GPIO4_INSTANCE,
|
||||
GPIO5_INSTANCE,
|
||||
GPIO6_INSTANCE,
|
||||
GPIO7_INSTANCE,
|
||||
GPIO8_INSTANCE,
|
||||
GPIO9_INSTANCE,
|
||||
GPIO10_INSTANCE,
|
||||
GPIO11_INSTANCE,
|
||||
GPIO12_INSTANCE,
|
||||
GPIO13_INSTANCE,
|
||||
GPIO14_INSTANCE,
|
||||
LPGPIO_INSTANCE
|
||||
} GPIO_INSTANCE;
|
||||
|
||||
typedef struct _GPIO_DRV_STATE {
|
||||
uint32_t initialized : 1; /* Driver Initialized*/
|
||||
uint32_t powered : 1; /* Driver powered */
|
||||
uint32_t reserved : 30;/* Reserved */
|
||||
} GPIO_DRV_STATE;
|
||||
|
||||
/**
|
||||
* @brief GPIO Resources
|
||||
*/
|
||||
typedef struct _GPIO_RESOURCES {
|
||||
GPIO_Type *reg_base; /**< GPIO PORT Base Address>**/
|
||||
IRQn_Type IRQ_base_num; /**< GPIO PORT IRQ base Num>**/
|
||||
uint16_t db_clkdiv; /**< GPIO PORT debounce clk divisor: only for GPIO 0-14 >**/
|
||||
GPIO_DRV_STATE state; /**< GPIO PORT status flag >**/
|
||||
uint8_t IRQ_priority[GPIO_PORT_MAX_PIN_NUMBER]; /**< GPIO PIN IRQ priority >**/
|
||||
GPIO_INSTANCE gpio_id; /**< GPIO instance >*/
|
||||
ARM_GPIO_SignalEvent_t cb_event[GPIO_PORT_MAX_PIN_NUMBER]; /**< GPIO Call back function >*/
|
||||
} GPIO_RESOURCES;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* DRIVER_GPIO_PRIVATE_H_ */
|
||||
|
||||
/************************ (C) COPYRIGHT ALIF SEMICONDUCTOR *****END OF FILE****/
|
||||
1241
src/hal/alif/Alif_CMSIS/Source/Driver_HWSEM.c
Normal file
1241
src/hal/alif/Alif_CMSIS/Source/Driver_HWSEM.c
Normal file
File diff suppressed because it is too large
Load Diff
78
src/hal/alif/Alif_CMSIS/Source/Driver_HWSEM_Private.h
Normal file
78
src/hal/alif/Alif_CMSIS/Source/Driver_HWSEM_Private.h
Normal file
@ -0,0 +1,78 @@
|
||||
/* Copyright (C) 2022 Alif Semiconductor - All Rights Reserved.
|
||||
* Use, distribution and modification of this code is permitted under the
|
||||
* terms stated in the Alif Semiconductor Software License Agreement
|
||||
*
|
||||
* You should have received a copy of the Alif Semiconductor Software
|
||||
* License Agreement with this file. If not, please write to:
|
||||
* contact@alifsemi.com, or visit: https://alifsemi.com/license
|
||||
*
|
||||
*/
|
||||
|
||||
/**************************************************************************//**
|
||||
* @file Driver_HWSEM_Private.h
|
||||
* @author Khushboo Singh
|
||||
* @email khushboo.singh@alifsemi.com
|
||||
* @version V1.0.0
|
||||
* @date 16-June-2022
|
||||
* @brief Device Specific Header file for hardware semaphore driver.
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef DRIVER_HWSEM_PRIVATE_H_
|
||||
#define DRIVER_HWSEM_PRIVATE_H_
|
||||
|
||||
/* System Includes */
|
||||
#include "RTE_Device.h"
|
||||
#include "RTE_Components.h"
|
||||
#include "Driver_Common.h"
|
||||
#include "Driver_HWSEM.h"
|
||||
|
||||
#include "hwsem.h"
|
||||
|
||||
#include CMSIS_device_header
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
/* Hardware Sem IDs */
|
||||
typedef enum _HWSEM_ID
|
||||
{
|
||||
HWSEMID0,
|
||||
HWSEMID1,
|
||||
HWSEMID2,
|
||||
HWSEMID3,
|
||||
HWSEMID4,
|
||||
HWSEMID5,
|
||||
HWSEMID6,
|
||||
HWSEMID7,
|
||||
HWSEMID8,
|
||||
HWSEMID9,
|
||||
HWSEMID10,
|
||||
HWSEMID11,
|
||||
HWSEMID12,
|
||||
HWSEMID13,
|
||||
HWSEMID14,
|
||||
HWSEMID15
|
||||
}HWSEM_ID;
|
||||
|
||||
/** \brief Hw Semaphore driver state */
|
||||
typedef volatile struct _HWSEM_DRIVER_STATE {
|
||||
uint32_t initialized : 1; /**< Driver Initialized */
|
||||
uint32_t reserved : 31; /**< Reserved */
|
||||
} HWSEM_DRIVER_STATE;
|
||||
|
||||
/** \brief Representation of Hw Semaphore. */
|
||||
typedef struct {
|
||||
HWSEM_Type *regs; /**< IOMEM base address of the Hw Semaphore module */
|
||||
ARM_HWSEM_SignalEvent_t cb_event; /**< Registered callback function */
|
||||
IRQn_Type irq; /**< IRQ number of the HSEM instance */
|
||||
HWSEM_DRIVER_STATE state; /**< HSEM driver state */
|
||||
uint8_t irq_priority; /**< IRQ priority can be modified by user */
|
||||
uint8_t sem_id; /**< HWSEM ID */
|
||||
} HWSEM_RESOURCES;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
#endif /* DRIVER_HWSEM_PRIVATE_H_ */
|
||||
2128
src/hal/alif/Alif_CMSIS/Source/Driver_I2C.c
Normal file
2128
src/hal/alif/Alif_CMSIS/Source/Driver_I2C.c
Normal file
File diff suppressed because it is too large
Load Diff
88
src/hal/alif/Alif_CMSIS/Source/Driver_I2C_Private.h
Normal file
88
src/hal/alif/Alif_CMSIS/Source/Driver_I2C_Private.h
Normal file
@ -0,0 +1,88 @@
|
||||
/* Copyright (C) 2022 Alif Semiconductor - All Rights Reserved.
|
||||
* Use, distribution and modification of this code is permitted under the
|
||||
* terms stated in the Alif Semiconductor Software License Agreement
|
||||
*
|
||||
* You should have received a copy of the Alif Semiconductor Software
|
||||
* License Agreement with this file. If not, please write to:
|
||||
* contact@alifsemi.com, or visit: https://alifsemi.com/license
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef DRIVER_I2C_PRIVATE_H_
|
||||
#define DRIVER_I2C_PRIVATE_H_
|
||||
|
||||
#include "Driver_I2C.h"
|
||||
#include "i2c.h"
|
||||
|
||||
/**** system includes ****/
|
||||
#include "RTE_Device.h"
|
||||
#include "RTE_Components.h"
|
||||
#include CMSIS_device_header
|
||||
|
||||
#if (RTE_I2C0_DMA_ENABLE || RTE_I2C1_DMA_ENABLE || \
|
||||
RTE_I2C2_DMA_ENABLE || RTE_I2C3_DMA_ENABLE)
|
||||
#define I2C_DMA_ENABLE 1
|
||||
#else
|
||||
#define I2C_DMA_ENABLE 0
|
||||
#endif
|
||||
|
||||
#if I2C_DMA_ENABLE
|
||||
#include <DMA_Common.h>
|
||||
#endif
|
||||
|
||||
typedef volatile struct _I2C_DRIVER_STATE
|
||||
{
|
||||
uint32_t initialized : 1; /**< Driver Initialized */
|
||||
uint32_t powered : 1; /**< Driver powered */
|
||||
uint32_t master_setup: 1; /**< i2c master setup */
|
||||
uint32_t slave_setup : 1; /**< i2c master setup */
|
||||
uint32_t reserved : 28; /**< Reserved */
|
||||
} I2C_DRIVER_STATE;
|
||||
|
||||
#if I2C_DMA_ENABLE
|
||||
typedef struct _I2C_DMA_HW_CONFIG
|
||||
{
|
||||
DMA_PERIPHERAL_CONFIG dma_tx; /* Tx interface */
|
||||
DMA_PERIPHERAL_CONFIG dma_rx; /* Rx interface */
|
||||
}I2C_DMA_HW_CONFIG;
|
||||
#endif
|
||||
|
||||
/* @brief Structure to save contexts for a i2c channel */
|
||||
typedef struct _I2C_RESOURCES
|
||||
{
|
||||
ARM_I2C_SignalEvent_t cb_event; /* Event callback */
|
||||
I2C_Type *regs; /* i2c register base address */
|
||||
ARM_I2C_STATUS status; /* I2C status */
|
||||
I2C_DRIVER_STATE state; /* i2c driver state */
|
||||
i2c_transfer_info_t transfer; /* Transfer structure for I2C */
|
||||
uint32_t clk; /* system clock */
|
||||
uint32_t addr_mode; /* I2C_ADDRESS_MODE */
|
||||
uint32_t slv_addr; /* slave address */
|
||||
uint32_t tar_addr; /* target slave device address */
|
||||
uint32_t irq_priority; /* i2c interrupt priority */
|
||||
IRQn_Type irq_num; /* i2c interrupt vector number */
|
||||
i2c_speed_mode_t speed_mode; /* I2C speed mode */
|
||||
uint8_t mode; /* current working mode as master or slave */
|
||||
#if I2C_DMA_ENABLE
|
||||
const bool dma_enable; /* I2C dma enable */
|
||||
const uint32_t dma_irq_priority; /* DMA IRQ priority number */
|
||||
ARM_DMA_SignalEvent_t dma_cb; /* I2S DMA Callback */
|
||||
I2C_DMA_HW_CONFIG *dma_cfg; /* DMA Controller configuration */
|
||||
#endif
|
||||
uint8_t tx_fifo_threshold; /* Tx Fifo Buffer threshold */
|
||||
uint8_t rx_fifo_threshold; /* Rx Fifo Buffer threshold */
|
||||
} I2C_RESOURCES;
|
||||
|
||||
#define I2C_SLAVE_MODE (0) /* Indicate that the device working as slave */
|
||||
#define I2C_MASTER_MODE (1) /* Indicate that the device working as master */
|
||||
|
||||
#define I2C_DIR_TRANSMITTER (0) /* direction transmitter */
|
||||
#define I2C_DIR_RECEIVER (1) /* direction receiver */
|
||||
|
||||
#define I2C_0_TARADDR (0x50) /* I2C target address */
|
||||
|
||||
#define I2C_7BIT_ADDRESS_MASK (0x7F) /* 7bit I2C address mask */
|
||||
|
||||
#define I2C_10BIT_ADDRESS_MASK (0x3FF) /* 10bit I2C address mask */
|
||||
|
||||
#endif /* DRIVER_I2C_PRIVATE_H_ */
|
||||
2459
src/hal/alif/Alif_CMSIS/Source/Driver_I2S.c
Normal file
2459
src/hal/alif/Alif_CMSIS/Source/Driver_I2S.c
Normal file
File diff suppressed because it is too large
Load Diff
168
src/hal/alif/Alif_CMSIS/Source/Driver_I2S_Private.h
Normal file
168
src/hal/alif/Alif_CMSIS/Source/Driver_I2S_Private.h
Normal file
@ -0,0 +1,168 @@
|
||||
/* Copyright (C) 2023 Alif Semiconductor - All Rights Reserved.
|
||||
* Use, distribution and modification of this code is permitted under the
|
||||
* terms stated in the Alif Semiconductor Software License Agreement
|
||||
*
|
||||
* You should have received a copy of the Alif Semiconductor Software
|
||||
* License Agreement with this file. If not, please write to:
|
||||
* contact@alifsemi.com, or visit: https://alifsemi.com/license
|
||||
*
|
||||
*/
|
||||
|
||||
/**************************************************************************//**
|
||||
* @file Driver_I2S_Private.h
|
||||
* @author Sudhir Sreedharan
|
||||
* @email sudhir@alifsemi.com
|
||||
* @version V3.0.0
|
||||
* @date 06-Jun-2023
|
||||
* @brief I2S Private header file.
|
||||
* @bug None.
|
||||
* @Note None
|
||||
******************************************************************************/
|
||||
#ifndef DRIVER_I2S_PRIVATE_H
|
||||
#define DRIVER_I2S_PRIVATE_H
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include <Driver_SAI.h>
|
||||
#include "RTE_Device.h"
|
||||
#include "RTE_Components.h"
|
||||
#include CMSIS_device_header
|
||||
#include <stdbool.h>
|
||||
#include "sys_ctrl_i2s.h"
|
||||
#include "i2s.h"
|
||||
|
||||
#if (RTE_I2S0_DMA_ENABLE || RTE_I2S1_DMA_ENABLE || RTE_I2S2_DMA_ENABLE || \
|
||||
RTE_I2S3_DMA_ENABLE || RTE_LPI2S_DMA_ENABLE)
|
||||
#define I2S_DMA_ENABLE 1
|
||||
#else
|
||||
#define I2S_DMA_ENABLE 0
|
||||
#endif
|
||||
|
||||
#if I2S_DMA_ENABLE
|
||||
#include <DMA_Common.h>
|
||||
#endif
|
||||
|
||||
#if ( RTE_I2S0_BLOCKING_MODE_ENABLE || RTE_I2S1_BLOCKING_MODE_ENABLE || \
|
||||
RTE_I2S2_BLOCKING_MODE_ENABLE || RTE_I2S3_BLOCKING_MODE_ENABLE || \
|
||||
RTE_LPI2S_BLOCKING_MODE_ENABLE )
|
||||
#define I2S_BLOCKING_MODE_ENABLE 1
|
||||
#else
|
||||
#define I2S_BLOCKING_MODE_ENABLE 0
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
/** \brief I2S Driver states. */
|
||||
typedef struct _I2S_DRIVER_STATE {
|
||||
uint32_t initialized : 1; /* Driver Initialized*/
|
||||
uint32_t powered : 1; /* Device powered */
|
||||
uint32_t reserved : 30;/* Reserved */
|
||||
} I2S_DRIVER_STATE;
|
||||
|
||||
typedef enum _I2S_FLAG {
|
||||
I2S_FLAG_DRV_MONO_MODE = (1U << 0), /*!< I2S Driver in Mono Mode */
|
||||
} I2S_FLAG;
|
||||
|
||||
typedef union _I2S_DRV_STATUS {
|
||||
uint32_t status;
|
||||
volatile ARM_SAI_STATUS status_b;
|
||||
} I2S_DRV_STATUS;
|
||||
|
||||
typedef struct _I2S_CONFIG_INFO {
|
||||
|
||||
/*!< I2S Word Select Size */
|
||||
I2S_WSS wss_len;
|
||||
|
||||
/*!< I2S SCLK Gating */
|
||||
I2S_SCLKG sclkg;
|
||||
|
||||
/*!< I2S word length */
|
||||
I2S_WLEN wlen;
|
||||
|
||||
/*!< I2S Rx FIFO Trigger Level */
|
||||
const uint8_t rx_fifo_trg_lvl;
|
||||
|
||||
/*!< I2S Tx FIFO Trigger Level */
|
||||
const uint8_t tx_fifo_trg_lvl;
|
||||
|
||||
/*!< I2S clock source in Hz */
|
||||
const uint32_t clk_source;
|
||||
|
||||
#if I2S_BLOCKING_MODE_ENABLE
|
||||
/*!< I2S instance blocking mode transfer enable */
|
||||
const bool blocking_mode;
|
||||
#endif
|
||||
|
||||
|
||||
#if I2S_DMA_ENABLE
|
||||
/*!< I2S dma enable */
|
||||
const bool dma_enable;
|
||||
|
||||
/*!< DMA IRQ priority number */
|
||||
const uint32_t dma_irq_priority;
|
||||
#endif
|
||||
|
||||
/*!< I2S irq priority number */
|
||||
const uint32_t irq_priority;
|
||||
|
||||
} I2S_CONFIG_INFO;
|
||||
|
||||
#if I2S_DMA_ENABLE
|
||||
typedef struct _I2S_DMA_HW_CONFIG {
|
||||
/*!< Tx interface */
|
||||
DMA_PERIPHERAL_CONFIG dma_tx;
|
||||
|
||||
/*!< Rx interface */
|
||||
DMA_PERIPHERAL_CONFIG dma_rx;
|
||||
} I2S_DMA_HW_CONFIG;
|
||||
#endif
|
||||
|
||||
/** \brief Resources for a I2S instance */
|
||||
typedef struct _I2S_RESOURCES {
|
||||
|
||||
/*!< I2S Application Event Callback */
|
||||
ARM_SAI_SignalEvent_t cb_event;
|
||||
|
||||
#if I2S_DMA_ENABLE
|
||||
/*!< I2S DMA Callback */
|
||||
ARM_DMA_SignalEvent_t dma_cb;
|
||||
|
||||
/*!< DMA Controller configuration */
|
||||
I2S_DMA_HW_CONFIG *dma_cfg;
|
||||
#endif
|
||||
|
||||
/*!< I2S ARM I2S Status */
|
||||
I2S_DRV_STATUS drv_status;
|
||||
|
||||
/*!< I2S Driver state */
|
||||
I2S_DRIVER_STATE state;
|
||||
|
||||
/*!< I2S Audio Sample Rate */
|
||||
uint32_t sample_rate;
|
||||
|
||||
/*!< I2S Controller configuration */
|
||||
I2S_CONFIG_INFO *cfg;
|
||||
|
||||
/*!< I2S physical address */
|
||||
I2S_Type *regs;
|
||||
|
||||
/*!< I2S Instance number */
|
||||
const I2S_INSTANCE instance;
|
||||
|
||||
/*!< I2S irq number */
|
||||
const IRQn_Type irq;
|
||||
|
||||
/* I2S transfer buffer information */
|
||||
i2s_transfer_t transfer;
|
||||
|
||||
/*!< I2S Driver Flags */
|
||||
uint8_t flags;
|
||||
|
||||
} I2S_RESOURCES;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif // DRIVER_I2S_PRIVATE_H
|
||||
2420
src/hal/alif/Alif_CMSIS/Source/Driver_I3C.c
Normal file
2420
src/hal/alif/Alif_CMSIS/Source/Driver_I3C.c
Normal file
File diff suppressed because it is too large
Load Diff
384
src/hal/alif/Alif_CMSIS/Source/Driver_I3C_I2C.c
Normal file
384
src/hal/alif/Alif_CMSIS/Source/Driver_I3C_I2C.c
Normal file
@ -0,0 +1,384 @@
|
||||
/* Copyright (C) 2023 Alif Semiconductor - All Rights Reserved.
|
||||
* Use, distribution and modification of this code is permitted under the
|
||||
* terms stated in the Alif Semiconductor Software License Agreement
|
||||
*
|
||||
* You should have received a copy of the Alif Semiconductor Software
|
||||
* License Agreement with this file. If not, please write to:
|
||||
* contact@alifsemi.com, or visit: https://alifsemi.com/license
|
||||
*
|
||||
*/
|
||||
|
||||
/******************************************************************************
|
||||
* @file Driver_I3C_I2C.c
|
||||
* @author Prasanna Ravi
|
||||
* @email prasanna.ravi@alifsemi.com
|
||||
* @version V1.0.0
|
||||
* @date 24-Feb-2022
|
||||
* @brief Driver for I2C over I3C adapter.
|
||||
* @bug None.
|
||||
* @Note None.
|
||||
******************************************************************************/
|
||||
#include "Driver_I2C.h"
|
||||
#include "Driver_I3C.h"
|
||||
#include "RTE_Device.h"
|
||||
|
||||
#if !(RTE_I3C)
|
||||
#error "I3C is not enabled in the RTE_Device.h"
|
||||
#endif
|
||||
|
||||
#if !(RTE_I2CI3C)
|
||||
#error "I2CI3C is not enabled in the RTE_Device.h"
|
||||
#endif
|
||||
|
||||
#define ARM_I3C_I2C_DRV_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(1, 0) /* driver version */
|
||||
|
||||
/* Driver Version */
|
||||
static const ARM_DRIVER_VERSION DriverVersion = {
|
||||
ARM_I2C_API_VERSION,
|
||||
ARM_I3C_I2C_DRV_VERSION
|
||||
};
|
||||
|
||||
/* I3C driver instance */
|
||||
extern ARM_DRIVER_I3C Driver_I3C;
|
||||
|
||||
/* Pointer to \ref ARM_I2C_SignalEvent */
|
||||
static ARM_I2C_SignalEvent_t i2c_event;
|
||||
|
||||
/* i2c status parameter */
|
||||
static ARM_I2C_STATUS i2c_status;
|
||||
|
||||
/* Driver Capabilities */
|
||||
static const ARM_I2C_CAPABILITIES DriverCapabilities = {
|
||||
0, /* supports 10-bit addressing */
|
||||
0 /* reserved */
|
||||
};
|
||||
|
||||
/**
|
||||
* @fn void i3c_driver_callback (uint32_t event)
|
||||
* @brief callback routine from the i3c driver mapped to i2c signal events
|
||||
* @param none
|
||||
* @retval none
|
||||
*/
|
||||
static void i3c_driver_callback (uint32_t event)
|
||||
{
|
||||
if(event & ARM_I3C_EVENT_TRANSFER_DONE)
|
||||
{
|
||||
i2c_event(ARM_I2C_EVENT_TRANSFER_DONE);
|
||||
}
|
||||
|
||||
if(event & ARM_I3C_EVENT_TRANSFER_ERROR)
|
||||
{
|
||||
i2c_event(ARM_I2C_EVENT_TRANSFER_INCOMPLETE);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @fn ARM_DRIVER_VERSION ARM_I3C_I2C_GetVersion (void)
|
||||
* @brief get i2c over i3c driver version
|
||||
* @param none
|
||||
* @retval driver version
|
||||
*/
|
||||
static ARM_DRIVER_VERSION ARM_I3C_I2C_GetVersion (void)
|
||||
{
|
||||
return DriverVersion;
|
||||
}
|
||||
|
||||
/**
|
||||
* @fn static ARM_I2C_CAPABILITIES ARM_I3C_I2C_GetCapabilities (void)
|
||||
* @brief get i2c over i3c capabilities
|
||||
* @param none
|
||||
* @retval driver capabilities
|
||||
*/
|
||||
static ARM_I2C_CAPABILITIES ARM_I3C_I2C_GetCapabilities (void)
|
||||
{
|
||||
return DriverCapabilities;
|
||||
}
|
||||
|
||||
/**
|
||||
* @fn int32_t ConvertI2CBusSpeedToI3C (uint32_t i2c_bus_speed)
|
||||
* @brief get i2c over i3c bus speed
|
||||
* @param i2c_bus_speed : i2c bus speed
|
||||
* ARM_I2C_BUS_SPEED_STANDARD
|
||||
* ARM_I2C_BUS_SPEED_FAST
|
||||
* ARM_I2C_BUS_SPEED_FAST_PLUS
|
||||
* @retval none
|
||||
*/
|
||||
static int32_t ConvertI2CBusSpeedToI3C (uint32_t i2c_bus_speed)
|
||||
{
|
||||
int32_t speed = 0;
|
||||
|
||||
switch (i2c_bus_speed)
|
||||
{
|
||||
case ARM_I2C_BUS_SPEED_STANDARD:
|
||||
/* Standard Speed (100kHz) */
|
||||
speed = I3C_BUS_MODE_MIXED_SLOW_I2C_SS_SPEED_100_KBPS;
|
||||
break;
|
||||
case ARM_I2C_BUS_SPEED_FAST:
|
||||
/* Fast Speed (400kHz) */
|
||||
speed = I3C_BUS_MODE_MIXED_FAST_I2C_FM_SPEED_400_KBPS;
|
||||
break;
|
||||
case ARM_I2C_BUS_SPEED_FAST_PLUS:
|
||||
/* Fast+ Speed (1MHz) */
|
||||
speed = I3C_BUS_MODE_MIXED_FAST_I2C_FMP_SPEED_1_MBPS;
|
||||
break;
|
||||
case ARM_I2C_BUS_SPEED_HIGH:
|
||||
/* Fast+ Speed (3.4MHz) */
|
||||
return ARM_DRIVER_ERROR_UNSUPPORTED;
|
||||
break;
|
||||
default:
|
||||
return ARM_DRIVER_ERROR_UNSUPPORTED;
|
||||
}
|
||||
return speed;
|
||||
}
|
||||
|
||||
/**
|
||||
* @fn int32_t ARM_I3C_I2C_Initialize (ARM_I2C_SignalEvent_t cb_event)
|
||||
* @brief CMSIS-Driver i2c over i3c initialize.
|
||||
* @param cb_event : Pointer to \ref ARM_I2C_SignalEvent
|
||||
* @retval \ref execution_status
|
||||
*/
|
||||
static int32_t ARM_I3C_I2C_Initialize (ARM_I2C_SignalEvent_t cb_event)
|
||||
{
|
||||
if (cb_event == NULL)
|
||||
{
|
||||
return ARM_DRIVER_ERROR_PARAMETER;
|
||||
}
|
||||
|
||||
i2c_event = cb_event;
|
||||
|
||||
return Driver_I3C.Initialize (i3c_driver_callback);
|
||||
}
|
||||
|
||||
/**
|
||||
* @fn int32_t ARM_I3C_I2C_Uninitialize (void)
|
||||
* @brief CMSIS-Driver i2c over i3c uninitialize
|
||||
* @note none
|
||||
* @retval \ref execution_status
|
||||
*/
|
||||
static int32_t ARM_I3C_I2C_Uninitialize (void)
|
||||
{
|
||||
i2c_event = NULL;
|
||||
|
||||
return Driver_I3C.Uninitialize ();
|
||||
}
|
||||
|
||||
/**
|
||||
* @fn int32_t ARM_I3C_I2C_PowerControl (ARM_POWER_STATE state)
|
||||
* @brief Power the driver and enable the NVIC
|
||||
* @param state : Power state
|
||||
* @return \ref execution_status
|
||||
*/
|
||||
static int32_t ARM_I3C_I2C_PowerControl (ARM_POWER_STATE state)
|
||||
{
|
||||
return Driver_I3C.PowerControl (state);
|
||||
}
|
||||
|
||||
/**
|
||||
* @fn static int32_t ARM_I3C_I2C_MasterTransmit (uint32_t addr,
|
||||
const uint8_t *data,
|
||||
uint32_t num,
|
||||
bool xfer_pending)
|
||||
* @brief CMSIS-Driver i2c master transmit
|
||||
* Start sending data to i2c over i3c transmitter
|
||||
* @param addr : Slave address (7-bit)
|
||||
* @param data : Pointer to buffer with data to send to i2c transmitter
|
||||
* @param num : Number of data items to send
|
||||
* @retval \ref execution_status
|
||||
*/
|
||||
static int32_t ARM_I3C_I2C_MasterTransmit (uint32_t addr,
|
||||
const uint8_t *data,
|
||||
uint32_t num,
|
||||
bool xfer_pending)
|
||||
{
|
||||
int32_t ret, detach_ret;
|
||||
ARM_I3C_DEVICE_TYPE dev_type = ARM_I3C_DEVICE_TYPE_I2C;
|
||||
|
||||
/* Currently this feature is not supported */
|
||||
(void) xfer_pending;
|
||||
|
||||
/* I2C Master Mode*/
|
||||
i2c_status.mode = 1;
|
||||
|
||||
ret = Driver_I3C.AttachSlvDev(dev_type, addr);
|
||||
if (ret != ARM_DRIVER_OK)
|
||||
{
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = Driver_I3C.MasterTransmit (addr, data, num);
|
||||
|
||||
detach_ret = Driver_I3C.Detachdev (addr);
|
||||
if(ret == ARM_DRIVER_OK)
|
||||
{
|
||||
ret = detach_ret;
|
||||
}
|
||||
|
||||
return ret;
|
||||
|
||||
}
|
||||
|
||||
/**
|
||||
* @fn static int32_t ARM_I3C_I2C_MasterReceive (uint32_t addr,
|
||||
uint8_t *data,
|
||||
uint32_t num,
|
||||
bool xfer_pending)
|
||||
* @brief CMSIS-Driver i2c master receive
|
||||
* Start receiving data from i2c over i3c receiver.
|
||||
* @param addr : addr Slave address (7-bit)
|
||||
* @param data : Pointer to buffer for data to receive from i2c receiver
|
||||
* @param num : Number of data items to receive
|
||||
* @retval \ref execution_status
|
||||
*/
|
||||
static int32_t ARM_I3C_I2C_MasterReceive (uint32_t addr,
|
||||
uint8_t *data,
|
||||
uint32_t num,
|
||||
bool xfer_pending)
|
||||
{
|
||||
int32_t ret, detach_ret;
|
||||
ARM_I3C_DEVICE_TYPE dev_type = ARM_I3C_DEVICE_TYPE_I2C;
|
||||
|
||||
/* Currently this feature is not supported */
|
||||
(void) xfer_pending;
|
||||
|
||||
/* I2C Master Mode*/
|
||||
i2c_status.mode = 1;
|
||||
|
||||
ret = Driver_I3C.AttachSlvDev(dev_type, addr);
|
||||
if (ret != ARM_DRIVER_OK)
|
||||
{
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = Driver_I3C.MasterReceive (addr, data, num);
|
||||
|
||||
detach_ret = Driver_I3C.Detachdev (addr);
|
||||
if(ret == ARM_DRIVER_OK)
|
||||
{
|
||||
ret = detach_ret;
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/**
|
||||
* @fn int32_t ARM_I3C_I2C_SlaveTransmit (const uint8_t *data,
|
||||
uint32_t num)
|
||||
* @brief CMSIS-Driver i2c slave transmit
|
||||
* Start sending data to i2c over i3c master.
|
||||
* @param data : Pointer to buffer with data to send to i2c master
|
||||
* @param num : Number of data items to send
|
||||
* @retval \ref execution_status
|
||||
*/
|
||||
static int32_t ARM_I3C_I2C_SlaveTransmit (const uint8_t *data,
|
||||
uint32_t num)
|
||||
{
|
||||
(void) data;
|
||||
(void) num;
|
||||
|
||||
return ARM_DRIVER_ERROR_UNSUPPORTED;
|
||||
}
|
||||
|
||||
/**
|
||||
* @fn int32_t ARM_I3C_I2C_SlaveReceive (uint8_t *data,
|
||||
uint32_t num)
|
||||
* @brief CMSIS-Driver i2c slave receive
|
||||
* Start receiving data from i2c over i3c master.
|
||||
* @param data : Pointer to buffer for data to receive from i2c master
|
||||
* @param num : Number of data items to receive
|
||||
* @retval \ref execution_status
|
||||
*/
|
||||
static int32_t ARM_I3C_I2C_SlaveReceive (uint8_t *data,
|
||||
uint32_t num)
|
||||
{
|
||||
(void) data;
|
||||
(void) num;
|
||||
|
||||
return ARM_DRIVER_ERROR_UNSUPPORTED;
|
||||
}
|
||||
|
||||
/**
|
||||
* @fn int32_t ARM_I3C_I2C_GetDataCount (void)
|
||||
* @brief CMSIS-Driver i2c get transfer data count
|
||||
* @retval transfer data count
|
||||
*/
|
||||
static int32_t ARM_I3C_I2C_GetDataCount (void)
|
||||
{
|
||||
return ARM_DRIVER_ERROR_UNSUPPORTED;
|
||||
}
|
||||
|
||||
/**
|
||||
* @fn int32_t ARM_I3C_I2C_Control (uint32_t control,
|
||||
uint32_t arg)
|
||||
* @brief CMSIS-Driver i2c control
|
||||
* Control i2c over i3c Interface.
|
||||
* @note none
|
||||
* @param control : Operation
|
||||
* @param arg : Argument of operation (optional)
|
||||
* @retval common \ref execution_status and driver specific \ref i2c_execution_status
|
||||
*/
|
||||
static int32_t ARM_I3C_I2C_Control (uint32_t control,
|
||||
uint32_t arg)
|
||||
{
|
||||
int32_t ret = ARM_DRIVER_OK;
|
||||
int32_t speed = 0;
|
||||
|
||||
switch (control)
|
||||
{
|
||||
case ARM_I2C_OWN_ADDRESS:
|
||||
return ARM_DRIVER_ERROR_UNSUPPORTED;
|
||||
break;
|
||||
case ARM_I2C_BUS_SPEED:
|
||||
speed = ConvertI2CBusSpeedToI3C (arg);
|
||||
|
||||
if (speed == ARM_DRIVER_ERROR_UNSUPPORTED)
|
||||
return ARM_DRIVER_ERROR_UNSUPPORTED;
|
||||
|
||||
ret = Driver_I3C.Control (I3C_MASTER_INIT, 0);
|
||||
ret = Driver_I3C.Control (I3C_MASTER_SET_BUS_MODE, speed);
|
||||
ret = Driver_I3C.Control (I3C_MASTER_SETUP_HOT_JOIN_ACCEPTANCE, 0);
|
||||
ret = Driver_I3C.Control (I3C_MASTER_SETUP_MR_ACCEPTANCE, 0);
|
||||
break;
|
||||
case ARM_I2C_BUS_CLEAR:
|
||||
return ARM_DRIVER_ERROR_UNSUPPORTED;
|
||||
break;
|
||||
case ARM_I2C_ABORT_TRANSFER:
|
||||
return ARM_DRIVER_ERROR_UNSUPPORTED;
|
||||
break;
|
||||
default:
|
||||
return ARM_DRIVER_ERROR_UNSUPPORTED;
|
||||
}
|
||||
return ret;
|
||||
}
|
||||
|
||||
/**
|
||||
* @fn ARM_I2C_STATUS ARM_I3C_I2C_GetStatus (void)
|
||||
* @brief CMSIS-Driver i2c get status
|
||||
* @note none
|
||||
* @retval ARM_i2c_STATUS
|
||||
*/
|
||||
static ARM_I2C_STATUS ARM_I3C_I2C_GetStatus (void)
|
||||
{
|
||||
return i2c_status;
|
||||
}
|
||||
|
||||
/* I2CI3C Driver Instance */
|
||||
#if (RTE_I2CI3C)
|
||||
|
||||
/* I2CI3C Driver Control Block */
|
||||
extern ARM_DRIVER_I2C Driver_I2CI3C;
|
||||
ARM_DRIVER_I2C Driver_I2CI3C = {
|
||||
ARM_I3C_I2C_GetVersion,
|
||||
ARM_I3C_I2C_GetCapabilities,
|
||||
ARM_I3C_I2C_Initialize,
|
||||
ARM_I3C_I2C_Uninitialize,
|
||||
ARM_I3C_I2C_PowerControl,
|
||||
ARM_I3C_I2C_MasterTransmit,
|
||||
ARM_I3C_I2C_MasterReceive,
|
||||
ARM_I3C_I2C_SlaveTransmit,
|
||||
ARM_I3C_I2C_SlaveReceive,
|
||||
ARM_I3C_I2C_GetDataCount,
|
||||
ARM_I3C_I2C_Control,
|
||||
ARM_I3C_I2C_GetStatus
|
||||
};
|
||||
|
||||
#endif /* RTE_I2CI3C */
|
||||
106
src/hal/alif/Alif_CMSIS/Source/Driver_I3C_Private.h
Normal file
106
src/hal/alif/Alif_CMSIS/Source/Driver_I3C_Private.h
Normal file
@ -0,0 +1,106 @@
|
||||
/* Copyright (C) 2023 Alif Semiconductor - All Rights Reserved.
|
||||
* Use, distribution and modification of this code is permitted under the
|
||||
* terms stated in the Alif Semiconductor Software License Agreement
|
||||
*
|
||||
* You should have received a copy of the Alif Semiconductor Software
|
||||
* License Agreement with this file. If not, please write to:
|
||||
* contact@alifsemi.com, or visit: https://alifsemi.com/license
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef DRIVER_I3C_PRIVATE_H
|
||||
#define DRIVER_I3C_PRIVATE_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
#include "RTE_Device.h"
|
||||
#include "RTE_Components.h"
|
||||
#include CMSIS_device_header
|
||||
|
||||
#include "Driver_I3C.h"
|
||||
#include "i3c.h"
|
||||
|
||||
/* Check if DMA Support is enable? */
|
||||
#if RTE_I3C_DMA_ENABLE
|
||||
#define I3C_DMA_ENABLE 1
|
||||
#else
|
||||
#define I3C_DMA_ENABLE 0
|
||||
#endif
|
||||
|
||||
#if I3C_DMA_ENABLE
|
||||
#include <DMA_Common.h>
|
||||
#endif
|
||||
|
||||
#define I3C_TARGET_SLAVE_TYPE_I2C (1U << 7U) /* Represents slave type */
|
||||
/**
|
||||
\brief I3C Driver states.
|
||||
*/
|
||||
typedef volatile struct _I3C_DRIVER_STATE
|
||||
{
|
||||
uint32_t initialized : 1; /* Driver initialized */
|
||||
uint32_t powered : 1; /* Driver powered */
|
||||
uint32_t is_master : 1; /* Driver master mode */
|
||||
uint32_t enabled : 1; /* Driver enabled */
|
||||
uint32_t reserved : 28;/* Reserved */
|
||||
} I3C_DRIVER_STATE;
|
||||
|
||||
/**
|
||||
\brief I3C Slave Device Address info
|
||||
*/
|
||||
typedef struct _I3C_SLAVE_DAT_TYPE
|
||||
{
|
||||
uint32_t datp; /* DAT (Device Address Table) offset */
|
||||
uint32_t maxdevs; /* maximum number of slaves supported */
|
||||
uint8_t addrs[I3C_MAX_DEVS]; /* Assigned dynamic(i3c) or static address(i2c slave) */
|
||||
uint32_t freepos; /* bitmask of used addresses */
|
||||
uint32_t last_asgd_addr_pos; /* Last assigned slave address positions */
|
||||
}I3C_SLAVE_DAT_TYPE;
|
||||
|
||||
#if I3C_DMA_ENABLE
|
||||
typedef struct _I3C_DMA_HW_CONFIG
|
||||
{
|
||||
DMA_PERIPHERAL_CONFIG dma_tx; /* DMA Tx interface */
|
||||
DMA_PERIPHERAL_CONFIG dma_rx; /* DMA Rx interface */
|
||||
} I3C_DMA_HW_CONFIG;
|
||||
#endif
|
||||
|
||||
/**
|
||||
\brief I3C Device Resources
|
||||
*/
|
||||
typedef struct _I3C_RESOURCES
|
||||
{
|
||||
I3C_Type *regs; /* Pointer to i3c regs */
|
||||
ARM_I3C_SignalEvent_t cb_event; /* Pointer to call back function */
|
||||
|
||||
#if I3C_DMA_ENABLE
|
||||
ARM_DMA_SignalEvent_t dma_cb; /* Pointer to DMA Callback */
|
||||
#endif
|
||||
|
||||
uint32_t core_clk; /* i3c core clock frequency */
|
||||
I3C_SLAVE_DAT_TYPE slave_dat; /* i3c slave devices address local information */
|
||||
i3c_xfer_t xfer; /* i3c transfer structure */
|
||||
ARM_I3C_STATUS status; /* i3c driver status */
|
||||
I3C_DRIVER_STATE state; /* I3C driver state */
|
||||
#if RTE_I3C_BLOCKING_MODE_ENABLE
|
||||
bool blocking_mode; /* I3C blocking mode transfer enable */
|
||||
#endif
|
||||
bool adaptive_mode; /* I3C slave I2C/I3C adaptive mode */
|
||||
IRQn_Type irq; /* i3c interrupt number */
|
||||
uint32_t irq_priority; /* i3c interrupt priority */
|
||||
|
||||
#if I3C_DMA_ENABLE
|
||||
I3C_DMA_HW_CONFIG *dma_cfg; /* DMA Controller configuration */
|
||||
const uint32_t dma_irq_priority; /* DMA IRQ priority number */
|
||||
#endif
|
||||
|
||||
}I3C_RESOURCES;
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* DRIVER_I3C_PRIVATE_H */
|
||||
400
src/hal/alif/Alif_CMSIS/Source/Driver_LPI2C.c
Normal file
400
src/hal/alif/Alif_CMSIS/Source/Driver_LPI2C.c
Normal file
@ -0,0 +1,400 @@
|
||||
/* Copyright (C) 2023 Alif Semiconductor - All Rights Reserved.
|
||||
* Use, distribution and modification of this code is permitted under the
|
||||
* terms stated in the Alif Semiconductor Software License Agreement
|
||||
*
|
||||
* You should have received a copy of the Alif Semiconductor Software
|
||||
* License Agreement with this file. If not, please write to:
|
||||
* contact@alifsemi.com, or visit: https://alifsemi.com/license
|
||||
*
|
||||
*/
|
||||
|
||||
/* system includes */
|
||||
#include "Driver_LPI2C_Private.h"
|
||||
|
||||
#define ARM_I2C_DRV_VERISON ARM_DRIVER_VERSION_MAJOR_MINOR(0,0) /*DRIVER VERSION*/
|
||||
|
||||
/* Driver Version */
|
||||
static const ARM_DRIVER_VERSION DriverVersion = {
|
||||
ARM_I2C_API_VERSION,
|
||||
ARM_I2C_DRV_VERISON
|
||||
};
|
||||
|
||||
/* Driver Capabilities */
|
||||
static const ARM_I2C_CAPABILITIES DriverCapabilities = {
|
||||
0, /* 10 bit addressing */
|
||||
0 /* reserved */
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief get lpi2c version
|
||||
* @note none
|
||||
* @param none
|
||||
* @retval driver version
|
||||
*/
|
||||
ARM_DRIVER_VERSION ARM_I2C_GetVersion(void)
|
||||
{
|
||||
return DriverVersion;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief get lpi2c capabilites
|
||||
* @note none
|
||||
* @param none
|
||||
* @retval driver capabilites
|
||||
*/
|
||||
static ARM_I2C_CAPABILITIES ARM_I2C_GetCapabilities(void)
|
||||
{
|
||||
return DriverCapabilities;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief lpi2c initialize
|
||||
* @note it will use initialize the lpi2c driver.
|
||||
* @param cb_event : Pointer to \ref ARM_LPI2C_SignalEvent
|
||||
* @param LPI2C : Pointer to lpi2c resources structure
|
||||
* @retval ARM_DRIVER_OK : successfully initialized
|
||||
*/
|
||||
static int32_t ARM_LPI2C_Initialize(ARM_I2C_SignalEvent_t cb_event,
|
||||
LPI2C_RESOURCES *LPI2C)
|
||||
{
|
||||
if (!cb_event)
|
||||
return ARM_DRIVER_ERROR_PARAMETER;
|
||||
|
||||
LPI2C->cb_event = cb_event;
|
||||
|
||||
LPI2C->state.initialized = 1U;
|
||||
|
||||
return ARM_DRIVER_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @func : int32_t ARM_LPI2C_Uninitialize(LPI2C_RESOURCES *LPI2C)
|
||||
* @brief : lpi2c uninitialize
|
||||
* @note : it will use uninitialize the lpi2c driver.
|
||||
* @param : lpi2c : Pointer to lpi2c resources structure
|
||||
* @retval : ARM_DRIVER_OK : successfully initialized
|
||||
*/
|
||||
static int32_t ARM_LPI2C_Uninitialize(LPI2C_RESOURCES *LPI2C)
|
||||
{
|
||||
|
||||
/* check lpi2c driver is initialized or not */
|
||||
if (LPI2C->state.initialized == 0)
|
||||
return ARM_DRIVER_OK;
|
||||
|
||||
/* check lpi2c driver is powered or not */
|
||||
if (LPI2C->state.powered == 1)
|
||||
return ARM_DRIVER_ERROR;
|
||||
|
||||
LPI2C->cb_event = 0U;
|
||||
|
||||
LPI2C->state.initialized = 0U;
|
||||
|
||||
return ARM_DRIVER_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @func : int32_t ARM_LPI2C_PowerControl (ARM_POWER_STATE state, LPI2C_RESOURCES *LPI2C)
|
||||
* @brief : Power the driver and enable the NVIC
|
||||
* @param : state : Power state
|
||||
* @param : LPI2C : Pointer to lpi2c resources structure
|
||||
* @return : ARM_DRIVER_OK
|
||||
*/
|
||||
static int32_t ARM_LPI2C_PowerControl (ARM_POWER_STATE state, LPI2C_RESOURCES *LPI2C)
|
||||
{
|
||||
switch (state)
|
||||
{
|
||||
case ARM_POWER_FULL:
|
||||
|
||||
/* check for Driver initialization */
|
||||
if (LPI2C->state.initialized == 0)
|
||||
{
|
||||
return ARM_DRIVER_ERROR;
|
||||
}
|
||||
|
||||
/* check for the power is done before initialization or not */
|
||||
if (LPI2C->state.powered == 1)
|
||||
{
|
||||
return ARM_DRIVER_OK;
|
||||
}
|
||||
|
||||
/* Clear Any Pending Irq */
|
||||
NVIC_ClearPendingIRQ(LPI2C->irq_num);
|
||||
|
||||
/* Set Priority */
|
||||
NVIC_SetPriority(LPI2C->irq_num, LPI2C->irq_priority);
|
||||
|
||||
/* Enable IRQ */
|
||||
NVIC_EnableIRQ(LPI2C->irq_num);
|
||||
|
||||
LPI2C->state.powered = 1;
|
||||
|
||||
break;
|
||||
case ARM_POWER_OFF:
|
||||
|
||||
if (LPI2C->state.powered == 0)
|
||||
{
|
||||
return ARM_DRIVER_OK;
|
||||
}
|
||||
|
||||
/* Disable the IRQ */
|
||||
NVIC_DisableIRQ(LPI2C->irq_num);
|
||||
|
||||
/* Clearing pending */
|
||||
NVIC_ClearPendingIRQ(LPI2C->irq_num);
|
||||
|
||||
LPI2C->state.powered = 0;
|
||||
break;
|
||||
case ARM_POWER_LOW:
|
||||
return ARM_DRIVER_ERROR_UNSUPPORTED;
|
||||
}
|
||||
return ARM_DRIVER_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @func : int32_t ARM_LPI2C_SlaveTransmit(LPI2C_RESOURCES *LPI2C,
|
||||
const uint8_t *data,
|
||||
uint32_t num)
|
||||
* @brief : lpi2c slave transmit
|
||||
* : Start sending data to i2c master.
|
||||
* @param : data : Pointer to buffer with data to send to i2c master
|
||||
* @param : num : Number of data items to send
|
||||
* @param : LPI2C : Pointer to lpi2c resources structure
|
||||
* @retval : ARM_DRIVER_ERROR_PARAMETER : error in parameter
|
||||
* @retval : ARM_DRIVER_ERROR : error in driver
|
||||
* @retval : ARM_DRIVER_OK : success in interrupt case
|
||||
*/
|
||||
static int32_t ARM_LPI2C_SlaveTransmit(LPI2C_RESOURCES *LPI2C,
|
||||
const uint8_t *data,
|
||||
uint32_t num)
|
||||
{
|
||||
|
||||
/* check lpi2c driver is initialized or not */
|
||||
if (LPI2C->state.initialized == 0)
|
||||
return ARM_DRIVER_ERROR;
|
||||
|
||||
/* check lpi2c driver is powered or not */
|
||||
if (LPI2C->state.powered == 0)
|
||||
return ARM_DRIVER_ERROR;
|
||||
|
||||
if ((data == NULL) || (num > 8U))
|
||||
return ARM_DRIVER_ERROR_PARAMETER;
|
||||
|
||||
if (LPI2C->status.busy == 1U)
|
||||
return ARM_DRIVER_ERROR;
|
||||
|
||||
/* Set busy state */
|
||||
LPI2C->status.busy = 1U;
|
||||
|
||||
LPI2C->transfer.tx_buf = data;
|
||||
LPI2C->transfer.tx_total_num = num;
|
||||
LPI2C->transfer.tx_curr_cnt = 0U;
|
||||
|
||||
LPI2C->transfer.rx_buf = NULL;
|
||||
LPI2C->transfer.rx_total_num = 0U;
|
||||
LPI2C->transfer.rx_curr_cnt = 0U;
|
||||
|
||||
/* Writing data to fifo */
|
||||
lpi2c_send(LPI2C->regs, &LPI2C->transfer);
|
||||
|
||||
if(LPI2C->transfer.status & LPI2C_XFER_STAT_COMPLETE)
|
||||
{
|
||||
LPI2C->status.busy = 0U;
|
||||
/* receive complete successfully. */
|
||||
LPI2C->cb_event(ARM_I2C_EVENT_TRANSFER_DONE);
|
||||
}
|
||||
|
||||
return ARM_DRIVER_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @func : int32_t ARM_LPI2C_SlaveTransmit(LPI2C_RESOURCES *LPI2C,
|
||||
const uint8_t *data,
|
||||
uint32_t num)
|
||||
* @brief : lpi2c slave receive
|
||||
* : Start receiving data from i2c master.
|
||||
* @note : none
|
||||
* @param : data : Pointer to buffer for data to receive from i2c master
|
||||
* @param : num : Number of data items to receive
|
||||
* @param : LPI2C : Pointer to lpi2c resources structure
|
||||
* @retval : ARM_DRIVER_ERROR_PARAMETER : error in parameter
|
||||
* @retval : ARM_DRIVER_ERROR : error in driver
|
||||
* @retval : ARM_DRIVER_OK : success in interrupt case
|
||||
*/
|
||||
static int32_t ARM_LPI2C_SlaveReceive(LPI2C_RESOURCES *LPI2C,
|
||||
uint8_t *data,
|
||||
uint32_t num)
|
||||
{
|
||||
/* check lpi2c driver is initialized or not */
|
||||
if (LPI2C->state.initialized == 0)
|
||||
return ARM_DRIVER_ERROR;
|
||||
|
||||
/* check lpi2c driver is powered or not */
|
||||
if (LPI2C->state.powered == 0)
|
||||
return ARM_DRIVER_ERROR;
|
||||
|
||||
if ((data == NULL) || (num > 8U))
|
||||
return ARM_DRIVER_ERROR_PARAMETER;
|
||||
|
||||
if (LPI2C->status.busy == 1U)
|
||||
return ARM_DRIVER_ERROR;
|
||||
|
||||
/* Set busy state */
|
||||
LPI2C->status.busy = 1U;
|
||||
|
||||
LPI2C->transfer.rx_buf = data;
|
||||
LPI2C->transfer.rx_total_num = num;
|
||||
LPI2C->transfer.rx_curr_cnt = 0U;
|
||||
|
||||
LPI2C->transfer.tx_buf = NULL;
|
||||
LPI2C->transfer.tx_total_num = 0U;
|
||||
LPI2C->transfer.tx_curr_cnt = 0U;
|
||||
|
||||
return ARM_DRIVER_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief : CMSIS-Driver lpi2c get transfer data count
|
||||
* @note : it can be either transmit or receive data count which perform last
|
||||
* (useful only in interrupt mode)
|
||||
* @param : LPI2C : Pointer to lpi2c resources structure
|
||||
* @retval : transfer data count
|
||||
*/
|
||||
static int32_t ARM_LPI2C_GetDataCount(const LPI2C_RESOURCES *LPI2C)
|
||||
{
|
||||
int32_t ret;
|
||||
|
||||
if (LPI2C->transfer.tx_buf != NULL)
|
||||
{
|
||||
ret = LPI2C->transfer.tx_curr_cnt;
|
||||
}
|
||||
else
|
||||
{
|
||||
ret = LPI2C->transfer.rx_curr_cnt;
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief : CMSIS-Driver lpi2c get status
|
||||
* @note : none
|
||||
* @param : LPI2C : Pointer to lpi2c resources structure
|
||||
* @retval : ARM_i2c_STATUS
|
||||
*/
|
||||
static ARM_I2C_STATUS ARM_LPI2C_GetStatus(const LPI2C_RESOURCES *LPI2C)
|
||||
{
|
||||
return LPI2C->status;
|
||||
}
|
||||
|
||||
/* LPI2C Driver Instance */
|
||||
#if (RTE_LPI2C)
|
||||
|
||||
/* LPI2C Driver Resources */
|
||||
static LPI2C_RESOURCES LPI2C_RES =
|
||||
{
|
||||
.regs = (LPI2C_TYPE *)LPI2C_BASE,
|
||||
.irq_num = (IRQn_Type)LPI2C_IRQ_IRQn,
|
||||
.irq_priority = (uint32_t)RTE_LPI2C_IRQ_PRIORITY
|
||||
};
|
||||
|
||||
void LPI2C_IRQHandler(void)
|
||||
{
|
||||
LPI2C_RESOURCES *res = &LPI2C_RES;
|
||||
|
||||
LPI2C_TYPE *lpi2c = (LPI2C_RES.regs);
|
||||
LPI2C_XFER_INFO_T *transfer = &(LPI2C_RES.transfer);
|
||||
|
||||
/* Storing receive value to the buffer */
|
||||
transfer->rx_buf[transfer->rx_curr_cnt++] = lpi2c->LPI2C_DATA;
|
||||
|
||||
if (transfer->rx_curr_cnt == (transfer->rx_total_num))
|
||||
{
|
||||
res->status.busy = 0U;
|
||||
/* receive complete successfully. */
|
||||
res->cb_event(ARM_I2C_EVENT_TRANSFER_DONE);
|
||||
}
|
||||
}
|
||||
|
||||
static int32_t LPI2C_Initialize (ARM_I2C_SignalEvent_t cb_event)
|
||||
{
|
||||
return ARM_LPI2C_Initialize(cb_event, &LPI2C_RES);
|
||||
}
|
||||
|
||||
static int32_t LPI2C_Uninitialize(void)
|
||||
{
|
||||
return ARM_LPI2C_Uninitialize(&LPI2C_RES);
|
||||
}
|
||||
|
||||
static int32_t LPI2C_PowerControl(ARM_POWER_STATE state)
|
||||
{
|
||||
return ARM_LPI2C_PowerControl(state, &LPI2C_RES);
|
||||
}
|
||||
|
||||
static int32_t LPI2C_MasterTransmit(uint32_t addr, const uint8_t *data,
|
||||
uint32_t num, bool xfer_pending)
|
||||
{
|
||||
ARG_UNUSED(addr);
|
||||
ARG_UNUSED(data);
|
||||
ARG_UNUSED(num);
|
||||
ARG_UNUSED(xfer_pending);
|
||||
/* lpi2c is slave-only */
|
||||
return ARM_DRIVER_ERROR;
|
||||
}
|
||||
|
||||
static int32_t LPI2C_MasterReceive(uint32_t addr, uint8_t *data,
|
||||
uint32_t num, bool xfer_pending)
|
||||
{
|
||||
|
||||
ARG_UNUSED(addr);
|
||||
ARG_UNUSED(data);
|
||||
ARG_UNUSED(num);
|
||||
ARG_UNUSED(xfer_pending);
|
||||
/* lpi2c is slave-only */
|
||||
return ARM_DRIVER_ERROR;
|
||||
}
|
||||
|
||||
static int32_t LPI2C_SlaveTransmit(const uint8_t *data, uint32_t num)
|
||||
{
|
||||
return (ARM_LPI2C_SlaveTransmit(&LPI2C_RES, data, num));
|
||||
}
|
||||
|
||||
static int32_t LPI2C_SlaveReceive(uint8_t *data, uint32_t num)
|
||||
{
|
||||
return (ARM_LPI2C_SlaveReceive(&LPI2C_RES, data, num));
|
||||
}
|
||||
|
||||
static int32_t LPI2C_GetDataCount(void)
|
||||
{
|
||||
return (ARM_LPI2C_GetDataCount(&LPI2C_RES));
|
||||
}
|
||||
|
||||
static int32_t LPI2C_Control(uint32_t control, uint32_t arg)
|
||||
{
|
||||
ARG_UNUSED(control);
|
||||
ARG_UNUSED(arg);
|
||||
return ARM_DRIVER_ERROR;
|
||||
}
|
||||
|
||||
static ARM_I2C_STATUS LPI2C_GetStatus(void)
|
||||
{
|
||||
return (ARM_LPI2C_GetStatus(&LPI2C_RES));
|
||||
}
|
||||
|
||||
/* LPI2C Driver Control Block */
|
||||
extern ARM_DRIVER_I2C Driver_LPI2C;
|
||||
ARM_DRIVER_I2C Driver_LPI2C = {
|
||||
ARM_I2C_GetVersion,
|
||||
ARM_I2C_GetCapabilities,
|
||||
LPI2C_Initialize,
|
||||
LPI2C_Uninitialize,
|
||||
LPI2C_PowerControl,
|
||||
LPI2C_MasterTransmit,
|
||||
LPI2C_MasterReceive,
|
||||
LPI2C_SlaveTransmit,
|
||||
LPI2C_SlaveReceive,
|
||||
LPI2C_GetDataCount,
|
||||
LPI2C_Control,
|
||||
LPI2C_GetStatus
|
||||
};
|
||||
|
||||
#endif /*(RTE_LPI2C)*/
|
||||
41
src/hal/alif/Alif_CMSIS/Source/Driver_LPI2C_Private.h
Normal file
41
src/hal/alif/Alif_CMSIS/Source/Driver_LPI2C_Private.h
Normal file
@ -0,0 +1,41 @@
|
||||
/* Copyright (C) 2023 Alif Semiconductor - All Rights Reserved.
|
||||
* Use, distribution and modification of this code is permitted under the
|
||||
* terms stated in the Alif Semiconductor Software License Agreement
|
||||
*
|
||||
* You should have received a copy of the Alif Semiconductor Software
|
||||
* License Agreement with this file. If not, please write to:
|
||||
* contact@alifsemi.com, or visit: https://alifsemi.com/license
|
||||
*
|
||||
*/
|
||||
|
||||
/*---Project include ----*/
|
||||
#include "Driver_I2C.h"
|
||||
#include "lpi2c.h"
|
||||
|
||||
/*---System include ----*/
|
||||
#include "RTE_Device.h"
|
||||
#include "RTE_Components.h"
|
||||
#include CMSIS_device_header
|
||||
|
||||
#ifndef DRIVER_LPI2C_PRIVATE_H_
|
||||
#define DRIVER_LPI2C_PRIVATE_H_
|
||||
|
||||
typedef volatile struct _LPI2C_DRIVER_STATE {
|
||||
uint32_t initialized : 1; /**< Driver Initialized */
|
||||
uint32_t powered : 1; /**< Driver powered */
|
||||
uint32_t reserved : 30; /**< Reserved */
|
||||
} LPI2C_DRIVER_STATE;
|
||||
|
||||
/* @brief Structure to save contexts for a lpi2c channel */
|
||||
typedef struct _LPI2C_RESOURCES{
|
||||
ARM_I2C_SignalEvent_t cb_event;
|
||||
ARM_I2C_STATUS status;
|
||||
LPI2C_TYPE *regs;
|
||||
LPI2C_DRIVER_STATE state;
|
||||
LPI2C_XFER_INFO_T transfer;
|
||||
uint32_t clk;
|
||||
IRQn_Type irq_num;
|
||||
uint32_t irq_priority;
|
||||
}LPI2C_RESOURCES;
|
||||
|
||||
#endif /* DRIVER_LPI2C_PRIVATE_H_ */
|
||||
423
src/hal/alif/Alif_CMSIS/Source/Driver_LPTIMER.c
Normal file
423
src/hal/alif/Alif_CMSIS/Source/Driver_LPTIMER.c
Normal file
@ -0,0 +1,423 @@
|
||||
/* Copyright (C) 2023 Alif Semiconductor - All Rights Reserved.
|
||||
* Use, distribution and modification of this code is permitted under the
|
||||
* terms stated in the Alif Semiconductor Software License Agreement
|
||||
*
|
||||
* You should have received a copy of the Alif Semiconductor Software
|
||||
* License Agreement with this file. If not, please write to:
|
||||
* contact@alifsemi.com, or visit: https://alifsemi.com/license
|
||||
*
|
||||
*/
|
||||
|
||||
/**************************************************************************//**
|
||||
* @file Driver_LPTIMER.c
|
||||
* @author Girish BN, Manoj A Murudi
|
||||
* @email girish.bn@alifsemi.com, manoj.murudi@alifsemi.com
|
||||
* @version V1.0.0
|
||||
* @date 27-March-2023
|
||||
* @brief CMSIS_Driver for LPTIMER.
|
||||
* @bug None.
|
||||
* @Note None
|
||||
******************************************************************************/
|
||||
|
||||
#include "Driver_LPTIMER.h"
|
||||
#include "Driver_LPTIMER_Private.h"
|
||||
|
||||
#if !(RTE_LPTIMER)
|
||||
#error "LPTIMER is not enabled in RTE_Device.h"
|
||||
#endif
|
||||
|
||||
#if !defined(RTE_Drivers_LPTIMER)
|
||||
#error "LPTIMER is not enabled in the RTE_Components.h"
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @fn int32_t ARM_LPTIMER_Initialize(LPTIMER_RESOURCES *LPTIMER_RES, uint8_t channel, ARM_LPTIMER_SignalEvent_t cb_event)
|
||||
* @brief Initialize the LPTIMER.
|
||||
* @note none.
|
||||
* @param LPTIMER_RES : Pointer to LPTIMER resources structure.
|
||||
* @param channel : Used LPTIMER channel.
|
||||
* @param cb_event : Pointer to user callback function.
|
||||
* @retval \ref execution_status
|
||||
*/
|
||||
static int32_t ARM_LPTIMER_Initialize (LPTIMER_RESOURCES *LPTIMER_RES, uint8_t channel, ARM_LPTIMER_SignalEvent_t cb_event)
|
||||
{
|
||||
if (cb_event == NULL)
|
||||
{
|
||||
return ARM_DRIVER_ERROR_PARAMETER;
|
||||
}
|
||||
|
||||
if (channel >= LPTIMER_MAX_CHANNEL_NUMBER)
|
||||
{
|
||||
return ARM_DRIVER_ERROR_PARAMETER;
|
||||
}
|
||||
if (LPTIMER_RES->ch_info[channel].state.initialized == 1)
|
||||
{
|
||||
return ARM_DRIVER_OK;
|
||||
}
|
||||
|
||||
LPTIMER_RES->ch_info[channel].CB_function_ptr = cb_event;
|
||||
|
||||
if (((channel == LPTIMER_CHANNEL_0) || (channel == LPTIMER_CHANNEL_2)) &&
|
||||
(LPTIMER_RES->ch_info[channel].clk_src > LPTIMER_CLK_EXT_SOURCE))
|
||||
{
|
||||
/* channel 0 & 2 does not support cascaded input */
|
||||
return ARM_DRIVER_ERROR;
|
||||
}
|
||||
else if (LPTIMER_RES->ch_info[channel].clk_src > LPTIMER_CLK_SOURCE_CASCADE)
|
||||
{
|
||||
return ARM_DRIVER_ERROR;
|
||||
}
|
||||
|
||||
/* Input Clock select for LPTIMER */
|
||||
select_lptimer_clk (LPTIMER_RES->ch_info[channel].clk_src, channel);
|
||||
|
||||
if (LPTIMER_RES->ch_info[channel].mode)
|
||||
{
|
||||
/* set lptimer as freerun mode */
|
||||
lptimer_set_mode_freerunning (LPTIMER_RES->regs, channel);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* set lptimer as user-defined mode */
|
||||
lptimer_set_mode_userdefined (LPTIMER_RES->regs, channel);
|
||||
}
|
||||
|
||||
/* unmask channel interrupt */
|
||||
lptimer_unmask_interrupt (LPTIMER_RES->regs, channel);
|
||||
|
||||
LPTIMER_RES->ch_info[channel].state.initialized = 1;
|
||||
|
||||
return ARM_DRIVER_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @fn int32_t ARM_LPTIMER_PowerControl (LPTIMER_RESOURCES *LPTIMER, uint8_t channel, ARM_POWER_STATE state).
|
||||
* @brief Handles the LPTIMER power.
|
||||
* @note none.
|
||||
* @param LPTIMER_RES : Pointer to LPTIMER resources structure.
|
||||
* @param channel : used LPTIMER channel.
|
||||
* @param state : power state.
|
||||
* @retval \ref execution_status
|
||||
*/
|
||||
static int32_t ARM_LPTIMER_PowerControl (LPTIMER_RESOURCES *LPTIMER_RES, uint8_t channel, ARM_POWER_STATE state)
|
||||
{
|
||||
if (channel >= LPTIMER_MAX_CHANNEL_NUMBER)
|
||||
{
|
||||
return ARM_DRIVER_ERROR_PARAMETER;
|
||||
}
|
||||
if (state > ARM_POWER_FULL)
|
||||
{
|
||||
return ARM_DRIVER_ERROR_PARAMETER;
|
||||
}
|
||||
|
||||
switch (state)
|
||||
{
|
||||
case ARM_POWER_OFF:
|
||||
{
|
||||
if (LPTIMER_RES->ch_info[channel].state.powered == 0)
|
||||
{
|
||||
return ARM_DRIVER_OK;
|
||||
}
|
||||
|
||||
NVIC_ClearPendingIRQ(LPTIMER_CHANNEL_IRQ(channel));
|
||||
NVIC_DisableIRQ(LPTIMER_CHANNEL_IRQ(channel));
|
||||
|
||||
LPTIMER_RES->ch_info[channel].state.powered = 0;
|
||||
break;
|
||||
}
|
||||
case ARM_POWER_FULL:
|
||||
{
|
||||
if (LPTIMER_RES->ch_info[channel].state.powered == 1)
|
||||
{
|
||||
return ARM_DRIVER_OK;
|
||||
}
|
||||
|
||||
if (LPTIMER_RES->ch_info[channel].state.initialized == 1)
|
||||
{
|
||||
NVIC_ClearPendingIRQ(LPTIMER_CHANNEL_IRQ(channel));
|
||||
NVIC_SetPriority(LPTIMER_CHANNEL_IRQ(channel), LPTIMER_RES->ch_info[channel].irq_priority);
|
||||
NVIC_EnableIRQ(LPTIMER_CHANNEL_IRQ(channel));
|
||||
|
||||
LPTIMER_RES->ch_info[channel].state.powered = 1;
|
||||
}
|
||||
else
|
||||
{
|
||||
return ARM_DRIVER_ERROR;
|
||||
}
|
||||
break;
|
||||
}
|
||||
case ARM_POWER_LOW:
|
||||
{
|
||||
return ARM_DRIVER_ERROR_UNSUPPORTED;
|
||||
}
|
||||
}
|
||||
|
||||
return ARM_DRIVER_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @fn int32_t ARM_LPTIMER_Control (LPTIMER_RESOURCES *LPTIMER_RES, uint8_t channel, uint32_t control_code, void *arg)
|
||||
* @brief Used to configure LPTIMER.
|
||||
* @note none.
|
||||
* @param LPTIMER_RES : Pointer to LPTIMER resources structure.
|
||||
* @param channel : used LPTIMER channel.
|
||||
* @param control_code : control code.
|
||||
* @param arg : argument.
|
||||
* @retval \ref execution_status
|
||||
*/
|
||||
static int32_t ARM_LPTIMER_Control (LPTIMER_RESOURCES *LPTIMER_RES, uint8_t channel, uint32_t control_code, void *arg)
|
||||
{
|
||||
if (arg == NULL)
|
||||
{
|
||||
return ARM_DRIVER_ERROR_PARAMETER;
|
||||
}
|
||||
if (channel >= LPTIMER_MAX_CHANNEL_NUMBER)
|
||||
{
|
||||
return ARM_DRIVER_ERROR_PARAMETER;
|
||||
}
|
||||
if (control_code > ARM_LPTIMER_GET_COUNT)
|
||||
{
|
||||
return ARM_DRIVER_ERROR_PARAMETER;
|
||||
}
|
||||
|
||||
if (LPTIMER_RES->ch_info[channel].state.powered == 0)
|
||||
{
|
||||
return ARM_DRIVER_ERROR;
|
||||
}
|
||||
|
||||
switch (control_code)
|
||||
{
|
||||
case ARM_LPTIMER_SET_COUNT1:
|
||||
{
|
||||
if (LPTIMER_RES->ch_info[channel].mode == LPTIMER_FREE_RUN_MODE)
|
||||
{
|
||||
/* load maximum counter value*/
|
||||
lptimer_load_max_count(LPTIMER_RES->regs, channel);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* load counter value */
|
||||
lptimer_load_count (LPTIMER_RES->regs, channel, arg);
|
||||
}
|
||||
|
||||
LPTIMER_RES->ch_info[channel].state.set_count1 = 1;
|
||||
break;
|
||||
}
|
||||
case ARM_LPTIMER_SET_COUNT2:
|
||||
{
|
||||
return ARM_DRIVER_ERROR_UNSUPPORTED;
|
||||
}
|
||||
case ARM_LPTIMER_GET_COUNT:
|
||||
{
|
||||
if (LPTIMER_RES->ch_info[channel].state.started == 0)
|
||||
{
|
||||
return ARM_DRIVER_ERROR;
|
||||
}
|
||||
|
||||
/* get current count value */
|
||||
*(uint32_t*)arg |= lptimer_get_count (LPTIMER_RES->regs, channel);
|
||||
break;
|
||||
}
|
||||
default:
|
||||
return ARM_DRIVER_ERROR;
|
||||
}
|
||||
|
||||
return ARM_DRIVER_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @fn int32_t ARM_LPTIMER_Start (LPTIMER_RESOURCES *LPTIMER, uint8_t channel)
|
||||
* @brief Used to start LPTIMER counter.
|
||||
* @note none.
|
||||
* @param LPTIMER_RES : Pointer to LPTIMER resources structure.
|
||||
* @param channel : used LPTIMER channel.
|
||||
* @retval \ref execution_status
|
||||
*/
|
||||
static int32_t ARM_LPTIMER_Start (LPTIMER_RESOURCES *LPTIMER_RES, uint8_t channel)
|
||||
{
|
||||
if (channel >= LPTIMER_MAX_CHANNEL_NUMBER)
|
||||
{
|
||||
return ARM_DRIVER_ERROR_PARAMETER;
|
||||
}
|
||||
|
||||
if (LPTIMER_RES->ch_info[channel].state.started == 1)
|
||||
{
|
||||
return ARM_DRIVER_OK;
|
||||
}
|
||||
|
||||
if (LPTIMER_RES->ch_info[channel].state.powered == 0)
|
||||
{
|
||||
return ARM_DRIVER_ERROR;
|
||||
}
|
||||
|
||||
if (LPTIMER_RES->ch_info[channel].state.set_count1 == 0)
|
||||
{
|
||||
return ARM_DRIVER_ERROR;
|
||||
}
|
||||
|
||||
/* enable channel counter */
|
||||
lptimer_enable_counter (LPTIMER_RES->regs, channel);
|
||||
|
||||
LPTIMER_RES->ch_info[channel].state.started = 1;
|
||||
|
||||
return ARM_DRIVER_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @fn int32_t ARM_LPTIMER_Stop (LPTIMER_RESOURCES *LPTIMER_RES, uint8_t channel)
|
||||
* @brief Used to stop LPTIMER counter.
|
||||
* @note none.
|
||||
* @param LPTIMER_RES : Pointer to LPTIMER resources structure.
|
||||
* @param channel : used LPTIMER channel.
|
||||
* @retval \ref execution_status
|
||||
*/
|
||||
static int32_t ARM_LPTIMER_Stop (LPTIMER_RESOURCES *LPTIMER_RES, uint8_t channel)
|
||||
{
|
||||
if (channel >= LPTIMER_MAX_CHANNEL_NUMBER)
|
||||
{
|
||||
return ARM_DRIVER_ERROR_PARAMETER;
|
||||
}
|
||||
|
||||
/* disable channel counter */
|
||||
lptimer_disable_counter (LPTIMER_RES->regs, channel);
|
||||
|
||||
LPTIMER_RES->ch_info[channel].state.started = 0;
|
||||
|
||||
return ARM_DRIVER_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @fn int32_t ARM_LPTIMER_Uninitialize (LPTIMER_RESOURCES *LPTIMER, uint8_t channel)
|
||||
* @brief Un-Initialize the LPTIMER.
|
||||
* @note none.
|
||||
* @param LPTIMER_RES : Pointer to lptimer resources structure.
|
||||
* @param channel : used LPTIMER channel.
|
||||
* @retval \ref execution_status
|
||||
*/
|
||||
static int32_t ARM_LPTIMER_Uninitialize (LPTIMER_RESOURCES *LPTIMER_RES, uint8_t channel)
|
||||
{
|
||||
if (channel >= LPTIMER_MAX_CHANNEL_NUMBER)
|
||||
{
|
||||
return ARM_DRIVER_ERROR_PARAMETER;
|
||||
}
|
||||
|
||||
if (LPTIMER_RES->ch_info[channel].state.initialized == 0)
|
||||
{
|
||||
return ARM_DRIVER_OK;
|
||||
}
|
||||
|
||||
LPTIMER_RES->ch_info[channel].CB_function_ptr = NULL;
|
||||
|
||||
LPTIMER_RES->ch_info[channel].state.initialized = 0;
|
||||
|
||||
return ARM_DRIVER_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @fn int32_t LPTIMER_Irq_Handler (LPTIMER_RESOURCES *LPTIMER_RES, uint8_t channel)
|
||||
* @brief LPTIMER interrupt handler.
|
||||
* @note none.
|
||||
* @param LPTIMER_RES : Pointer to lptimer resources structure.
|
||||
* @param channel : used LPTIMER channel.
|
||||
* @retval \ref execution_status
|
||||
*/
|
||||
static int32_t LPTIMER_Irq_Handler (LPTIMER_RESOURCES *LPTIMER_RES, uint8_t channel)
|
||||
{
|
||||
/* clear channel interrupt */
|
||||
lptimer_clear_interrupt (LPTIMER_RES->regs, channel);
|
||||
|
||||
LPTIMER_RES->ch_info[channel].CB_function_ptr(ARM_LPTIMER_EVENT_UNDERFLOW);
|
||||
|
||||
return ARM_DRIVER_OK;
|
||||
}
|
||||
|
||||
/* LPTIMER0 Driver Instance */
|
||||
#if (RTE_LPTIMER)
|
||||
|
||||
static LPTIMER_RESOURCES LPTIMER0 = {
|
||||
.regs = (LPTIMER_Type*) LPTIMER_BASE,
|
||||
.ch_info[0] = {
|
||||
.mode = RTE_LPTIMER_CHANNEL0_FREE_RUN_MODE,
|
||||
.clk_src = RTE_LPTIMER_CHANNEL0_CLK_SRC,
|
||||
.irq_priority = RTE_LPTIMER_CHANNEL0_IRQ_PRIORITY
|
||||
},
|
||||
.ch_info[1] = {
|
||||
.mode = RTE_LPTIMER_CHANNEL1_FREE_RUN_MODE,
|
||||
.clk_src = RTE_LPTIMER_CHANNEL1_CLK_SRC,
|
||||
.irq_priority = RTE_LPTIMER_CHANNEL1_IRQ_PRIORITY
|
||||
},
|
||||
.ch_info[2] = {
|
||||
.mode = RTE_LPTIMER_CHANNEL2_FREE_RUN_MODE,
|
||||
.clk_src = RTE_LPTIMER_CHANNEL2_CLK_SRC,
|
||||
.irq_priority = RTE_LPTIMER_CHANNEL2_IRQ_PRIORITY
|
||||
},
|
||||
.ch_info[3] = {
|
||||
.mode = RTE_LPTIMER_CHANNEL3_FREE_RUN_MODE,
|
||||
.clk_src = RTE_LPTIMER_CHANNEL3_CLK_SRC,
|
||||
.irq_priority = RTE_LPTIMER_CHANNEL3_IRQ_PRIORITY
|
||||
}
|
||||
};
|
||||
|
||||
void LPTIMER0_IRQHandler (void)
|
||||
{
|
||||
LPTIMER_Irq_Handler (&LPTIMER0, LPTIMER_CHANNEL_0);
|
||||
}
|
||||
|
||||
void LPTIMER1_IRQHandler (void)
|
||||
{
|
||||
LPTIMER_Irq_Handler (&LPTIMER0, LPTIMER_CHANNEL_1);
|
||||
}
|
||||
|
||||
void LPTIMER2_IRQHandler (void)
|
||||
{
|
||||
LPTIMER_Irq_Handler (&LPTIMER0, LPTIMER_CHANNEL_2);
|
||||
}
|
||||
|
||||
void LPTIMER3_IRQHandler (void)
|
||||
{
|
||||
LPTIMER_Irq_Handler (&LPTIMER0, LPTIMER_CHANNEL_3);
|
||||
}
|
||||
|
||||
static int32_t ARM_LPTIMER0_Initialize (uint8_t channel, ARM_LPTIMER_SignalEvent_t cb_unit_event)
|
||||
{
|
||||
return ARM_LPTIMER_Initialize (&LPTIMER0, channel, cb_unit_event);
|
||||
}
|
||||
|
||||
static int32_t ARM_LPTIMER0_PowerControl (uint8_t channel, ARM_POWER_STATE state)
|
||||
{
|
||||
return ARM_LPTIMER_PowerControl (&LPTIMER0, channel, state);
|
||||
}
|
||||
|
||||
static int32_t ARM_LPTIMER0_Control (uint8_t channel, uint32_t control_code, void *arg)
|
||||
{
|
||||
return ARM_LPTIMER_Control (&LPTIMER0, channel, control_code, arg);
|
||||
}
|
||||
|
||||
static int32_t ARM_LPTIMER0_Start (uint8_t channel)
|
||||
{
|
||||
return ARM_LPTIMER_Start (&LPTIMER0, channel);
|
||||
}
|
||||
|
||||
static int32_t ARM_LPTIMER0_Stop (uint8_t channel)
|
||||
{
|
||||
return ARM_LPTIMER_Stop (&LPTIMER0, channel);
|
||||
}
|
||||
|
||||
static int32_t ARM_LPTIMER0_Uninitialize (uint8_t channel)
|
||||
{
|
||||
return ARM_LPTIMER_Uninitialize (&LPTIMER0, channel);
|
||||
}
|
||||
|
||||
/*LPTIMER Resources Control Block */
|
||||
extern ARM_DRIVER_LPTIMER DRIVER_LPTIMER0;
|
||||
ARM_DRIVER_LPTIMER DRIVER_LPTIMER0 = {
|
||||
ARM_LPTIMER0_Initialize,
|
||||
ARM_LPTIMER0_PowerControl,
|
||||
ARM_LPTIMER0_Control,
|
||||
ARM_LPTIMER0_Start,
|
||||
ARM_LPTIMER0_Stop,
|
||||
ARM_LPTIMER0_Uninitialize
|
||||
};
|
||||
#endif /* RTE_LPTIMER */
|
||||
|
||||
/************************ (C) COPYRIGHT ALIF SEMICONDUCTOR *****END OF FILE****/
|
||||
78
src/hal/alif/Alif_CMSIS/Source/Driver_LPTIMER_Private.h
Normal file
78
src/hal/alif/Alif_CMSIS/Source/Driver_LPTIMER_Private.h
Normal file
@ -0,0 +1,78 @@
|
||||
/* Copyright (C) 2023 Alif Semiconductor - All Rights Reserved.
|
||||
* Use, distribution and modification of this code is permitted under the
|
||||
* terms stated in the Alif Semiconductor Software License Agreement
|
||||
*
|
||||
* You should have received a copy of the Alif Semiconductor Software
|
||||
* License Agreement with this file. If not, please write to:
|
||||
* contact@alifsemi.com, or visit: https://alifsemi.com/license
|
||||
*
|
||||
*/
|
||||
|
||||
/**************************************************************************//**
|
||||
* @file Driver_LPTIMER_Private.h
|
||||
* @author Girish BN, Manoj A Murudi
|
||||
* @email girish.bn@alifsemi.com, manoj.murudi@alifsemi.com
|
||||
* @version V1.0.0
|
||||
* @date 27-March-2023
|
||||
* @brief Header file for LPTIMER.
|
||||
* @bug None.
|
||||
* @Note None
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef DRIVER_LPTIMER_PRIVATE_H_
|
||||
#define DRIVER_LPTIMER_PRIVATE_H_
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
#include "RTE_Device.h"
|
||||
#include "RTE_Components.h"
|
||||
#include CMSIS_device_header
|
||||
|
||||
#include "Driver_LPTIMER.h"
|
||||
#include "lptimer.h"
|
||||
#include "sys_ctrl_lptimer.h"
|
||||
|
||||
#define LPTIMER_MAX_CHANNEL_NUMBER 0x4U
|
||||
#define LPTIMER_CHANNEL_0 0x0U
|
||||
#define LPTIMER_CHANNEL_1 0x1U
|
||||
#define LPTIMER_CHANNEL_2 0x2U
|
||||
#define LPTIMER_CHANNEL_3 0x3U
|
||||
|
||||
#define LPTIMER_FREE_RUN_MODE 0x1U /* To enable Free Run mode in lptimer */
|
||||
#define LPTIMER_USER_RUN_MODE 0x0U /* To enable user mode in lptimer */
|
||||
#define LPTIMER_CHANNEL_IRQ(chnl) (LPTIMER0_IRQ_IRQn + chnl) /* Get corresponding irq number */
|
||||
|
||||
/** \brief LPTIMER Driver states. */
|
||||
typedef volatile struct _LPTIMER_DRIVER_STATE {
|
||||
uint32_t initialized : 1; /* Driver Initialized*/
|
||||
uint32_t powered : 1; /* Driver powered */
|
||||
uint32_t started : 1; /* Driver counter started */
|
||||
uint32_t set_count1 : 1; /* Driver set count 1 */
|
||||
uint32_t reserved : 28;/* Reserved */
|
||||
} LPTIMER_DRIVER_STATE;
|
||||
|
||||
/** \brief LPTIMER channel information block. */
|
||||
typedef struct _LPTIMER_CHANNEL_INFO {
|
||||
uint8_t irq_priority; /**< channel IRQ priority information >*/
|
||||
bool mode; /**< channel mode user or free run >*/
|
||||
LPTIMER_CLK_SRC clk_src; /**< channel clock source >*/
|
||||
LPTIMER_DRIVER_STATE state; /**< channel state >*/
|
||||
ARM_LPTIMER_SignalEvent_t CB_function_ptr; /**< channel call back function >*/
|
||||
} LPTIMER_CHANNEL_INFO;
|
||||
|
||||
/** \brief Resources for a LPTIMER instance. */
|
||||
typedef struct _LPTIMER_RESOURCES {
|
||||
LPTIMER_Type *regs; /**< LPTIMER Register address >*/
|
||||
LPTIMER_CHANNEL_INFO ch_info[LPTIMER_MAX_CHANNEL_NUMBER]; /**< Pointer to Info structure of LPTIMER>*/
|
||||
} LPTIMER_RESOURCES;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* DRIVER_LPTIMER_PRIVATE_H_ */
|
||||
|
||||
/************************ (C) COPYRIGHT ALIF SEMICONDUCTOR *****END OF FILE****/
|
||||
801
src/hal/alif/Alif_CMSIS/Source/Driver_MIPI_CSI2.c
Normal file
801
src/hal/alif/Alif_CMSIS/Source/Driver_MIPI_CSI2.c
Normal file
@ -0,0 +1,801 @@
|
||||
/* Copyright (C) 2023 Alif Semiconductor - All Rights Reserved.
|
||||
#include <Driver_MIPI_CSI2.h>
|
||||
* Use, distribution and modification of this code is permitted under the
|
||||
* terms stated in the Alif Semiconductor Software License Agreement
|
||||
*
|
||||
* You should have received a copy of the Alif Semiconductor Software
|
||||
* License Agreement with this file. If not, please write to:
|
||||
* contact@alifsemi.com, or visit: https://alifsemi.com/license
|
||||
*
|
||||
*/
|
||||
/**************************************************************************//**
|
||||
* @file Driver_MIPI_CSI2.c
|
||||
* @author Prasanna Ravi and Chandra Bhushan Singh
|
||||
* @email prasanna.ravi@alifsemi.com and chandrabhushan.singh@alifsemi.com
|
||||
* @version V1.0.0
|
||||
* @date 15-April-2023
|
||||
* @brief CMSIS-Driver for MIPI CSI2.
|
||||
* @bug None.
|
||||
* @Note None.
|
||||
******************************************************************************/
|
||||
|
||||
#include <math.h>
|
||||
|
||||
/* System Includes */
|
||||
#include "RTE_Device.h"
|
||||
#include "RTE_Components.h"
|
||||
#include CMSIS_device_header
|
||||
|
||||
/* CSI includes */
|
||||
#include "Driver_MIPI_CSI2.h"
|
||||
#include "csi.h"
|
||||
#include "DPHY_CSI2.h"
|
||||
#include "sys_ctrl_csi.h"
|
||||
#include "Driver_CSI_Private.h"
|
||||
#include "Camera_Sensor.h"
|
||||
|
||||
#if !(RTE_MIPI_CSI2)
|
||||
#error "MIPI CSI2 is not enabled in the RTE_Device.h"
|
||||
#endif
|
||||
#if (!defined(RTE_Drivers_MIPI_CSI2))
|
||||
#error "MIPI CSI2 not configured in RTE_Components.h!"
|
||||
#endif
|
||||
|
||||
#define ARM_MIPI_CSI2_DRV_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(1, 0)
|
||||
|
||||
/*Driver version*/
|
||||
static const ARM_DRIVER_VERSION DriverVersion =
|
||||
{
|
||||
ARM_MIPI_CSI2_API_VERSION,
|
||||
ARM_MIPI_CSI2_DRV_VERSION
|
||||
};
|
||||
|
||||
/* Driver Capabilities */
|
||||
static const ARM_MIPI_CSI2_CAPABILITIES DriverCapabilities =
|
||||
{
|
||||
0, /* Not supports reentrant_operation */
|
||||
1, /* IPI interface supported*/
|
||||
0, /* IDI interface not supported*/
|
||||
0 /* reserved (must be zero) */
|
||||
};
|
||||
|
||||
/* CSI, CPI related Data mode settings table */
|
||||
static const CSI_CPI_DATA_MODE_SETTINGS cpi_data_mode_settings[] =
|
||||
{
|
||||
{CSI_DT_RAW6, CSI_IPI_COLOR_COM_TYPE_COLOR16, CPI_COLOR_MODE_CONFIG_IPI16_RAW6, CPI_DATA_MODE_BIT_8, 8},
|
||||
{CSI_DT_RAW7, CSI_IPI_COLOR_COM_TYPE_COLOR16, CPI_COLOR_MODE_CONFIG_IPI16_RAW7, CPI_DATA_MODE_BIT_8, 8},
|
||||
{CSI_DT_RAW8, CSI_IPI_COLOR_COM_TYPE_COLOR16, CPI_COLOR_MODE_CONFIG_IPI16_RAW8, CPI_DATA_MODE_BIT_8, 8},
|
||||
{CSI_DT_RAW10, CSI_IPI_COLOR_COM_TYPE_COLOR16, CPI_COLOR_MODE_CONFIG_IPI16_RAW10, CPI_DATA_MODE_BIT_16, 10},
|
||||
{CSI_DT_RAW12, CSI_IPI_COLOR_COM_TYPE_COLOR16, CPI_COLOR_MODE_CONFIG_IPI16_RAW12, CPI_DATA_MODE_BIT_16, 12},
|
||||
{CSI_DT_RAW14, CSI_IPI_COLOR_COM_TYPE_COLOR16, CPI_COLOR_MODE_CONFIG_IPI16_RAW14, CPI_DATA_MODE_BIT_16, 14},
|
||||
{CSI_DT_RAW16, CSI_IPI_COLOR_COM_TYPE_COLOR16, CPI_COLOR_MODE_CONFIG_IPI16_RAW16, CPI_DATA_MODE_BIT_16, 16},
|
||||
{CSI_DT_RGB444, CSI_IPI_COLOR_COM_TYPE_COLOR48, CPI_COLOR_MODE_CONFIG_IPI48_RGB444, CPI_DATA_MODE_BIT_16, 16},
|
||||
{CSI_DT_RGB555, CSI_IPI_COLOR_COM_TYPE_COLOR48, CPI_COLOR_MODE_CONFIG_IPI48_RGB555, CPI_DATA_MODE_BIT_16, 16},
|
||||
{CSI_DT_RGB565, CSI_IPI_COLOR_COM_TYPE_COLOR48, CPI_COLOR_MODE_CONFIG_IPI48_RGB565, CPI_DATA_MODE_BIT_16, 16},
|
||||
{CSI_DT_RGB666, CSI_IPI_COLOR_COM_TYPE_COLOR48, CPI_COLOR_MODE_CONFIG_IPI48_RGB666, CPI_DATA_MODE_BIT_32, 18},
|
||||
{CSI_DT_RGB888, CSI_IPI_COLOR_COM_TYPE_COLOR48, CPI_COLOR_MODE_CONFIG_IPI48_XRGB888, CPI_DATA_MODE_BIT_32, 24},
|
||||
};
|
||||
|
||||
/* CSI, CPI config informations */
|
||||
static CPI_INFO cpi_info;
|
||||
|
||||
/**
|
||||
\fn ARM_DRIVER_VERSION MIPI_CSI2_GetVersion (void)
|
||||
\brief Get MIPI CSI2 driver version.
|
||||
\return \ref ARM_DRIVER_VERSION
|
||||
*/
|
||||
static ARM_DRIVER_VERSION MIPI_CSI2_GetVersion (void)
|
||||
{
|
||||
return DriverVersion;
|
||||
}
|
||||
|
||||
/**
|
||||
\fn ARM_MIPI_CSI2_CAPABILITIES MIPI_CSI2_GetCapabilities (void)
|
||||
\brief Get MIPI CSI2 driver capabilities
|
||||
\return \ref ARM_MIPI_DPHY_CAPABILITIES
|
||||
*/
|
||||
static ARM_MIPI_CSI2_CAPABILITIES MIPI_CSI2_GetCapabilities (void)
|
||||
{
|
||||
return DriverCapabilities;
|
||||
}
|
||||
|
||||
/**
|
||||
\fn int32_t CSI2_Initialize (ARM_MIPI_CSI2_SignalEvent_t cb_event,
|
||||
CSI_RESOURCES *CSI2)
|
||||
\brief Initialize MIPI CSI2 Interface.
|
||||
\param[in] cb_event Pointer to ARM_MIPI_CSI2_SignalEvent_t
|
||||
\param[in] CSI2 Pointer to CSI resources
|
||||
\return \ref execution_status
|
||||
*/
|
||||
static int32_t CSI2_Initialize (ARM_MIPI_CSI2_SignalEvent_t cb_event,
|
||||
CSI_RESOURCES *CSI2)
|
||||
{
|
||||
int32_t ret = ARM_DRIVER_OK;
|
||||
CAMERA_SENSOR_DEVICE *camera_sensor;
|
||||
CSI_IPI_INFO *ipi_info = CSI2->ipi_info;
|
||||
CSI_FRAME_INFO *frame_info = ipi_info->frame_info;
|
||||
CSI_INFO *csi_info;
|
||||
unsigned int index;
|
||||
float pixclock;
|
||||
|
||||
if(CSI2->status.initialized == 1)
|
||||
{
|
||||
/* Driver already initialized */
|
||||
return ARM_DRIVER_OK;
|
||||
}
|
||||
|
||||
if (!cb_event)
|
||||
{
|
||||
return ARM_DRIVER_ERROR_PARAMETER;
|
||||
}
|
||||
|
||||
camera_sensor = Get_Camera_Sensor();
|
||||
|
||||
if (!(camera_sensor && camera_sensor->csi_info))
|
||||
{
|
||||
return ARM_DRIVER_ERROR_PARAMETER;
|
||||
}
|
||||
|
||||
if(camera_sensor->interface != CAMERA_SENSOR_INTERFACE_MIPI)
|
||||
{
|
||||
return ARM_DRIVER_ERROR_PARAMETER;
|
||||
}
|
||||
|
||||
csi_info = camera_sensor->csi_info;
|
||||
|
||||
/* Get Data type related informations */
|
||||
for( index = 0; index < ARRAY_SIZE(cpi_data_mode_settings) &&
|
||||
(cpi_data_mode_settings[index].data_type != csi_info->dt);
|
||||
index++);
|
||||
|
||||
if(cpi_data_mode_settings[index].data_type != csi_info->dt)
|
||||
{
|
||||
return ARM_DRIVER_ERROR_PARAMETER;
|
||||
}
|
||||
|
||||
CSI2->pixel_data_type = csi_info->dt;
|
||||
CSI2->n_lanes = csi_info->n_lanes;
|
||||
CSI2->vc_id = csi_info->vc_id;
|
||||
ipi_info->ipi_color_com = cpi_data_mode_settings[index].ipi_color_com;
|
||||
|
||||
/* Balancing bandwidth by making output bandwidth is 20% greater then input bandwidth
|
||||
* pixel clock = (mipi_clk_freq * number_of_lane * 2 "DDR" * 1.2f "percentage" ) / (bits_per_pixel) */
|
||||
pixclock = (csi_info->frequency *
|
||||
csi_info->n_lanes * 2 * 1.2f) / cpi_data_mode_settings[index].bpp;
|
||||
|
||||
/* Pixel clock divider */
|
||||
CSI2->csi_pixclk_div = (int)(((RTE_CSI2_PIX_CLK_SEL ? (float)PLL_CLK3 : (float)(PLL_CLK1/2))/pixclock) + 0.5f);
|
||||
|
||||
/* Timing calculation for Camera mode */
|
||||
if(ipi_info->ipi_mode == CSI_IPI_MODE_CAM_TIMIMG)
|
||||
{
|
||||
float time_PPI_ns = (8.0f / csi_info->frequency) * 1000000000;
|
||||
float time_IPI_ns = (1.0f / pixclock) * 1000000000;
|
||||
float pkt2pkt_time_ns = csi_info->pkt2pkt_time.time_ns;
|
||||
uint32_t bytes_to_transmit = (camera_sensor->width * cpi_data_mode_settings[index].bpp) / 8;
|
||||
uint32_t mem_req_1, mem_req_2, min_memory_depth;
|
||||
|
||||
if (!csi_info->pkt2pkt_time.line_sync_pkt_enable)
|
||||
{
|
||||
csi_info->pkt2pkt_time.time_ns = 0;
|
||||
}
|
||||
|
||||
/* The rising edge of VSYNC comes at least 3 data clock cycles prior to DATA_EN (alias to HSYNC), So we adding 3 for HSA */
|
||||
frame_info->hsa_time = CSI2_HSA_MIN + 1;
|
||||
|
||||
/* For the pixel data to be processed correctly, the back porch time must not be less than the time between the
|
||||
* packets plus some margin.
|
||||
* (IPI_HSA_TIME + IPI_HBP_TIME)*TIPI > Pkt2PktTime + (2*ShortPktBytes/N_LANES + 2)*TPPI-HS/BytesPerHsClk
|
||||
* IPI_HBP_TIME = ((((Pkt2PktTime + (2*ShortPktBytes/N_LANES + 2)*TPPI-HS/BytesPerHsClk) / TIPI) - IPI_HSA_TIME) + 1)
|
||||
*/
|
||||
frame_info->hbp_time = ((ceil((pkt2pkt_time_ns + (2* CSI2_SHORT_PKT_BYTES / csi_info->n_lanes + 2)
|
||||
* time_PPI_ns / CSI2_BYTES_PER_HS_CLK) / time_IPI_ns) - frame_info->hsa_time) + 1);
|
||||
|
||||
if(frame_info->hbp_time < CSI2_HBP_MIN)
|
||||
{
|
||||
frame_info->hbp_time = CSI2_HBP_MIN;
|
||||
}
|
||||
|
||||
/* FIFO underflow occurs when the IPI has a higher throughput than the PHY. Configure the Horizontal Sync Delay (HSD)
|
||||
* to avoid FIFO underflow.
|
||||
* IPI_HSD_TIME > (Pkt2PktTime + (((LongPktBytes + Bytes2Transmit)/N_LANES)*TPPI-HS/BytesPerHsClk))/TIPI
|
||||
* - (IPI_HSA_TIME + IPI_HBP_TIME + IPI_HACT_TIME)
|
||||
* IPI_HSD_TIME = ((Pkt2PktTime + (((LongPktBytes + Bytes2Transmit)/N_LANES)*TPPI-HS/BytesPerHsClk))/TIPI
|
||||
* - (IPI_HSA_TIME + IPI_HBP_TIME + IPI_HACT_TIME) + 1)
|
||||
*/
|
||||
frame_info->hsd_time = (ceil((pkt2pkt_time_ns + (((CSI2_LONG_PKT_BYTES + bytes_to_transmit) / csi_info->n_lanes)
|
||||
* time_PPI_ns / CSI2_BYTES_PER_HS_CLK)) / time_IPI_ns)
|
||||
- (frame_info->hsa_time + frame_info->hbp_time + camera_sensor->width) + 1);
|
||||
|
||||
if(frame_info->hsd_time < CSI2_HSD_MIN)
|
||||
{
|
||||
frame_info->hsd_time = CSI2_HSD_MIN;
|
||||
}
|
||||
|
||||
frame_info->hactive_time = 0;
|
||||
frame_info->vsa_line = 0;
|
||||
frame_info->vbp_line = 0;
|
||||
frame_info->vfp_line = 0;
|
||||
frame_info->vactive_line = 0;
|
||||
|
||||
/* Memory calculation requirements
|
||||
* MEM_req_1 = (((IPI_HSD_TIME + IPI_HSA_TIME + IPI_HBP_TIME)*TIPI - Pkt2PktTime)/TPPI-HS)*N_LANES*BytesPerHsClk
|
||||
*
|
||||
* MEM_req_2 = (((IPI_HSD_TIME + IPI_HSA_TIME + IPI_HBP_TIME + IPI_HACT_TIME)*TIPI - Pkt2PktTime
|
||||
* - (((LongPktBytes + Bytes2Transmit)/N_LANES)*TPPI-HS))/TPPI-HS)*N_LANES*BytesPerHsClk
|
||||
*
|
||||
* Min_Memory_Depth = MAX (MEM_req_1, MEM_req_2, 32)*8/ Memory_Width
|
||||
*/
|
||||
mem_req_1 = (ceil(((frame_info->hsd_time + frame_info->hsa_time + frame_info->hbp_time)* time_IPI_ns - pkt2pkt_time_ns)
|
||||
/ time_PPI_ns) * csi_info->n_lanes * CSI2_BYTES_PER_HS_CLK);
|
||||
|
||||
mem_req_2 = (ceil(((frame_info->hsd_time + frame_info->hsa_time + frame_info->hbp_time + camera_sensor->width)* time_IPI_ns
|
||||
- pkt2pkt_time_ns - (((CSI2_LONG_PKT_BYTES + bytes_to_transmit) / csi_info->n_lanes) * time_PPI_ns)) / time_PPI_ns)
|
||||
* csi_info->n_lanes * CSI2_BYTES_PER_HS_CLK);
|
||||
|
||||
min_memory_depth = MAX(mem_req_1, mem_req_2, 32) * 8 / CSI2_HOST_IPI_DWIDTH;
|
||||
|
||||
if(CSI_IPI_FIFO_DEPTH < min_memory_depth)
|
||||
{
|
||||
return ARM_DRIVER_ERROR;
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
/* Overwrite the CSI color mode on CPI */
|
||||
if(csi_info->cpi_cfg.override)
|
||||
{
|
||||
for(index = 0; index < ARRAY_SIZE(cpi_data_mode_settings) &&
|
||||
(cpi_data_mode_settings[index].cpi_color_mode != csi_info->cpi_cfg.cpi_color_mode); index++);
|
||||
|
||||
if(cpi_data_mode_settings[index].cpi_color_mode != csi_info->cpi_cfg.cpi_color_mode)
|
||||
{
|
||||
return ARM_DRIVER_ERROR_PARAMETER;
|
||||
}
|
||||
}
|
||||
|
||||
/* CPI config information */
|
||||
cpi_info.vsync_wait = CPI_WAIT_VSYNC_ENABLE;
|
||||
cpi_info.vsync_mode = CPI_CAPTURE_DATA_ENABLE_IF_HSYNC_HIGH;
|
||||
cpi_info.pixelclk_pol = CPI_SIG_POLARITY_INVERT_DISABLE;
|
||||
cpi_info.hsync_pol = CPI_SIG_POLARITY_INVERT_DISABLE;
|
||||
cpi_info.vsync_pol = CPI_SIG_POLARITY_INVERT_DISABLE;
|
||||
cpi_info.data_mode = cpi_data_mode_settings[index].cpi_data_mode;
|
||||
cpi_info.data_endianness = CPI_DATA_ENDIANNESS_LSB_FIRST;
|
||||
cpi_info.code10on8 = CPI_CODE10ON8_CODING_DISABLE;
|
||||
cpi_info.data_mask = CPI_DATA_MASK_BIT_16;
|
||||
cpi_info.csi_mode = cpi_data_mode_settings[index].cpi_color_mode;
|
||||
|
||||
/* Registering CPI Info related to CSI */
|
||||
camera_sensor->cpi_info = &cpi_info;
|
||||
|
||||
CSI2->cb_event = cb_event;
|
||||
|
||||
/*DPHY initialization*/
|
||||
ret = CSI2_DPHY_Initialize(csi_info->frequency, csi_info->n_lanes);
|
||||
if(ret != ARM_DRIVER_OK)
|
||||
{
|
||||
return ret;
|
||||
}
|
||||
|
||||
CSI2->status.initialized = 1;
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/**
|
||||
|
||||
\fn int32_t CSI2_Uninitialize (CSI_RESOURCES *CSI2)
|
||||
\brief uninitialize MIPI CSI2 Interface.
|
||||
\param[in] CSI2 Pointer to CSI resources
|
||||
\return \ref execution_status
|
||||
*/
|
||||
static int32_t CSI2_Uninitialize (CSI_RESOURCES *CSI2)
|
||||
{
|
||||
int32_t ret = ARM_DRIVER_OK;
|
||||
CSI2->cb_event = NULL;
|
||||
|
||||
if (CSI2->status.initialized == 0)
|
||||
{
|
||||
/* Driver is already uninitialized */
|
||||
return ARM_DRIVER_OK;
|
||||
}
|
||||
|
||||
if (CSI2->status.powered == 1)
|
||||
{
|
||||
/* Driver is not powered off */
|
||||
return ARM_DRIVER_ERROR;
|
||||
}
|
||||
|
||||
/*DPHY Uninitialization*/
|
||||
ret = CSI2_DPHY_Uninitialize();
|
||||
if(ret != ARM_DRIVER_OK)
|
||||
{
|
||||
return ret;
|
||||
}
|
||||
|
||||
/* Reset driver flags. */
|
||||
CSI2->status.initialized = 0;
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/**
|
||||
|
||||
\fn int32_t CSI2_PowerControl (ARM_POWER_STATE state, CSI_RESOURCES *CSI2)
|
||||
\brief Control CSI2 Interface Power.
|
||||
\param[in] state Power state
|
||||
\param[in] CSI2 Pointer to CSI resources
|
||||
\return \ref execution_status
|
||||
*/
|
||||
static int32_t CSI2_PowerControl (ARM_POWER_STATE state, CSI_RESOURCES *CSI2)
|
||||
{
|
||||
if (CSI2->status.initialized == 0)
|
||||
{
|
||||
/* Driver is not initialized */
|
||||
return ARM_DRIVER_ERROR;
|
||||
}
|
||||
|
||||
switch (state)
|
||||
{
|
||||
case ARM_POWER_OFF:
|
||||
{
|
||||
if (CSI2->status.powered == 0)
|
||||
{
|
||||
/* Driver is already powered off */
|
||||
return ARM_DRIVER_OK;
|
||||
}
|
||||
|
||||
/*Disabling the IRQs*/
|
||||
csi_clear_phy_pkt_discard_intr_mask(CSI2->regs);
|
||||
csi_clear_phy_pkt_construction_intr_mask(CSI2->regs);
|
||||
csi_clear_phy_intr_mask(CSI2->regs);
|
||||
csi_clear_phy_line_construction_intr_mask(CSI2->regs);
|
||||
csi_clear_ipi_intr_mask(CSI2->regs);
|
||||
csi_clear_frame_bndry_err_intr_mask(CSI2->regs);
|
||||
csi_clear_frame_seq_err_intr_mask(CSI2->regs);
|
||||
csi_clear_frame_crc_err_intr_mask(CSI2->regs);
|
||||
csi_clear_frame_payload_err_intr_mask(CSI2->regs);
|
||||
csi_clear_dt_err_intr_mask(CSI2->regs);
|
||||
csi_clear_ecc_intr_mask(CSI2->regs);
|
||||
|
||||
NVIC_DisableIRQ (CSI2->irq);
|
||||
NVIC_ClearPendingIRQ (CSI2->irq);
|
||||
|
||||
clear_csi_pixel_clk();
|
||||
|
||||
CSI2->status.powered = 0;
|
||||
|
||||
break;
|
||||
}
|
||||
|
||||
case ARM_POWER_FULL:
|
||||
{
|
||||
if (CSI2->status.powered == 1)
|
||||
{
|
||||
/* Driver is already powered ON */
|
||||
return ARM_DRIVER_OK;
|
||||
}
|
||||
|
||||
NVIC_ClearPendingIRQ (CSI2->irq);
|
||||
NVIC_SetPriority (CSI2->irq, CSI2->irq_priority);
|
||||
NVIC_EnableIRQ (CSI2->irq);
|
||||
|
||||
set_csi_pixel_clk(RTE_CSI2_PIX_CLK_SEL, CSI2->csi_pixclk_div);
|
||||
|
||||
CSI2->status.powered = 1;
|
||||
|
||||
break;
|
||||
}
|
||||
|
||||
case ARM_POWER_LOW:
|
||||
|
||||
default:
|
||||
{
|
||||
return ARM_DRIVER_ERROR_UNSUPPORTED;
|
||||
}
|
||||
}
|
||||
|
||||
return ARM_DRIVER_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
|
||||
\fn int32_t CSI2_ConfigureHost (uint32_t int_event, CSI_RESOURCES *CSI2)
|
||||
\brief Configure CSI2 Host Interface.
|
||||
\param[in] int_event interrupt event to be enabled.
|
||||
\param[in] CSI2 Pointer to CSI resources
|
||||
\return \ref execution_status
|
||||
*/
|
||||
static int32_t CSI2_ConfigureHost (uint32_t intr_event, CSI_RESOURCES *CSI2)
|
||||
{
|
||||
if(CSI2->status.powered != 1)
|
||||
{
|
||||
return ARM_DRIVER_ERROR;
|
||||
}
|
||||
|
||||
csi_enable_software_reset_state(CSI2->regs);
|
||||
|
||||
if(intr_event & CSI2_EVENT_PHY_FATAL)
|
||||
{
|
||||
csi_set_phy_pkt_discard_intr_mask(CSI2->regs);
|
||||
}
|
||||
|
||||
if(intr_event & CSI2_EVENT_PKT_FATAL)
|
||||
{
|
||||
csi_set_phy_pkt_construction_intr_mask(CSI2->regs);
|
||||
}
|
||||
|
||||
if(intr_event & CSI2_EVENT_PHY)
|
||||
{
|
||||
csi_set_phy_intr_mask(CSI2->regs);
|
||||
}
|
||||
|
||||
if(intr_event & CSI2_EVENT_LINE)
|
||||
{
|
||||
csi_set_phy_line_construction_intr_mask(CSI2->regs);
|
||||
}
|
||||
|
||||
if(intr_event & CSI2_EVENT_IPI_FATAL)
|
||||
{
|
||||
csi_set_ipi_intr_mask(CSI2->regs);
|
||||
}
|
||||
|
||||
if(intr_event & CSI2_EVENT_BNDRY_FRAME_FATAL)
|
||||
{
|
||||
csi_set_frame_bndry_err_intr_mask(CSI2->regs);
|
||||
}
|
||||
|
||||
if(intr_event & CSI2_EVENT_SEQ_FRAME_FATAL)
|
||||
{
|
||||
csi_set_frame_seq_err_intr_mask(CSI2->regs);
|
||||
}
|
||||
|
||||
if(intr_event & CSI2_EVENT_CRC_FRAME_FATAL)
|
||||
{
|
||||
csi_set_frame_crc_err_intr_mask(CSI2->regs);
|
||||
}
|
||||
|
||||
if(intr_event & CSI2_EVENT_PLD_CRC_FATAL)
|
||||
{
|
||||
csi_set_frame_payload_err_intr_mask(CSI2->regs);
|
||||
}
|
||||
|
||||
if(intr_event & CSI2_EVENT_DATA_ID)
|
||||
{
|
||||
csi_set_dt_err_intr_mask(CSI2->regs);
|
||||
}
|
||||
|
||||
if(intr_event & CSI2_EVENT_ECC_CORRECT)
|
||||
{
|
||||
csi_set_ecc_intr_mask(CSI2->regs);
|
||||
}
|
||||
|
||||
return ARM_DRIVER_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
|
||||
\fn void MIPI_CSI2_ISR (CSI_RESOURCES *CSI2)
|
||||
\brief MIPI CSI2 interrupt service routine
|
||||
\param[in] CSI2 Pointer to CSI resources
|
||||
*/
|
||||
static void MIPI_CSI2_ISR (CSI_RESOURCES *CSI2)
|
||||
{
|
||||
uint32_t global_event_status = 0U;
|
||||
uint32_t event = 0U;
|
||||
|
||||
global_event_status = csi_get_interrupt_status(CSI2->regs);
|
||||
|
||||
/*If cb_event is not registered Disable and clear the interrupt*/
|
||||
if(!CSI2->cb_event)
|
||||
{
|
||||
NVIC_DisableIRQ (CSI2->irq);
|
||||
}
|
||||
|
||||
if(global_event_status & CSI_IRQ_PHY_FATAL)
|
||||
{
|
||||
(void)csi_get_phy_pkt_discard_intr_status(CSI2->regs);
|
||||
event |= CSI2_EVENT_PHY_FATAL;
|
||||
}
|
||||
|
||||
if(global_event_status & CSI_IRQ_PKT_FATAL)
|
||||
{
|
||||
(void)csi_get_phy_pkt_construction_intr_status(CSI2->regs);
|
||||
event |= CSI2_EVENT_PKT_FATAL;
|
||||
}
|
||||
|
||||
if(global_event_status & CSI_IRQ_BNDRY_FRAME_FATAL)
|
||||
{
|
||||
(void)csi_get_frame_bndry_err_intr_status(CSI2->regs);
|
||||
event |= CSI2_EVENT_BNDRY_FRAME_FATAL;
|
||||
}
|
||||
|
||||
if(global_event_status & CSI_IRQ_SEQ_FRAME_FATAL)
|
||||
{
|
||||
(void)csi_get_frame_seq_err_intr_status(CSI2->regs);
|
||||
event |= CSI2_EVENT_SEQ_FRAME_FATAL;
|
||||
}
|
||||
|
||||
if(global_event_status & CSI_IRQ_CRC_FRAME_FATAL)
|
||||
{
|
||||
(void)csi_get_frame_crc_err_intr_status(CSI2->regs);
|
||||
event |= CSI2_EVENT_CRC_FRAME_FATAL;
|
||||
}
|
||||
|
||||
if(global_event_status & CSI_IRQ_PLD_CRC_FATAL)
|
||||
{
|
||||
(void)csi_get_frame_payload_err_intr_status(CSI2->regs);
|
||||
event |= CSI2_EVENT_PLD_CRC_FATAL;
|
||||
}
|
||||
|
||||
if(global_event_status & CSI_IRQ_DATA_ID)
|
||||
{
|
||||
(void)csi_get_dt_err_intr_status(CSI2->regs);
|
||||
event |= CSI2_EVENT_DATA_ID;
|
||||
}
|
||||
|
||||
if(global_event_status & CSI_IRQ_ECC_CORRECT)
|
||||
{
|
||||
(void)csi_get_ecc_intr_status(CSI2->regs);
|
||||
event |= CSI2_EVENT_ECC_CORRECT;
|
||||
}
|
||||
|
||||
if(global_event_status & CSI_IRQ_PHY)
|
||||
{
|
||||
(void)csi_get_phy_intr_status(CSI2->regs);
|
||||
event |= CSI2_EVENT_PHY;
|
||||
}
|
||||
|
||||
if(global_event_status & CSI_IRQ_LINE)
|
||||
{
|
||||
(void)csi_get_phy_line_construction_intr_status(CSI2->regs);
|
||||
event |= CSI2_EVENT_LINE;
|
||||
}
|
||||
|
||||
if(global_event_status & CSI_IRQ_IPI_FATAL)
|
||||
{
|
||||
(void)csi_get_ipi_intr_status(CSI2->regs);
|
||||
event |= CSI2_EVENT_IPI_FATAL;
|
||||
}
|
||||
|
||||
if(event != 0 && CSI2->cb_event)
|
||||
{
|
||||
CSI2->cb_event(event);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
\fn int32_t CSI2_ConfigureIPI (CSI_RESOURCES *CSI2)
|
||||
\brief Configure CSI2 IPI Interface.
|
||||
\param[in] CSI2 Pointer to CSI resources
|
||||
\return \ref execution_status
|
||||
*/
|
||||
static int32_t CSI2_ConfigureIPI (CSI_RESOURCES *CSI2)
|
||||
{
|
||||
uint32_t packet_config = 0;
|
||||
uint16_t hline_time;
|
||||
|
||||
if(CSI2->status.powered != 1)
|
||||
{
|
||||
return ARM_DRIVER_ERROR;
|
||||
}
|
||||
|
||||
csi_set_ipi_mode(CSI2->regs, CSI2->ipi_info->ipi_mode);
|
||||
|
||||
csi_set_ipi_color_cop(CSI2->regs, CSI2->ipi_info->ipi_color_com);
|
||||
|
||||
if(CSI2->ipi_info->ipi_memflush == ENABLE)
|
||||
{
|
||||
csi_enable_ipi_mem_flush_auto(CSI2->regs);
|
||||
}
|
||||
else
|
||||
{
|
||||
csi_set_ipi_mem_flush_manual(CSI2->regs);
|
||||
}
|
||||
|
||||
csi_set_ipi_vc_id(CSI2->regs, CSI2->vc_id);
|
||||
|
||||
csi_set_ipi_data_type(CSI2->regs, CSI2->pixel_data_type);
|
||||
|
||||
csi_set_ipi_sync_event_type(CSI2->regs, CSI2->ipi_info->adv_features->sync_evnt_mode);
|
||||
|
||||
csi_set_ipi_line_event_selection(CSI2->regs, CSI2->ipi_info->adv_features->event_sel);
|
||||
|
||||
if(CSI2->ipi_info->adv_features->event_sel == ENABLE)
|
||||
{
|
||||
if(CSI2->ipi_info->adv_features->en_video == ENABLE)
|
||||
{
|
||||
packet_config |= CSI_IPI_EVENT_SELECTION_EN_VIDEO;
|
||||
}
|
||||
if(CSI2->ipi_info->adv_features->en_line_start == ENABLE)
|
||||
{
|
||||
packet_config |= CSI_IPI_EVENT_SELECTION_EN_LINE_START;
|
||||
}
|
||||
if(CSI2->ipi_info->adv_features->en_null == ENABLE)
|
||||
{
|
||||
packet_config |= CSI_IPI_EVENT_SELECTION_EN_NULL;
|
||||
}
|
||||
if(CSI2->ipi_info->adv_features->en_blanking == ENABLE)
|
||||
{
|
||||
packet_config |= CSI_IPI_EVENT_SELECTION_EN_BLANKING;
|
||||
}
|
||||
if(CSI2->ipi_info->adv_features->en_embedded == ENABLE)
|
||||
{
|
||||
packet_config |= CSI_IPI_EVENT_SELECTION_EN_EMBEDDED;
|
||||
}
|
||||
|
||||
csi_set_packet_configuration(CSI2->regs, packet_config);
|
||||
}
|
||||
|
||||
if(CSI2->ipi_info->adv_features->ipi_dt_overwrite == ENABLE)
|
||||
{
|
||||
csi_enable_ipi_dt_overwrite(CSI2->regs);
|
||||
csi_set_ipi_dt_overwrite(CSI2->regs, CSI2->ipi_info->adv_features->ipi_dt);
|
||||
}
|
||||
else
|
||||
{
|
||||
csi_disable_ipi_dt_overwrite(CSI2->regs);
|
||||
}
|
||||
|
||||
hline_time = CSI2->ipi_info->frame_info->hactive_time + CSI2->ipi_info->frame_info->hsa_time
|
||||
+ CSI2->ipi_info->frame_info->hbp_time + CSI2->ipi_info->frame_info->hsd_time;
|
||||
|
||||
csi_set_horizontal_timing(CSI2->regs, CSI2->ipi_info->frame_info->hsa_time,
|
||||
CSI2->ipi_info->frame_info->hbp_time,
|
||||
CSI2->ipi_info->frame_info->hsd_time,
|
||||
hline_time);
|
||||
|
||||
csi_set_vertical_timing(CSI2->regs, CSI2->ipi_info->frame_info->vsa_line,
|
||||
CSI2->ipi_info->frame_info->vbp_line,
|
||||
CSI2->ipi_info->frame_info->vfp_line,
|
||||
CSI2->ipi_info->frame_info->vactive_line);
|
||||
|
||||
csi_disable_software_reset_state(CSI2->regs);
|
||||
|
||||
CSI2->status.csi_configured = 1;
|
||||
|
||||
return ARM_DRIVER_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
|
||||
\fn int32_t CSI2_StartIPI (CSI_RESOURCES *CSI2)
|
||||
\brief Enable CSI2 IPI Interface.
|
||||
\param[in] CSI2 Pointer to CSI resources
|
||||
\return \ref execution_status
|
||||
*/
|
||||
static int32_t CSI2_StartIPI (CSI_RESOURCES *CSI2)
|
||||
{
|
||||
if (CSI2->status.csi_configured == 0)
|
||||
{
|
||||
return ARM_DRIVER_ERROR;
|
||||
}
|
||||
|
||||
csi_enable_ipi_mode(CSI2->regs);
|
||||
|
||||
return ARM_DRIVER_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
|
||||
\fn int32_t CSI2_StopIPI (CSI_RESOURCES *CSI2)
|
||||
\brief Disable CSI2 IPI Interface.
|
||||
\param[in] CSI2 Pointer to CSI resources
|
||||
\return \ref execution_status
|
||||
*/
|
||||
static int32_t CSI2_StopIPI (CSI_RESOURCES *CSI2)
|
||||
{
|
||||
if (CSI2->status.powered == 0)
|
||||
{
|
||||
return ARM_DRIVER_ERROR;
|
||||
}
|
||||
|
||||
csi_disable_ipi_mode(CSI2->regs);
|
||||
|
||||
return ARM_DRIVER_OK;
|
||||
}
|
||||
|
||||
/* CSI frame configuration */
|
||||
CSI_FRAME_INFO CSI_FRAME_CFG =
|
||||
{
|
||||
.hsa_time = RTE_MIPI_CSI2_IPI_HSA_TIME,
|
||||
.hbp_time = RTE_MIPI_CSI2_IPI_HBP_TIME,
|
||||
.hsd_time = RTE_MIPI_CSI2_IPI_HSD_TIME,
|
||||
.hactive_time = RTE_MIPI_CSI2_IPI_HACTIVE_TIME,
|
||||
.vsa_line = RTE_MIPI_CSI2_IPI_VSA_LINE,
|
||||
.vbp_line = RTE_MIPI_CSI2_IPI_VBP_LINE,
|
||||
.vfp_line = RTE_MIPI_CSI2_IPI_VFP_LINE,
|
||||
.vactive_line = RTE_MIPI_CSI2_IPI_VACTIVE_LINE,
|
||||
};
|
||||
|
||||
/* CSI IPI advanced configuration */
|
||||
CSI_IPI_ADV_INFO CSI_IPI_ADV_FEATURES_CFG =
|
||||
{
|
||||
.sync_evnt_mode = RTE_MIPI_CSI2_SYNC_ET_MODE,
|
||||
.event_sel = RTE_MIPI_CSI2_SYNC_ET_SEL,
|
||||
.en_embedded = RTE_MIPI_CSI2_EN_EMBEDDED,
|
||||
.en_blanking = RTE_MIPI_CSI2_EN_BLANKING,
|
||||
.en_null = RTE_MIPI_CSI2_EN_NULL,
|
||||
.en_line_start = RTE_MIPI_CSI2_EN_LINE_START,
|
||||
.en_video = RTE_MIPI_CSI2_EN_VIDEO,
|
||||
.ipi_dt = RTE_MIPI_CSI2_EN_DT,
|
||||
.ipi_dt_overwrite = RTE_MIPI_CSI2_EN_DT_OVERWRITE,
|
||||
};
|
||||
|
||||
/* CSI IPI configuration */
|
||||
CSI_IPI_INFO CSI_IPI_CFG =
|
||||
{
|
||||
.ipi_mode = RTE_MIPI_CSI2_IPI_MODE,
|
||||
.ipi_memflush = RTE_MIPI_CSI2_MEMFLUSH,
|
||||
.frame_info = &CSI_FRAME_CFG,
|
||||
.adv_features = &CSI_IPI_ADV_FEATURES_CFG,
|
||||
};
|
||||
|
||||
/* CSI resources */
|
||||
CSI_RESOURCES CSI2 =
|
||||
{
|
||||
.regs = (CSI_Type *)CSI_BASE,
|
||||
.cb_event = NULL,
|
||||
.ipi_info = &CSI_IPI_CFG,
|
||||
.irq = (IRQn_Type)CSI_IRQ_IRQn,
|
||||
.irq_priority = RTE_MIPI_CSI2_IRQ_PRI,
|
||||
};
|
||||
|
||||
static int32_t MIPI_CSI2_Initialize (ARM_MIPI_CSI2_SignalEvent_t cb_event)
|
||||
{
|
||||
return CSI2_Initialize(cb_event, &CSI2);
|
||||
}
|
||||
|
||||
static int32_t MIPI_CSI2_Uninitialize (void)
|
||||
{
|
||||
return CSI2_Uninitialize(&CSI2);
|
||||
}
|
||||
|
||||
static int32_t MIPI_CSI2_PowerControl (ARM_POWER_STATE state)
|
||||
{
|
||||
return CSI2_PowerControl (state, &CSI2);
|
||||
}
|
||||
|
||||
static int32_t MIPI_CSI2_ConfigureHost (uint32_t int_event)
|
||||
{
|
||||
return CSI2_ConfigureHost (int_event, &CSI2);
|
||||
}
|
||||
|
||||
static int32_t MIPI_CSI2_ConfigureIPI (void)
|
||||
{
|
||||
return CSI2_ConfigureIPI(&CSI2);
|
||||
}
|
||||
|
||||
static int32_t MIPI_CSI2_StartIPI(void)
|
||||
{
|
||||
return CSI2_StartIPI(&CSI2);
|
||||
}
|
||||
|
||||
static int32_t MIPI_CSI2_StopIPI(void)
|
||||
{
|
||||
return CSI2_StopIPI(&CSI2);
|
||||
}
|
||||
void CSI_IRQHandler (void)
|
||||
{
|
||||
MIPI_CSI2_ISR(&CSI2);
|
||||
}
|
||||
|
||||
/**
|
||||
\brief Access structure of the MIPI CSI2 Driver.
|
||||
*/
|
||||
extern ARM_DRIVER_MIPI_CSI2 Driver_MIPI_CSI2;
|
||||
ARM_DRIVER_MIPI_CSI2 Driver_MIPI_CSI2 =
|
||||
{
|
||||
MIPI_CSI2_GetVersion,
|
||||
MIPI_CSI2_GetCapabilities,
|
||||
MIPI_CSI2_Initialize,
|
||||
MIPI_CSI2_Uninitialize,
|
||||
MIPI_CSI2_PowerControl,
|
||||
MIPI_CSI2_ConfigureHost,
|
||||
MIPI_CSI2_ConfigureIPI,
|
||||
MIPI_CSI2_StartIPI,
|
||||
MIPI_CSI2_StopIPI,
|
||||
};
|
||||
|
||||
/************************ (C) COPYRIGHT ALIF SEMICONDUCTOR *****END OF FILE****/
|
||||
822
src/hal/alif/Alif_CMSIS/Source/Driver_MIPI_DSI.c
Normal file
822
src/hal/alif/Alif_CMSIS/Source/Driver_MIPI_DSI.c
Normal file
@ -0,0 +1,822 @@
|
||||
/* Copyright (C) 2022 Alif Semiconductor - All Rights Reserved.
|
||||
* Use, distribution and modification of this code is permitted under the
|
||||
* terms stated in the Alif Semiconductor Software License Agreement
|
||||
*
|
||||
* You should have received a copy of the Alif Semiconductor Software
|
||||
* License Agreement with this file. If not, please write to:
|
||||
* contact@alifsemi.com, or visit: https://alifsemi.com/license
|
||||
*
|
||||
*/
|
||||
|
||||
/**************************************************************************//**
|
||||
* @file Driver_MIPI_DSI.c
|
||||
* @author Prasanna Ravi
|
||||
* @email prasanna.ravi@alifsemi.com
|
||||
* @version V1.0.0
|
||||
* @date 28-Sep-2023
|
||||
* @brief CMSIS-Driver for MIPI DSI.
|
||||
* @bug None.
|
||||
* @Note None.
|
||||
******************************************************************************/
|
||||
|
||||
#include "Driver_MIPI_DSI.h"
|
||||
#include "Driver_DSI_Private.h"
|
||||
#include "RTE_Device.h"
|
||||
#include "DPHY_DSI.h"
|
||||
#include "display.h"
|
||||
|
||||
#define ARM_MIPI_DSI_DRV_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(1, 0) /*driver version*/
|
||||
|
||||
#if !(RTE_MIPI_DSI)
|
||||
#error "MIPI DSI is not enabled in the RTE_Device.h"
|
||||
#endif
|
||||
|
||||
#if (!defined(RTE_Drivers_MIPI_DSI))
|
||||
#error "MIPI DSI not configured in RTE_Components.h!"
|
||||
#endif
|
||||
|
||||
/* High speed transition timing range */
|
||||
static const DSI_DPHY_HS_TRANSITION_TIMINGS_RANGE hstransition_timing_range[] =
|
||||
{
|
||||
{ 80, 21, 17, 15, 10 }, { 90, 23, 17, 16, 10 }, { 100, 22, 17, 16, 10 },
|
||||
{ 110, 25, 18, 17, 11 }, { 120, 26, 20, 18, 11 }, { 130, 27, 19, 19, 11 },
|
||||
{ 140, 27, 19, 19, 11 }, { 150, 28, 20, 20, 12 }, { 160, 30, 21, 22, 13 },
|
||||
{ 170, 30, 21, 23, 13 }, { 180, 31, 21, 23, 13 }, { 190, 32, 22, 24, 13 },
|
||||
{ 205, 35, 22, 25, 13 }, { 220, 37, 26, 27, 15 }, { 235, 38, 28, 27, 16 },
|
||||
{ 250, 41, 29, 30, 17 }, { 275, 43, 29, 32, 18 }, { 300, 45, 32, 35, 19 },
|
||||
{ 325, 48, 33, 36, 18 }, { 350, 51, 35, 40, 20 }, { 400, 59, 37, 44, 21 },
|
||||
{ 450, 65, 40, 49, 23 }, { 500, 71, 41, 54, 24 }, { 550, 77, 44, 57, 26 },
|
||||
{ 600, 82, 46, 64, 27 }, { 650, 87, 48, 67, 28}, { 700, 94, 52, 71, 29 },
|
||||
{ 750, 99, 52, 75, 31 }, { 800, 105, 55, 82, 32 }, { 850, 110, 58, 85, 32 },
|
||||
{ 900, 115, 58, 88, 35 }, { 950, 120, 62, 93, 36 }, { 1000, 128, 63, 99, 38 },
|
||||
{ 1050, 132, 65, 102, 38 }, { 1100, 138, 67, 106, 39 }, { 1150, 146, 69, 112, 42 },
|
||||
{ 1200, 151, 71, 117, 43 }, { 1250, 153, 74, 120, 45 }, { 1300, 160, 73, 124, 46 },
|
||||
{ 1350, 165, 76, 130, 47 }, { 1400, 172, 78, 134, 49 }, { 1450, 177, 80, 138, 49 },
|
||||
{ 1500, 183, 81, 143, 52 }, { 1550, 191, 84, 147, 52 }, { 1600, 194, 85, 152, 52 },
|
||||
{ 1650, 201, 86, 155, 53 }, { 1700, 208, 88, 161, 53 }, { 1750, 212, 89, 165, 53 },
|
||||
{ 1800, 220, 90, 171, 54 }, { 1850, 223, 92, 175, 54 }, { 1900, 231, 91, 180, 55 },
|
||||
{ 1950, 236, 95, 185, 56 }, { 2000, 243, 97, 190, 56 }, { 2050, 248, 99, 194, 58 },
|
||||
{ 2100, 252, 100, 199, 59 }, { 2150, 259, 102, 204, 61 }, { 2200, 266, 105, 210, 62 },
|
||||
{ 2250, 269, 109, 213, 63 }, { 2300, 272, 109, 217, 65 }, { 2350, 281, 112, 225, 66},
|
||||
{ 2400, 283, 115, 226, 66 }, { 2450, 282, 115, 226, 67 }, { 2500, 281, 118, 227, 67 }
|
||||
};
|
||||
|
||||
/* CDC config informations */
|
||||
static CDC_INFO cdc_info;
|
||||
|
||||
/*Driver Version*/
|
||||
static const ARM_DRIVER_VERSION DriverVersion =
|
||||
{
|
||||
ARM_MIPI_DSI_API_VERSION,
|
||||
ARM_MIPI_DSI_DRV_VERSION
|
||||
};
|
||||
|
||||
/* Driver Capabilities */
|
||||
static const ARM_MIPI_DSI_CAPABILITIES DriverCapabilities =
|
||||
{
|
||||
0, /* Not supports reentrant_operation */
|
||||
1, /* DPI interface supported*/
|
||||
0, /* DBI interface not supported*/
|
||||
0 /* reserved (must be zero) */
|
||||
};
|
||||
|
||||
/**
|
||||
\fn ARM_DRIVER_VERSION ARM_MIPI_DSI_GetVersion (void)
|
||||
\brief Get MIPI DSI driver version.
|
||||
\return \ref ARM_DRIVER_VERSION
|
||||
*/
|
||||
static ARM_DRIVER_VERSION ARM_MIPI_DSI_GetVersion (void)
|
||||
{
|
||||
return DriverVersion;
|
||||
}
|
||||
|
||||
/**
|
||||
\fn ARM_MIPI_DSI_CAPABILITIES MIPI_DSI_GetCapabilities (void)
|
||||
\brief Get MIPI DSI driver capabilities
|
||||
\return \ref ARM_MIPI_DPHY_CAPABILITIES
|
||||
*/
|
||||
static ARM_MIPI_DSI_CAPABILITIES ARM_MIPI_DSI_GetCapabilities (void)
|
||||
{
|
||||
return DriverCapabilities;
|
||||
}
|
||||
/**
|
||||
\fn int32_t DSI_Initialize (ARM_MIPI_DSI_SignalEvent_t cb_event,
|
||||
DISPLAY_PANEL_DEVICE *display_panel, DSI_RESOURCES *dsi)
|
||||
\brief Initialize MIPI DSI Interface.
|
||||
\param[in] cb_event Pointer to ARM_MIPI_DSI_SignalEvent_t.
|
||||
\param[in] display_panel Pointer to display panel resources.
|
||||
\param[in] dsi Pointer to DSI resources.
|
||||
\return \ref execution_status.
|
||||
*/
|
||||
static int32_t DSI_Initialize (ARM_MIPI_DSI_SignalEvent_t cb_event,
|
||||
DISPLAY_PANEL_DEVICE *display_panel, DSI_RESOURCES *dsi)
|
||||
{
|
||||
int32_t ret = ARM_DRIVER_OK;
|
||||
DSI_INFO *dsi_info;
|
||||
uint32_t pixclk;
|
||||
|
||||
if(dsi->state.initialized == 1)
|
||||
{
|
||||
return ARM_DRIVER_OK;
|
||||
}
|
||||
|
||||
if (!cb_event)
|
||||
{
|
||||
return ARM_DRIVER_ERROR_PARAMETER;
|
||||
}
|
||||
|
||||
dsi_info = display_panel->dsi_info;
|
||||
|
||||
if (!(display_panel && dsi_info))
|
||||
{
|
||||
return ARM_DRIVER_ERROR_PARAMETER;
|
||||
}
|
||||
|
||||
/* LCD Manufacturer provides the Frame timing values
|
||||
* HTOTAL = WIDTH + HSYNC + HFP + HBP
|
||||
* VTOTAL = HEIGHT + VSYNC + VFP + VBP
|
||||
* Calculate the pixel clock for DPI controller
|
||||
* PIXCLK = FPS x HTOTAL x VTOTAL
|
||||
*/
|
||||
dsi->horizontal_timing = (display_panel->hsync_time
|
||||
+ display_panel->hbp_time
|
||||
+ display_panel->hfp_time
|
||||
+ display_panel->hactive_time);
|
||||
|
||||
dsi->vertical_timing = (display_panel->vsync_line
|
||||
+ display_panel->vbp_line
|
||||
+ display_panel->vfp_line
|
||||
+ display_panel->vactive_line);
|
||||
|
||||
pixclk = (dsi->horizontal_timing * dsi->vertical_timing * RTE_CDC200_DPI_FPS);
|
||||
|
||||
/* SCALE = LANEBYTECLK / PIXCLK
|
||||
* MIPI data rate must be exactly equal, not greater than, for 1.5 scale to work
|
||||
* MIPI data rate + 33% allows for scaling times 2
|
||||
* 24 x 1.333 / 16 = 2
|
||||
* LANEBYTECLK = PIXCLK * SCALE
|
||||
* lanebyteclk frequency is 1/4th of the DPHY frequency
|
||||
* PLL frequency = LANEBYTECLK * 4
|
||||
* = PIXCLK * SCALE * 4
|
||||
*/
|
||||
dsi->frequency = pixclk * 2 * 4;
|
||||
|
||||
/*Checking LCD Panel supports MIPI DSI DPHY data rate*/
|
||||
if((dsi->frequency * 2) > (dsi_info->max_bitrate * 1000000))
|
||||
{
|
||||
return ARM_DRIVER_ERROR_PARAMETER;
|
||||
}
|
||||
|
||||
if(dsi_dpi_get_hsync_polarity(dsi->reg_base) == DSI_POLARITY_ACTIVE_LOW)
|
||||
{
|
||||
cdc_info.hsync_polarity = CDC_POLARITY_ACTIVE_LOW;
|
||||
}
|
||||
else
|
||||
{
|
||||
cdc_info.hsync_polarity = CDC_POLARITY_ACTIVE_HIGH;
|
||||
}
|
||||
|
||||
if(dsi_dpi_get_vsync_polarity(dsi->reg_base) == DSI_POLARITY_ACTIVE_LOW)
|
||||
{
|
||||
cdc_info.vsync_polarity = CDC_POLARITY_ACTIVE_LOW;
|
||||
}
|
||||
else
|
||||
{
|
||||
cdc_info.vsync_polarity = CDC_POLARITY_ACTIVE_HIGH;
|
||||
}
|
||||
|
||||
cdc_info.pclk_polarity = CDC_PIXCLK_POLARITY_FEED_THROUGH;
|
||||
|
||||
if(dsi_dpi_get_dataen_polarity(dsi->reg_base) == DSI_POLARITY_ACTIVE_LOW)
|
||||
{
|
||||
cdc_info.blank_polarity = CDC_POLARITY_ACTIVE_HIGH;
|
||||
}
|
||||
else
|
||||
{
|
||||
cdc_info.blank_polarity = CDC_POLARITY_ACTIVE_LOW;
|
||||
}
|
||||
|
||||
/* Registering CPI Info related to CSI */
|
||||
display_panel->cdc_info = &cdc_info;
|
||||
|
||||
dsi->cb_event = cb_event;
|
||||
|
||||
/*DPHY initialization*/
|
||||
ret = DSI_DPHY_Initialize(dsi->frequency, dsi_info->n_lanes);
|
||||
if(ret != ARM_DRIVER_OK)
|
||||
{
|
||||
return ret;
|
||||
}
|
||||
|
||||
/*LCD Panel Initialization*/
|
||||
ret = display_panel->ops->Init();
|
||||
if(ret != ARM_DRIVER_OK)
|
||||
{
|
||||
return ret;
|
||||
}
|
||||
|
||||
dsi->dpi_info->vid_pkt_size = display_panel->hactive_time;
|
||||
|
||||
dsi->state.initialized = 1;
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/**
|
||||
\fn int32_t DSI_Uninitialize (DISPLAY_PANEL_DEVICE *display_panel, DSI_RESOURCES *dsi)
|
||||
\brief uninitialize MIPI DSI Interface.
|
||||
\param[in] display_panel Pointer to display panel resources.
|
||||
\param[in] dsi Pointer to DSI resources.
|
||||
\return \ref execution_status.
|
||||
*/
|
||||
static int32_t DSI_Uninitialize (DISPLAY_PANEL_DEVICE *display_panel, DSI_RESOURCES *dsi)
|
||||
{
|
||||
int32_t ret = ARM_DRIVER_OK;
|
||||
dsi->cb_event = NULL;
|
||||
|
||||
if(dsi->state.initialized == 0)
|
||||
{
|
||||
return ARM_DRIVER_OK;
|
||||
}
|
||||
|
||||
if (dsi->state.powered == 1)
|
||||
{
|
||||
return ARM_DRIVER_ERROR;
|
||||
}
|
||||
|
||||
/*DPHY Uninitialization*/
|
||||
ret = DSI_DPHY_Uninitialize();
|
||||
if(ret != ARM_DRIVER_OK)
|
||||
{
|
||||
return ret;
|
||||
}
|
||||
|
||||
/*LCD Panel Un-Initialization*/
|
||||
ret = display_panel->ops->Uninit();
|
||||
if(ret != ARM_DRIVER_OK)
|
||||
{
|
||||
return ret;
|
||||
}
|
||||
|
||||
dsi->state.initialized = 0;
|
||||
return ret;
|
||||
}
|
||||
|
||||
/**
|
||||
\fn int32_t DSI_PowerControl (ARM_POWER_STATE state,
|
||||
DSI_RESOURCES *dsi)
|
||||
\brief Control DSI Interface Power.
|
||||
\param[in] state Power state.
|
||||
\param[in] dsi Pointer to DSI resources.
|
||||
\return \ref execution_status.
|
||||
*/
|
||||
static int32_t DSI_PowerControl (ARM_POWER_STATE state,
|
||||
DSI_RESOURCES *dsi)
|
||||
{
|
||||
if (dsi->state.initialized == 0)
|
||||
{
|
||||
return ARM_DRIVER_ERROR;
|
||||
}
|
||||
|
||||
switch (state)
|
||||
{
|
||||
case ARM_POWER_OFF:
|
||||
{
|
||||
if (dsi->state.powered == 0)
|
||||
{
|
||||
return ARM_DRIVER_OK;
|
||||
}
|
||||
|
||||
NVIC_DisableIRQ (dsi->irq);
|
||||
NVIC_ClearPendingIRQ (dsi->irq);
|
||||
|
||||
dsi->state.powered = 0;
|
||||
break;
|
||||
}
|
||||
|
||||
case ARM_POWER_FULL:
|
||||
{
|
||||
if (dsi->state.powered == 1)
|
||||
{
|
||||
return ARM_DRIVER_OK;
|
||||
}
|
||||
|
||||
NVIC_ClearPendingIRQ (dsi->irq);
|
||||
NVIC_SetPriority (dsi->irq, dsi->irq_priority);
|
||||
NVIC_EnableIRQ (dsi->irq);
|
||||
|
||||
dsi->state.powered = 1;
|
||||
|
||||
break;
|
||||
}
|
||||
|
||||
case ARM_POWER_LOW:
|
||||
default:
|
||||
{
|
||||
return ARM_DRIVER_ERROR_UNSUPPORTED;
|
||||
}
|
||||
}
|
||||
|
||||
return ARM_DRIVER_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
\fn int32_t DSI_ConfigureHost (DSI_RESOURCES *dsi)
|
||||
\brief Configure DSI Host Interface.
|
||||
\param[in] dsi Pointer to DSI resources.
|
||||
\return \ref execution_status.
|
||||
*/
|
||||
static int32_t DSI_ConfigureHost (DSI_RESOURCES *dsi)
|
||||
{
|
||||
if (dsi->state.powered == 0)
|
||||
{
|
||||
return ARM_DRIVER_ERROR;
|
||||
}
|
||||
|
||||
dsi_irq0_enable(dsi->reg_base, DSI_IRQ0_ACK_WITH_ERR_0 | \
|
||||
DSI_IRQ0_ACK_WITH_ERR_1 | \
|
||||
DSI_IRQ0_ACK_WITH_ERR_2 | \
|
||||
DSI_IRQ0_ACK_WITH_ERR_3 | \
|
||||
DSI_IRQ0_ACK_WITH_ERR_4 | \
|
||||
DSI_IRQ0_ACK_WITH_ERR_5 | \
|
||||
DSI_IRQ0_ACK_WITH_ERR_6 | \
|
||||
DSI_IRQ0_ACK_WITH_ERR_7 | \
|
||||
DSI_IRQ0_ACK_WITH_ERR_8 | \
|
||||
DSI_IRQ0_ACK_WITH_ERR_9 | \
|
||||
DSI_IRQ0_ACK_WITH_ERR_10 | \
|
||||
DSI_IRQ0_ACK_WITH_ERR_11 | \
|
||||
DSI_IRQ0_ACK_WITH_ERR_12 | \
|
||||
DSI_IRQ0_ACK_WITH_ERR_13 | \
|
||||
DSI_IRQ0_ACK_WITH_ERR_14 | \
|
||||
DSI_IRQ0_ACK_WITH_ERR_15 | \
|
||||
DSI_IRQ0_DPHY_ERRORS_0 | \
|
||||
DSI_IRQ0_DPHY_ERRORS_1 | \
|
||||
DSI_IRQ0_DPHY_ERRORS_2 | \
|
||||
DSI_IRQ0_DPHY_ERRORS_3 | \
|
||||
DSI_IRQ0_DPHY_ERRORS_4);
|
||||
|
||||
dsi_irq1_enable(dsi->reg_base, DSI_IRQ1_TO_HS_TX | \
|
||||
DSI_IRQ1_TO_LP_RX | \
|
||||
DSI_IRQ1_ECC_SINGLE_ERR | \
|
||||
DSI_IRQ1_ECC_MILTI_ERR | \
|
||||
DSI_IRQ1_CRC_ERR | \
|
||||
DSI_IRQ1_PKT_SIZE_ERR | \
|
||||
DSI_IRQ1_EOPT_ERR | \
|
||||
DSI_IRQ1_DPI_PLD_WR_ERR | \
|
||||
DSI_IRQ1_GEN_CMD_WR_ERR | \
|
||||
DSI_IRQ1_GEN_PLD_WR_ERR | \
|
||||
DSI_IRQ1_GEN_PLD_SEND_ERR | \
|
||||
DSI_IRQ1_GEN_PLD_RD_ERR | \
|
||||
DSI_IRQ1_GEN_PLD_RECEV_ERR);
|
||||
|
||||
dsi->state.host_configured = 1;
|
||||
|
||||
return ARM_DRIVER_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
\fn int32_t DSI_ConfigureDPI (DISPLAY_PANEL_DEVICE *display_panel, DSI_RESOURCES *dsi)
|
||||
\brief Configure DSI DPI Interface.
|
||||
\param[in] display_panel Pointer to display panel resources.
|
||||
\param[in] dsi Pointer to DSI resources.
|
||||
\return \ref execution_status.
|
||||
*/
|
||||
static int32_t DSI_ConfigureDPI (DISPLAY_PANEL_DEVICE *display_panel, DSI_RESOURCES *dsi)
|
||||
{
|
||||
DSI_INFO *dsi_info;
|
||||
DSI_DPI_INFO *dpi_info = (DSI_DPI_INFO *)dsi->dpi_info;
|
||||
|
||||
dsi_info = display_panel->dsi_info;
|
||||
|
||||
if(dsi->state.host_configured == 0)
|
||||
{
|
||||
return ARM_DRIVER_ERROR;
|
||||
}
|
||||
|
||||
dsi_dpi_set_color_coding(dsi->reg_base, dsi_info->color_coding);
|
||||
|
||||
dsi_set_video_packet_size(dsi->reg_base, dpi_info->vid_pkt_size);
|
||||
|
||||
dsi_set_video_number_chunks(dsi->reg_base, dpi_info->vid_num_chunks);
|
||||
|
||||
dsi_set_video_null_packet_size(dsi->reg_base, dpi_info->vid_null_size);
|
||||
|
||||
dsi_set_video_hsa_time(dsi->reg_base, display_panel->hsync_time << 1);
|
||||
|
||||
dsi_set_video_hbp_time(dsi->reg_base, display_panel->hbp_time << 1);
|
||||
|
||||
dsi_set_video_hline_time(dsi->reg_base, ((display_panel->hsync_time << 1) \
|
||||
+ (display_panel->hbp_time << 1) \
|
||||
+ (display_panel->hfp_time << 1) \
|
||||
+ (display_panel->hactive_time << 1)));
|
||||
|
||||
dsi_set_video_vsa_lines(dsi->reg_base, display_panel->vsync_line);
|
||||
|
||||
dsi_set_video_vbp_lines(dsi->reg_base, display_panel->vbp_line);
|
||||
|
||||
dsi_set_video_vfp_lines(dsi->reg_base, display_panel->vfp_line);
|
||||
|
||||
dsi_set_video_vactive_lines(dsi->reg_base, display_panel->vactive_line);
|
||||
|
||||
dsi->state.dpi_configured = 1;
|
||||
|
||||
return ARM_DRIVER_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
\fn int32_t DSI_Control (ARM_MIPI_DSI_CONTROL control, uint32_t arg,
|
||||
DISPLAY_PANEL_DEVICE *display_panel, DSI_RESOURCES *dsi)
|
||||
\brief Control DSI Interface.
|
||||
\param[in] control DSI host and DPI Configuration.
|
||||
\param[in] arg Argument of operation (optional)
|
||||
\param[in] display_panel Pointer to display panel resources.
|
||||
\param[in] dsi Pointer to DSI resources.
|
||||
\return \ref execution_status.
|
||||
*/
|
||||
static int32_t DSI_Control (ARM_MIPI_DSI_CONTROL control, uint32_t arg,
|
||||
DISPLAY_PANEL_DEVICE *display_panel,DSI_RESOURCES *dsi)
|
||||
{
|
||||
ARG_UNUSED(arg);
|
||||
int32_t ret = ARM_DRIVER_OK;
|
||||
|
||||
switch(control)
|
||||
{
|
||||
case DSI_CONFIGURE_HOST:
|
||||
{
|
||||
ret = DSI_ConfigureHost(dsi);
|
||||
if(ret != ARM_DRIVER_OK)
|
||||
{
|
||||
return ret;
|
||||
}
|
||||
break;
|
||||
}
|
||||
|
||||
case DSI_CONFIGURE_DPI:
|
||||
{
|
||||
ret = DSI_ConfigureDPI(display_panel, dsi);
|
||||
if(ret != ARM_DRIVER_OK)
|
||||
{
|
||||
return ret;
|
||||
}
|
||||
break;
|
||||
}
|
||||
|
||||
default:
|
||||
{
|
||||
return ARM_DRIVER_ERROR_UNSUPPORTED;
|
||||
}
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/**
|
||||
\fn int32_t DSI_StartCommandMode (DISPLAY_PANEL_DEVICE *display_panel, DSI_RESOURCES *dsi)
|
||||
\brief Configure DSI to start Command mode.
|
||||
\param[in] display_panel Pointer to display panel resources.
|
||||
\param[in] dsi Pointer to DSI resources.
|
||||
\return \ref execution_status.
|
||||
*/
|
||||
static int32_t DSI_StartCommandMode (DISPLAY_PANEL_DEVICE *display_panel, DSI_RESOURCES *dsi)
|
||||
{
|
||||
int32_t ret = ARM_DRIVER_OK;
|
||||
DSI_DPI_INFO *dpi_info = (DSI_DPI_INFO *)dsi->dpi_info;
|
||||
uint16_t clklp2hs_time, lp2hs_time, clkhs2lp_time, hs2lp_time;
|
||||
uint32_t bitrate_mbps;
|
||||
uint8_t range = 0;
|
||||
|
||||
if(dsi->state.host_configured == 0)
|
||||
{
|
||||
return ARM_DRIVER_ERROR;
|
||||
}
|
||||
|
||||
bitrate_mbps = (dsi->frequency * 2)/1000000;
|
||||
|
||||
for(range = 0; (range < ARRAY_SIZE(hstransition_timing_range) - 1) &&
|
||||
((bitrate_mbps) > hstransition_timing_range[range].bitrate_mbps);
|
||||
++range);
|
||||
|
||||
clklp2hs_time = hstransition_timing_range[range].clklp2hs_time;
|
||||
clkhs2lp_time = hstransition_timing_range[range].clkhs2lp_time;
|
||||
lp2hs_time = hstransition_timing_range[range].lp2hs_time;
|
||||
hs2lp_time = hstransition_timing_range[range].hs2lp_time;
|
||||
|
||||
dsi_power_up_disable(dsi->reg_base);
|
||||
|
||||
dsi_auto_clklane_enable(dsi->reg_base);
|
||||
|
||||
dsi_set_phy_clklp2hs_time(dsi->reg_base, clklp2hs_time);
|
||||
|
||||
dsi_set_phy_clkhs2lp_time(dsi->reg_base, clkhs2lp_time);
|
||||
|
||||
dsi_set_phy_lp2hs_time(dsi->reg_base, lp2hs_time);
|
||||
|
||||
dsi_set_phy_hs2lp_time(dsi->reg_base, hs2lp_time);
|
||||
|
||||
dsi_reception_enable(dsi->reg_base);
|
||||
|
||||
dsi_command_mode_enable(dsi->reg_base);
|
||||
|
||||
dsi_set_video_mode_type(dsi->reg_base, dpi_info->vid_mode);
|
||||
|
||||
dsi_command_transmission_enable(dsi->reg_base);
|
||||
|
||||
dsi_set_tx_escap_clock_divider(dsi->reg_base, dsi->tx_ecs_clk_div);
|
||||
|
||||
dsi_set_command_mode_config(dsi->reg_base, DSI_CMD_MODE_CFG_GEN_SW_0P_TX | \
|
||||
DSI_CMD_MODE_CFG_GEN_SW_1P_TX | \
|
||||
DSI_CMD_MODE_CFG_GEN_SW_2P_TX | \
|
||||
DSI_CMD_MODE_CFG_GEN_SR_0P_TX | \
|
||||
DSI_CMD_MODE_CFG_GEN_SR_1P_TX | \
|
||||
DSI_CMD_MODE_CFG_GEN_SR_2P_TX | \
|
||||
DSI_CMD_MODE_CFG_GEN_LW_TX | \
|
||||
DSI_CMD_MODE_CFG_DCS_SW_0P_TX | \
|
||||
DSI_CMD_MODE_CFG_DCS_SW_1P_TX | \
|
||||
DSI_CMD_MODE_CFG_DCS_SR_0P_TX | \
|
||||
DSI_CMD_MODE_CFG_DCS_LW_TX | \
|
||||
DSI_CMD_MODE_CFG_MAX_RD_PKT_SIZE);
|
||||
|
||||
dsi_power_up_enable(dsi->reg_base);
|
||||
|
||||
/*Configure LCD Panel*/
|
||||
ret = display_panel->ops->Control(DISPALY_PANEL_CONFIG);
|
||||
if(ret != ARM_DRIVER_OK)
|
||||
{
|
||||
return ret;
|
||||
}
|
||||
|
||||
dsi->state.panel_initialized = 1;
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/**
|
||||
\fn int32_t DSI_StartVideoMode (DISPLAY_PANEL_DEVICE *display_panel,DSI_RESOURCES *dsi)
|
||||
\brief Configure DSI to start Video mode.
|
||||
\param[in] display_panel Pointer to display panel resources.
|
||||
\param[in] dsi Pointer to DSI resources.
|
||||
\return \ref execution_status.
|
||||
*/
|
||||
static int32_t DSI_StartVideoMode (DISPLAY_PANEL_DEVICE *display_panel, DSI_RESOURCES *dsi)
|
||||
{
|
||||
int32_t ret = ARM_DRIVER_OK;
|
||||
|
||||
if((dsi->state.dpi_configured == 0) && (dsi->state.panel_initialized) == 0)
|
||||
{
|
||||
return ARM_DRIVER_ERROR;
|
||||
}
|
||||
|
||||
dsi_power_up_disable(dsi->reg_base);
|
||||
|
||||
dsi_auto_clklane_disable(dsi->reg_base);
|
||||
|
||||
dsi_phy_txrequestclkhs_enable(dsi->reg_base);
|
||||
|
||||
dsi_hs_eotp_enable(dsi->reg_base);
|
||||
|
||||
dsi_video_mode_enable(dsi->reg_base);
|
||||
|
||||
dsi_power_up_enable(dsi->reg_base);
|
||||
|
||||
/*Start LCD Panel*/
|
||||
ret = display_panel->ops->Start();
|
||||
if(ret != ARM_DRIVER_OK)
|
||||
{
|
||||
return ret;
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/**
|
||||
\fn int32_t DSI_Stop (DISPLAY_PANEL_DEVICE *display_panel, DSI_RESOURCES *dsi)
|
||||
\brief Shutdown DSI.
|
||||
\param[in] display_panel Pointer to display panel resources.
|
||||
\param[in] dsi Pointer to DSI resources
|
||||
\return \ref execution_status
|
||||
*/
|
||||
static int32_t DSI_Stop (DISPLAY_PANEL_DEVICE *display_panel, DSI_RESOURCES *dsi)
|
||||
{
|
||||
int32_t ret = ARM_DRIVER_OK;
|
||||
|
||||
if(dsi->state.powered == 0)
|
||||
{
|
||||
return ARM_DRIVER_ERROR;
|
||||
}
|
||||
|
||||
dsi_power_up_disable(dsi->reg_base);
|
||||
|
||||
/*Stop LCD Panel*/
|
||||
ret = display_panel->ops->Stop();
|
||||
if(ret != ARM_DRIVER_OK)
|
||||
{
|
||||
return ret;
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/**
|
||||
\fn void MIPI_DSI_ISR (DSI_RESOURCES *dsi)
|
||||
\brief MIPI DSI interrupt service routine
|
||||
\param[in] dsi Pointer to DSI resources
|
||||
*/
|
||||
static void MIPI_DSI_ISR (DSI_RESOURCES *dsi)
|
||||
{
|
||||
uint32_t int_st = dsi_irq0_status(dsi->reg_base);
|
||||
|
||||
if(int_st & (DSI_IRQ0_ACK_WITH_ERR_0 | DSI_IRQ0_ACK_WITH_ERR_1 | \
|
||||
DSI_IRQ0_ACK_WITH_ERR_2 | DSI_IRQ0_ACK_WITH_ERR_3 | \
|
||||
DSI_IRQ0_ACK_WITH_ERR_4 | DSI_IRQ0_ACK_WITH_ERR_5 | \
|
||||
DSI_IRQ0_ACK_WITH_ERR_6 | DSI_IRQ0_ACK_WITH_ERR_7 | \
|
||||
DSI_IRQ0_ACK_WITH_ERR_8 | DSI_IRQ0_ACK_WITH_ERR_9 | \
|
||||
DSI_IRQ0_ACK_WITH_ERR_10 | DSI_IRQ0_ACK_WITH_ERR_11 | \
|
||||
DSI_IRQ0_ACK_WITH_ERR_12 | DSI_IRQ0_ACK_WITH_ERR_13 | \
|
||||
DSI_IRQ0_ACK_WITH_ERR_14 | DSI_IRQ0_ACK_WITH_ERR_15))
|
||||
{
|
||||
dsi->cb_event(DSI_PHY_ERROR_EVENT);
|
||||
}
|
||||
|
||||
if(int_st & (DSI_IRQ0_DPHY_ERRORS_0 | DSI_IRQ0_DPHY_ERRORS_1 | \
|
||||
DSI_IRQ0_DPHY_ERRORS_3 | DSI_IRQ0_DPHY_ERRORS_4))
|
||||
{
|
||||
dsi->cb_event(DSI_ACK_ERROR_EVENT);
|
||||
}
|
||||
|
||||
int_st = dsi_irq1_status(dsi->reg_base);
|
||||
|
||||
if(int_st & (DSI_IRQ1_TO_HS_TX | DSI_IRQ1_TO_LP_RX | \
|
||||
DSI_IRQ1_ECC_SINGLE_ERR | DSI_IRQ1_ECC_MILTI_ERR | \
|
||||
DSI_IRQ1_CRC_ERR | DSI_IRQ1_PKT_SIZE_ERR | \
|
||||
DSI_IRQ1_EOPT_ERR))
|
||||
{
|
||||
dsi->cb_event(DSI_PKT_ERROR_EVENT);
|
||||
}
|
||||
|
||||
if(int_st & (DSI_IRQ1_DPI_PLD_WR_ERR | DSI_IRQ1_GEN_CMD_WR_ERR | \
|
||||
DSI_IRQ1_GEN_PLD_WR_ERR | DSI_IRQ1_GEN_PLD_SEND_ERR | \
|
||||
DSI_IRQ1_GEN_PLD_RD_ERR | DSI_IRQ1_GEN_PLD_RECEV_ERR | \
|
||||
DSI_IRQ1_DPI_BUFF_PLD_UNDER))
|
||||
{
|
||||
dsi->cb_event(DSI_DPI_ERROR_EVENT);
|
||||
}
|
||||
}
|
||||
|
||||
/* DSI LCD Panel access structure */
|
||||
static DISPLAY_PANEL_DEVICE *display_panel;
|
||||
|
||||
static DSI_DPI_INFO DPI_INFO =
|
||||
{
|
||||
.vid_mode = RTE_MIPI_DSI_VID_MODE_TYPE,
|
||||
.vid_num_chunks = RTE_MIPI_DSI_VID_NUM_CHUNKS,
|
||||
.vid_null_size = RTE_MIPI_DSI_VID_NULL_SIZE,
|
||||
};
|
||||
|
||||
static DSI_RESOURCES DSI_RES =
|
||||
{
|
||||
.reg_base = (DSI_Type*)DSI_BASE,
|
||||
.tx_ecs_clk_div = RTE_MIPI_DSI_TX_ESC_CLK_DIVISION,
|
||||
.dpi_info = &DPI_INFO,
|
||||
.irq = DSI_IRQ_IRQn,
|
||||
.irq_priority = RTE_MIPI_DSI_IRQ_PRI,
|
||||
};
|
||||
|
||||
/**
|
||||
\fn void DSI_DCS_Short_Write (uint8_t cmd, uint8_t data)
|
||||
\brief Perform MIPI DSI DCS Short write.
|
||||
\param[in] cmd is DCS command info.
|
||||
\param[in] data to send.
|
||||
*/
|
||||
void DSI_DCS_Short_Write (uint8_t cmd, uint8_t data)
|
||||
{
|
||||
dsi_dcs_short_write(DSI_RES.reg_base, cmd, data, display_panel->dsi_info->vc_id);
|
||||
|
||||
sys_busy_loop_us(100);
|
||||
}
|
||||
|
||||
/**
|
||||
\fn void DSI_DCS_CMD_Short_Write (uint8_t cmd)
|
||||
\brief Perform MIPI DSI DCS Short write only command.
|
||||
\param[in] cmd is DCS command info.
|
||||
*/
|
||||
void DSI_DCS_CMD_Short_Write (uint8_t cmd)
|
||||
{
|
||||
dsi_dcs_cmd_short_write(DSI_RES.reg_base, cmd, display_panel->dsi_info->vc_id);
|
||||
|
||||
sys_busy_loop_us(100);
|
||||
}
|
||||
|
||||
/**
|
||||
\fn void DSI_DCS_Long_Write (uint8_t cmd, uint32_t data)
|
||||
\brief Perform MIPI DSI DCS Short write.
|
||||
\param[in] data pointer to data buffer.
|
||||
\param[in] len data buffer length.
|
||||
*/
|
||||
void DSI_DCS_Long_Write (uint8_t* data, uint32_t len)
|
||||
{
|
||||
dsi_dcs_long_write(DSI_RES.reg_base, data, len, display_panel->dsi_info->vc_id);
|
||||
|
||||
sys_busy_loop_us(100);
|
||||
}
|
||||
|
||||
/**
|
||||
\fn int32_t ARM_MIPI_DSI_Initialize (ARM_MIPI_DSI_SignalEvent_t cb_event)
|
||||
\brief Initialize MIPI DSI Interface.
|
||||
\param[in] cb_event Pointer to ARM_MIPI_DSI_SignalEvent_t
|
||||
\return \ref execution_status
|
||||
*/
|
||||
static int32_t ARM_MIPI_DSI_Initialize (ARM_MIPI_DSI_SignalEvent_t cb_event)
|
||||
{
|
||||
display_panel = Get_Display_Panel();
|
||||
return DSI_Initialize (cb_event, display_panel, &DSI_RES);
|
||||
}
|
||||
|
||||
/**
|
||||
\fn int32_t ARM_MIPI_DSI_Uninitialize (void)
|
||||
\brief uninitialize MIPI DSI Interface.
|
||||
\return \ref execution_status
|
||||
*/
|
||||
static int32_t ARM_MIPI_DSI_Uninitialize (void)
|
||||
{
|
||||
return DSI_Uninitialize (display_panel, &DSI_RES);
|
||||
}
|
||||
|
||||
/**
|
||||
\fn int32_t ARM_MIPI_DSI_PowerControl (ARM_POWER_STATE state)
|
||||
\brief Control DSI Interface Power.
|
||||
\param[in] state Power state
|
||||
\return \ref execution_status
|
||||
*/
|
||||
static int32_t ARM_MIPI_DSI_PowerControl (ARM_POWER_STATE state)
|
||||
{
|
||||
return DSI_PowerControl (state, &DSI_RES);
|
||||
}
|
||||
|
||||
/**
|
||||
\fn int32_t ARM_MIPI_DSI_Control (ARM_MIPI_DSI_CONTROL control, uint32_t arg)
|
||||
\brief Control DSI Interface.
|
||||
\param[in] control DSI host and DPI Configuration.
|
||||
\param[in] arg Argument of operation (optional)
|
||||
\return \ref execution_status
|
||||
*/
|
||||
static int32_t ARM_MIPI_DSI_Control (ARM_MIPI_DSI_CONTROL control, uint32_t arg)
|
||||
{
|
||||
return DSI_Control (control, arg, display_panel, &DSI_RES);
|
||||
}
|
||||
|
||||
/**
|
||||
\fn int32_t ARM_MIPI_DSI_StartCommandMode (void)
|
||||
\brief Configure DSI to start Command mode.
|
||||
\return \ref execution_status
|
||||
*/
|
||||
static int32_t ARM_MIPI_DSI_StartCommandMode (void)
|
||||
{
|
||||
return DSI_StartCommandMode (display_panel,&DSI_RES);
|
||||
}
|
||||
|
||||
/**
|
||||
\fn int32_t ARM_MIPI_DSI_StartVideoMode (void)
|
||||
\brief Configure DSI to start Video mode.
|
||||
\return \ref execution_status
|
||||
*/
|
||||
static int32_t ARM_MIPI_DSI_StartVideoMode (void)
|
||||
{
|
||||
return DSI_StartVideoMode (display_panel, &DSI_RES);
|
||||
}
|
||||
|
||||
/**
|
||||
\fn int32_t ARM_MIPI_DSI_Stop (void)
|
||||
\brief Shutdown DSI.
|
||||
\return \ref execution_status
|
||||
*/
|
||||
static int32_t ARM_MIPI_DSI_Stop (void)
|
||||
{
|
||||
return DSI_Stop (display_panel, &DSI_RES);
|
||||
}
|
||||
|
||||
/**
|
||||
\fn void DSI_IRQHandler (void)
|
||||
\brief DSi IRQ Handler.
|
||||
*/
|
||||
void DSI_IRQHandler(void)
|
||||
{
|
||||
MIPI_DSI_ISR (&DSI_RES);
|
||||
}
|
||||
|
||||
/**
|
||||
\brief Access structure of the MIPI DSI Driver.
|
||||
*/
|
||||
extern ARM_DRIVER_MIPI_DSI Driver_MIPI_DSI;
|
||||
|
||||
ARM_DRIVER_MIPI_DSI Driver_MIPI_DSI =
|
||||
{
|
||||
ARM_MIPI_DSI_GetVersion,
|
||||
ARM_MIPI_DSI_GetCapabilities,
|
||||
ARM_MIPI_DSI_Initialize,
|
||||
ARM_MIPI_DSI_Uninitialize,
|
||||
ARM_MIPI_DSI_PowerControl,
|
||||
ARM_MIPI_DSI_Control,
|
||||
ARM_MIPI_DSI_StartCommandMode,
|
||||
ARM_MIPI_DSI_StartVideoMode,
|
||||
ARM_MIPI_DSI_Stop
|
||||
};
|
||||
347
src/hal/alif/Alif_CMSIS/Source/Driver_MRAM.c
Normal file
347
src/hal/alif/Alif_CMSIS/Source/Driver_MRAM.c
Normal file
@ -0,0 +1,347 @@
|
||||
/* Copyright (C) 2023 Alif Semiconductor - All Rights Reserved.
|
||||
* Use, distribution and modification of this code is permitted under the
|
||||
* terms stated in the Alif Semiconductor Software License Agreement
|
||||
*
|
||||
* You should have received a copy of the Alif Semiconductor Software
|
||||
* License Agreement with this file. If not, please write to:
|
||||
* contact@alifsemi.com, or visit: https://alifsemi.com/license
|
||||
*
|
||||
*/
|
||||
|
||||
/**************************************************************************//**
|
||||
* @file Driver_MRAM.c
|
||||
* @author Tanay Rami
|
||||
* @email tanay@alifsemi.com
|
||||
* @version V1.0.0
|
||||
* @date 01-June-2023
|
||||
* @brief ARM CMSIS-Driver for MRAM(On-Chip NVM(Non-Volatile Memory)).
|
||||
* @bug None.
|
||||
* @Note None.
|
||||
******************************************************************************/
|
||||
|
||||
/* System Includes */
|
||||
#include "string.h"
|
||||
|
||||
/* Project Includes */
|
||||
#include "Driver_MRAM_Private.h"
|
||||
#include "mram.h"
|
||||
|
||||
#if !(RTE_MRAM)
|
||||
#error "MRAM is not enabled in the RTE_Device.h"
|
||||
#endif
|
||||
|
||||
#if (defined(RTE_Drivers_MRAM) && !RTE_MRAM)
|
||||
#error "MRAM not configured in RTE_Device.h!"
|
||||
#endif
|
||||
|
||||
#define ARM_MRAM_DRV_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(1, 0) /* driver version */
|
||||
|
||||
/* MRAM Device Resources. */
|
||||
static MRAM_RESOURCES mram =
|
||||
{
|
||||
.state = {0}
|
||||
};
|
||||
|
||||
/* Driver Version */
|
||||
static const ARM_DRIVER_VERSION DriverVersion = {
|
||||
ARM_MRAM_API_VERSION,
|
||||
ARM_MRAM_DRV_VERSION
|
||||
};
|
||||
|
||||
/* Driver Capabilities */
|
||||
static const ARM_MRAM_CAPABILITIES DriverCapabilities = {
|
||||
0, /* data_width = 0:128-bit */
|
||||
0 /* reserved (must be zero) */
|
||||
};
|
||||
|
||||
|
||||
/**
|
||||
\fn ARM_DRIVER_VERSION MRAM_GetVersion(void)
|
||||
\brief Get driver version.
|
||||
\return \ref ARM_DRIVER_VERSION
|
||||
*/
|
||||
static ARM_DRIVER_VERSION MRAM_GetVersion(void)
|
||||
{
|
||||
return DriverVersion;
|
||||
}
|
||||
|
||||
/**
|
||||
\fn ARM_MRAM_CAPABILITIES MRAM_GetCapabilities(void)
|
||||
\brief Get driver capabilities.
|
||||
\return \ref ARM_MRAM_CAPABILITIES
|
||||
*/
|
||||
static ARM_MRAM_CAPABILITIES MRAM_GetCapabilities(void)
|
||||
{
|
||||
return DriverCapabilities;
|
||||
}
|
||||
|
||||
/**
|
||||
\fn int32_t MRAM_Initialize(void)
|
||||
\brief Initialize the MRAM Interface.
|
||||
\return \ref execution_status
|
||||
*/
|
||||
static int32_t MRAM_Initialize(void)
|
||||
{
|
||||
if (mram.state.initialized == 1)
|
||||
return ARM_DRIVER_OK;
|
||||
|
||||
/* Validate User MRAM size. */
|
||||
if (MRAM_USER_SIZE > MRAM_SIZE)
|
||||
return ARM_DRIVER_ERROR;
|
||||
|
||||
/* set the state as initialized. */
|
||||
mram.state.initialized = 1;
|
||||
|
||||
return ARM_DRIVER_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
\fn int32_t MRAM_Uninitialize(void)
|
||||
\brief De-initialize the MRAM Interface.
|
||||
\return \ref execution_status
|
||||
*/
|
||||
static int32_t MRAM_Uninitialize(void)
|
||||
{
|
||||
mram.state.initialized = 0;
|
||||
|
||||
return ARM_DRIVER_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
\fn int32_t MRAM_PowerControl(ARM_POWER_STATE state)
|
||||
\brief Control the MRAM interface power.
|
||||
\param[in] state Power state
|
||||
\return \ref execution_status
|
||||
*/
|
||||
static int32_t MRAM_PowerControl(ARM_POWER_STATE state)
|
||||
{
|
||||
switch (state)
|
||||
{
|
||||
case ARM_POWER_OFF:
|
||||
/* Reset the power state. */
|
||||
mram.state.powered = 0;
|
||||
break;
|
||||
|
||||
case ARM_POWER_LOW:
|
||||
break;
|
||||
|
||||
case ARM_POWER_FULL:
|
||||
if (mram.state.initialized == 0U)
|
||||
return ARM_DRIVER_ERROR;
|
||||
|
||||
if (mram.state.powered)
|
||||
break;
|
||||
|
||||
/* Set the state as powered */
|
||||
mram.state.powered = 1;
|
||||
break;
|
||||
|
||||
default:
|
||||
return ARM_DRIVER_ERROR_UNSUPPORTED;
|
||||
}
|
||||
|
||||
return ARM_DRIVER_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
\fn int32_t MRAM_ReadData(uint32_t addr, void *data, uint32_t cnt)
|
||||
\brief Read data from MRAM.
|
||||
\param[in] addr MRAM address-offset.
|
||||
\param[out] data Pointer to a buffer storing the data read from MRAM.
|
||||
\param[in] cnt Number of data items to read.
|
||||
\return number of data items read or \ref execution_status
|
||||
*/
|
||||
static int32_t MRAM_ReadData(uint32_t addr, void *data, uint32_t cnt)
|
||||
{
|
||||
if(mram.state.powered == 0U)
|
||||
return ARM_DRIVER_ERROR;
|
||||
|
||||
/* validate MRAM address and count. */
|
||||
if(addr > MRAM_USER_SIZE)
|
||||
return ARM_DRIVER_ERROR_PARAMETER;
|
||||
|
||||
if((addr + cnt) > MRAM_USER_SIZE)
|
||||
return ARM_DRIVER_ERROR_PARAMETER;
|
||||
|
||||
/* addr is MRAM address-offset,
|
||||
* so add MRAM Base-address to it. */
|
||||
addr += MRAM_BASE;
|
||||
|
||||
/* read from MRAM */
|
||||
mram_read(data, (void*)addr, cnt);
|
||||
|
||||
return cnt;
|
||||
}
|
||||
|
||||
/**
|
||||
\fn void MRAM_write(uint8_t *p_dst, const uint8_t *p_src)
|
||||
\brief write 128-bit data from source to destination(MRAM).
|
||||
\Note It is CRITICAL that this code running on the Application core
|
||||
contains the following:
|
||||
- H/W Limitations with Rev A silicon:
|
||||
The code that is performing the MRAM writes
|
||||
CANNOT be located and executing from MRAM.
|
||||
I.E. the code must be executing from SRAM.
|
||||
No code can be running from MRAM when you want to
|
||||
write to the MRAM.
|
||||
- The code should disable interrupts around the code
|
||||
where the MRAM writes and cache flush occur.
|
||||
- The code should include the function / Intrinsic “__DSB()”
|
||||
to make sure all the data writes are flushed out
|
||||
and have occurred.
|
||||
\param[out] p_dst Pointer to destination address.
|
||||
\param[in] p_src Pointer to source address.
|
||||
\return none
|
||||
*/
|
||||
static void MRAM_write(uint8_t *p_dst, const uint8_t *p_src)
|
||||
{
|
||||
/* write 128bit to MRAM. */
|
||||
mram_write_128bit(p_dst, p_src);
|
||||
|
||||
/* clean/flush Dcache. */
|
||||
RTSS_CleanDCache_by_Addr((uint32_t *)p_dst, MRAM_SECTOR_SIZE);
|
||||
}
|
||||
|
||||
/**
|
||||
\fn int32_t MRAM_ProgramData(uint32_t addr, const void *data, uint32_t cnt)
|
||||
\brief Program data to MRAM.
|
||||
\param[in] addr MRAM address-offset.
|
||||
\param[in] data Pointer to a buffer containing the data to be programmed to MRAM.
|
||||
\param[in] cnt Number of data items to program.
|
||||
\return number of data items programmed or \ref execution_status
|
||||
*/
|
||||
static int32_t MRAM_ProgramData(uint32_t addr, const void *data, uint32_t cnt)
|
||||
{
|
||||
if(mram.state.powered == 0U)
|
||||
return ARM_DRIVER_ERROR;
|
||||
|
||||
/* validate MRAM address and count. */
|
||||
if(addr > MRAM_USER_SIZE)
|
||||
return ARM_DRIVER_ERROR_PARAMETER;
|
||||
|
||||
if((addr + cnt) > MRAM_USER_SIZE)
|
||||
return ARM_DRIVER_ERROR_PARAMETER;
|
||||
|
||||
/* addr is MRAM address-offset,
|
||||
* so add MRAM Base-address to it. */
|
||||
addr += MRAM_BASE;
|
||||
|
||||
/* check address with aligned to 16-Bytes.*/
|
||||
uint32_t aligned_addr = addr & MRAM_ADDR_ALIGN_MASK;
|
||||
uint8_t *p_aligned_addr = (uint8_t *) aligned_addr;
|
||||
uint8_t *p_data = (uint8_t *) data;
|
||||
uint32_t count = cnt;
|
||||
|
||||
/* use temporary buffer to store data in case of unaligned memory.*/
|
||||
uint8_t temp_buff[MRAM_SECTOR_SIZE] = {0}; /* 128-Bit */
|
||||
|
||||
/* is MRAM address aligned to 16-Byte? */
|
||||
if(addr != aligned_addr)
|
||||
{
|
||||
/* unaligned MRAM address:
|
||||
* - make it to nearest aligned 16-Byte address,
|
||||
* by writing only unaligned bytes.
|
||||
*/
|
||||
|
||||
uint8_t offset = addr & (~MRAM_ADDR_ALIGN_MASK);
|
||||
uint8_t unaligned_bytes = MRAM_SECTOR_SIZE - offset;
|
||||
|
||||
/* is unaligned bytes more than remaining count? */
|
||||
if(unaligned_bytes > count)
|
||||
{
|
||||
/* then take only remaining count. */
|
||||
unaligned_bytes = count;
|
||||
}
|
||||
|
||||
/* copy original one sector data from MRAM address to buffer. */
|
||||
memcpy(temp_buff, p_aligned_addr, MRAM_SECTOR_SIZE);
|
||||
|
||||
/* overwrite buffer with new data as per offset and unaligned bytes. */
|
||||
memcpy(temp_buff + offset, p_data, unaligned_bytes);
|
||||
|
||||
/* now, copy 128bit from buffer to MRAM. */
|
||||
MRAM_write(p_aligned_addr, temp_buff);
|
||||
|
||||
p_aligned_addr += MRAM_SECTOR_SIZE;
|
||||
p_data += unaligned_bytes;
|
||||
count -= unaligned_bytes;
|
||||
}
|
||||
|
||||
uint32_t sector_cnt = count / MRAM_SECTOR_SIZE;
|
||||
uint8_t unaligned_cnt = count % MRAM_SECTOR_SIZE;
|
||||
|
||||
/* program 128-bit to absolute sector. */
|
||||
while(sector_cnt--)
|
||||
{
|
||||
/* as MRAM address is 16-byte aligned,
|
||||
* directly copy 128bit from source-data to MRAM. */
|
||||
MRAM_write(p_aligned_addr, p_data);
|
||||
|
||||
p_aligned_addr += MRAM_SECTOR_SIZE;
|
||||
p_data += MRAM_SECTOR_SIZE;
|
||||
}
|
||||
|
||||
/* program remaining unaligned data. */
|
||||
if(unaligned_cnt)
|
||||
{
|
||||
/* copy original one sector data from MRAM address to buffer.*/
|
||||
memcpy(temp_buff, p_aligned_addr, MRAM_SECTOR_SIZE);
|
||||
|
||||
/* overwrite buffer with new data as per remaining unaligned count.*/
|
||||
memcpy(temp_buff, p_data, unaligned_cnt);
|
||||
|
||||
/* now, copy 128bit from buffer to MRAM. */
|
||||
MRAM_write(p_aligned_addr, temp_buff);
|
||||
}
|
||||
|
||||
return cnt;
|
||||
}
|
||||
|
||||
/**
|
||||
\fn int32_t MRAM_EraseSector(uint32_t addr)
|
||||
\brief Erase MRAM Sector.
|
||||
\param[in] addr MRAM Sector address-offset.
|
||||
\return \ref execution_status
|
||||
*/
|
||||
static int32_t MRAM_EraseSector(uint32_t addr)
|
||||
{
|
||||
/* Added to fix Warning:
|
||||
* unused parameter [-Wunused-parameter] */
|
||||
ARG_UNUSED(addr);
|
||||
|
||||
return ARM_DRIVER_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
\fn int32_t MRAM_EraseChip(void)
|
||||
\brief Erase complete MRAM.
|
||||
Optional function for faster full chip erase.
|
||||
\return \ref execution_status
|
||||
*/
|
||||
static int32_t MRAM_EraseChip(void)
|
||||
{
|
||||
return ARM_DRIVER_OK;
|
||||
}
|
||||
// End MRAM Interface
|
||||
|
||||
|
||||
/* MRAM Driver Instance */
|
||||
#if (RTE_MRAM)
|
||||
|
||||
/* MRAM Driver Control Block */
|
||||
extern ARM_DRIVER_MRAM Driver_MRAM;
|
||||
ARM_DRIVER_MRAM Driver_MRAM =
|
||||
{
|
||||
MRAM_GetVersion,
|
||||
MRAM_GetCapabilities,
|
||||
MRAM_Initialize,
|
||||
MRAM_Uninitialize,
|
||||
MRAM_PowerControl,
|
||||
MRAM_ReadData,
|
||||
MRAM_ProgramData,
|
||||
MRAM_EraseSector,
|
||||
MRAM_EraseChip
|
||||
};
|
||||
#endif /* RTE_MRAM */
|
||||
|
||||
/************************ (C) COPYRIGHT ALIF SEMICONDUCTOR *****END OF FILE****/
|
||||
65
src/hal/alif/Alif_CMSIS/Source/Driver_MRAM_Private.h
Normal file
65
src/hal/alif/Alif_CMSIS/Source/Driver_MRAM_Private.h
Normal file
@ -0,0 +1,65 @@
|
||||
/* Copyright (C) 2023 Alif Semiconductor - All Rights Reserved.
|
||||
* Use, distribution and modification of this code is permitted under the
|
||||
* terms stated in the Alif Semiconductor Software License Agreement
|
||||
*
|
||||
* You should have received a copy of the Alif Semiconductor Software
|
||||
* License Agreement with this file. If not, please write to:
|
||||
* contact@alifsemi.com, or visit: https://alifsemi.com/license
|
||||
*
|
||||
*/
|
||||
|
||||
/**************************************************************************//**
|
||||
* @file Driver_MRAM_Private.h
|
||||
* @author Tanay Rami
|
||||
* @email tanay@alifsemi.com
|
||||
* @version V1.0.0
|
||||
* @date 01-June-2023
|
||||
* @brief Device Specific Header file for MRAM (On-chip NVM (Non-Volatile Memory))
|
||||
* Driver.
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef DRIVER_MRAM_PRIVATE_H
|
||||
#define DRIVER_MRAM_PRIVATE_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* System Includes */
|
||||
#include "RTE_Device.h"
|
||||
#include "RTE_Components.h"
|
||||
#include CMSIS_device_header
|
||||
|
||||
/* Project Includes */
|
||||
#include "Driver_MRAM.h"
|
||||
|
||||
/**
|
||||
\brief MRAM(On-Chip NVM) Total Size
|
||||
*/
|
||||
#define MRAM_USER_SIZE RTE_MRAM_SIZE
|
||||
|
||||
/**
|
||||
\brief MRAM Driver states.
|
||||
*/
|
||||
typedef volatile struct _MRAM_DRIVER_STATE
|
||||
{
|
||||
uint32_t initialized : 1; /* Driver initialized */
|
||||
uint32_t powered : 1; /* Driver powered */
|
||||
uint32_t reserved : 30;/* Reserved */
|
||||
} MRAM_DRIVER_STATE;
|
||||
|
||||
/**
|
||||
\brief MRAM(On-Chip NVM) Device Resources
|
||||
*/
|
||||
typedef struct _MRAM_RESOURCES
|
||||
{
|
||||
MRAM_DRIVER_STATE state; /* MRAM driver state */
|
||||
} MRAM_RESOURCES;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* DRIVER_MRAM_PRIVATE_H */
|
||||
|
||||
/************************ (C) COPYRIGHT ALIF SEMICONDUCTOR *****END OF FILE****/
|
||||
1292
src/hal/alif/Alif_CMSIS/Source/Driver_OSPI.c
Normal file
1292
src/hal/alif/Alif_CMSIS/Source/Driver_OSPI.c
Normal file
File diff suppressed because it is too large
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Reference in New Issue
Block a user