diff --git a/src/omv/boards/PORTENTA/omv_boardconfig.h b/src/omv/boards/PORTENTA/omv_boardconfig.h index a1a4084c5..80b557ac2 100644 --- a/src/omv/boards/PORTENTA/omv_boardconfig.h +++ b/src/omv/boards/PORTENTA/omv_boardconfig.h @@ -76,6 +76,9 @@ // Core VBAT for selftests #define OMV_CORE_VBAT "3.0" +// Defined for cpu frequency scaling to override the revid. +#define OMV_MAX_CPU_FREQ (400) + // PLL1 400MHz/40MHz for SDMMC and FDCAN // USB and RNG are clocked from the HSI48 #define OMV_OSC_PLL1M (5) diff --git a/src/omv/py/py_cpufreq.c b/src/omv/py/py_cpufreq.c index 0cc97d16d..1659bbbb6 100644 --- a/src/omv/py/py_cpufreq.c +++ b/src/omv/py/py_cpufreq.c @@ -15,22 +15,42 @@ #include STM32_HAL_H #include "py_cpufreq.h" #include "py_helper.h" +#include "omv_boardconfig.h" #if defined(STM32F7) || defined(STM32H7) -#define ARRAY_LENGTH(x) (sizeof(x)/sizeof(x[0])) - #if defined(STM32H7) -static const uint32_t cpufreq_freqs[] = {120, 240, 480}; +#define N_FREQUENCIES (4) +static const uint32_t CPUFREQ_FREQS_REV_V [N_FREQUENCIES] = {60, 120, 240, 480}; +static const uint32_t CPUFREQ_FREQS_REV_XY[N_FREQUENCIES] = {50, 100, 200, 400}; #elif defined(STM32F7) -static const uint32_t cpufreq_pllq[] = {5, 6, 7, 8, 9}; -static const uint32_t cpufreq_freqs[] = {120, 144, 168, 192, 216}; -static const uint32_t cpufreq_latency[] = { // Flash latency (see table 11) +#define N_FREQUENCIES (5) +static const uint32_t cpufreq_pllq[N_FREQUENCIES] = {5, 6, 7, 8, 9}; +static const uint32_t cpufreq_freqs[N_FREQUENCIES] = {120, 144, 168, 192, 216}; +static const uint32_t cpufreq_latency[N_FREQUENCIES] = { // Flash latency (see table 11) FLASH_LATENCY_3, FLASH_LATENCY_4, FLASH_LATENCY_5, FLASH_LATENCY_7, FLASH_LATENCY_7 }; #endif -uint32_t cpufreq_get_cpuclk() +#if defined(STM32H7) +static const uint32_t *cpufreq_get_frequencies() +{ + #if (OMV_MAX_CPU_FREQ == 400) + (void)CPUFREQ_FREQS_REV_V; + // If the maximum frequency is set to 400 use rev x/y frequencies. + return CPUFREQ_FREQS_REV_XY; + #else + // Otherwise, determine the frequencies dynamically using the revid. + if (HAL_GetREVID() >= 0x2003) { + return CPUFREQ_FREQS_REV_V; + } else { + return CPUFREQ_FREQS_REV_XY; + } + #endif +} +#endif + +static uint32_t cpufreq_get_cpuclk() { uint32_t cpuclk = HAL_RCC_GetSysClockFreq(); @@ -48,6 +68,9 @@ uint32_t cpufreq_get_cpuclk() case RCC_SYSCLK_DIV4: cpuclk /= 4; break; + case RCC_SYSCLK_DIV8: + cpuclk /= 8; + break; default: break; } @@ -68,8 +91,11 @@ mp_obj_t py_cpufreq_get_current_frequencies() mp_obj_t py_cpufreq_get_supported_frequencies() { + #if defined(STM32H7) + const uint32_t *cpufreq_freqs = cpufreq_get_frequencies(); + #endif mp_obj_t freq_list = mp_obj_new_list(0, NULL); - for (int i=0; i